2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
4 #ifndef _ASM_POWERPC_SYSTEM_H
5 #define _ASM_POWERPC_SYSTEM_H
7 #include <linux/kernel.h>
9 #include <asm/hw_irq.h>
13 * The sync instruction guarantees that all memory accesses initiated
14 * by this processor have been performed (with respect to all other
15 * mechanisms that access memory). The eieio instruction is a barrier
16 * providing an ordering (separately) for (a) cacheable stores and (b)
17 * loads and stores to non-cacheable memory (e.g. I/O devices).
19 * mb() prevents loads and stores being reordered across this point.
20 * rmb() prevents loads being reordered across this point.
21 * wmb() prevents stores being reordered across this point.
22 * read_barrier_depends() prevents data-dependent loads being reordered
23 * across this point (nop on PPC).
25 * We have to use the sync instructions for mb(), since lwsync doesn't
26 * order loads with respect to previous stores. Lwsync is fine for
27 * rmb(), though. Note that rmb() actually uses a sync on 32-bit
30 * For wmb(), we use sync since wmb is used in drivers to order
31 * stores to system memory with respect to writes to the device.
32 * However, smp_wmb() can be a lighter-weight eieio barrier on
33 * SMP since it is only used to order updates to system memory.
35 #define mb() __asm__ __volatile__ ("sync" : : : "memory")
36 #define rmb() __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory")
37 #define wmb() __asm__ __volatile__ ("sync" : : : "memory")
38 #define read_barrier_depends() do { } while(0)
40 #define set_mb(var, value) do { var = value; mb(); } while (0)
45 #define smp_rmb() rmb()
46 #define smp_wmb() eieio()
47 #define smp_read_barrier_depends() read_barrier_depends()
49 #define smp_mb() barrier()
50 #define smp_rmb() barrier()
51 #define smp_wmb() barrier()
52 #define smp_read_barrier_depends() do { } while(0)
53 #endif /* CONFIG_SMP */
56 * This is a barrier which prevents following instructions from being
57 * started until the value of the argument x is known. For example, if
58 * x is a variable loaded from memory, this prevents following
59 * instructions from being executed until the load has been performed.
61 #define data_barrier(x) \
62 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
67 #ifdef CONFIG_DEBUGGER
69 extern int (*__debugger)(struct pt_regs *regs);
70 extern int (*__debugger_ipi)(struct pt_regs *regs);
71 extern int (*__debugger_bpt)(struct pt_regs *regs);
72 extern int (*__debugger_sstep)(struct pt_regs *regs);
73 extern int (*__debugger_iabr_match)(struct pt_regs *regs);
74 extern int (*__debugger_dabr_match)(struct pt_regs *regs);
75 extern int (*__debugger_fault_handler)(struct pt_regs *regs);
77 #define DEBUGGER_BOILERPLATE(__NAME) \
78 static inline int __NAME(struct pt_regs *regs) \
80 if (unlikely(__ ## __NAME)) \
81 return __ ## __NAME(regs); \
85 DEBUGGER_BOILERPLATE(debugger)
86 DEBUGGER_BOILERPLATE(debugger_ipi)
87 DEBUGGER_BOILERPLATE(debugger_bpt)
88 DEBUGGER_BOILERPLATE(debugger_sstep)
89 DEBUGGER_BOILERPLATE(debugger_iabr_match)
90 DEBUGGER_BOILERPLATE(debugger_dabr_match)
91 DEBUGGER_BOILERPLATE(debugger_fault_handler)
94 static inline int debugger(struct pt_regs *regs) { return 0; }
95 static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
96 static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
97 static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
98 static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
99 static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
100 static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
103 extern int set_dabr(unsigned long dabr);
104 extern void print_backtrace(unsigned long *);
105 extern void show_regs(struct pt_regs * regs);
106 extern void flush_instruction_cache(void);
107 extern void hard_reset_now(void);
108 extern void poweroff_now(void);
111 extern long _get_L2CR(void);
112 extern long _get_L3CR(void);
113 extern void _set_L2CR(unsigned long);
114 extern void _set_L3CR(unsigned long);
116 #define _get_L2CR() 0L
117 #define _get_L3CR() 0L
118 #define _set_L2CR(val) do { } while(0)
119 #define _set_L3CR(val) do { } while(0)
122 extern void via_cuda_init(void);
123 extern void read_rtc_time(void);
124 extern void pmac_find_display(void);
125 extern void giveup_fpu(struct task_struct *);
126 extern void disable_kernel_fp(void);
127 extern void enable_kernel_fp(void);
128 extern void flush_fp_to_thread(struct task_struct *);
129 extern void enable_kernel_altivec(void);
130 extern void giveup_altivec(struct task_struct *);
131 extern void load_up_altivec(struct task_struct *);
132 extern int emulate_altivec(struct pt_regs *);
133 extern void enable_kernel_spe(void);
134 extern void giveup_spe(struct task_struct *);
135 extern void load_up_spe(struct task_struct *);
136 extern int fix_alignment(struct pt_regs *);
137 extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
138 extern void cvt_df(double *from, float *to, struct thread_struct *thread);
141 extern void discard_lazy_cpu_state(void);
143 static inline void discard_lazy_cpu_state(void)
148 #ifdef CONFIG_ALTIVEC
149 extern void flush_altivec_to_thread(struct task_struct *);
151 static inline void flush_altivec_to_thread(struct task_struct *t)
157 extern void flush_spe_to_thread(struct task_struct *);
159 static inline void flush_spe_to_thread(struct task_struct *t)
164 extern int call_rtas(const char *, int, int, unsigned long *, ...);
165 extern void cacheable_memzero(void *p, unsigned int nb);
166 extern void *cacheable_memcpy(void *, const void *, unsigned int);
167 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
168 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
169 extern int die(const char *, struct pt_regs *, long);
170 extern void _exception(int, struct pt_regs *, int, unsigned long);
171 #ifdef CONFIG_BOOKE_WDT
172 extern u32 booke_wdt_enabled;
173 extern u32 booke_wdt_period;
174 #endif /* CONFIG_BOOKE_WDT */
177 extern void note_scsi_host(struct device_node *, void *);
179 extern struct task_struct *__switch_to(struct task_struct *,
180 struct task_struct *);
181 #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
183 struct thread_struct;
184 extern struct task_struct *_switch(struct thread_struct *prev,
185 struct thread_struct *next);
187 extern unsigned int rtas_data;
188 extern int mem_init_done; /* set on boot once kmalloc can be called */
189 extern unsigned long memory_limit;
190 extern unsigned long klimit;
192 extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
193 extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
195 extern int powersave_nap; /* set if nap mode can be used in idle loop */
200 * Changes the memory location '*ptr' to be val and returns
201 * the previous value stored there.
203 static __inline__ unsigned long
204 __xchg_u32(volatile void *p, unsigned long val)
208 __asm__ __volatile__(
210 "1: lwarx %0,0,%2 \n"
215 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
225 * Changes the memory location '*ptr' to be val and returns
226 * the previous value stored there.
228 static __inline__ unsigned long
229 __xchg_u32_local(volatile void *p, unsigned long val)
233 __asm__ __volatile__(
234 "1: lwarx %0,0,%2 \n"
238 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
246 static __inline__ unsigned long
247 __xchg_u64(volatile void *p, unsigned long val)
251 __asm__ __volatile__(
253 "1: ldarx %0,0,%2 \n"
258 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
265 static __inline__ unsigned long
266 __xchg_u64_local(volatile void *p, unsigned long val)
270 __asm__ __volatile__(
271 "1: ldarx %0,0,%2 \n"
275 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
284 * This function doesn't exist, so you'll get a linker error
285 * if something tries to do an invalid xchg().
287 extern void __xchg_called_with_bad_pointer(void);
289 static __inline__ unsigned long
290 __xchg(volatile void *ptr, unsigned long x, unsigned int size)
294 return __xchg_u32(ptr, x);
297 return __xchg_u64(ptr, x);
300 __xchg_called_with_bad_pointer();
304 static __inline__ unsigned long
305 __xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
309 return __xchg_u32_local(ptr, x);
312 return __xchg_u64_local(ptr, x);
315 __xchg_called_with_bad_pointer();
318 #define xchg(ptr,x) \
320 __typeof__(*(ptr)) _x_ = (x); \
321 (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
324 #define xchg_local(ptr,x) \
326 __typeof__(*(ptr)) _x_ = (x); \
327 (__typeof__(*(ptr))) __xchg_local((ptr), \
328 (unsigned long)_x_, sizeof(*(ptr))); \
332 * Compare and exchange - if *p == old, set it to new,
333 * and return the old value of *p.
335 #define __HAVE_ARCH_CMPXCHG 1
337 static __inline__ unsigned long
338 __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
342 __asm__ __volatile__ (
344 "1: lwarx %0,0,%2 # __cmpxchg_u32\n\
353 : "=&r" (prev), "+m" (*p)
354 : "r" (p), "r" (old), "r" (new)
360 static __inline__ unsigned long
361 __cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
366 __asm__ __volatile__ (
367 "1: lwarx %0,0,%2 # __cmpxchg_u32\n\
375 : "=&r" (prev), "+m" (*p)
376 : "r" (p), "r" (old), "r" (new)
383 static __inline__ unsigned long
384 __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
388 __asm__ __volatile__ (
390 "1: ldarx %0,0,%2 # __cmpxchg_u64\n\
398 : "=&r" (prev), "+m" (*p)
399 : "r" (p), "r" (old), "r" (new)
405 static __inline__ unsigned long
406 __cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
411 __asm__ __volatile__ (
412 "1: ldarx %0,0,%2 # __cmpxchg_u64\n\
419 : "=&r" (prev), "+m" (*p)
420 : "r" (p), "r" (old), "r" (new)
427 /* This function doesn't exist, so you'll get a linker error
428 if something tries to do an invalid cmpxchg(). */
429 extern void __cmpxchg_called_with_bad_pointer(void);
431 static __inline__ unsigned long
432 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
437 return __cmpxchg_u32(ptr, old, new);
440 return __cmpxchg_u64(ptr, old, new);
443 __cmpxchg_called_with_bad_pointer();
447 static __inline__ unsigned long
448 __cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
453 return __cmpxchg_u32_local(ptr, old, new);
456 return __cmpxchg_u64_local(ptr, old, new);
459 __cmpxchg_called_with_bad_pointer();
463 #define cmpxchg(ptr,o,n) \
465 __typeof__(*(ptr)) _o_ = (o); \
466 __typeof__(*(ptr)) _n_ = (n); \
467 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
468 (unsigned long)_n_, sizeof(*(ptr))); \
472 #define cmpxchg_local(ptr,o,n) \
474 __typeof__(*(ptr)) _o_ = (o); \
475 __typeof__(*(ptr)) _n_ = (n); \
476 (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
477 (unsigned long)_n_, sizeof(*(ptr))); \
482 * We handle most unaligned accesses in hardware. On the other hand
483 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
484 * powers of 2 writes until it reaches sufficient alignment).
486 * Based on this we disable the IP header alignment in network drivers.
487 * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
488 * cacheline alignment of buffers.
490 #define NET_IP_ALIGN 0
491 #define NET_SKB_PAD L1_CACHE_BYTES
494 #define arch_align_stack(x) (x)
496 /* Used in very early kernel initialization. */
497 extern unsigned long reloc_offset(void);
498 extern unsigned long add_reloc_offset(unsigned long);
499 extern void reloc_got2(unsigned long);
501 #define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
503 static inline void create_instruction(unsigned long addr, unsigned int instr)
506 p = (unsigned int *)addr;
508 asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p));
511 /* Flags for create_branch:
512 * "b" == create_branch(addr, target, 0);
513 * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE);
514 * "bl" == create_branch(addr, target, BRANCH_SET_LINK);
515 * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
517 #define BRANCH_SET_LINK 0x1
518 #define BRANCH_ABSOLUTE 0x2
520 static inline void create_branch(unsigned long addr,
521 unsigned long target, int flags)
523 unsigned int instruction;
525 if (! (flags & BRANCH_ABSOLUTE))
526 target = target - addr;
528 /* Mask out the flags and target, so they don't step on each other. */
529 instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC);
531 create_instruction(addr, instruction);
534 static inline void create_function_call(unsigned long addr, void * func)
536 unsigned long func_addr;
540 * On PPC64 the function pointer actually points to the function's
541 * descriptor. The first entry in the descriptor is the address
542 * of the function text.
544 func_addr = *(unsigned long *)func;
546 func_addr = (unsigned long)func;
548 create_branch(addr, func_addr, BRANCH_SET_LINK);
551 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
552 extern void account_system_vtime(struct task_struct *);
555 extern struct dentry *powerpc_debugfs_root;
557 #endif /* __KERNEL__ */
558 #endif /* _ASM_POWERPC_SYSTEM_H */