1 #ifndef __ASM_CPU_SH4_DMA_H
2 #define __ASM_CPU_SH4_DMA_H
4 #define DMAOR_INIT ( 0x8000 | DMAOR_DME )
7 #define SH_DMAC_BASE 0xfc808020
9 #define CHCR_TS_MASK 0x18
10 #define CHCR_TS_SHIFT 3
12 #include <asm/cpu/dma-sh7780.h>
14 #define SH_DMAC_BASE 0xffa00000
16 /* Definitions for the SuperH DMAC */
17 #define TM_BURST 0x0000080
18 #define TS_8 0x00000010
19 #define TS_16 0x00000020
20 #define TS_32 0x00000030
21 #define TS_64 0x00000000
23 #define CHCR_TS_MASK 0x30
24 #define CHCR_TS_SHIFT 4
26 #define DMAOR_COD 0x00000008
29 * The SuperH DMAC supports a number of transmit sizes, we list them here,
30 * with their respective values as they appear in the CHCR registers.
32 * Defaults to a 64-bit transfer size.
43 * The DMA count is defined as the number of bytes to transfer.
45 static unsigned int ts_shift[] __attribute__ ((used)) = {
54 #endif /* __ASM_CPU_SH4_DMA_H */