1 #ifndef __ASM_SH_SYSTEM_H
2 #define __ASM_SH_SYSTEM_H
5 * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
6 * Copyright (C) 2002 Paul Mundt
12 * switch_to() should switch tasks to task nr n, first
15 #define switch_to(prev, next, last) do { \
16 struct task_struct *__last; \
17 register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \
18 register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \
19 register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \
20 register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \
21 register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \
22 register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \
23 __asm__ __volatile__ (".balign 4\n\t" \
24 "stc.l gbr, @-r15\n\t" \
25 "sts.l pr, @-r15\n\t" \
26 "mov.l r8, @-r15\n\t" \
27 "mov.l r9, @-r15\n\t" \
28 "mov.l r10, @-r15\n\t" \
29 "mov.l r11, @-r15\n\t" \
30 "mov.l r12, @-r15\n\t" \
31 "mov.l r13, @-r15\n\t" \
32 "mov.l r14, @-r15\n\t" \
33 "mov.l r15, @r1 ! save SP\n\t" \
34 "mov.l @r6, r15 ! change to new stack\n\t" \
36 "mov.l %0, @r2 ! save PC\n\t" \
38 "jmp @%0 ! call __switch_to\n\t" \
39 " lds r7, pr ! with return to new PC\n\t" \
42 ".long __switch_to\n" \
44 "mov.l @r15+, r14\n\t" \
45 "mov.l @r15+, r13\n\t" \
46 "mov.l @r15+, r12\n\t" \
47 "mov.l @r15+, r11\n\t" \
48 "mov.l @r15+, r10\n\t" \
49 "mov.l @r15+, r9\n\t" \
50 "mov.l @r15+, r8\n\t" \
51 "lds.l @r15+, pr\n\t" \
52 "ldc.l @r15+, gbr\n\t" \
54 : "r" (__ts1), "r" (__ts2), "r" (__ts4), \
55 "r" (__ts5), "r" (__ts6), "r" (__ts7) \
61 * On SMP systems, when the scheduler does migration-cost autodetection,
62 * it needs a way to flush as much of the CPU's caches as possible.
66 static inline void sched_cacheflush(void)
70 #ifdef CONFIG_CPU_SH4A
73 unsigned long __addr; \
74 __addr = 0xa8000000; \
75 __asm__ __volatile__( \
78 : "m" (__m(__addr))); \
82 static __inline__ unsigned long tas(volatile int *m)
86 __asm__ __volatile__ ("tas.b @%1\n\t"
88 : "=r" (retval): "r" (m): "t", "memory");
93 * A brief note on ctrl_barrier(), the control register write barrier.
95 * Legacy SH cores typically require a sequence of 8 nops after
96 * modification of a control register in order for the changes to take
97 * effect. On newer cores (like the sh4a and sh5) this is accomplished
100 * Also note that on sh4a in the icbi case we can forego a synco for the
101 * write barrier, as it's not necessary for control registers.
103 * Historically we have only done this type of barrier for the MMUCR, but
104 * it's also necessary for the CCR, so we make it generic here instead.
106 #ifdef CONFIG_CPU_SH4A
107 #define mb() __asm__ __volatile__ ("synco": : :"memory")
109 #define wmb() __asm__ __volatile__ ("synco": : :"memory")
110 #define ctrl_barrier() __icbi()
111 #define read_barrier_depends() do { } while(0)
113 #define mb() __asm__ __volatile__ ("": : :"memory")
115 #define wmb() __asm__ __volatile__ ("": : :"memory")
116 #define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
117 #define read_barrier_depends() do { } while(0)
121 #define smp_mb() mb()
122 #define smp_rmb() rmb()
123 #define smp_wmb() wmb()
124 #define smp_read_barrier_depends() read_barrier_depends()
126 #define smp_mb() barrier()
127 #define smp_rmb() barrier()
128 #define smp_wmb() barrier()
129 #define smp_read_barrier_depends() do { } while(0)
132 #define set_mb(var, value) do { xchg(&var, value); } while (0)
134 /* Interrupt Control */
135 #ifdef CONFIG_CPU_HAS_SR_RB
136 static inline void local_irq_enable(void)
138 unsigned long __dummy0, __dummy1;
140 __asm__ __volatile__("stc sr, %0\n\t"
142 "stc r6_bank, %1\n\t"
145 : "=&r" (__dummy0), "=r" (__dummy1)
150 static inline void local_irq_enable(void)
152 unsigned long __dummy0, __dummy1;
154 __asm__ __volatile__ (
158 : "=&r" (__dummy0), "=r" (__dummy1)
164 static __inline__ void local_irq_disable(void)
166 unsigned long __dummy;
167 __asm__ __volatile__("stc sr, %0\n\t"
175 #define local_save_flags(x) \
176 __asm__("stc sr, %0; and #0xf0, %0" : "=&z" (x) :/**/: "memory" )
178 #define irqs_disabled() \
180 unsigned long flags; \
181 local_save_flags(flags); \
185 static __inline__ unsigned long local_irq_save(void)
187 unsigned long flags, __dummy;
189 __asm__ __volatile__("stc sr, %1\n\t"
195 : "=&z" (flags), "=&r" (__dummy)
202 static __inline__ void local_irq_restore(unsigned long x)
204 if ((x & 0x000000f0) != 0x000000f0)
208 local_save_flags(flags);
211 extern void dump_stack(void);
212 printk(KERN_ERR "BUG!\n");
219 #define local_irq_restore(x) do { \
220 if ((x & 0x000000f0) != 0x000000f0) \
221 local_irq_enable(); \
225 #define really_restore_flags(x) do { \
226 if ((x & 0x000000f0) != 0x000000f0) \
227 local_irq_enable(); \
229 local_irq_disable(); \
234 * When handling TLB or caches, we need to do it from P2 area.
236 #define jump_to_P2() \
238 unsigned long __dummy; \
239 __asm__ __volatile__( \
248 : "r" (0x20000000)); \
254 #define back_to_P1() \
256 unsigned long __dummy; \
258 __asm__ __volatile__( \
265 : "=&r" (__dummy)); \
268 /* For spinlocks etc */
269 #define local_irq_save(x) x = local_irq_save()
271 static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
273 unsigned long flags, retval;
275 local_irq_save(flags);
278 local_irq_restore(flags);
282 static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
284 unsigned long flags, retval;
286 local_irq_save(flags);
289 local_irq_restore(flags);
293 extern void __xchg_called_with_bad_pointer(void);
295 #define __xchg(ptr, x, size) \
297 unsigned long __xchg__res; \
298 volatile void *__xchg_ptr = (ptr); \
301 __xchg__res = xchg_u32(__xchg_ptr, x); \
304 __xchg__res = xchg_u8(__xchg_ptr, x); \
307 __xchg_called_with_bad_pointer(); \
315 #define xchg(ptr,x) \
316 ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
318 static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
324 local_irq_save(flags);
328 local_irq_restore(flags); /* implies memory barrier */
332 /* This function doesn't exist, so you'll get a linker error
333 * if something tries to do an invalid cmpxchg(). */
334 extern void __cmpxchg_called_with_bad_pointer(void);
336 #define __HAVE_ARCH_CMPXCHG 1
338 static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
339 unsigned long new, int size)
343 return __cmpxchg_u32(ptr, old, new);
345 __cmpxchg_called_with_bad_pointer();
349 #define cmpxchg(ptr,o,n) \
351 __typeof__(*(ptr)) _o_ = (o); \
352 __typeof__(*(ptr)) _n_ = (n); \
353 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
354 (unsigned long)_n_, sizeof(*(ptr))); \
358 * disable hlt during certain critical i/o operations
360 #define HAVE_DISABLE_HLT
361 void disable_hlt(void);
362 void enable_hlt(void);
364 #define arch_align_stack(x) (x)