2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 /* Please note that modifications to all structs defined here are
31 * subject to backwards-compatibility constraints.
36 /* Each region is a minimum of 16k, and there are at most 255 of them.
38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
39 * of chars for next/prev indices */
40 #define I915_LOG_MIN_TEX_REGION_SIZE 14
42 typedef struct _drm_i915_init {
45 I915_CLEANUP_DMA = 0x02,
46 I915_RESUME_DMA = 0x03
48 unsigned int mmio_offset;
49 int sarea_priv_offset;
50 unsigned int ring_start;
51 unsigned int ring_end;
52 unsigned int ring_size;
53 unsigned int front_offset;
54 unsigned int back_offset;
55 unsigned int depth_offset;
59 unsigned int pitch_bits;
60 unsigned int back_pitch;
61 unsigned int depth_pitch;
66 typedef struct _drm_i915_sarea {
67 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
68 int last_upload; /* last time texture was uploaded */
69 int last_enqueue; /* last time a buffer was enqueued */
70 int last_dispatch; /* age of the most recently dispatched buffer */
71 int ctxOwner; /* last context to upload state */
73 int pf_enabled; /* is pageflipping allowed? */
75 int pf_current_page; /* which buffer is being displayed? */
76 int perf_boxes; /* performance boxes to be displayed */
77 int width, height; /* screen size in pixels */
79 drm_handle_t front_handle;
83 drm_handle_t back_handle;
87 drm_handle_t depth_handle;
91 drm_handle_t tex_handle;
94 int log_tex_granularity;
96 int rotation; /* 0, 90, 180 or 270 */
100 int virtualX, virtualY;
102 unsigned int front_tiled;
103 unsigned int back_tiled;
104 unsigned int depth_tiled;
105 unsigned int rotated_tiled;
106 unsigned int rotated2_tiled;
118 /* Flags for perf_boxes
120 #define I915_BOX_RING_EMPTY 0x1
121 #define I915_BOX_FLIP 0x2
122 #define I915_BOX_WAIT 0x4
123 #define I915_BOX_TEXTURE_LOAD 0x8
124 #define I915_BOX_LOST_CONTEXT 0x10
126 /* I915 specific ioctls
127 * The device specific ioctl range is 0x40 to 0x79.
129 #define DRM_I915_INIT 0x00
130 #define DRM_I915_FLUSH 0x01
131 #define DRM_I915_FLIP 0x02
132 #define DRM_I915_BATCHBUFFER 0x03
133 #define DRM_I915_IRQ_EMIT 0x04
134 #define DRM_I915_IRQ_WAIT 0x05
135 #define DRM_I915_GETPARAM 0x06
136 #define DRM_I915_SETPARAM 0x07
137 #define DRM_I915_ALLOC 0x08
138 #define DRM_I915_FREE 0x09
139 #define DRM_I915_INIT_HEAP 0x0a
140 #define DRM_I915_CMDBUFFER 0x0b
141 #define DRM_I915_DESTROY_HEAP 0x0c
142 #define DRM_I915_SET_VBLANK_PIPE 0x0d
143 #define DRM_I915_GET_VBLANK_PIPE 0x0e
144 #define DRM_I915_VBLANK_SWAP 0x0f
145 #define DRM_I915_HWS_ADDR 0x11
146 #define DRM_I915_GEM_INIT 0x13
147 #define DRM_I915_GEM_EXECBUFFER 0x14
148 #define DRM_I915_GEM_PIN 0x15
149 #define DRM_I915_GEM_UNPIN 0x16
150 #define DRM_I915_GEM_BUSY 0x17
151 #define DRM_I915_GEM_THROTTLE 0x18
152 #define DRM_I915_GEM_ENTERVT 0x19
153 #define DRM_I915_GEM_LEAVEVT 0x1a
154 #define DRM_I915_GEM_CREATE 0x1b
155 #define DRM_I915_GEM_PREAD 0x1c
156 #define DRM_I915_GEM_PWRITE 0x1d
157 #define DRM_I915_GEM_MMAP 0x1e
158 #define DRM_I915_GEM_SET_DOMAIN 0x1f
159 #define DRM_I915_GEM_SW_FINISH 0x20
160 #define DRM_I915_GEM_SET_TILING 0x21
161 #define DRM_I915_GEM_GET_TILING 0x22
163 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
164 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
165 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
166 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
167 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
168 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
169 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
170 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
171 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
172 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
173 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
174 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
175 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
176 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
177 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
178 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
179 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
180 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
181 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
182 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
183 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
184 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
185 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
186 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
187 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
188 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
189 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
190 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
191 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
192 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
194 /* Allow drivers to submit batchbuffers directly to hardware, relying
195 * on the security mechanisms provided by hardware.
197 typedef struct _drm_i915_batchbuffer {
198 int start; /* agp offset */
199 int used; /* nr bytes in use */
200 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
201 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
202 int num_cliprects; /* mulitpass with multiple cliprects? */
203 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
204 } drm_i915_batchbuffer_t;
206 /* As above, but pass a pointer to userspace buffer which can be
207 * validated by the kernel prior to sending to hardware.
209 typedef struct _drm_i915_cmdbuffer {
210 char __user *buf; /* pointer to userspace command buffer */
211 int sz; /* nr bytes in buf */
212 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
213 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
214 int num_cliprects; /* mulitpass with multiple cliprects? */
215 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
216 } drm_i915_cmdbuffer_t;
218 /* Userspace can request & wait on irq's:
220 typedef struct drm_i915_irq_emit {
222 } drm_i915_irq_emit_t;
224 typedef struct drm_i915_irq_wait {
226 } drm_i915_irq_wait_t;
228 /* Ioctl to query kernel params:
230 #define I915_PARAM_IRQ_ACTIVE 1
231 #define I915_PARAM_ALLOW_BATCHBUFFER 2
232 #define I915_PARAM_LAST_DISPATCH 3
233 #define I915_PARAM_CHIPSET_ID 4
234 #define I915_PARAM_HAS_GEM 5
236 typedef struct drm_i915_getparam {
239 } drm_i915_getparam_t;
241 /* Ioctl to set kernel params:
243 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
244 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
245 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
247 typedef struct drm_i915_setparam {
250 } drm_i915_setparam_t;
252 /* A memory manager for regions of shared memory:
254 #define I915_MEM_REGION_AGP 1
256 typedef struct drm_i915_mem_alloc {
260 int __user *region_offset; /* offset from start of fb or agp */
261 } drm_i915_mem_alloc_t;
263 typedef struct drm_i915_mem_free {
266 } drm_i915_mem_free_t;
268 typedef struct drm_i915_mem_init_heap {
272 } drm_i915_mem_init_heap_t;
274 /* Allow memory manager to be torn down and re-initialized (eg on
277 typedef struct drm_i915_mem_destroy_heap {
279 } drm_i915_mem_destroy_heap_t;
281 /* Allow X server to configure which pipes to monitor for vblank signals
283 #define DRM_I915_VBLANK_PIPE_A 1
284 #define DRM_I915_VBLANK_PIPE_B 2
286 typedef struct drm_i915_vblank_pipe {
288 } drm_i915_vblank_pipe_t;
290 /* Schedule buffer swap at given vertical blank:
292 typedef struct drm_i915_vblank_swap {
293 drm_drawable_t drawable;
294 enum drm_vblank_seq_type seqtype;
295 unsigned int sequence;
296 } drm_i915_vblank_swap_t;
298 typedef struct drm_i915_hws_addr {
300 } drm_i915_hws_addr_t;
302 struct drm_i915_gem_init {
304 * Beginning offset in the GTT to be managed by the DRM memory
309 * Ending offset in the GTT to be managed by the DRM memory
315 struct drm_i915_gem_create {
317 * Requested size for the object.
319 * The (page-aligned) allocated size for the object will be returned.
323 * Returned handle for the object.
325 * Object handles are nonzero.
331 struct drm_i915_gem_pread {
332 /** Handle for the object being read. */
335 /** Offset into the object to read from */
337 /** Length of data to read */
340 * Pointer to write the data into.
342 * This is a fixed-size type for 32/64 compatibility.
347 struct drm_i915_gem_pwrite {
348 /** Handle for the object being written to. */
351 /** Offset into the object to write to */
353 /** Length of data to write */
356 * Pointer to read the data from.
358 * This is a fixed-size type for 32/64 compatibility.
363 struct drm_i915_gem_mmap {
364 /** Handle for the object being mapped. */
367 /** Offset in the object to map. */
370 * Length of data to map.
372 * The value will be page-aligned.
376 * Returned pointer the data was mapped at.
378 * This is a fixed-size type for 32/64 compatibility.
383 struct drm_i915_gem_set_domain {
384 /** Handle for the object */
387 /** New read domains */
388 uint32_t read_domains;
390 /** New write domain */
391 uint32_t write_domain;
394 struct drm_i915_gem_sw_finish {
395 /** Handle for the object */
399 struct drm_i915_gem_relocation_entry {
401 * Handle of the buffer being pointed to by this relocation entry.
403 * It's appealing to make this be an index into the mm_validate_entry
404 * list to refer to the buffer, but this allows the driver to create
405 * a relocation list for state buffers and not re-write it per
406 * exec using the buffer.
408 uint32_t target_handle;
411 * Value to be added to the offset of the target buffer to make up
412 * the relocation entry.
416 /** Offset in the buffer the relocation entry will be written into */
420 * Offset value of the target buffer that the relocation entry was last
423 * If the buffer has the same offset as last time, we can skip syncing
424 * and writing the relocation. This value is written back out by
425 * the execbuffer ioctl when the relocation is written.
427 uint64_t presumed_offset;
430 * Target memory domains read by this operation.
432 uint32_t read_domains;
435 * Target memory domains written by this operation.
437 * Note that only one domain may be written by the whole
438 * execbuffer operation, so that where there are conflicts,
439 * the application will get -EINVAL back.
441 uint32_t write_domain;
445 * Intel memory domains
447 * Most of these just align with the various caches in
448 * the system and are used to flush and invalidate as
449 * objects end up cached in different domains.
452 #define I915_GEM_DOMAIN_CPU 0x00000001
453 /** Render cache, used by 2D and 3D drawing */
454 #define I915_GEM_DOMAIN_RENDER 0x00000002
455 /** Sampler cache, used by texture engine */
456 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
457 /** Command queue, used to load batch buffers */
458 #define I915_GEM_DOMAIN_COMMAND 0x00000008
459 /** Instruction cache, used by shader programs */
460 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
461 /** Vertex address cache */
462 #define I915_GEM_DOMAIN_VERTEX 0x00000020
463 /** GTT domain - aperture and scanout */
464 #define I915_GEM_DOMAIN_GTT 0x00000040
467 struct drm_i915_gem_exec_object {
469 * User's handle for a buffer to be bound into the GTT for this
474 /** Number of relocations to be performed on this buffer */
475 uint32_t relocation_count;
477 * Pointer to array of struct drm_i915_gem_relocation_entry containing
478 * the relocations to be performed in this buffer.
482 /** Required alignment in graphics aperture */
486 * Returned value of the updated offset of the object, for future
487 * presumed_offset writes.
492 struct drm_i915_gem_execbuffer {
494 * List of buffers to be validated with their relocations to be
495 * performend on them.
497 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
499 * These buffers must be listed in an order such that all relocations
500 * a buffer is performing refer to buffers that have already appeared
501 * in the validate list.
503 uint64_t buffers_ptr;
504 uint32_t buffer_count;
506 /** Offset in the batchbuffer to start execution from. */
507 uint32_t batch_start_offset;
508 /** Bytes used in batchbuffer from batch_start_offset */
512 uint32_t num_cliprects;
513 /** This is a struct drm_clip_rect *cliprects */
514 uint64_t cliprects_ptr;
517 struct drm_i915_gem_pin {
518 /** Handle of the buffer to be pinned. */
522 /** alignment required within the aperture */
525 /** Returned GTT offset of the buffer. */
529 struct drm_i915_gem_unpin {
530 /** Handle of the buffer to be unpinned. */
535 struct drm_i915_gem_busy {
536 /** Handle of the buffer to check for busy */
539 /** Return busy status (1 if busy, 0 if idle) */
543 #define I915_TILING_NONE 0
544 #define I915_TILING_X 1
545 #define I915_TILING_Y 2
547 #define I915_BIT_6_SWIZZLE_NONE 0
548 #define I915_BIT_6_SWIZZLE_9 1
549 #define I915_BIT_6_SWIZZLE_9_10 2
550 #define I915_BIT_6_SWIZZLE_9_11 3
551 #define I915_BIT_6_SWIZZLE_9_10_11 4
552 /* Not seen by userland */
553 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
555 struct drm_i915_gem_set_tiling {
556 /** Handle of the buffer to have its tiling state updated */
560 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
563 * This value is to be set on request, and will be updated by the
564 * kernel on successful return with the actual chosen tiling layout.
566 * The tiling mode may be demoted to I915_TILING_NONE when the system
567 * has bit 6 swizzling that can't be managed correctly by GEM.
569 * Buffer contents become undefined when changing tiling_mode.
571 uint32_t tiling_mode;
574 * Stride in bytes for the object when in I915_TILING_X or
580 * Returned address bit 6 swizzling required for CPU access through
583 uint32_t swizzle_mode;
586 struct drm_i915_gem_get_tiling {
587 /** Handle of the buffer to get tiling state for. */
591 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
594 uint32_t tiling_mode;
597 * Returned address bit 6 swizzling required for CPU access through
600 uint32_t swizzle_mode;
603 #endif /* _I915_DRM_H_ */