1 --- gcc/config/arm/arm.c.orig 2004-03-11 14:50:36.000000000 +0000
2 +++ gcc/config/arm/arm.c 2004-03-11 14:58:05.000000000 +0000
6 /* Nonzero if this chip is an XScale. */
7 -int arm_is_xscale = 0;
8 +int arm_arch_xscale = 0;
10 +/* Nonzero if tuning for XScale */
11 +int arm_tune_xscale = 0;
13 /* Nonzero if this chip is an ARM6 or an ARM7. */
14 int arm_is_6_or_7 = 0;
16 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
17 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
18 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
19 - arm_is_xscale = (insn_flags & FL_XSCALE) != 0;
20 + arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
22 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
23 arm_is_strong = (tune_flags & FL_STRONG) != 0;
24 thumb_code = (TARGET_ARM == 0);
25 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
26 && !(tune_flags & FL_ARCH4))) != 0;
27 + arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
29 /* Default value for floating point code... if no co-processor
30 bus, then schedule for emulated floating point. Otherwise,
32 if (optimize_size || (tune_flags & FL_LDSCHED))
33 arm_constant_limit = 1;
36 + if (arm_arch_xscale)
37 arm_constant_limit = 2;
39 /* If optimizing for size, bump the number of instructions that we
42 /* Some true dependencies can have a higher cost depending
43 on precisely how certain input operands are used. */
46 && REG_NOTE_KIND (link) == 0
47 && recog_memoized (insn) < 0
48 && recog_memoized (dep) < 0)
51 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
52 for counts of 3 or 4 regs. */
53 - if (arm_is_xscale && count <= 2 && ! optimize_size)
54 + if (arm_tune_xscale && count <= 2 && ! optimize_size)
60 /* See arm_gen_load_multiple for discussion of
61 the pros/cons of ldm/stm usage for XScale. */
62 - if (arm_is_xscale && count <= 2 && ! optimize_size)
63 + if (arm_tune_xscale && count <= 2 && ! optimize_size)
68 --- gcc/config/arm/arm.h 23 Apr 2003 16:39:30 -0000 1.189
69 +++ gcc/config/arm/arm.h 14 May 2003 21:26:33 -0000
70 @@ -610,7 +610,10 @@ extern int arm_is_strong;
71 extern int arm_is_cirrus;
73 /* Nonzero if this chip is an XScale. */
74 -extern int arm_is_xscale;
75 +extern int arm_arch_xscale;
77 +/* Nonzero if tuning for XScale */
78 +extern int arm_tune_xscale;
80 /* Nonzero if this chip is an ARM6 or an ARM7. */
81 extern int arm_is_6_or_7;
82 @@ -728,7 +731,7 @@ extern int arm_is_6_or_7;
83 #define BIGGEST_ALIGNMENT 32
85 /* Make strings word-aligned so strcpy from constants will be faster. */
86 -#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
87 +#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_arch_xscale ? 1 : 2)
89 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
90 ((TREE_CODE (EXP) == STRING_CST \
91 @@ -2119,8 +2122,8 @@ do { \
95 -#define MOVE_RATIO (arm_is_xscale ? 4 : 2)
96 +#define MOVE_RATIO (arm_arch_xscale ? 4 : 2)
98 /* Define if operations between registers always perform the operation
99 on the full register even if a narrower mode is specified. */
101 --- gcc/config/arm/arm.md.old 2003-05-23 21:28:39.000000000 +0200
102 +++ gcc/config/arm/arm.md 2003-05-23 21:30:02.000000000 +0200
105 ;; Operand number of an input operand that is shifted. Zero if the
106 ;; given instruction does not shift one of its input operands.
107 -(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_is_xscale")))
108 +(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_tune_xscale")))
109 (define_attr "shift" "" (const_int 0))
111 ; Floating Point Unit. If we only have floating point emulation, then there
112 @@ -1185,7 +1185,7 @@
114 (set (match_operand:SI 0 "s_register_operand" "=&r,&r")
115 (mult:SI (match_dup 2) (match_dup 1)))]
116 - "TARGET_ARM && !arm_is_xscale"
117 + "TARGET_ARM && !arm_arch_xscale"
118 "mul%?s\\t%0, %2, %1"
119 [(set_attr "conds" "set")
120 (set_attr "type" "mult")]
121 @@ -1198,7 +1198,7 @@
122 (match_operand:SI 1 "s_register_operand" "%?r,0"))
124 (clobber (match_scratch:SI 0 "=&r,&r"))]
125 - "TARGET_ARM && !arm_is_xscale"
126 + "TARGET_ARM && !arm_arch_xscale"
127 "mul%?s\\t%0, %2, %1"
128 [(set_attr "conds" "set")
129 (set_attr "type" "mult")]
130 @@ -1229,7 +1229,7 @@
131 (set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
132 (plus:SI (mult:SI (match_dup 2) (match_dup 1))
134 - "TARGET_ARM && !arm_is_xscale"
135 + "TARGET_ARM && !arm_arch_xscale"
136 "mla%?s\\t%0, %2, %1, %3"
137 [(set_attr "conds" "set")
138 (set_attr "type" "mult")]
139 @@ -1244,7 +1244,7 @@
140 (match_operand:SI 3 "s_register_operand" "?r,r,0,0"))
142 (clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))]
143 - "TARGET_ARM && !arm_is_xscale"
144 + "TARGET_ARM && !arm_arch_xscale"
145 "mla%?s\\t%0, %2, %1, %3"
146 [(set_attr "conds" "set")
147 (set_attr "type" "mult")]
148 @@ -1338,7 +1338,7 @@
149 (match_operand:HI 1 "s_register_operand" "%r"))
151 (match_operand:HI 2 "s_register_operand" "r"))))]
152 - "TARGET_ARM && arm_is_xscale"
153 + "TARGET_ARM && arm_arch_xscale"
154 "smulbb%?\\t%0, %1, %2"
155 [(set_attr "type" "mult")]
157 @@ -1350,7 +1350,7 @@
158 (match_operand:HI 2 "s_register_operand" "%r"))
160 (match_operand:HI 3 "s_register_operand" "r")))))]
161 - "TARGET_ARM && arm_is_xscale"
162 + "TARGET_ARM && arm_arch_xscale"
163 "smlabb%?\\t%0, %2, %3, %1"
164 [(set_attr "type" "mult")]
166 @@ -1363,7 +1363,7 @@
167 (match_operand:HI 2 "s_register_operand" "%r"))
169 (match_operand:HI 3 "s_register_operand" "r")))))]
170 - "TARGET_ARM && arm_is_xscale"
171 + "TARGET_ARM && arm_arch_xscale"
172 "smlalbb%?\\t%Q0, %R0, %2, %3"
173 [(set_attr "type" "mult")])