3 # Patch managed by http://www.holgerschurig.de/patcher.html
6 --- linux-2.4.27/Makefile~2.4.27-vrs1-pxa1-jpm1
7 +++ linux-2.4.27/Makefile
12 -EXTRAVERSION =-vrs1-pxa1
13 +EXTRAVERSION =-vrs1-pxa1-jpm1
15 KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
17 --- linux-2.4.27/arch/arm/mach-sa1100/Makefile~2.4.27-vrs1-pxa1-jpm1
18 +++ linux-2.4.27/arch/arm/mach-sa1100/Makefile
20 export-objs := assabet.o consus.o badge4.o dma-sa1100.o dma-sa1111.o \
21 flexanet.o freebird.o frodo.o generic.o h3600.o \
22 huw_webpanel.o irq.o sa1111.o sa1111-pcibuf.o \
23 - system3.o yopy.o usb_ctl.o usb_recv.o usb_send.o simputer.o ssp.o
24 + system3.o yopy.o usb_ctl.o usb_recv.o usb_send.o simputer.o ssp.o \
27 # These aren't present yet, and prevents a plain -ac kernel building.
30 ifeq ($(CONFIG_CPU_FREQ),y)
31 obj-$(CONFIG_SA1100_ASSABET) += cpu-sa1110.o
32 obj-$(CONFIG_SA1100_CEP) += cpu-sa1110.o
33 -obj-$(CONFIG_SA1100_CONSUS) += cpu-sa1110.o
34 obj-$(CONFIG_SA1100_CERF) += cpu-sa1110.o
35 obj-$(CONFIG_SA1100_HACKKIT) += cpu-sa1110.o
36 obj-$(CONFIG_SA1100_PT_SYSTEM3) += cpu-sa1110.o
38 obj-$(CONFIG_SA1100_BRUTUS) += brutus.o
39 obj-$(CONFIG_SA1100_CEP) += cep.o
40 obj-$(CONFIG_SA1100_CERF) += cerf.o
41 -obj-$(CONFIG_SA1100_CONSUS) += consus.o
42 obj-$(CONFIG_SA1100_EMPEG) += empeg.o
43 obj-$(CONFIG_SA1100_FLEXANET) += flexanet.o
44 obj-$(CONFIG_SA1100_FREEBIRD) += freebird.o
46 leds-$(CONFIG_SA1100_ASSABET) += leds-assabet.o
47 leds-$(CONFIG_SA1100_BRUTUS) += leds-brutus.o
48 leds-$(CONFIG_SA1100_CERF) += leds-cerf.o
49 -leds-$(CONFIG_SA1100_CONSUS) += leds-consus.o
50 leds-$(CONFIG_SA1100_FLEXANET) += leds-flexanet.o
51 leds-$(CONFIG_SA1100_FRODO) += leds-frodo.o
52 leds-$(CONFIG_SA1100_GRAPHICSCLIENT) += leds-graphicsclient.o
55 # Miscelaneous functions
56 obj-$(CONFIG_PM) += pm.o sleep.o
57 +obj-$(CONFIG_APM) += apm.o
60 +export-objs += simpad_pm.o
61 +obj-$(CONFIG_SIMPAD_PM) += simpad_pm.o
63 obj-$(CONFIG_SA1100_SSP) += ssp.o
65 include $(TOPDIR)/Rules.make
66 --- linux-2.4.27/drivers/video/fbmem.c~2.4.27-vrs1-pxa1-jpm1
67 +++ linux-2.4.27/drivers/video/fbmem.c
69 extern int chips_init(void);
70 extern int g364fb_init(void);
71 extern int sa1100fb_init(void);
72 +extern int mq200fb_init(void);
73 extern int pxafb_init(void);
74 extern int fm2fb_init(void);
75 extern int fm2fb_setup(char*);
77 #ifdef CONFIG_FB_SA1100
78 { "sa1100", sa1100fb_init, NULL },
80 +#ifdef CONFIG_FB_MQ200
81 + { "mq200fb", mq200fb_init, NULL },
84 { "pxa", pxafb_init, NULL },
86 --- linux-2.4.27/arch/arm/config.in~2.4.27-vrs1-pxa1-jpm1
87 +++ linux-2.4.27/arch/arm/config.in
89 dep_bool ' Shannon' CONFIG_SA1100_SHANNON $CONFIG_ARCH_SA1100
90 dep_bool ' Sherman' CONFIG_SA1100_SHERMAN $CONFIG_ARCH_SA1100
91 dep_bool ' Simpad' CONFIG_SA1100_SIMPAD $CONFIG_ARCH_SA1100
92 +if [ "$CONFIG_SA1100_SIMPAD" = "y" ]; then
93 + bool ' T-Sinus PAD' CONFIG_SA1100_SIMPAD_SINUSPAD
95 dep_bool ' Simputer' CONFIG_SA1100_SIMPUTER $CONFIG_ARCH_SA1100
96 dep_bool ' Tulsa' CONFIG_SA1100_PFS168 $CONFIG_ARCH_SA1100
97 dep_bool ' Victor' CONFIG_SA1100_VICTOR $CONFIG_ARCH_SA1100
99 tristate 'Kernel support for ELF binaries' CONFIG_BINFMT_ELF
100 tristate 'Kernel support for MISC binaries' CONFIG_BINFMT_MISC
101 dep_bool 'Power Management support (experimental)' CONFIG_PM $CONFIG_EXPERIMENTAL
102 +dep_tristate 'Advanced power management emulation support' CONFIG_APM $CONFIG_PM
103 +if [ "$CONFIG_APM" != "n" ]; then
104 + bool ' SIMpad power management' CONFIG_SIMPAD_PM
106 dep_tristate 'RISC OS personality' CONFIG_ARTHUR $CONFIG_CPU_32
107 string 'Default kernel command string' CONFIG_CMDLINE ""
110 +++ linux-2.4.27/arch/arm/def-configs/simpad
113 +# Automatically generated by make menuconfig: don't edit
116 +# CONFIG_EISA is not set
117 +# CONFIG_SBUS is not set
118 +# CONFIG_MCA is not set
120 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
121 +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
122 +# CONFIG_GENERIC_BUST_SPINLOCK is not set
123 +# CONFIG_GENERIC_ISA_DMA is not set
126 +# Code maturity level options
128 +CONFIG_EXPERIMENTAL=y
129 +# CONFIG_OBSOLETE is not set
132 +# Loadable module support
135 +# CONFIG_MODVERSIONS is not set
141 +# CONFIG_ARCH_ANAKIN is not set
142 +# CONFIG_ARCH_ARCA5K is not set
143 +# CONFIG_ARCH_CLPS7500 is not set
144 +# CONFIG_ARCH_CLPS711X is not set
145 +# CONFIG_ARCH_CO285 is not set
146 +# CONFIG_ARCH_EBSA110 is not set
147 +# CONFIG_ARCH_CAMELOT is not set
148 +# CONFIG_ARCH_FOOTBRIDGE is not set
149 +# CONFIG_ARCH_INTEGRATOR is not set
150 +# CONFIG_ARCH_OMAHA is not set
151 +# CONFIG_ARCH_L7200 is not set
152 +# CONFIG_ARCH_MX1ADS is not set
153 +# CONFIG_ARCH_RPC is not set
154 +# CONFIG_ARCH_RISCSTATION is not set
155 +CONFIG_ARCH_SA1100=y
156 +# CONFIG_ARCH_SHARK is not set
157 +# CONFIG_ARCH_AT91RM9200DK is not set
160 +# Archimedes/A5000 Implementations
162 +# CONFIG_ARCH_ARC is not set
163 +# CONFIG_ARCH_A5K is not set
166 +# Footbridge Implementations
168 +# CONFIG_ARCH_CATS is not set
169 +# CONFIG_ARCH_PERSONAL_SERVER is not set
170 +# CONFIG_ARCH_EBSA285_ADDIN is not set
171 +# CONFIG_ARCH_EBSA285_HOST is not set
172 +# CONFIG_ARCH_NETWINDER is not set
175 +# SA11x0 Implementations
177 +# CONFIG_SA1100_ACCELENT is not set
178 +# CONFIG_SA1100_ASSABET is not set
179 +# CONFIG_ASSABET_NEPONSET is not set
180 +# CONFIG_SA1100_ADSAGC is not set
181 +# CONFIG_SA1100_ADSBITSY is not set
182 +# CONFIG_SA1100_ADSBITSYPLUS is not set
183 +# CONFIG_SA1100_BRUTUS is not set
184 +# CONFIG_SA1100_CEP is not set
185 +# CONFIG_SA1100_CERF is not set
186 +# CONFIG_SA1100_H3100 is not set
187 +# CONFIG_SA1100_H3600 is not set
188 +# CONFIG_SA1100_H3800 is not set
189 +# CONFIG_SA1100_H3XXX is not set
190 +# CONFIG_H3600_SLEEVE is not set
191 +# CONFIG_SA1100_EXTENEX1 is not set
192 +# CONFIG_SA1100_FLEXANET is not set
193 +# CONFIG_SA1100_FREEBIRD is not set
194 +# CONFIG_SA1100_FRODO is not set
195 +# CONFIG_SA1100_GRAPHICSCLIENT is not set
196 +# CONFIG_SA1100_GRAPHICSMASTER is not set
197 +# CONFIG_SA1100_HACKKIT is not set
198 +# CONFIG_SA1100_BADGE4 is not set
199 +# CONFIG_SA1100_JORNADA720 is not set
200 +# CONFIG_SA1100_HUW_WEBPANEL is not set
201 +# CONFIG_SA1100_ITSY is not set
202 +# CONFIG_SA1100_LART is not set
203 +# CONFIG_SA1100_NANOENGINE is not set
204 +# CONFIG_SA1100_OMNIMETER is not set
205 +# CONFIG_SA1100_PANGOLIN is not set
206 +# CONFIG_SA1100_PLEB is not set
207 +# CONFIG_SA1100_PT_SYSTEM3 is not set
208 +# CONFIG_SA1100_SHANNON is not set
209 +# CONFIG_SA1100_SHERMAN is not set
210 +CONFIG_SA1100_SIMPAD=y
211 +# CONFIG_SA1100_SIMPAD_SINUSPAD is not set
212 +# CONFIG_SA1100_SIMPUTER is not set
213 +# CONFIG_SA1100_PFS168 is not set
214 +# CONFIG_SA1100_VICTOR is not set
215 +# CONFIG_SA1100_XP860 is not set
216 +# CONFIG_SA1100_YOPY is not set
218 +CONFIG_SA1100_USB_NETLINK=m
219 +CONFIG_SA1100_USB_CHAR=m
220 +# CONFIG_SA1100_SSP is not set
223 +# CLPS711X/EP721X Implementations
225 +# CONFIG_ARCH_AUTCPU12 is not set
226 +# CONFIG_ARCH_CDB89712 is not set
227 +# CONFIG_ARCH_CLEP7312 is not set
228 +# CONFIG_ARCH_EDB7211 is not set
229 +# CONFIG_ARCH_FORTUNET is not set
230 +# CONFIG_ARCH_GUIDEA07 is not set
231 +# CONFIG_ARCH_P720T is not set
232 +# CONFIG_ARCH_EP7211 is not set
233 +# CONFIG_ARCH_EP7212 is not set
234 +# CONFIG_ARCH_ACORN is not set
235 +# CONFIG_FOOTBRIDGE is not set
236 +# CONFIG_FOOTBRIDGE_HOST is not set
237 +# CONFIG_FOOTBRIDGE_ADDIN is not set
239 +# CONFIG_CPU_26 is not set
240 +# CONFIG_CPU_ARM610 is not set
241 +# CONFIG_CPU_ARM710 is not set
242 +# CONFIG_CPU_ARM720T is not set
243 +# CONFIG_CPU_ARM920T is not set
244 +# CONFIG_CPU_ARM922T is not set
245 +# CONFIG_PLD is not set
246 +# CONFIG_CPU_ARM926T is not set
247 +# CONFIG_CPU_ARM1020 is not set
248 +# CONFIG_CPU_ARM1026 is not set
249 +# CONFIG_CPU_SA110 is not set
251 +# CONFIG_CPU_32v3 is not set
253 +CONFIG_DISCONTIGMEM=y
258 +# CONFIG_PCI is not set
260 +# CONFIG_ISA_DMA is not set
261 +# CONFIG_ZBOOT_ROM is not set
262 +CONFIG_ZBOOT_ROM_TEXT=0
263 +CONFIG_ZBOOT_ROM_BSS=0
268 +# PCMCIA/CardBus support
271 +CONFIG_PCMCIA_PROBE=y
272 +# CONFIG_I82092 is not set
273 +# CONFIG_I82365 is not set
274 +# CONFIG_TCIC is not set
275 +# CONFIG_PCMCIA_CLPS6700 is not set
276 +CONFIG_PCMCIA_SA1100=y
279 +# CONFIG_BSD_PROCESS_ACCT is not set
282 +# CONFIG_FPE_FASTFPE is not set
284 +# CONFIG_KCORE_AOUT is not set
285 +# CONFIG_BINFMT_AOUT is not set
287 +CONFIG_BINFMT_MISC=m
291 +# CONFIG_ARTHUR is not set
292 +CONFIG_CMDLINE="mtdparts=sa1100:512k(boot),1m(kernel),-(root) console=ttySA root=1f02 noinitrd mem=64M"
296 +CONFIG_ALIGNMENT_TRAP=y
299 +# Parallel port support
301 +# CONFIG_PARPORT is not set
304 +# Memory Technology Devices (MTD)
307 +# CONFIG_MTD_DEBUG is not set
308 +CONFIG_MTD_PARTITIONS=y
309 +# CONFIG_MTD_CONCAT is not set
310 +CONFIG_MTD_REDBOOT_PARTS=y
311 +CONFIG_MTD_CMDLINE_PARTS=y
312 +# CONFIG_MTD_AFS_PARTS is not set
315 +# CONFIG_FTL is not set
316 +# CONFIG_NFTL is not set
319 +# RAM/ROM/Flash chip drivers
322 +CONFIG_MTD_JEDECPROBE=y
323 +CONFIG_MTD_GEN_PROBE=y
324 +CONFIG_MTD_CFI_ADV_OPTIONS=y
325 +CONFIG_MTD_CFI_NOSWAP=y
326 +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
327 +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
328 +CONFIG_MTD_CFI_GEOMETRY=y
329 +# CONFIG_MTD_CFI_B1 is not set
331 +# CONFIG_MTD_CFI_B4 is not set
332 +# CONFIG_MTD_CFI_B8 is not set
334 +# CONFIG_MTD_CFI_I2 is not set
335 +# CONFIG_MTD_CFI_I4 is not set
336 +# CONFIG_MTD_CFI_I8 is not set
337 +CONFIG_MTD_CFI_INTELEXT=y
338 +# CONFIG_MTD_CFI_AMDSTD is not set
339 +# CONFIG_MTD_RAM is not set
341 +# CONFIG_MTD_ABSENT is not set
342 +# CONFIG_MTD_OBSOLETE_CHIPS is not set
343 +# CONFIG_MTD_AMDSTD is not set
344 +# CONFIG_MTD_SHARP is not set
345 +# CONFIG_MTD_JEDEC is not set
348 +# Mapping drivers for chip access
350 +# CONFIG_MTD_PHYSMAP is not set
351 +# CONFIG_MTD_NORA is not set
352 +# CONFIG_MTD_ARM_INTEGRATOR is not set
353 +# CONFIG_MTD_CDB89712 is not set
355 +# CONFIG_MTD_DC21285 is not set
356 +# CONFIG_MTD_IQ80310 is not set
357 +# CONFIG_MTD_FORTUNET is not set
358 +# CONFIG_MTD_EPXA is not set
359 +# CONFIG_MTD_AUTCPU12 is not set
360 +# CONFIG_MTD_EDB7312 is not set
361 +# CONFIG_MTD_IMPA7 is not set
362 +# CONFIG_MTD_PCI is not set
365 +# Self-contained MTD device drivers
367 +# CONFIG_MTD_PMC551 is not set
368 +# CONFIG_MTD_SLRAM is not set
370 +CONFIG_MTDRAM_TOTAL_SIZE=32768
371 +CONFIG_MTDRAM_ERASE_SIZE=1
372 +CONFIG_MTDRAM_ABS_POS=C2000000
373 +# CONFIG_MTD_BLKMTD is not set
374 +# CONFIG_MTD_DOC1000 is not set
375 +# CONFIG_MTD_DOC2000 is not set
376 +# CONFIG_MTD_DOC2001 is not set
377 +# CONFIG_MTD_DOCPROBE is not set
380 +# NAND Flash Device Drivers
382 +# CONFIG_MTD_NAND is not set
385 +# Plug and Play configuration
387 +# CONFIG_PNP is not set
388 +# CONFIG_ISAPNP is not set
393 +# CONFIG_BLK_DEV_FD is not set
394 +# CONFIG_BLK_DEV_XD is not set
395 +# CONFIG_PARIDE is not set
396 +# CONFIG_BLK_CPQ_DA is not set
397 +# CONFIG_BLK_CPQ_CISS_DA is not set
398 +# CONFIG_CISS_SCSI_TAPE is not set
399 +# CONFIG_BLK_DEV_DAC960 is not set
400 +# CONFIG_BLK_DEV_UMEM is not set
401 +CONFIG_BLK_DEV_LOOP=y
402 +# CONFIG_BLK_DEV_NBD is not set
403 +CONFIG_BLK_DEV_RAM=y
404 +CONFIG_BLK_DEV_RAM_SIZE=8192
405 +# CONFIG_BLK_DEV_INITRD is not set
408 +# Multi-device support (RAID and LVM)
410 +# CONFIG_MD is not set
411 +# CONFIG_BLK_DEV_MD is not set
412 +# CONFIG_MD_LINEAR is not set
413 +# CONFIG_MD_RAID0 is not set
414 +# CONFIG_MD_RAID1 is not set
415 +# CONFIG_MD_RAID5 is not set
416 +# CONFIG_MD_MULTIPATH is not set
417 +# CONFIG_BLK_DEV_LVM is not set
420 +# Networking options
423 +CONFIG_PACKET_MMAP=y
424 +# CONFIG_NETLINK_DEV is not set
425 +# CONFIG_NETFILTER is not set
426 +# CONFIG_FILTER is not set
429 +# CONFIG_IP_MULTICAST is not set
430 +# CONFIG_IP_ADVANCED_ROUTER is not set
432 +CONFIG_IP_PNP_DHCP=y
433 +CONFIG_IP_PNP_BOOTP=y
434 +# CONFIG_IP_PNP_RARP is not set
435 +# CONFIG_NET_IPIP is not set
436 +# CONFIG_NET_IPGRE is not set
437 +# CONFIG_ARPD is not set
438 +# CONFIG_INET_ECN is not set
439 +# CONFIG_SYN_COOKIES is not set
440 +# CONFIG_IPV6 is not set
441 +# CONFIG_KHTTPD is not set
442 +# CONFIG_ATM is not set
443 +# CONFIG_VLAN_8021Q is not set
444 +# CONFIG_IPX is not set
445 +# CONFIG_ATALK is not set
450 +# CONFIG_DEV_APPLETALK is not set
451 +# CONFIG_DECNET is not set
452 +# CONFIG_BRIDGE is not set
453 +# CONFIG_X25 is not set
454 +# CONFIG_LAPB is not set
455 +# CONFIG_LLC is not set
456 +# CONFIG_NET_DIVERT is not set
457 +# CONFIG_ECONET is not set
458 +# CONFIG_WAN_ROUTER is not set
459 +# CONFIG_NET_FASTROUTE is not set
460 +# CONFIG_NET_HW_FLOWCONTROL is not set
463 +# QoS and/or fair queueing
465 +# CONFIG_NET_SCHED is not set
470 +# CONFIG_NET_PKTGEN is not set
473 +# Network device support
480 +# CONFIG_ARCNET is not set
482 +# CONFIG_BONDING is not set
483 +# CONFIG_EQUALIZER is not set
484 +# CONFIG_TUN is not set
485 +# CONFIG_ETHERTAP is not set
488 +# Ethernet (10 or 100Mbit)
490 +CONFIG_NET_ETHERNET=y
491 +# CONFIG_ARM_AM79C961A is not set
492 +# CONFIG_ARM_CIRRUS is not set
493 +# CONFIG_SUNLANCE is not set
494 +# CONFIG_SUNBMAC is not set
495 +# CONFIG_SUNQE is not set
496 +# CONFIG_SUNGEM is not set
497 +# CONFIG_NET_VENDOR_3COM is not set
498 +# CONFIG_LANCE is not set
499 +# CONFIG_NET_VENDOR_SMC is not set
500 +# CONFIG_NET_VENDOR_RACAL is not set
501 +# CONFIG_AT1700 is not set
502 +# CONFIG_DEPCA is not set
503 +# CONFIG_HP100 is not set
504 +# CONFIG_NET_ISA is not set
506 +# CONFIG_PCNET32 is not set
507 +# CONFIG_ADAPTEC_STARFIRE is not set
508 +# CONFIG_AC3200 is not set
509 +# CONFIG_APRICOT is not set
510 +# CONFIG_CS89x0 is not set
511 +# CONFIG_TULIP is not set
512 +# CONFIG_TC35815 is not set
513 +# CONFIG_DM9102 is not set
514 +# CONFIG_EEPRO100 is not set
515 +# CONFIG_LNE390 is not set
516 +# CONFIG_FEALNX is not set
517 +# CONFIG_NATSEMI is not set
518 +# CONFIG_NE2K_PCI is not set
519 +# CONFIG_NE3210 is not set
520 +# CONFIG_ES3210 is not set
521 +# CONFIG_8139CP is not set
522 +# CONFIG_8139TOO is not set
523 +# CONFIG_8139TOO_PIO is not set
524 +# CONFIG_8139TOO_TUNE_TWISTER is not set
525 +# CONFIG_8139TOO_8129 is not set
526 +# CONFIG_8139_NEW_RX_RESET is not set
527 +# CONFIG_SIS900 is not set
528 +# CONFIG_EPIC100 is not set
529 +# CONFIG_SUNDANCE is not set
530 +# CONFIG_VIA_RHINE is not set
531 +# CONFIG_VIA_RHINE_MMIO is not set
532 +# CONFIG_WINBOND_840 is not set
533 +# CONFIG_NET_POCKET is not set
536 +# Ethernet (1000 Mbit)
538 +# CONFIG_ACENIC is not set
539 +# CONFIG_DL2K is not set
540 +# CONFIG_MYRI_SBUS is not set
541 +# CONFIG_NS83820 is not set
542 +# CONFIG_HAMACHI is not set
543 +# CONFIG_YELLOWFIN is not set
544 +# CONFIG_SK98LIN is not set
545 +# CONFIG_TIGON3 is not set
546 +# CONFIG_FDDI is not set
547 +# CONFIG_HIPPI is not set
548 +# CONFIG_PLIP is not set
549 +# CONFIG_PPP is not set
550 +# CONFIG_SLIP is not set
553 +# Wireless LAN (non-hamradio)
556 +# CONFIG_STRIP is not set
557 +# CONFIG_WAVELAN is not set
558 +# CONFIG_ARLAN is not set
559 +# CONFIG_AIRONET4500 is not set
560 +# CONFIG_AIRONET4500_NONCS is not set
561 +# CONFIG_AIRONET4500_PROC is not set
563 +# CONFIG_HERMES is not set
564 +# CONFIG_PCMCIA_HERMES is not set
566 +CONFIG_NET_WIRELESS=y
569 +# Token Ring devices
571 +# CONFIG_TR is not set
572 +# CONFIG_NET_FC is not set
573 +# CONFIG_RCPCI is not set
574 +# CONFIG_SHAPER is not set
579 +# CONFIG_WAN is not set
582 +# PCMCIA network device support
585 +CONFIG_PCMCIA_3C589=m
586 +CONFIG_PCMCIA_3C574=m
587 +# CONFIG_PCMCIA_FMVJ18X is not set
588 +CONFIG_PCMCIA_PCNET=m
589 +# CONFIG_PCMCIA_AXNET is not set
590 +# CONFIG_PCMCIA_NMCLAN is not set
591 +CONFIG_PCMCIA_SMC91C92=m
592 +CONFIG_PCMCIA_XIRC2PS=m
593 +# CONFIG_ARCNET_COM20020_CS is not set
594 +# CONFIG_PCMCIA_IBMTR is not set
595 +CONFIG_NET_PCMCIA_RADIO=y
596 +# CONFIG_PCMCIA_RAYCS is not set
597 +# CONFIG_PCMCIA_NETWAVE is not set
598 +CONFIG_PCMCIA_WAVELAN=m
599 +# CONFIG_AIRONET4500_CS is not set
602 +# Amateur Radio support
604 +# CONFIG_HAMRADIO is not set
607 +# IrDA (infrared) support
611 +# CONFIG_IRNET is not set
613 +# CONFIG_IRDA_ULTRA is not set
614 +# CONFIG_IRDA_CACHE_LAST_LSAP is not set
615 +# CONFIG_IRDA_FAST_RR is not set
616 +# CONFIG_IRDA_DEBUG is not set
619 +# Infrared-port device drivers
623 +# CONFIG_DONGLE is not set
624 +# CONFIG_USB_IRDA is not set
625 +# CONFIG_NSC_FIR is not set
626 +# CONFIG_WINBOND_FIR is not set
627 +# CONFIG_TOSHIBA_FIR is not set
628 +# CONFIG_SMC_IRCC_FIR is not set
629 +# CONFIG_ALI_FIR is not set
630 +# CONFIG_VLSI_FIR is not set
634 +# ATA/ATAPI/MFM/RLL support
639 +# IDE, ATA and ATAPI Block devices
641 +CONFIG_BLK_DEV_IDE=m
642 +# CONFIG_BLK_DEV_HD_IDE is not set
643 +# CONFIG_BLK_DEV_HD is not set
644 +CONFIG_BLK_DEV_IDEDISK=m
645 +# CONFIG_IDEDISK_MULTI_MODE is not set
646 +# CONFIG_IDEDISK_STROKE is not set
647 +# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
648 +# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
649 +# CONFIG_BLK_DEV_IDEDISK_IBM is not set
650 +# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
651 +# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
652 +# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
653 +# CONFIG_BLK_DEV_IDEDISK_WD is not set
654 +# CONFIG_BLK_DEV_COMMERIAL is not set
655 +# CONFIG_BLK_DEV_TIVO is not set
656 +CONFIG_BLK_DEV_IDECS=m
657 +# CONFIG_BLK_DEV_IDECD is not set
658 +# CONFIG_BLK_DEV_IDETAPE is not set
659 +# CONFIG_BLK_DEV_IDEFLOPPY is not set
660 +# CONFIG_BLK_DEV_IDESCSI is not set
661 +# CONFIG_IDE_TASK_IOCTL is not set
662 +# CONFIG_BLK_DEV_CMD640 is not set
663 +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
664 +# CONFIG_BLK_DEV_ISAPNP is not set
665 +# CONFIG_IDE_CHIPSETS is not set
666 +# CONFIG_IDEDMA_AUTO is not set
667 +# CONFIG_DMA_NONPCI is not set
668 +# CONFIG_BLK_DEV_IDE_MODES is not set
669 +# CONFIG_BLK_DEV_ATARAID is not set
670 +# CONFIG_BLK_DEV_ATARAID_PDC is not set
671 +# CONFIG_BLK_DEV_ATARAID_HPT is not set
676 +# CONFIG_SCSI is not set
679 +# I2O device support
681 +# CONFIG_I2O is not set
682 +# CONFIG_I2O_BLOCK is not set
683 +# CONFIG_I2O_LAN is not set
684 +# CONFIG_I2O_SCSI is not set
685 +# CONFIG_I2O_PROC is not set
690 +# CONFIG_ISDN is not set
693 +# Input core support
696 +# CONFIG_INPUT_KEYBDEV is not set
697 +# CONFIG_INPUT_MOUSEDEV is not set
698 +# CONFIG_INPUT_JOYDEV is not set
699 +# CONFIG_INPUT_EVDEV is not set
707 +# CONFIG_SERIAL_EXTENDED is not set
708 +# CONFIG_SERIAL_NONSTANDARD is not set
713 +# CONFIG_SERIAL_ANAKIN is not set
714 +# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
715 +# CONFIG_SERIAL_AMBA is not set
716 +# CONFIG_SERIAL_AMBA_CONSOLE is not set
717 +# CONFIG_SERIAL_CLPS711X is not set
718 +# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
719 +# CONFIG_SERIAL_21285 is not set
720 +# CONFIG_SERIAL_21285_OLD is not set
721 +# CONFIG_SERIAL_21285_CONSOLE is not set
722 +# CONFIG_SERIAL_UART00 is not set
723 +# CONFIG_SERIAL_UART00_CONSOLE is not set
724 +CONFIG_SERIAL_SA1100=y
725 +CONFIG_SERIAL_SA1100_CONSOLE=y
726 +CONFIG_SA1100_DEFAULT_BAUDRATE=115200
727 +# CONFIG_SERIAL_OMAHA is not set
728 +# CONFIG_SERIAL_OMAHA_CONSOLE is not set
729 +# CONFIG_SERIAL_AT91US3 is not set
730 +# CONFIG_SERIAL_AT91US3_CONSOLE is not set
731 +# CONFIG_SERIAL_8250 is not set
732 +# CONFIG_SERIAL_8250_CONSOLE is not set
733 +# CONFIG_SERIAL_8250_EXTENDED is not set
734 +# CONFIG_SERIAL_8250_MANY_PORTS is not set
735 +# CONFIG_SERIAL_8250_SHARE_IRQ is not set
736 +# CONFIG_SERIAL_8250_DETECT_IRQ is not set
737 +# CONFIG_SERIAL_8250_MULTIPORT is not set
738 +# CONFIG_SERIAL_8250_HUB6 is not set
739 +CONFIG_SERIAL_CORE=y
740 +CONFIG_SERIAL_CORE_CONSOLE=y
741 +CONFIG_UNIX98_PTYS=y
742 +CONFIG_UNIX98_PTY_COUNT=32
747 +# CONFIG_I2C is not set
750 +# L3 serial bus support
752 +# CONFIG_L3 is not set
753 +# CONFIG_L3_ALGOBIT is not set
754 +# CONFIG_L3_BIT_SA1100_GPIO is not set
755 +# CONFIG_L3_SA1111 is not set
756 +# CONFIG_BIT_SA1100_GPIO is not set
761 +# CONFIG_BUSMOUSE is not set
762 +# CONFIG_MOUSE is not set
767 +# CONFIG_INPUT_GAMEPORT is not set
768 +# CONFIG_INPUT_NS558 is not set
769 +# CONFIG_INPUT_LIGHTNING is not set
770 +# CONFIG_INPUT_PCIGAME is not set
771 +# CONFIG_INPUT_CS461X is not set
772 +# CONFIG_INPUT_EMU10K1 is not set
773 +# CONFIG_INPUT_SERIO is not set
774 +# CONFIG_INPUT_SERPORT is not set
775 +# CONFIG_INPUT_ANALOG is not set
776 +# CONFIG_INPUT_A3D is not set
777 +# CONFIG_INPUT_ADI is not set
778 +# CONFIG_INPUT_COBRA is not set
779 +# CONFIG_INPUT_GF2K is not set
780 +# CONFIG_INPUT_GRIP is not set
781 +# CONFIG_INPUT_INTERACT is not set
782 +# CONFIG_INPUT_TMDC is not set
783 +# CONFIG_INPUT_SIDEWINDER is not set
784 +# CONFIG_INPUT_IFORCE_USB is not set
785 +# CONFIG_INPUT_IFORCE_232 is not set
786 +# CONFIG_INPUT_WARRIOR is not set
787 +# CONFIG_INPUT_MAGELLAN is not set
788 +# CONFIG_INPUT_SPACEORB is not set
789 +# CONFIG_INPUT_SPACEBALL is not set
790 +# CONFIG_INPUT_STINGER is not set
791 +# CONFIG_INPUT_DB9 is not set
792 +# CONFIG_INPUT_GAMECON is not set
793 +# CONFIG_INPUT_TURBOGRAFX is not set
794 +# CONFIG_QIC02_TAPE is not set
799 +# CONFIG_WATCHDOG is not set
800 +# CONFIG_NVRAM is not set
801 +# CONFIG_RTC is not set
803 +# CONFIG_DTLK is not set
804 +# CONFIG_R3964 is not set
805 +# CONFIG_APPLICOM is not set
808 +# Ftape, the floppy tape device driver
810 +# CONFIG_FTAPE is not set
811 +# CONFIG_AGP is not set
812 +# CONFIG_DRM is not set
815 +# PCMCIA character devices
817 +CONFIG_PCMCIA_SERIAL_CS=m
821 +# Multimedia devices
823 +# CONFIG_VIDEO_DEV is not set
828 +# CONFIG_QUOTA is not set
829 +# CONFIG_AUTOFS_FS is not set
830 +# CONFIG_AUTOFS4_FS is not set
831 +CONFIG_REISERFS_FS=m
832 +# CONFIG_REISERFS_CHECK is not set
833 +CONFIG_REISERFS_PROC_INFO=y
834 +# CONFIG_ADFS_FS is not set
835 +# CONFIG_ADFS_FS_RW is not set
836 +# CONFIG_AFFS_FS is not set
837 +# CONFIG_HFS_FS is not set
838 +# CONFIG_BFS_FS is not set
841 +# CONFIG_JBD_DEBUG is not set
846 +# CONFIG_EFS_FS is not set
848 +CONFIG_JFFS_FS_VERBOSE=0
849 +CONFIG_JFFS_PROC_FS=y
851 +CONFIG_JFFS2_FS_DEBUG=0
853 +# CONFIG_TMPFS is not set
855 +# CONFIG_ISO9660_FS is not set
856 +# CONFIG_JOLIET is not set
857 +# CONFIG_ZISOFS is not set
858 +# CONFIG_MINIX_FS is not set
859 +# CONFIG_VXFS_FS is not set
860 +# CONFIG_NTFS_FS is not set
861 +# CONFIG_NTFS_RW is not set
862 +# CONFIG_HPFS_FS is not set
865 +CONFIG_DEVFS_MOUNT=y
866 +CONFIG_DEVFS_DEBUG=y
867 +# CONFIG_DEVPTS_FS is not set
868 +# CONFIG_QNX4FS_FS is not set
869 +# CONFIG_QNX4FS_RW is not set
870 +# CONFIG_ROMFS_FS is not set
872 +# CONFIG_SYSV_FS is not set
873 +# CONFIG_UDF_FS is not set
874 +# CONFIG_UDF_RW is not set
875 +# CONFIG_UFS_FS is not set
876 +# CONFIG_UFS_FS_WRITE is not set
879 +# Network File Systems
881 +# CONFIG_CODA_FS is not set
882 +# CONFIG_INTERMEZZO_FS is not set
885 +# CONFIG_ROOT_NFS is not set
886 +# CONFIG_NFSD is not set
887 +# CONFIG_NFSD_V3 is not set
892 +# CONFIG_SMB_NLS_DEFAULT is not set
893 +# CONFIG_NCP_FS is not set
894 +# CONFIG_NCPFS_PACKET_SIGNING is not set
895 +# CONFIG_NCPFS_IOCTL_LOCKING is not set
896 +# CONFIG_NCPFS_STRONG is not set
897 +# CONFIG_NCPFS_NFS_NS is not set
898 +# CONFIG_NCPFS_OS2_NS is not set
899 +# CONFIG_NCPFS_SMALLDOS is not set
900 +# CONFIG_NCPFS_NLS is not set
901 +# CONFIG_NCPFS_EXTRAS is not set
902 +# CONFIG_ZISOFS_FS is not set
903 +CONFIG_ZLIB_FS_INFLATE=m
908 +# CONFIG_PARTITION_ADVANCED is not set
909 +CONFIG_MSDOS_PARTITION=y
914 +# Native Language Support
916 +CONFIG_NLS_DEFAULT="iso8859-1"
917 +CONFIG_NLS_CODEPAGE_437=y
918 +# CONFIG_NLS_CODEPAGE_737 is not set
919 +# CONFIG_NLS_CODEPAGE_775 is not set
920 +CONFIG_NLS_CODEPAGE_850=y
921 +# CONFIG_NLS_CODEPAGE_852 is not set
922 +# CONFIG_NLS_CODEPAGE_855 is not set
923 +# CONFIG_NLS_CODEPAGE_857 is not set
924 +# CONFIG_NLS_CODEPAGE_860 is not set
925 +# CONFIG_NLS_CODEPAGE_861 is not set
926 +# CONFIG_NLS_CODEPAGE_862 is not set
927 +# CONFIG_NLS_CODEPAGE_863 is not set
928 +# CONFIG_NLS_CODEPAGE_864 is not set
929 +# CONFIG_NLS_CODEPAGE_865 is not set
930 +# CONFIG_NLS_CODEPAGE_866 is not set
931 +# CONFIG_NLS_CODEPAGE_869 is not set
932 +# CONFIG_NLS_CODEPAGE_936 is not set
933 +# CONFIG_NLS_CODEPAGE_950 is not set
934 +# CONFIG_NLS_CODEPAGE_932 is not set
935 +# CONFIG_NLS_CODEPAGE_949 is not set
936 +# CONFIG_NLS_CODEPAGE_874 is not set
937 +# CONFIG_NLS_ISO8859_8 is not set
938 +# CONFIG_NLS_CODEPAGE_1250 is not set
939 +# CONFIG_NLS_CODEPAGE_1251 is not set
940 +CONFIG_NLS_ISO8859_1=y
941 +# CONFIG_NLS_ISO8859_2 is not set
942 +# CONFIG_NLS_ISO8859_3 is not set
943 +# CONFIG_NLS_ISO8859_4 is not set
944 +# CONFIG_NLS_ISO8859_5 is not set
945 +# CONFIG_NLS_ISO8859_6 is not set
946 +# CONFIG_NLS_ISO8859_7 is not set
947 +# CONFIG_NLS_ISO8859_9 is not set
948 +# CONFIG_NLS_ISO8859_13 is not set
949 +# CONFIG_NLS_ISO8859_14 is not set
950 +CONFIG_NLS_ISO8859_15=y
951 +# CONFIG_NLS_KOI8_R is not set
952 +# CONFIG_NLS_KOI8_U is not set
953 +# CONFIG_NLS_UTF8 is not set
959 +# CONFIG_VGA_CONSOLE is not set
962 +# Frame-buffer support
965 +CONFIG_DUMMY_CONSOLE=y
966 +# CONFIG_FB_ACORN is not set
967 +# CONFIG_FB_ANAKIN is not set
968 +# CONFIG_FB_CLPS711X is not set
969 +# CONFIG_FB_SA1100 is not set
970 +# CONFIG_FB_CYBER2000 is not set
972 +# CONFIG_FB_VIRTUAL is not set
973 +CONFIG_FBCON_ADVANCED=y
974 +# CONFIG_FBCON_MFB is not set
975 +# CONFIG_FBCON_CFB2 is not set
978 +CONFIG_FBCON_CFB16=y
979 +# CONFIG_FBCON_CFB24 is not set
980 +# CONFIG_FBCON_CFB32 is not set
981 +# CONFIG_FBCON_AFB is not set
982 +# CONFIG_FBCON_ILBM is not set
983 +# CONFIG_FBCON_IPLAN2P2 is not set
984 +# CONFIG_FBCON_IPLAN2P4 is not set
985 +# CONFIG_FBCON_IPLAN2P8 is not set
986 +# CONFIG_FBCON_MAC is not set
987 +# CONFIG_FBCON_VGA_PLANES is not set
988 +# CONFIG_FBCON_VGA is not set
989 +# CONFIG_FBCON_HGA is not set
990 +# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
991 +CONFIG_FBCON_FONTS=y
994 +# CONFIG_FONT_SUN8x16 is not set
995 +# CONFIG_FONT_SUN12x22 is not set
996 +# CONFIG_FONT_6x11 is not set
997 +# CONFIG_FONT_PEARL_8x8 is not set
998 +# CONFIG_FONT_ACORN_8x8 is not set
1004 +# CONFIG_SOUND_BT878 is not set
1005 +# CONFIG_SOUND_CMPCI is not set
1006 +# CONFIG_SOUND_EMU10K1 is not set
1007 +# CONFIG_MIDI_EMU10K1 is not set
1008 +# CONFIG_SOUND_FUSION is not set
1009 +# CONFIG_SOUND_CS4281 is not set
1010 +# CONFIG_SOUND_ES1370 is not set
1011 +# CONFIG_SOUND_ES1371 is not set
1012 +# CONFIG_SOUND_ESSSOLO1 is not set
1013 +# CONFIG_SOUND_MAESTRO is not set
1014 +# CONFIG_SOUND_MAESTRO3 is not set
1015 +# CONFIG_SOUND_ICH is not set
1016 +# CONFIG_SOUND_RME96XX is not set
1017 +# CONFIG_SOUND_SONICVIBES is not set
1018 +# CONFIG_SOUND_TRIDENT is not set
1019 +# CONFIG_SOUND_MSNDCLAS is not set
1020 +# CONFIG_SOUND_MSNDPIN is not set
1021 +# CONFIG_SOUND_VIA82CXXX is not set
1022 +# CONFIG_MIDI_VIA82CXXX is not set
1023 +CONFIG_SOUND_SA1100=y
1024 +# CONFIG_SOUND_UDA1341 is not set
1025 +# CONFIG_SOUND_ASSABET_UDA1341 is not set
1026 +# CONFIG_SOUND_H3600_UDA1341 is not set
1027 +# CONFIG_SOUND_PANGOLIN_UDA1341 is not set
1028 +# CONFIG_SOUND_SA1111_UDA1341 is not set
1029 +# CONFIG_SOUND_SA1111_AC97 is not set
1030 +# CONFIG_SOUND_SA1100SSP is not set
1031 +# CONFIG_SOUND_OSS is not set
1032 +# CONFIG_SOUND_VIDC is not set
1033 +# CONFIG_SOUND_WAVEARTIST is not set
1034 +# CONFIG_SOUND_TVMIXER is not set
1037 +# Multimedia Capabilities Port drivers
1040 +CONFIG_MCP_SA1100=y
1041 +CONFIG_MCP_UCB1200=y
1042 +CONFIG_MCP_UCB1200_AUDIO=y
1043 +CONFIG_MCP_UCB1200_TS=y
1049 +CONFIG_SWITCHES_SA1100=y
1050 +CONFIG_SWITCHES_UCB1X00=y
1055 +# CONFIG_USB is not set
1058 +# Bluetooth support
1060 +# CONFIG_BLUEZ is not set
1065 +CONFIG_FRAME_POINTER=y
1066 +CONFIG_DEBUG_USER=y
1067 +# CONFIG_DEBUG_INFO is not set
1068 +# CONFIG_NO_PGT_CACHE is not set
1069 +# CONFIG_DEBUG_KERNEL is not set
1070 +# CONFIG_DEBUG_SLAB is not set
1071 +# CONFIG_MAGIC_SYSRQ is not set
1072 +# CONFIG_DEBUG_SPINLOCK is not set
1073 +# CONFIG_DEBUG_WAITQ is not set
1074 +# CONFIG_DEBUG_BUGVERBOSE is not set
1075 +# CONFIG_DEBUG_ERRORS is not set
1076 +# CONFIG_DEBUG_LL is not set
1077 +# CONFIG_DEBUG_DC21285_PORT is not set
1078 +# CONFIG_DEBUG_CLPS711X_UART2 is not set
1079 --- linux-2.4.27/arch/arm/kernel/head-armv.S~2.4.27-vrs1-pxa1-jpm1
1080 +++ linux-2.4.27/arch/arm/kernel/head-armv.S
1082 .section ".text.init",#alloc,#execinstr
1083 .type stext, #function
1089 * NOTE! Any code which is placed here should be done for one of
1090 --- linux-2.4.27/arch/arm/kernel/irq.c~2.4.27-vrs1-pxa1-jpm1
1091 +++ linux-2.4.27/arch/arm/kernel/irq.c
1094 spin_lock_irqsave(&irq_controller_lock, flags);
1095 if (!desc->disable_depth++) {
1096 -#ifndef CONFIG_CPU_SA1100
1097 +// #ifndef CONFIG_CPU_SA1100
1102 spin_unlock_irqrestore(&irq_controller_lock, flags);
1105 +++ linux-2.4.27/arch/arm/mach-sa1100/apm.c
1108 + * bios-less APM driver for ARM Linux
1109 + * Jamey Hicks <jamey@crl.dec.com>
1110 + * adapted from the APM BIOS driver for Linux by Stephen Rothwell (sfr@linuxcare.com)
1112 + * APM 1.2 Reference:
1113 + * Intel Corporation, Microsoft Corporation. Advanced Power Management
1114 + * (APM) BIOS Interface Specification, Revision 1.2, February 1996.
1116 + * [This document is available from Microsoft at:
1117 + * http://www.microsoft.com/hwdev/busbios/amp_12.htm]
1120 +#include <linux/config.h>
1121 +#include <linux/module.h>
1123 +#include <linux/poll.h>
1124 +#include <linux/types.h>
1125 +#include <linux/stddef.h>
1126 +#include <linux/timer.h>
1127 +#include <linux/fcntl.h>
1128 +#include <linux/slab.h>
1129 +#include <linux/stat.h>
1130 +#include <linux/proc_fs.h>
1131 +#include <linux/miscdevice.h>
1132 +#include <linux/apm_bios.h>
1133 +#include <linux/init.h>
1134 +#include <linux/sched.h>
1135 +#include <linux/pm.h>
1136 +#include <linux/kernel.h>
1137 +#include <linux/smp_lock.h>
1139 +#include <asm/system.h>
1140 +#include <asm/hardware.h>
1142 +#include <asm/arch-sa1100/pm.h>
1145 +#ifdef CONFIG_IPAQ_HANDHELD
1146 +#include <asm/arch-sa1100/h3600_hal.h>
1149 +#ifdef CONFIG_SA1100_SIMPAD
1150 +#include <asm/arch-sa1100/simpad_pm.h>
1153 +#if defined(CONFIG_APM_DISPLAY_BLANK) && defined(CONFIG_VT)
1154 +extern int (*console_blank_hook)(int);
1157 +struct apm_bios_info apm_bios_info = {
1158 + /* this driver simulates APM version 1.2 */
1160 + flags: APM_32_BIT_SUPPORT
1164 + * The apm_bios device is one of the misc char devices.
1165 + * This is its minor number.
1167 +#define APM_MINOR_DEV 134
1170 + * See Documentation/Config.help for the configuration options.
1172 + * Various options can be changed at boot time as follows:
1173 + * (We allow underscores for compatibility with the modules code)
1174 + * apm=on/off enable/disable APM
1175 + * [no-]debug log some debugging messages
1176 + * [no-]power[-_]off power off on shutdown
1180 + * Need to poll the APM BIOS every second
1182 +#define APM_CHECK_TIMEOUT (HZ)
1185 + * Ignore suspend events for this amount of time after a resume
1187 +#define DEFAULT_BOUNCE_INTERVAL (3 * HZ)
1190 + * Maximum number of events stored
1192 +#define APM_MAX_EVENTS 20
1195 + * The per-file APM data
1199 + struct apm_user * next;
1201 + int suspend_wait: 1;
1202 + int suspend_result;
1203 + int suspends_pending;
1204 + int standbys_pending;
1205 + int suspends_read;
1206 + int standbys_read;
1209 + apm_event_t events[APM_MAX_EVENTS];
1213 + * The magic number in apm_user
1215 +#define APM_BIOS_MAGIC 0x4101
1220 +//static int suspends_pending;
1221 +//static int standbys_pending;
1222 +//static int ignore_normal_resume;
1224 +#ifdef CONFIG_APM_RTC_IS_GMT
1225 +# define clock_cmos_diff 0
1226 +# define got_clock_diff 1
1228 +//static long clock_cmos_diff;
1229 +//static int got_clock_diff;
1232 +static int apm_disabled;
1234 +static int power_off;
1236 +static int power_off = 1;
1238 +static int exit_kapmd;
1239 +static int kapmd_running;
1241 +static DECLARE_WAIT_QUEUE_HEAD(apm_waitqueue);
1242 +static DECLARE_WAIT_QUEUE_HEAD(apm_suspend_waitqueue);
1243 +static struct apm_user * user_list = NULL;
1245 +static char driver_version[] = "1.13"; /* no spaces */
1247 +typedef struct lookup_t {
1252 +static const lookup_t error_table[] = {
1253 +/* N/A { APM_SUCCESS, "Operation succeeded" }, */
1254 + { APM_DISABLED, "Power management disabled" },
1255 + { APM_CONNECTED, "Real mode interface already connected" },
1256 + { APM_NOT_CONNECTED, "Interface not connected" },
1257 + { APM_16_CONNECTED, "16 bit interface already connected" },
1258 +/* N/A { APM_16_UNSUPPORTED, "16 bit interface not supported" }, */
1259 + { APM_32_CONNECTED, "32 bit interface already connected" },
1260 + { APM_32_UNSUPPORTED, "32 bit interface not supported" },
1261 + { APM_BAD_DEVICE, "Unrecognized device ID" },
1262 + { APM_BAD_PARAM, "Parameter out of range" },
1263 + { APM_NOT_ENGAGED, "Interface not engaged" },
1264 + { APM_BAD_FUNCTION, "Function not supported" },
1265 + { APM_RESUME_DISABLED, "Resume timer disabled" },
1266 + { APM_BAD_STATE, "Unable to enter requested state" },
1267 +/* N/A { APM_NO_EVENTS, "No events pending" }, */
1268 + { APM_NO_ERROR, "BIOS did not set a return code" },
1269 + { APM_NOT_PRESENT, "No APM present" }
1271 +#define ERROR_COUNT (sizeof(error_table)/sizeof(lookup_t))
1273 +static int apm_get_power_status(u_char *ac_line_status,
1274 + u_char *battery_status,
1275 + u_char *battery_flag,
1276 + u_char *battery_percentage,
1277 + u_short *battery_life)
1279 +#ifdef CONFIG_IPAQ_HANDHELD
1280 + h3600_apm_get_power_status(ac_line_status, battery_status, battery_flag, battery_percentage, battery_life);
1282 +#ifdef CONFIG_SA1100_SIMPAD
1283 + simpad_apm_get_power_status(ac_line_status, battery_status, battery_flag, battery_percentage, battery_life);
1285 + return APM_SUCCESS;
1288 +static int queue_empty(struct apm_user *as)
1290 + return as->event_head == as->event_tail;
1293 +static apm_event_t get_queued_event(struct apm_user *as)
1295 + as->event_tail = (as->event_tail + 1) % APM_MAX_EVENTS;
1296 + return as->events[as->event_tail];
1299 +static int check_apm_user(struct apm_user *as, const char *func)
1301 + if ((as == NULL) || (as->magic != APM_BIOS_MAGIC)) {
1302 + printk(KERN_ERR "apm: %s passed bad filp\n", func);
1308 +static ssize_t do_read(struct file *fp, char *buf, size_t count, loff_t *ppos)
1310 + struct apm_user * as;
1312 + apm_event_t event;
1313 + DECLARE_WAITQUEUE(wait, current);
1315 + as = fp->private_data;
1316 + if (check_apm_user(as, "read"))
1318 + if (count < sizeof(apm_event_t))
1320 + if (queue_empty(as)) {
1321 + if (fp->f_flags & O_NONBLOCK)
1323 + add_wait_queue(&apm_waitqueue, &wait);
1324 + printk("do_read: waiting\n");
1326 + set_current_state(TASK_INTERRUPTIBLE);
1327 + if (queue_empty(as) && !signal_pending(current)) {
1331 + set_current_state(TASK_RUNNING);
1332 + remove_wait_queue(&apm_waitqueue, &wait);
1335 + while ((i >= sizeof(event)) && !queue_empty(as)) {
1336 + event = get_queued_event(as);
1337 + printk(" do_read: event=%d\n", event);
1338 + if (copy_to_user(buf, &event, sizeof(event))) {
1344 + case APM_SYS_SUSPEND:
1345 + case APM_USER_SUSPEND:
1346 + as->suspends_read++;
1349 + case APM_SYS_STANDBY:
1350 + case APM_USER_STANDBY:
1351 + as->standbys_read++;
1354 + buf += sizeof(event);
1355 + i -= sizeof(event);
1359 + if (signal_pending(current))
1360 + return -ERESTARTSYS;
1364 +static unsigned int do_poll(struct file *fp, poll_table * wait)
1366 + struct apm_user * as;
1368 + as = fp->private_data;
1369 + if (check_apm_user(as, "poll"))
1371 + poll_wait(fp, &apm_waitqueue, wait);
1372 + if (!queue_empty(as))
1373 + return POLLIN | POLLRDNORM;
1377 +static int do_ioctl(struct inode * inode, struct file *filp,
1378 + u_int cmd, u_long arg)
1380 + struct apm_user * as;
1382 + as = filp->private_data;
1383 + if (check_apm_user(as, "ioctl"))
1388 + case APM_IOC_SUSPEND:
1390 + pm_suggest_suspend();
1399 +static int do_release(struct inode * inode, struct file * filp)
1401 + struct apm_user * as;
1403 + as = filp->private_data;
1404 + if (check_apm_user(as, "release"))
1406 + filp->private_data = NULL;
1413 +static int do_open(struct inode * inode, struct file * filp)
1415 + struct apm_user * as;
1417 + as = (struct apm_user *)kmalloc(sizeof(*as), GFP_KERNEL);
1419 + printk(KERN_ERR "apm: cannot allocate struct of size %d bytes\n",
1423 + as->magic = APM_BIOS_MAGIC;
1424 + as->event_tail = as->event_head = 0;
1425 + as->suspends_pending = as->standbys_pending = 0;
1426 + as->suspends_read = as->standbys_read = 0;
1428 + * XXX - this is a tiny bit broken, when we consider BSD
1429 + * process accounting. If the device is opened by root, we
1430 + * instantly flag that we used superuser privs. Who knows,
1431 + * we might close the device immediately without doing a
1432 + * privileged operation -- cevans
1434 + as->suser = capable(CAP_SYS_ADMIN);
1435 + as->next = user_list;
1437 + filp->private_data = as;
1441 +static int apm_get_info(char *buf, char **start, off_t fpos, int length)
1444 + unsigned short dx;
1445 + unsigned short error;
1446 + unsigned char ac_line_status = 0xff;
1447 + unsigned char battery_status = 0xff;
1448 + unsigned char battery_flag = 0xff;
1449 + unsigned char percentage = 0xff;
1450 + int time_units = -1;
1451 + char *units = "?";
1455 + if ((smp_num_cpus == 1) &&
1456 + !(error = apm_get_power_status(&ac_line_status,
1457 + &battery_status, &battery_flag, &percentage, &dx))) {
1458 + if (apm_bios_info.version > 0x100) {
1459 + if (dx != 0xffff) {
1460 + units = (dx & 0x8000) ? "min" : "sec";
1461 + time_units = dx & 0x7fff;
1465 + /* Arguments, with symbols from linux/apm_bios.h. Information is
1466 + from the Get Power Status (0x0a) call unless otherwise noted.
1468 + 0) Linux driver version (this will change if format changes)
1469 + 1) APM BIOS Version. Usually 1.0, 1.1 or 1.2.
1470 + 2) APM flags from APM Installation Check (0x00):
1471 + bit 0: APM_16_BIT_SUPPORT
1472 + bit 1: APM_32_BIT_SUPPORT
1473 + bit 2: APM_IDLE_SLOWS_CLOCK
1474 + bit 3: APM_BIOS_DISABLED
1475 + bit 4: APM_BIOS_DISENGAGED
1479 + 0x02: On backup power (BIOS >= 1.1 only)
1486 + 0x04: Selected battery not present (BIOS >= 1.2 only)
1493 + bit 7: No system battery
1495 + 6) Remaining battery life (percentage of charge):
1498 + 7) Remaining battery life (time units):
1499 + Number of remaining minutes or seconds
1501 + 8) min = minutes; sec = seconds */
1503 + p += sprintf(p, "%s %d.%d 0x%02x 0x%02x 0x%02x 0x%02x %d%% %d %s\n",
1505 + (apm_bios_info.version >> 8) & 0xff,
1506 + apm_bios_info.version & 0xff,
1507 + apm_bios_info.flags,
1519 +static int __init apm_setup(char *str)
1523 + while ((str != NULL) && (*str != '\0')) {
1524 + if (strncmp(str, "off", 3) == 0)
1526 + if (strncmp(str, "on", 2) == 0)
1528 + invert = (strncmp(str, "no-", 3) == 0);
1531 + if (strncmp(str, "debug", 5) == 0)
1533 + if ((strncmp(str, "power-off", 9) == 0) ||
1534 + (strncmp(str, "power_off", 9) == 0))
1535 + power_off = !invert;
1536 + str = strchr(str, ',');
1538 + str += strspn(str, ", \t");
1543 +__setup("apm=", apm_setup);
1546 +static struct file_operations apm_bios_fops = {
1547 + owner: THIS_MODULE,
1552 + release: do_release,
1555 +static struct miscdevice apm_device = {
1561 +#define APM_INIT_ERROR_RETURN return -1
1564 + * Just start the APM thread. We do NOT want to do APM BIOS
1565 + * calls from anything but the APM thread, if for no other reason
1566 + * than the fact that we don't trust the APM BIOS. This way,
1567 + * most common APM BIOS problems that lead to protection errors
1568 + * etc will have at least some level of being contained...
1570 + * In short, if something bad happens, at least we have a choice
1571 + * of just killing the apm thread..
1573 +static int __init apm_init(void)
1575 + if (apm_bios_info.version == 0) {
1576 + printk(KERN_INFO "apm: BIOS not found.\n");
1577 + APM_INIT_ERROR_RETURN;
1580 + "apm: BIOS version %d.%d Flags 0x%02x (Driver version %s)\n",
1581 + ((apm_bios_info.version >> 8) & 0xff),
1582 + (apm_bios_info.version & 0xff),
1583 + apm_bios_info.flags,
1586 + if (apm_disabled) {
1587 + printk(KERN_NOTICE "apm: disabled on user request.\n");
1588 + APM_INIT_ERROR_RETURN;
1591 + if (PM_IS_ACTIVE()) {
1592 + printk(KERN_NOTICE "apm: overridden by ACPI.\n");
1593 + APM_INIT_ERROR_RETURN;
1597 + create_proc_info_entry("apm", 0, NULL, apm_get_info);
1599 + misc_register(&apm_device);
1604 +static void __exit apm_exit(void)
1606 + misc_deregister(&apm_device);
1607 + remove_proc_entry("apm", NULL);
1609 + pm_power_off = NULL;
1611 + while (kapmd_running)
1616 +module_init(apm_init);
1617 +module_exit(apm_exit);
1619 +MODULE_AUTHOR("Jamey Hicks, pulling bits from original by Stephen Rothwell");
1620 +MODULE_DESCRIPTION("A minimal emulation of APM");
1621 +MODULE_PARM(debug, "i");
1622 +MODULE_PARM_DESC(debug, "Enable debug mode");
1623 +MODULE_PARM(power_off, "i");
1624 +MODULE_PARM_DESC(power_off, "Enable power off");
1627 --- linux-2.4.27/arch/arm/mach-sa1100/leds.c~2.4.27-vrs1-pxa1-jpm1
1628 +++ linux-2.4.27/arch/arm/mach-sa1100/leds.c
1630 leds_event = pfs168_leds_event;
1631 if (machine_is_pt_system3())
1632 leds_event = system3_leds_event;
1633 + if (machine_is_simpad())
1634 + leds_event = simpad_leds_event;
1636 leds_event(led_start);
1638 --- linux-2.4.27/arch/arm/mach-sa1100/leds.h~2.4.27-vrs1-pxa1-jpm1
1639 +++ linux-2.4.27/arch/arm/mach-sa1100/leds.h
1641 extern void hackkit_leds_event(led_event_t evt);
1642 extern void lart_leds_event(led_event_t evt);
1643 extern void pfs168_leds_event(led_event_t evt);
1644 +extern void simpad_leds_event(led_event_t evt);
1645 extern void system3_leds_event(led_event_t evt);
1647 --- linux-2.4.27/arch/arm/mach-sa1100/pm.c~2.4.27-vrs1-pxa1-jpm1
1648 +++ linux-2.4.27/arch/arm/mach-sa1100/pm.c
1650 SLEEP_SAVE_PPDR, SLEEP_SAVE_PPSR, SLEEP_SAVE_PPAR, SLEEP_SAVE_PSDR,
1654 SLEEP_SAVE_Ser1SDCR0,
1663 /* ... maybe a global variable initialized by arch code to set this? */
1672 /* restore current time */
1673 xtime.tv_sec = RCNR + delta;
1675 --- linux-2.4.27/arch/arm/mach-sa1100/simpad.c~2.4.27-vrs1-pxa1-jpm1
1676 +++ linux-2.4.27/arch/arm/mach-sa1100/simpad.c
1678 #include <linux/tty.h>
1679 #include <linux/proc_fs.h>
1680 #include <linux/string.h>
1681 +#include <linux/pm.h>
1683 #include <asm/hardware.h>
1684 #include <asm/setup.h>
1689 +void set_cs3(long value)
1691 + *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow = value;
1694 void set_cs3_bit(int value)
1696 cs3_shadow |= value;
1698 *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow;
1701 +EXPORT_SYMBOL(set_cs3_bit);
1702 +EXPORT_SYMBOL(clear_cs3_bit);
1704 +static void simpad_power_off(void)
1707 + set_cs3(0x800); /* only SD_MEDIAQ */
1709 + /* disable internal oscillator, float CS lines */
1710 + PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
1711 + /* enable wake-up on GPIO0 (Assabet...) */
1712 + PWER = GFER = GRER = 1;
1714 + * set scratchpad to zero, just in case it is used as a
1715 + * restart address by the bootloader.
1719 + /* enter sleep mode */
1724 +static int __init simpad_init(void)
1726 + pm_power_off = simpad_power_off;
1730 +__initcall(simpad_init);
1733 fixup_simpad(struct machine_desc *desc, struct param_struct *params,
1734 char **cmdline, struct meminfo *mi)
1736 -#ifdef CONFIG_SA1100_SIMPAD_DRAM_64MB /* DRAM */
1737 - SET_BANK( 0, 0xc0000000, 64*1024*1024 );
1739 +#ifdef CONFIG_SA1100_SIMPAD_SINUSPAD
1740 SET_BANK( 0, 0xc0000000, 32*1024*1024 );
1742 + SET_BANK( 0, 0xc0000000, 64*1024*1024 );
1745 - ROOT_DEV = MKDEV(RAMDISK_MAJOR,0);
1747 setup_ramdisk( 1, 0, 0, 8192 );
1748 setup_initrd( __phys_to_virt(0xc0800000), 4*1024*1024 );
1752 static struct map_desc simpad_io_desc[] __initdata = {
1753 - /* virtual physical length domain r w c b */
1754 - { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 },
1755 - { 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* MQ200 */
1756 - { 0xf1000000, 0x18000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Paules CS3, write only */
1757 + /* virtual physical length domain r w c b */
1758 + { 0xe8000000, 0x00000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 },
1759 + { 0xe9000000, 0x08000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 },
1760 + { 0xf1000000, 0x18000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* CS3, write only */
1761 + { 0xf2000000, 0x40000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* CS4, tda8007 */
1762 + { 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* MQ200 */
1767 static void simpad_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
1769 if (port->mapbase == (u_int)&Ser1UTCR0) {
1770 @@ -81,20 +118,32 @@
1772 static void __init simpad_map_io(void)
1775 - iotable_init(simpad_io_desc);
1777 + iotable_init(simpad_io_desc);
1779 - PSPR = 0xc0008000;
1780 - GPDR &= ~GPIO_GPIO0;
1781 - cs3_shadow = (EN1 | EN0 | LED2_ON | DISPLAY_ON | RS232_ON |
1782 - ENABLE_5V | RESET_SIMCARD);
1783 - *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow;
1784 + set_cs3_bit (EN1 | EN0 | LED2_ON | DISPLAY_ON | RS232_ON |
1785 + ENABLE_5V | nRESET_SIMCARD);
1787 - //It is only possible to register 3 UART in serial_sa1100.c
1788 - sa1100_register_uart(0, 3);
1789 - sa1100_register_uart(1, 1);
1790 + //It is only possible to register 3 UART in serial_sa1100.c
1791 + sa1100_register_uart(0, 3);
1792 + sa1100_register_uart(1, 1);
1794 - set_GPIO_IRQ_edge(GPIO_UCB1300_IRQ, GPIO_RISING_EDGE);
1795 + GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD);
1796 + GPDR |= GPIO_UART_TXD;
1797 + GPDR &= ~GPIO_UART_RXD;
1800 + set_GPIO_IRQ_edge(GPIO_UCB1300_IRQ, GPIO_RISING_EDGE);
1801 + set_GPIO_IRQ_edge(GPIO_POWER_BUTTON, GPIO_FALLING_EDGE);
1804 + * Set up registers for sleep mode.
1807 + PWER = PWER_GPIO0;
1813 #ifdef CONFIG_PROC_FS
1814 @@ -140,7 +189,17 @@
1820 +static int proc_cs3_write(struct file * file, const char * buffer,
1821 + size_t count, loff_t *ppos)
1823 + unsigned long newRegValue;
1826 + newRegValue = simple_strtoul(buffer,&endp,0);
1827 + set_cs3( newRegValue );
1828 + return (count+endp-buffer);
1831 static struct proc_dir_entry *proc_cs3;
1833 @@ -148,7 +207,10 @@
1835 proc_cs3 = create_proc_entry("cs3", 0, 0);
1838 proc_cs3->read_proc = proc_cs3_read;
1839 + proc_cs3->write_proc = (void*)proc_cs3_write;
1845 MACHINE_START(SIMPAD, "Simpad")
1846 MAINTAINER("Juergen Messerer")
1847 BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000)
1848 + BOOT_PARAMS(0xc0000100)
1850 MAPIO(simpad_map_io)
1851 INITIRQ(sa1100_init_irq)
1853 +++ linux-2.4.27/arch/arm/mach-sa1100/simpad_pm.c
1856 +* Powermanagement layer for SIMPad.
1858 +* Copyright 2003 Peter Pregler
1859 +* Copyright 2000,2001 Compaq Computer Corporation.
1861 +* Use consistent with the GNU GPL is permitted,
1862 +* provided that this copyright notice is
1863 +* preserved in its entirety in all copies and derived works.
1865 +* COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
1866 +* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
1867 +* FITNESS FOR ANY PARTICULAR PURPOSE.
1869 +* Author: Peter Pregler (based on work for ipaq by Andrew Christian)
1873 +#include <linux/module.h>
1874 +#include <linux/version.h>
1876 +#include <linux/init.h>
1877 +#include <linux/fs.h>
1878 +#include <linux/delay.h>
1879 +#include <linux/poll.h>
1880 +#include <asm/uaccess.h> /* get_user,copy_to_user */
1881 +#include <linux/string.h>
1882 +#include <linux/interrupt.h>
1883 +#include <linux/sysctl.h>
1884 +#include <linux/console.h>
1885 +#include <linux/devfs_fs_kernel.h>
1887 +#include <linux/tqueue.h>
1888 +#include <linux/sched.h>
1889 +#include <linux/pm.h>
1890 +#include <linux/proc_fs.h>
1891 +#include <linux/apm_bios.h>
1892 +#include <linux/kmod.h>
1894 +#include <asm/hardware.h>
1895 +#include <asm/arch-sa1100/simpad_pm.h>
1897 +MODULE_AUTHOR("Peter Pregler");
1898 +MODULE_DESCRIPTION("Power manamgement abstraction layer for the SIMpad");
1900 +/****************************************************************************/
1901 +/* Functions exported for use by the kernel and kernel modules */
1902 +/****************************************************************************/
1904 +int simpad_apm_get_power_status(u_char *ac_line_status,
1905 + u_char *battery_status,
1906 + u_char *battery_flag,
1907 + u_char *battery_percentage,
1908 + u_short *battery_life)
1910 + struct simpad_battery bstat;
1911 + unsigned char ac = APM_AC_UNKNOWN;
1912 + unsigned char level = APM_BATTERY_STATUS_UNKNOWN;
1913 + int status, result;
1915 + result = simpad_get_battery(&bstat);
1917 + printk("%s: unable to access battery information: result=%d\n", __FUNCTION__, result);
1921 + switch (bstat.ac_status) {
1922 + case SIMPAD_AC_STATUS_AC_OFFLINE:
1923 + ac = APM_AC_OFFLINE;
1925 + case SIMPAD_AC_STATUS_AC_ONLINE:
1926 + ac = APM_AC_ONLINE;
1928 + case SIMPAD_AC_STATUS_AC_BACKUP:
1929 + ac = APM_AC_BACKUP;
1933 + if (ac_line_status != NULL)
1934 + *ac_line_status = ac;
1936 + status = bstat.status;
1937 + if (status & (SIMPAD_BATT_STATUS_CHARGING | SIMPAD_BATT_STATUS_CHARGE_MAIN))
1938 + level = APM_BATTERY_STATUS_CHARGING;
1939 + else if (status & (SIMPAD_BATT_STATUS_HIGH | SIMPAD_BATT_STATUS_FULL))
1940 + level = APM_BATTERY_STATUS_HIGH;
1941 + else if (status & SIMPAD_BATT_STATUS_LOW)
1942 + level = APM_BATTERY_STATUS_LOW;
1943 + else if (status & SIMPAD_BATT_STATUS_CRITICAL)
1944 + level = APM_BATTERY_STATUS_CRITICAL;
1946 + if (battery_status != NULL)
1947 + *battery_status = level;
1949 + if (battery_percentage != NULL)
1950 + *battery_percentage = bstat.percentage;
1952 + /* we have a dumb battery - so we know nothing */
1953 + if (battery_life != NULL) {
1954 + *battery_life = APM_BATTERY_LIFE_UNKNOWN;
1958 + printk("apm_get_power: ac: %02x / bs: %02x / bf: %02x / perc: %02x / life: %d\n",
1959 + *ac_line_status, *battery_status, *battery_flag,
1960 + *battery_percentage, *battery_life );
1965 +EXPORT_SYMBOL(simpad_apm_get_power_status);
1968 +/***********************************************************************************/
1969 +/* Initialization */
1970 +/***********************************************************************************/
1972 +#ifdef CONFIG_FB_MQ200
1973 +extern void (*mq200_blank_helper)(int blank);
1976 +int __init simpad_hal_init_module(void)
1979 + printk(KERN_INFO "SIMpad Registering HAL abstraction layer\n");
1981 + /* Request the appropriate underlying module to provide services */
1983 +#ifdef CONFIG_FB_SA1100
1984 + sa1100fb_blank_helper = simpad_hal_backlight_helper;
1990 +void simpad_hal_cleanup_module(void)
1993 + printk(KERN_INFO "SIMpad shutting down HAL abstraction layer\n");
1995 +#ifdef CONFIG_FB_SA1100
1996 + sa1100fb_blank_helper = NULL;
2000 +module_init(simpad_hal_init_module);
2001 +module_exit(simpad_hal_cleanup_module);
2002 --- linux-2.4.27/drivers/char/Config.in~2.4.27-vrs1-pxa1-jpm1
2003 +++ linux-2.4.27/drivers/char/Config.in
2005 tristate ' MT6N TTL I/O suport' CONFIG_TRIZEPS2_TTLIO
2008 +if [ "$CONFIG_SA1100_SIMPAD" = "y" ]; then
2009 + tristate 'Smartcardreader(TDA8007) support' CONFIG_TDA8007
2012 --- linux-2.4.27/drivers/char/Makefile~2.4.27-vrs1-pxa1-jpm1
2013 +++ linux-2.4.27/drivers/char/Makefile
2015 obj-y += ipmi/ipmi.o
2018 +obj-$(CONFIG_TDA8007) += tda8007.o
2020 include $(TOPDIR)/Rules.make
2024 +++ linux-2.4.27/drivers/char/tda8007.c
2027 + * linux/drivers/char/tda8007.c
2029 + * Copyright (C) 2001 juergen.messerer@freesurf.ch, All Rights Reserved.
2031 + * This program is free software; you can redistribute it and/or modify
2032 + * it under the terms of the GNU General Public License as published by
2033 + * the Free Software Foundation; either version 2 of the License.
2035 + * The TDA8007B driver provides basic services for handling IO,
2036 + * interrupts, and accessing registers.
2039 +#include <linux/delay.h>
2040 +#include <linux/module.h>
2041 +#include <linux/kernel.h>
2042 +#include <linux/slab.h>
2043 +#include <linux/init.h>
2044 +#include <linux/errno.h>
2045 +#include <linux/interrupt.h>
2046 +#include <linux/proc_fs.h>
2048 +#include <asm/dma.h>
2049 +#include <asm/hardware.h>
2050 +#include <asm/irq.h>
2051 +#include <asm/arch/simpad.h>
2052 +#include <asm/uaccess.h>
2054 +#include "tda8007b.h"
2056 +#define TDA8007_DIRNAME "driver/tda8007"
2057 +#define REG_DIRNAME "registers"
2059 +extern void clear_cs3_bit(int value);
2061 +static struct proc_dir_entry *regdir;
2062 +static struct proc_dir_entry *tda8007dir;
2064 +static ssize_t proc_tda8007_read(struct file * file, char * buf,
2065 + size_t nbytes, loff_t *ppos);
2066 +static ssize_t proc_tda8007_write(struct file * file, const char * buffer,
2067 + size_t count, loff_t *ppos);
2069 +static struct file_operations proc_reg_operations = {
2070 + read: proc_tda8007_read,
2071 + write: proc_tda8007_write
2074 +static int __init tda8007_init();
2076 +/* ------------------------------------------------------------------------- */
2077 +void tda8007_reg_write(int reg, int val)
2079 + printk("Address:%x \n", CS4_BASE+reg);
2080 + printk("Value:%x \n", val);
2081 + TDA_REG_WRITE(reg,val);
2083 +/* ------------------------------------------------------------------------- */
2084 +int tda8007_reg_read(int reg)
2086 + printk("Address:%x \n", CS4_BASE+reg);
2087 + return(TDA_REG_READ(reg)&0xff);
2089 +/* ------------------------------------------------------------------------- */
2091 +/* ------------------------------------------------------------------------- */
2092 +static void tda8007_irq(int irqnr, void *devid, struct pt_regs *regs)
2094 + printk("\n****tda8007_irq****\n");
2096 +/* ------------------------------------------------------------------------- */
2097 +static int tda_card_present( uint cardport )
2101 + switch( cardport )
2104 + if( tda8007_reg_read(TDA_MSR) & TDA_MSR_PR1 )
2108 + if( tda8007_reg_read(TDA_MSR) & TDA_MSR_PR2 )
2118 +/* ------------------------------------------------------------------------- */
2119 +void tda_inituart(void)
2121 + int hsr_reg, fcr_reg;
2123 + printk("Init TDA8007 Uart\n");
2124 + hsr_reg = tda8007_reg_read(TDA_HSR);
2125 + tda8007_reg_write(TDA_PCR, 0x00);
2127 + tda8007_reg_write(TDA_CSR, 0x00);
2128 + tda8007_reg_write(TDA_CSR, TDA_CSR_SC1); /* select Card 1 */
2130 + tda8007_reg_write(TDA_CSR, TDA_CSR_nRIU|TDA_CSR_SC1);
2131 + tda8007_reg_write(TDA_PCR, 0x00);
2133 + tda8007_reg_write(TDA_PDR, TDA_PDR_VAL); /* Rat v. jandu 8.9.2000 */
2134 + tda8007_reg_write(TDA_UCR2, TDA_UCR2_DIV);
2136 + tda8007_reg_write(TDA_CCR, 0x40|TDA_CCR_AC1); /*1=XTAL/2 2=XTAL/4 3=XTAL/8 */
2137 + tda8007_reg_write(TDA_GTR, TDA_GTR_GT1);
2139 + fcr_reg = tda8007_reg_read(TDA_FCR);
2140 + tda8007_reg_write(TDA_FCR, (fcr_reg & 0xf0) | TDA_FCR_FL1);
2142 + tda8007_reg_write(TDA_FCR, TDA_FCR_FL2|TDA_FCR_FL1|TDA_FCR_FL0);
2143 + tda8007_reg_write(TDA_UCR1, TDA_UCR_SS|TDA_UCR_CONV);
2144 + tda8007_reg_write(TDA_PCR, 0x00);
2146 + while( tda8007_reg_read(TDA_USR) & TDA_USR_TBE_RBF )
2148 + hsr_reg = tda8007_reg_read(TDA_URR);
2152 +/* ------------------------------------------------------------------------- */
2153 +void start_tda8007_sync(int volt)
2156 + if( tda_card_present( CARD_PORT1 ) )
2158 + printk("Card Present ");
2159 + tda8007_reg_write(TDA_TOR1, TDA_TOR1_TOL2|TDA_TOR1_TOL3);
2160 + tda8007_reg_write(TDA_TOR2, TDA_TOR2_TOL16|TDA_TOR2_TOL15|
2161 + TDA_TOR2_TOL13|TDA_TOR2_TOL12|
2163 + tda8007_reg_write(TDA_TOR3, 0x00);
2164 + tda8007_reg_write(TDA_TOC, TDA_TOC_MODE2);
2166 + tda8007_reg_write(TDA_UCR2, TDA_UCR_DISAUX|TDA_UCR2_DIV); // DIS_AUX ASYNC MODE
2169 + volt = TDA_PCR_3V_5V;
2173 + tda8007_reg_write(TDA_PCR, 0x00|volt); // Set /Reset,3V
2175 + tda8007_reg_write(TDA_PCR, TDA_PCR_START|volt); // /Reset,3V,Start
2177 + tda8007_reg_write(TDA_PCR, TDA_PCR_RSTIN|TDA_PCR_START|volt); // Set Reset High
2179 + while( 1 )// !serstat()
2181 + if( ((msr[i]=tda8007_reg_read(TDA_MSR)) & TDA_MSR_FE) == 0 )
2183 + hsr[i]=tda8007_reg_read(TDA_HSR);
2184 + usr[i]=tda8007_reg_read(TDA_USR);
2185 + csr[i]=tda8007_reg_read(TDA_CSR);
2186 + urr[i]=tda8007_reg_read(TDA_URR);
2192 + tda8007_reg_write(TDA_UCR1,
2193 + tda8007_reg_read(TDA_UCR1) & ~TDA_UCR_SS);
2194 + /* Set Autoconv high */
2195 + tda8007_reg_write(TDA_UCR2,
2196 + tda8007_reg_read(TDA_UCR2) | TDA_UCR_nAUTOCONV);
2199 + if( i >= BUFFSIZE )
2201 + printk("Buffer Overflow");
2204 + // tda8007_reg_write(TDA_FCR, TDA_FCR_PEC0|TDA_FCR_FL0);
2206 + hsr[i]=tda8007_reg_read(TDA_HSR);
2207 + msr[i]=tda8007_reg_read(TDA_MSR);
2208 + csr[i]=tda8007_reg_read(TDA_CSR);
2209 + urr[i]=tda8007_reg_read(TDA_URR);
2213 + printk("No Characters received\n");
2215 + for(j=0;j<i-1; j++)
2216 + printk("Buffer[%3d]=USR(0x%02x) HSR(0x%02x) MSR(0x%02x) CSR(0x%02x) URR(0x%02x=%c)\n",
2217 + j,usr[j],hsr[j],msr[j],csr[j],urr[j],pascii(urr[j]));
2219 + printk("Now USR(0x%02x) HSR(0x%02x) MSR(0x%02x) CSR(0x%02x) URR(0x%02x=%c)\n",
2220 + usr[j],hsr[j],msr[j],csr[j],urr[j],pascii(urr[j]));
2222 + tda8007_reg_write(TDA_PCR, TDA_PCR_RSTIN|volt); // remove start
2224 + tda8007_reg_write(TDA_PCR, 0x00|volt); // remove Reset
2229 + tda8007_reg_write(TDA_PCR, TDA_PCR_3V_5V);
2233 +/* -------------------------------------------------------------------------*/
2234 +int test_tda8007(void)
2236 + int c, i,j, reg,end=0;
2238 + printk("\nTDA8007 TEST:");
2240 + for( i=0; i < 0x10; i++ )
2241 + printk("\nTDA8007 Reg %2d = 0x%02x ", i, tda8007_reg_read(i)&0xff);
2243 + for( i=0 ;i < 0x10; i++ )
2245 + tdaregs[i]=tda8007_reg_read(i) & 0xff;
2249 + printk("\nTDA8007 IRQ=%s Command:",
2250 + (GPLR&(1<<10) ? "HIGH":"LOW"));
2260 + printk("\nReg?:");
2261 + //reg=gethex(serin,serout);
2262 + printk("\nVal?:");
2263 + //i=gethex(serin,serout);
2264 + tda8007_reg_write(reg,i);
2265 + j=tda8007_reg_read(reg);
2266 + printk("Reg 0x%02x (0x%02x) now 0x%02x\n", reg, i, j);
2270 + printk("\nInit\n");
2274 + for( i=0; i < 0x10; i++ )
2275 + printk("\nTDA8007 Reg %2d = 0x%02x ", i,
2276 + tda8007_reg_read(i)&0xff);
2283 + while( 1 ) // serstat() == 0
2285 + for( i=0 ;i < 0x10; i++ )
2287 + tdaregs[i]=tda8007_reg_read(i) & 0xff;
2294 + start_tda8007_sync(5);
2297 + start_tda8007_sync(3);
2300 + while( 1 )//serstat() == 0
2302 + for( i=0 ;i < 0x10; i++ )
2304 + tda8007_reg_write(i,0x10-i);
2315 + }while( end == 0 );
2318 +/*-------------------------------------------------------------------------*/
2319 +static int tda8007_ioctl(struct inode *ino, struct file *filp,
2320 + uint cmd, ulong arg)
2322 + unsigned int val, gain;
2325 + if (_IOC_TYPE(cmd) != 'M')
2328 + switch (_IOC_NR(cmd))
2339 + case TDA_CARD_PRESENT:
2342 + case TDA_CARD_VOLT:
2352 +/* ------------------------------------------------------------------------- */
2353 +static ssize_t proc_tda8007_read( struct file *file, char *buf, size_t nbytes,
2356 + char outputbuf[80];
2359 + int i_ino = (file->f_dentry->d_inode)->i_ino;
2360 + tda8007_reg_entry_t* current_reg = NULL;
2362 + if ((*ppos) > 0) /* Assume reading completed in previous read*/
2365 + for (i=0; i<NUM_OF_TDA8007_REG_ENTRY; i++)
2367 + if (tda8007_regs[i].low_ino==i_ino)
2369 + if( tda8007_regs[i].mode == 2 ) /* write only */
2371 + printk("%s\n", tda8007_regs[i].description);
2372 + printk("Read operation is on this register not possible!\n");
2375 + current_reg = &tda8007_regs[i];
2381 + if (current_reg==NULL)
2384 + printk("%s\n", current_reg->description);
2385 + count += sprintf(outputbuf, "%s: 0x%x\n", current_reg->name,
2386 + tda8007_reg_read( current_reg->addr ));
2387 + /* count = sprintf(outputbuf, "value: 0x%x\n",
2388 + tda8007_reg_read( current_reg->addr ));*/
2392 + if (count>nbytes) /* Assume output can be read at one time */
2395 + if (copy_to_user(buf, outputbuf, count))
2400 +/* ------------------------------------------------------------------------- */
2401 +static ssize_t proc_tda8007_write(struct file * file, const char * buffer,
2402 + size_t count, loff_t *ppos)
2405 + unsigned long newRegValue;
2407 + int i_ino = (file->f_dentry->d_inode)->i_ino;
2408 + tda8007_reg_entry_t* current_reg=NULL;
2410 + for (i=0; i<NUM_OF_TDA8007_REG_ENTRY; i++)
2412 + if (tda8007_regs[i].low_ino==i_ino)
2414 + if( tda8007_regs[i].mode == 1 ) /* read only */
2416 + printk("%s\n", tda8007_regs[i].description);
2417 + printk("Write operation is on this register not possible!\n");
2420 + current_reg = &tda8007_regs[i];
2424 + if (current_reg==NULL)
2427 + newRegValue = simple_strtoul(buffer,&endp,0);
2428 + tda8007_reg_write( current_reg->addr, newRegValue);
2429 + return (count+endp-buffer);
2431 +/* ------------------------------------------------------------------------- */
2432 +static int __init tda8007_init()
2434 + int i, hsr_reg, res;
2435 + int ret = -ENODEV;
2436 + struct proc_dir_entry *entry;
2437 + int tda8007_major = 60;
2439 + res = register_chrdev( tda8007_major, "tda8007", NULL );
2442 + printk(KERN_WARNING "tda8007: can't get major%d\n", tda8007_major);
2446 + if( tda8007_major == 0 )
2447 + tda8007_major = res;
2449 + set_GPIO_IRQ_edge(GPIO_SMART_CARD, GPIO_RISING_EDGE);
2451 + ret = request_irq( IRQ_GPIO_SMART_CARD, tda8007_irq,
2452 + SA_INTERRUPT, "SMARTCARD_CD", NULL );
2454 + printk(KERN_ERR "tda8007: unable to grab irq%d: %d\n",
2455 + IRQ_GPIO_SMART_CARD, ret);
2459 + printk("\nInit TDA8007 IRQ=%s\n",
2460 + (GPLR&(1<<10) ? "HIGH":"LOW"));
2462 +// clear_cs3_bit(RESET_SIMCARD);
2465 +#ifdef CONFIG_PROC_FS
2466 + /* Create two dir entries for the TDA8007 */
2467 + tda8007dir = proc_mkdir("tda8007"/*TDA8007_DIRNAME*/, NULL);
2468 + if (tda8007dir == NULL) {
2469 + printk(KERN_ERR "tda80007: can't create /proc/" TDA8007_DIRNAME "\n");
2473 + regdir = proc_mkdir(REG_DIRNAME, tda8007dir);
2474 + if (regdir == NULL) {
2475 + printk(KERN_ERR "tda8007: can't create /proc/" TDA8007_DIRNAME "/" REG_DIRNAME "\n");
2479 + for(i=0;i<NUM_OF_TDA8007_REG_ENTRY;i++) {
2480 + entry = create_proc_entry(tda8007_regs[i].name,
2481 + S_IWUSR |S_IRUSR | S_IRGRP | S_IROTH,
2484 + tda8007_regs[i].low_ino = entry->low_ino;
2485 + entry->proc_fops = &proc_reg_operations;
2489 + "tda8007: can't create /proc/" REG_DIRNAME
2490 + "/%s\n", tda8007_regs[i].name);
2495 +#endif // CONFIG_PROC_FS
2498 + tda8007_reg_write(TDA_CSR, 0);
2499 + tda8007_reg_write(TDA_CSR, TDA_CSR_nRIU);
2500 + for( i=0; i < 16; i++ )
2501 + tda8007_reg_write(i,0);
2503 + tda8007_reg_write(TDA_CSR, TDA_CSR_nRIU|TDA_CSR_SC2);
2504 + tda8007_reg_write(TDA_PCR, 0); /* START=0 */
2505 + tda8007_reg_write(TDA_CSR, TDA_CSR_nRIU|TDA_CSR_SC1);
2506 + tda8007_reg_write(TDA_PCR, 0); /* START=0 */
2507 + tda8007_reg_write(TDA_TOC, 0);
2508 + tda8007_reg_write(TDA_FCR, TDA_FCR_FL2|TDA_FCR_FL1|TDA_FCR_FL0);
2510 + tda8007_reg_write(TDA_UCR2, TDA_UCR_DISAUX|TDA_UCR2_DIV); // DIS_AUX DIS_CLK
2511 + tda8007_reg_write(TDA_UCR2, TDA_UCR_DISAUX|TDA_UCR2_DIV); // DIS_AUX CLK SYNC-MODE
2512 + hsr_reg = tda8007_reg_read(TDA_HSR);
2514 + tda8007_reg_write(TDA_CCR, TDA_CCR_AC1|TDA_CCR_AC0); /* XTAL/8 */
2518 +/* ------------------------------------------------------------------------- */
2519 +static void __exit tda8007_exit(void)
2523 + free_irq(IRQ_GPIO_SMART_CARD, NULL);
2524 + /* kfree(my_ucb);*/
2528 + for(i=0;i<NUM_OF_TDA8007_REG_ENTRY;i++) {
2529 + remove_proc_entry( tda8007_regs[i].name, regdir);
2533 +/* ------------------------------------------------------------------------- */
2534 +module_init(tda8007_init);
2535 +module_exit(tda8007_exit);
2537 +MODULE_AUTHOR("Juergen Messerer <juergen.messerer@freesurf.ch>");
2538 +MODULE_DESCRIPTION("TDA8007 driver");
2539 +MODULE_LICENSE("GPL");
2541 +++ linux-2.4.27/drivers/char/tda8007b.h
2544 + * Double multiprotocol IC car interface (Philips SmartCard reader)
2546 + * linux/drivers/char/tda8007b.h
2548 + * Copyright (C) 2002 juergen.messerer@freesurf.ch, All Rights Reserved.
2550 + * This program is free software; you can redistribute it and/or modify
2551 + * it under the terms of the GNU General Public License as published by
2552 + * the Free Software Foundation; either version 2 of the License.
2557 +#define CS4BUSTYPE unsigned volatile long
2558 +#define CS4_BASE 0xf2000000
2560 +#define CARD_PORT1 1
2561 +#define CARD_PORT2 2
2562 +#define CARD_PORT3 3
2564 +#define TDA_REG_READ(reg) *(CS4BUSTYPE *)(CS4_BASE+reg)
2565 +#define TDA_REG_WRITE(reg,val) *(CS4BUSTYPE *)(CS4_BASE+reg)=val
2567 +#define TDA_MULTIPLEXED_MODE 0
2569 +#define TDA_UCR2_DIV 0
2570 +#define TDA_PDR_VAL 12
2572 +#define pascii(i) ((i>=' ' && i < 0x7f) ? (i):'.')
2574 +#define BUFFSIZE 128
2577 +#define TDA_WRITE 2
2582 +#define TDA_CARD_PRESENT 4
2583 +#define TDA_CARD_VOLT 5
2591 +/*************************** Control Register ********************************/
2594 + * Card select register (read/write)
2595 + * all significant bits are cleared execept SC1 which is set (xxxx'0001)
2597 +#define TDA_CSR 0x00
2598 +#define TDA_CSR_SC1 (1 << 0)
2599 +#define TDA_CSR_SC2 (1 << 1)
2600 +#define TDA_CSR_SC3 (1 << 2)
2601 +#define TDA_CSR_nRIU (1 << 3)
2604 + * Clock configuration register (read/write)
2605 + * all bits are cleared (0000'0000)
2607 +#define TDA_CCR 0x01
2608 +#define TDA_CCR_AC0 (1 << 0)
2609 +#define TDA_CCR_AC1 (1 << 1)
2610 +#define TDA_CCR_AC2 (1 << 2)
2611 +#define TDA_CCR_SC (1 << 3)
2612 +#define TDA_CCR_CST (1 << 4)
2613 +#define TDA_CCR_SHL (1 << 5)
2616 + * Programmable divider register (read/write)
2617 + * all bits are cleared (0000'0000)
2619 +#define TDA_PDR 0x02
2620 +#define TDA_PDR_PD0 (1 << 0)
2621 +#define TDA_PDR_PD1 (1 << 1)
2622 +#define TDA_PDR_PD2 (1 << 2)
2623 +#define TDA_PDR_PD3 (1 << 3)
2624 +#define TDA_PDR_PD4 (1 << 4)
2625 +#define TDA_PDR_PD5 (1 << 5)
2626 +#define TDA_PDR_PD6 (1 << 6)
2627 +#define TDA_PDR_PD7 (1 << 7)
2630 + * UART configuration register 2(read/write)
2631 + * all relevant bits are cleared after reset (x000'0000)
2633 +#define TDA_UCR2 0x03
2634 +#define TDA_UCR_PSC (1 << 0)
2635 +#define TDA_UCR_CKU (1 << 1)
2636 +#define TDA_UCR_nAUTOCONV (1 << 2)
2637 +#define TDA_UCR_SAN (1 << 3)
2638 +#define TDA_UCR_PDWN (1 << 4)
2639 +#define TDA_UCR_DISAUX (1 << 5)
2640 +#define TDA_UCR_DISTBE_RBF (1 << 6)
2643 + * Guard time register (read/write)
2644 + * all bits are cleared (0000'0000)
2646 +#define TDA_GTR 0x05
2647 +#define TDA_GTR_GT0 (1 << 0)
2648 +#define TDA_GTR_GT1 (1 << 1)
2649 +#define TDA_GTR_GT2 (1 << 2)
2650 +#define TDA_GTR_GT3 (1 << 3)
2651 +#define TDA_GTR_GT4 (1 << 4)
2652 +#define TDA_GTR_GT5 (1 << 5)
2653 +#define TDA_GTR_GT6 (1 << 6)
2654 +#define TDA_GTR_GT7 (1 << 7)
2657 + * UART configuration register 1(read/write)
2658 + * all relevant bits are cleared after reset (x000'0000)
2660 +#define TDA_UCR1 0x06
2661 +#define TDA_UCR_CONV (1 << 0)
2662 +#define TDA_UCR_SS (1 << 1)
2663 +#define TDA_UCR_LCT (1 << 2)
2664 +#define TDA_UCR_T_R (1 << 3)
2665 +#define TDA_UCR_PROT (1 << 4)
2666 +#define TDA_UCR_FC (1 << 5)
2667 +#define TDA_UCR_FIP (1 << 6)
2670 + * Power control register (read/write)
2671 + * all relevant bits are cleared after reset (xx11'0000)
2673 +#define TDA_PCR 0x07
2674 +#define TDA_PCR_START (1 << 0)
2675 +#define TDA_PCR_3V_5V (1 << 1)
2676 +#define TDA_PCR_RSTIN (1 << 2)
2677 +#define TDA_PCR_1V8 (1 << 3)
2678 +#define TDA_PCR_C4 (1 << 4)
2679 +#define TDA_PCR_C8 (1 << 5)
2682 + * Time-out configuration register (read/write)
2683 + * all bits are cleared (0000'0000)
2685 +#define TDA_TOC 0x08
2686 +#define TDA_TOC_STOP_ALL 0x00
2687 +#define TDA_TOC_MODE1 0x61
2688 +#define TDA_TOC_MODE2 0x65
2689 +#define TDA_TOC_MODE3 0x68
2690 +#define TDA_TOC_MODE4 0x7c
2691 +#define TDA_TOC_MODE5 0xe5
2694 + * Time-out register 1(write only)
2695 + * all bits are cleared (0000'0000)
2697 +#define TDA_TOR1 0x09
2698 +#define TDA_TOR1_TOL0 (1 << 0)
2699 +#define TDA_TOR1_TOL1 (1 << 1)
2700 +#define TDA_TOR1_TOL2 (1 << 2)
2701 +#define TDA_TOR1_TOL3 (1 << 3)
2702 +#define TDA_TOR1_TOL4 (1 << 4)
2703 +#define TDA_TOR1_TOL5 (1 << 5)
2704 +#define TDA_TOR1_TOL6 (1 << 6)
2705 +#define TDA_TOR1_TOL7 (1 << 7)
2708 + * Time-out register 2(write only)
2709 + * all bits are cleared (0000'0000)
2711 +#define TDA_TOR2 0x0a
2712 +#define TDA_TOR2_TOL10 (1 << 0)
2713 +#define TDA_TOR2_TOL11 (1 << 1)
2714 +#define TDA_TOR2_TOL12 (1 << 2)
2715 +#define TDA_TOR2_TOL13 (1 << 3)
2716 +#define TDA_TOR2_TOL14 (1 << 4)
2717 +#define TDA_TOR2_TOL15 (1 << 5)
2718 +#define TDA_TOR2_TOL16 (1 << 6)
2719 +#define TDA_TOR2_TOL17 (1 << 7)
2722 + * Time-out register 3(write only)
2723 + * all bits are cleared (0000'0000)
2725 +#define TDA_TOR3 0x0b
2726 +#define TDA_TOR3_TOL16 (1 << 0)
2727 +#define TDA_TOR3_TOL17 (1 << 1)
2728 +#define TDA_TOR3_TOL18 (1 << 2)
2729 +#define TDA_TOR3_TOL19 (1 << 3)
2730 +#define TDA_TOR3_TOL20 (1 << 4)
2731 +#define TDA_TOR3_TOL21 (1 << 5)
2732 +#define TDA_TOR3_TOL22 (1 << 6)
2733 +#define TDA_TOR3_TOL23 (1 << 7)
2736 + * Mixed status register (read only)
2737 + * bits TBE, RBF and BGT are cleared, bit FE is set after reset (x10x'xxx0)
2739 +#define TDA_MSR 0x0c
2740 +#define TDA_MSR_TBE_RBF (1 << 0)
2741 +#define TDA_MSR_INTAUX (1 << 1)
2742 +#define TDA_MSR_PR1 (1 << 2)
2743 +#define TDA_MSR_PR2 (1 << 3)
2744 +#define TDA_MSR_BGT (1 << 5)
2745 +#define TDA_MSR_FE (1 << 6)
2748 + * FIFO control register (write only)
2749 + * all relevant bits are cleared after reset (x000'x000)
2751 +#define TDA_FCR 0x0c
2752 +#define TDA_FCR_FL0 (1 << 0)
2753 +#define TDA_FCR_FL1 (1 << 1)
2754 +#define TDA_FCR_FL2 (1 << 2)
2755 +#define TDA_FCR_PEC0 (1 << 4)
2756 +#define TDA_FCR_PEC1 (1 << 5)
2757 +#define TDA_FCR_PEC2 (1 << 6)
2760 + * UART transmit register (write only)
2761 + * all bits are cleared (0000'0000)
2763 +#define TDA_UTR 0x0d
2764 +#define TDA_UTR_UT0 (1 << 0)
2765 +#define TDA_UTR_UT1 (1 << 1)
2766 +#define TDA_UTR_UT2 (1 << 2)
2767 +#define TDA_UTR_UT3 (1 << 3)
2768 +#define TDA_UTR_UT4 (1 << 4)
2769 +#define TDA_UTR_UT5 (1 << 5)
2770 +#define TDA_UTR_UT6 (1 << 6)
2771 +#define TDA_UTR_UT7 (1 << 7)
2774 + * UART receive register (read only)
2775 + * all bits are cleared (0000'0000)
2777 +#define TDA_URR 0x0d
2778 +#define TDA_URR_UR0 (1 << 0)
2779 +#define TDA_URR_UR1 (1 << 1)
2780 +#define TDA_URR_UR2 (1 << 2)
2781 +#define TDA_URR_UR3 (1 << 3)
2782 +#define TDA_URR_UR4 (1 << 4)
2783 +#define TDA_URR_UR5 (1 << 5)
2784 +#define TDA_URR_UR6 (1 << 6)
2785 +#define TDA_URR_UR7 (1 << 7)
2788 + * UART status register (read only)
2789 + * all bits are cleared (0x00'0000)
2791 +#define TDA_USR 0x0e
2792 +#define TDA_USR_TBE_RBF (1 << 0)
2793 +#define TDA_USR_FER (1 << 1)
2794 +#define TDA_USR_OVR (1 << 2)
2795 +#define TDA_USR_PE (1 << 3)
2796 +#define TDA_USR_EA (1 << 4)
2797 +#define TDA_USR_TO1 (1 << 5)
2798 +#define TDA_USR_TO3 (1 << 7)
2801 + * Hardware status register (read only)
2802 + * all significant bits are cleared, except SUPL (x001'0000)
2804 +#define TDA_HSR 0x0f
2805 +#define TDA_HSR_PTL (1 << 0)
2806 +#define TDA_HSR_INTAUXL (1 << 1)
2807 +#define TDA_HSR_PRL1 (1 << 2)
2808 +#define TDA_HSR_PRL2 (1 << 3)
2809 +#define TDA_HSR_SUPL (1 << 4)
2810 +#define TDA_HSR_PRTL1 (1 << 5)
2811 +#define TDA_HSR_PRTL2 (1 << 6)
2813 +typedef struct tda8007_reg_entry {
2816 + char* description;
2818 + unsigned short low_ino;
2819 +} tda8007_reg_entry_t;
2828 +static tda8007_reg_entry_t tda8007_regs[] =
2830 + {TDA_CSR, "TDA_CSR", "Card select register (read/write)", 3},
2831 + {TDA_CCR, "TDA_CCR", "Clock configuration register (read/write)", 3},
2832 + {TDA_PDR, "TDA_PDR", "Programmable divider register (read/write)", 3},
2833 + {TDA_UCR2, "TDA_UCR2", "UART configuration register 2(read/write)", 3},
2834 + {TDA_GTR, "TDA_GTR", "Guard time register (read/write)", 3},
2835 + {TDA_UCR1, "TDA_UCR1", "UART configuration register 1(read/write)", 3},
2836 + {TDA_PCR, "TDA_PCR", "Power control register (read/write)", 3},
2837 + {TDA_TOC, "TDA_TOC", "Time-out configuration register (read/write)", 3},
2838 + {TDA_MSR, "TDA_MSR", "Mixed status register (read only)", 1},
2839 + {TDA_URR, "TDA_URR", "UART receive register (read only)", 1},
2840 + {TDA_USR, "TDA_USR", "UART status register (read only)", 1},
2841 + {TDA_HSR, "TDA_HSR", "Hardware status register (read only)", 1},
2842 + {TDA_TOR1, "TDA_TOR1", "Time-out register 1(write only)", 2},
2843 + {TDA_TOR2, "TDA_TOR2", "Time-out register 2(write only)", 2},
2844 + {TDA_TOR3, "TDA_TOR3", "Time-out register 3(write only)", 2},
2845 + {TDA_FCR, "TDA_FCR", "FIFO control register (write only)", 2},
2846 + {TDA_UTR, "TDA_UTR", "UART transmit register (write only)", 2}
2848 +#define NUM_OF_TDA8007_REG_ENTRY (sizeof(tda8007_regs)/sizeof(tda8007_reg_entry_t))
2854 +#endif /* TDA8007B_H */
2855 --- linux-2.4.27/drivers/misc/Config.in~2.4.27-vrs1-pxa1-jpm1
2856 +++ linux-2.4.27/drivers/misc/Config.in
2858 dep_tristate ' UCB1400 Touchscreen support' CONFIG_MCP_UCB1400_TS $CONFIG_ARCH_PXA $CONFIG_SOUND
2861 +mainmenu_option next_comment
2862 +comment 'Console Switches'
2864 +tristate 'Console Switch Support' CONFIG_SWITCHES
2865 +if [ "$CONFIG_SWITCHES" != "n" ]; then
2866 + dep_bool ' SA-1100 switches' CONFIG_SWITCHES_SA1100 $CONFIG_ARCH_SA1100
2867 + if [ "$CONFIG_MCP_UCB1200" != "n" ]; then
2868 + bool ' UCB1x00 switches' CONFIG_SWITCHES_UCB1X00
2873 --- linux-2.4.27/drivers/misc/Makefile~2.4.27-vrs1-pxa1-jpm1
2874 +++ linux-2.4.27/drivers/misc/Makefile
2876 obj-$(CONFIG_MCP_UCB1400_TS) += mcp-pxa.o ucb1x00-core.o ucb1x00-ts.o
2877 obj-$(CONFIG_PXA_CERF_PDA) += cerf_ucb1400gpio.o
2879 +ifeq ($(CONFIG_SA1100_ASSABET),y)
2880 +obj-$(CONFIG_MCP_UCB1200) += ucb1x00-assabet.o
2883 +ifeq ($(CONFIG_SA1100_SIMPAD),y)
2884 +export-objs += ucb1x00-simpad.o
2885 +obj-$(CONFIG_MCP_UCB1200) += ucb1x00-simpad.o
2888 +obj-$(CONFIG_SWITCHES) += switches.o
2890 +switches-objs-y += switches-core.o
2891 +switches-objs-$(CONFIG_SWITCHES_SA1100) += switches-sa1100.o
2892 +switches-objs-$(CONFIG_SWITCHES_UCB1X00) += switches-ucb1x00.o
2894 include $(TOPDIR)/Rules.make
2896 +switches.o: $(switches-objs-y)
2897 + $(LD) $(LD_RFLAG) -r -o $@ $(switches-objs-y)
2901 +++ linux-2.4.27/drivers/misc/switches-core.c
2904 + * linux/drivers/misc/switches-core.c
2906 + * Copyright (C) 2000-2001 John Dorsey
2908 + * This program is free software; you can redistribute it and/or modify
2909 + * it under the terms of the GNU General Public License version 2 as
2910 + * published by the Free Software Foundation.
2912 + * 5 October 2000 - created.
2914 + * 25 October 2000 - userland file interface added.
2916 + * 13 January 2001 - added support for Spot.
2918 + * 11 September 2001 - UCB1200 driver framework support added.
2920 + * 19 December 2001 - separated out SA-1100 and UCB1x00 code.
2923 +#include <linux/config.h>
2924 +#include <linux/init.h>
2925 +#include <linux/fs.h>
2926 +#include <linux/kernel.h>
2927 +#include <linux/miscdevice.h>
2928 +#include <linux/module.h>
2929 +#include <linux/mm.h>
2930 +#include <linux/poll.h>
2931 +#include <linux/sched.h>
2932 +#include <linux/slab.h>
2933 +#include <linux/wait.h>
2935 +#include <asm/uaccess.h>
2937 +#include "switches.h"
2940 +MODULE_AUTHOR("John Dorsey");
2941 +MODULE_DESCRIPTION("Console switch support");
2942 +MODULE_LICENSE("GPL");
2945 +struct switches_action {
2946 + struct list_head list;
2947 + switches_mask_t mask;
2951 +static int switches_users = 0;
2953 +static spinlock_t switches_lock = SPIN_LOCK_UNLOCKED;
2955 +DECLARE_WAIT_QUEUE_HEAD(switches_wait);
2956 +LIST_HEAD(switches_event_queue);
2959 +static ssize_t switches_read(struct file *file, char *buffer,
2960 + size_t count, loff_t *pos)
2962 + unsigned long flags;
2963 + struct list_head *event;
2964 + struct switches_action *action;
2966 + if (count < sizeof(struct switches_mask_t))
2969 + while (list_empty(&switches_event_queue)) {
2971 + if (file->f_flags & O_NDELAY)
2974 + interruptible_sleep_on(&switches_wait);
2976 + if (signal_pending(current))
2977 + return -ERESTARTSYS;
2981 + if (verify_area(VERIFY_WRITE, buffer, sizeof(struct switches_mask_t)))
2984 + spin_lock_irqsave(&switches_lock, flags);
2986 + event = switches_event_queue.next;
2987 + action = list_entry(event, struct switches_action, list);
2988 + copy_to_user(buffer, &(action->mask), sizeof(struct switches_mask_t));
2992 + spin_unlock_irqrestore(&switches_lock, flags);
2994 + return sizeof(struct switches_mask_t);
2998 +static ssize_t switches_write(struct file *file, const char *buffer,
2999 + size_t count, loff_t *ppos)
3004 +static unsigned int switches_poll(struct file *file, poll_table *wait)
3007 + poll_wait(file, &switches_wait, wait);
3009 + if (!list_empty(&switches_event_queue))
3010 + return POLLIN | POLLRDNORM;
3016 +static int switches_open(struct inode *inode, struct file *file)
3019 + if (switches_users > 0)
3022 + MOD_INC_USE_COUNT;
3028 +static int switches_release(struct inode *inode, struct file *file)
3032 + MOD_DEC_USE_COUNT;
3037 +static struct file_operations switches_ops = {
3038 + read: switches_read,
3039 + write: switches_write,
3040 + poll: switches_poll,
3041 + open: switches_open,
3042 + release: switches_release
3045 +static struct miscdevice switches_misc = {
3046 + MISC_DYNAMIC_MINOR, SWITCHES_NAME, &switches_ops
3049 +int switches_event(switches_mask_t *mask)
3051 + struct switches_action *action;
3053 + if ((switches_users > 0) && (SWITCHES_COUNT(mask) > 0)) {
3055 + if ((action = (struct switches_action *)
3056 + kmalloc(sizeof(struct switches_action),
3057 + GFP_ATOMIC)) == NULL) {
3058 + printk(KERN_ERR "%s: unable to allocate action "
3059 + "descriptor\n", SWITCHES_NAME);
3063 + action->mask = *mask;
3065 + spin_lock(&switches_lock);
3066 + list_add_tail(&action->list, &switches_event_queue);
3067 + spin_unlock(&switches_lock);
3069 + wake_up_interruptible(&switches_wait);
3077 +static int __init switches_init(void)
3080 +#ifdef CONFIG_SWITCHES_SA1100
3081 + if (switches_sa1100_init() < 0) {
3082 + printk(KERN_ERR "%s: unable to initialize SA-1100 switches\n",
3088 +#ifdef CONFIG_SWITCHES_UCB1X00
3089 + if (switches_ucb1x00_init() < 0) {
3090 + printk(KERN_ERR "%s: unable to initialize UCB1x00 switches\n",
3096 + if (misc_register(&switches_misc) < 0) {
3097 + printk(KERN_ERR "%s: unable to register misc device\n",
3102 + printk("Console switches initialized\n");
3108 +static void __exit switches_exit(void)
3111 +#ifdef CONFIG_SWITCHES_SA1100
3112 + switches_sa1100_exit();
3115 +#ifdef CONFIG_SWITCHES_UCB1X00
3116 + switches_ucb1x00_exit();
3119 + if (misc_deregister(&switches_misc) < 0)
3120 + printk(KERN_ERR "%s: unable to deregister misc device\n",
3125 +module_init(switches_init);
3126 +module_exit(switches_exit);
3130 +++ linux-2.4.27/drivers/misc/switches-sa1100.c
3133 + * linux/drivers/misc/switches-sa1100.c
3135 + * Copyright (C) 2001 John Dorsey
3137 + * This program is free software; you can redistribute it and/or modify
3138 + * it under the terms of the GNU General Public License version 2 as
3139 + * published by the Free Software Foundation.
3141 + * 19 December 2001 - created from sa1100_switches.c.
3144 +#include <linux/config.h>
3145 +#include <linux/init.h>
3146 +#include <linux/kernel.h>
3147 +#include <linux/sched.h>
3149 +#include <asm/hardware.h>
3150 +#include <asm/irq.h>
3152 +#ifdef CONFIG_SA1100_ASSABET
3153 +#include <asm/arch/assabet.h>
3156 +#ifdef CONFIG_SA1100_SIMPAD
3157 +#include <asm/arch/simpad.h>
3160 +#include "switches.h"
3163 +static void switches_sa1100_handler(int irq, void *dev_id,
3164 + struct pt_regs *regs);
3167 +#ifdef CONFIG_SA1100_ASSABET
3171 + * We have two general-purpose switches, S1 and S2, available via GPIO
3172 + * on Assabet. This code sets bits in the range [1, 2] in the mask that
3173 + * we return to userland.
3176 +static int assabet_switches_sa1100_init(void)
3179 + if (machine_has_neponset())
3180 + NCR_0 |= NCR_GP01_OFF;
3182 + set_irq_type(IRQ_GPIO0, IRQT_BOTHEDGE);
3183 + set_irq_type(IRQ_GPIO1, IRQT_BOTHEDGE);
3185 + if (request_irq(IRQ_GPIO0, switches_sa1100_handler, SA_INTERRUPT,
3186 + SWITCHES_NAME, NULL) < 0) {
3187 + printk(KERN_ERR "%s: unable to register IRQ for GPIO 0\n",
3192 + if (request_irq(IRQ_GPIO1, switches_sa1100_handler, SA_INTERRUPT,
3193 + SWITCHES_NAME, NULL) < 0) {
3194 + printk(KERN_ERR "%s: unable to register IRQ for GPIO 1\n",
3203 +static void assabet_switches_sa1100_shutdown(void)
3206 + free_irq(IRQ_GPIO1, NULL);
3207 + free_irq(IRQ_GPIO0, NULL);
3211 +static void assabet_switches_sa1100_handler(int irq, switches_mask_t *mask)
3213 + unsigned int s, last, this;
3214 + static unsigned int states = 0;
3218 + case IRQ_GPIO0: s = 0; break;
3220 + case IRQ_GPIO1: s = 1; break;
3226 + last = ((states & (1 << s)) != 0);
3227 + this = ((GPLR & GPIO_GPIO(s)) != 0);
3229 + if (last == this) /* debounce */
3232 + SWITCHES_SET(mask, s + 1, this);
3234 + states = this ? (states | (1 << s)) : (states & ~(1 << s));
3237 +#endif /* CONFIG_SA1100_ASSABET */
3240 +#ifdef CONFIG_SA1100_SPOT
3244 + * Spot (R2, R3) has a single general-purpose switch (S1), which is
3245 + * also the power-on switch. We set bit [1] in the mask we return to
3249 +static int spot_switches_sa1100_init(void)
3252 + set_GPIO_IRQ_edge(GPIO_SW1, GPIO_BOTH_EDGES);
3254 + if (request_irq(IRQ_GPIO_SW1, switches_sa1100_handler, SA_INTERRUPT,
3255 + SWITCHES_NAME, NULL) < 0) {
3256 + printk(KERN_ERR "%s: unable to register IRQ for SW1\n",
3265 +static void spot_switches_sa1100_shutdown(void)
3268 + free_irq(IRQ_GPIO_SW1, NULL);
3272 +static void spot_switches_sa1100_handler(int irq, switches_mask_t *mask)
3274 + unsigned int s, last, this;
3275 + static unsigned int states = 0;
3279 + case IRQ_GPIO_SW1: s = 0; break;
3285 + last = ((states & (1 << s)) != 0);
3286 + this = ((GPLR & GPIO_GPIO(s)) != 0);
3288 + if (last == this) /* debounce */
3291 + SWITCHES_SET(mask, s + 1, this);
3293 + states = this ? (states | (1 << s)) : (states & ~(1 << s));
3296 +#endif /* CONFIG_SA1100_SPOT */
3298 +#ifdef CONFIG_SA1100_SIMPAD
3302 + * SIMpad has a single general-purpose switch (S0), which is
3303 + * also the power-on switch. We set bit [1] in the mask we return to
3307 +static int simpad_switches_sa1100_init(void)
3310 + set_GPIO_IRQ_edge(GPIO_GPIO0, GPIO_BOTH_EDGES);
3312 + if (request_irq(IRQ_GPIO0, switches_sa1100_handler, SA_INTERRUPT,
3313 + SWITCHES_NAME, NULL) < 0) {
3314 + printk(KERN_ERR "%s: unable to register IRQ for SW0\n",
3323 +static void simpad_switches_sa1100_shutdown(void)
3326 + free_irq(IRQ_GPIO0, NULL);
3330 +static void simpad_switches_sa1100_handler(int irq, switches_mask_t *mask)
3332 + unsigned int s, last, this;
3333 + static unsigned int states = 0;
3337 + case IRQ_GPIO0: s = 0; break;
3343 + last = ((states & (1 << s)) != 0);
3344 + this = ((GPLR & GPIO_GPIO(s)) != 0);
3346 + if (last == this) /* debounce */
3349 + SWITCHES_SET(mask, s + 1, this);
3351 + states = this ? (states | (1 << s)) : (states & ~(1 << s));
3354 +#endif /* CONFIG_SA1100_SIMPAD */
3358 +/* switches_sa1100_handler()
3359 + * ^^^^^^^^^^^^^^^^^^^^^^^^^
3360 + * This routine is a generalized handler for SA-1100 switches
3361 + * which manages action descriptors and calls a board-specific
3362 + * service routine. This routine is appropriate for GPIO switches
3363 + * or other primary interrupt sources, and can be registered as a
3364 + * first-class IRQ handler using request_irq().
3366 +static void switches_sa1100_handler(int irq, void *dev_id,
3367 + struct pt_regs *regs)
3369 + switches_mask_t mask;
3371 + SWITCHES_ZERO(&mask);
3373 + /* Porting note: call a board-specific switch interrupt handler
3374 + * here. The handler can assume that sufficient storage for
3375 + * `mask' has been allocated, and that the corresponding
3376 + * switches_mask_t structure has been zeroed.
3379 + if (machine_is_assabet()) {
3380 +#ifdef CONFIG_SA1100_ASSABET
3381 + assabet_switches_sa1100_handler(irq, &mask);
3383 + } else if (machine_is_spot()) {
3384 +#ifdef CONFIG_SA1100_SPOT
3385 + spot_switches_sa1100_handler(irq, &mask);
3387 + } else if (machine_is_simpad()) {
3388 +#ifdef CONFIG_SA1100_SIMPAD
3389 + simpad_switches_sa1100_handler(irq, &mask);
3393 + switches_event(&mask);
3397 +int __init switches_sa1100_init(void)
3400 + /* Porting note: call a board-specific init routine here. */
3402 + if (machine_is_assabet()) {
3403 +#ifdef CONFIG_SA1100_ASSABET
3404 + if (assabet_switches_sa1100_init() < 0)
3407 + } else if (machine_is_spot()) {
3408 +#ifdef CONFIG_SA1100_SPOT
3409 + if (spot_switches_sa1100_init() < 0)
3412 + } else if (machine_is_simpad()) {
3413 +#ifdef CONFIG_SA1100_SIMPAD
3414 + if (simpad_switches_sa1100_init() < 0)
3423 +void __exit switches_sa1100_exit(void)
3426 + /* Porting note: call a board-specific shutdown routine here. */
3428 + if (machine_is_assabet()) {
3429 +#ifdef CONFIG_SA1100_ASSABET
3430 + assabet_switches_sa1100_shutdown();
3432 + } else if (machine_is_spot()) {
3433 +#ifdef CONFIG_SA1100_SPOT
3434 + spot_switches_sa1100_shutdown();
3436 + } else if (machine_is_simpad()) {
3437 +#ifdef CONFIG_SA1100_SIMPAD
3438 + simpad_switches_sa1100_shutdown();
3444 +++ linux-2.4.27/drivers/misc/switches-ucb1x00.c
3447 + * linux/drivers/misc/switches-ucb1x00.c
3449 + * Copyright (C) 2001 John Dorsey
3451 + * This program is free software; you can redistribute it and/or modify
3452 + * it under the terms of the GNU General Public License version 2 as
3453 + * published by the Free Software Foundation.
3455 + * 19 December 2001 - created from sa1100_switches.c.
3458 +#include <linux/config.h>
3459 +#include <linux/init.h>
3460 +#include <linux/kernel.h>
3461 +#include <linux/sched.h>
3463 +#include <asm/dma.h>
3464 +#include <asm/hardware.h>
3465 +#include <asm/irq.h>
3467 +#ifdef CONFIG_SA1100_ASSABET
3468 +#include <asm/arch/assabet.h>
3471 +#ifdef CONFIG_SA1100_SIMPAD
3472 +#include <asm/arch/simpad.h>
3475 +#include "switches.h"
3476 +#include "ucb1x00.h"
3479 +static struct ucb1x00 *ucb1x00;
3481 +static void switches_ucb1x00_handler(int irq, void *devid);
3484 +#ifdef CONFIG_SA1100_ASSABET
3488 + * Six switches are routed to GPIO pins on the UCB1300: S3 -- S8.
3489 + * This code sets bits in the range [3, 8] in the mask that we
3490 + * return to userland. Note that we transpose signals SW7 and SW8;
3491 + * see assabet_switches_ucb1x00_handler().
3494 +static int assabet_switches_ucb1x00_init(void)
3498 + /* Note that ucb1x00_init() must complete before this point: */
3500 + if ((ucb1x00 = ucb1x00_get()) == NULL) {
3501 + printk(KERN_ERR "%s: UCB1300 driver not ready; switches "
3502 + "3 -- 8 will not be available\n",
3507 + ucb1x00_enable(ucb1x00);
3509 + ucb1x00_io_set_dir(ucb1x00,
3510 + UCB_IO_0 | UCB_IO_1 | UCB_IO_2 |
3511 + UCB_IO_3 | UCB_IO_4 | UCB_IO_5, 0);
3513 + for (i = 0; i < 6; ++i) {
3515 + ucb1x00_enable_irq(ucb1x00, i, UCB_RISING | UCB_FALLING);
3517 + if (ucb1x00_hook_irq(ucb1x00, i,
3518 + switches_ucb1x00_handler, NULL) < 0) {
3519 + printk(KERN_ERR "%s: unable to hook IRQ for "
3520 + "UCB1300 IO_%d\n", SWITCHES_NAME, i);
3530 +static void assabet_switches_ucb1x00_shutdown(void)
3534 + for (i = 5; i >= 0; --i) {
3536 + ucb1x00_disable_irq(ucb1x00, i, UCB_RISING | UCB_FALLING);
3538 + /* Only error conditions are ENOENT and EINVAL; silently
3541 + ucb1x00_free_irq(ucb1x00, i, NULL);
3547 +static void assabet_switches_ucb1x00_handler(int irq, switches_mask_t *mask)
3549 + unsigned int last, this;
3550 + static unsigned int states = 0;
3552 + last = ((states & (1 << irq)) != 0);
3553 + this = ((ucb1x00_io_read(ucb1x00) & (1 << irq)) != 0);
3555 + if (last == this) /* debounce */
3558 + /* Intel StrongARM SA-1110 Development Board
3559 + * Schematics Figure 5, Sheet 5 of 12
3561 + * See switches S8 and S7. Notice their
3562 + * relationship to signals SW7 and SW8. Hmmm.
3569 + SWITCHES_SET(mask, 8, this);
3574 + SWITCHES_SET(mask, 7, this);
3579 + SWITCHES_SET(mask, irq + 3, this);
3583 + states = this ? (states | (1 << irq)) : (states & ~(1 << irq));
3586 +#endif /* CONFIG_SA1100_ASSABET */
3588 +#ifdef CONFIG_SA1100_SIMPAD
3592 + * Six switches are routed to GPIO pins on the UCB1300: S3 -- S8.
3593 + * This code sets bits in the range [3, 8] in the mask that we
3594 + * return to userland.
3597 +static int simpad_switches_ucb1x00_init(void)
3601 + /* Note that ucb1x00_init() must complete before this point: */
3603 + if ((ucb1x00 = ucb1x00_get()) == NULL) {
3604 + printk(KERN_ERR "%s: UCB1300 driver not ready; switches "
3605 + "3 -- 8 will not be available\n",
3610 + ucb1x00_enable(ucb1x00);
3612 + ucb1x00_io_set_dir(ucb1x00,
3613 + UCB_IO_0 | UCB_IO_1 | UCB_IO_2 |
3614 + UCB_IO_3 | UCB_IO_4 | UCB_IO_5,
3615 + UCB_IO_8 | UCB_IO_9);
3617 + ucb1x00_disable(ucb1x00);
3619 + for (i = 0; i < 6; ++i) {
3621 + if (ucb1x00_hook_irq(ucb1x00, i,
3622 + switches_ucb1x00_handler, NULL) < 0) {
3623 + printk(KERN_ERR "%s: unable to hook IRQ for "
3624 + "UCB1300 IO_%d\n", SWITCHES_NAME, i);
3628 + ucb1x00_enable_irq(ucb1x00, i, UCB_RISING | UCB_FALLING);
3635 +int simpad_switches_ucb1x00_reinit(void)
3638 + ucb1x00_enable(ucb1x00);
3640 + ucb1x00_io_set_dir(ucb1x00,
3641 + UCB_IO_0 | UCB_IO_1 | UCB_IO_2 |
3642 + UCB_IO_3 | UCB_IO_4 | UCB_IO_5,
3643 + UCB_IO_8 | UCB_IO_9);
3645 + ucb1x00_disable(ucb1x00);
3647 + for (i = 0; i < 6; ++i)
3648 + ucb1x00_enable_irq(ucb1x00, i, UCB_RISING | UCB_FALLING);
3653 +static void simpad_switches_ucb1x00_shutdown(void)
3657 + for (i = 5; i >= 0; --i) {
3659 + ucb1x00_disable_irq(ucb1x00, i, UCB_RISING | UCB_FALLING);
3661 + /* Only error conditions are ENOENT and EINVAL; silently
3664 + ucb1x00_free_irq(ucb1x00, i, NULL);
3670 +static void simpad_switches_ucb1x00_handler(int irq, switches_mask_t *mask)
3672 + unsigned int last, this;
3673 + static unsigned int states = 0;
3675 + last = ((states & (1 << irq)) != 0);
3676 + this = ((~ucb1x00_io_read(ucb1x00) & (1 << irq)) != 0);
3678 + if (last == this) /* debounce */
3693 + SWITCHES_SET(mask, irq + 3, this);
3697 + states = this ? (states | (1 << irq)) : (states & ~(1 << irq));
3700 +#endif /* CONFIG_SA1100_SIMPAD */
3703 +/* switches_ucb1x00_handler()
3704 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^
3705 + * This routine is a generalized handler for UCB1x00 GPIO switches
3706 + * which calls a board-specific service routine and passes an event
3707 + * mask to the core event handler. This routine is appropriate for
3708 + * systems which use the ucb1x00 framework, and can be registered
3709 + * using ucb1x00_hook_irq().
3711 +static void switches_ucb1x00_handler(int irq, void *devid)
3713 + switches_mask_t mask;
3715 + SWITCHES_ZERO(&mask);
3717 + /* Porting note: call a board-specific UCB1x00 switch handler here.
3718 + * The handler can assume that sufficient storage for `mask' has
3719 + * been allocated, and that the corresponding switches_mask_t
3720 + * structure has been zeroed.
3723 + if (machine_is_assabet()) {
3724 +#ifdef CONFIG_SA1100_ASSABET
3725 + assabet_switches_ucb1x00_handler(irq, &mask);
3728 + if (machine_is_simpad()) {
3729 +#ifdef CONFIG_SA1100_SIMPAD
3730 + simpad_switches_ucb1x00_handler(irq, &mask);
3734 + switches_event(&mask);
3738 +int __init switches_ucb1x00_init(void)
3741 + /* Porting note: call a board-specific init routine here. */
3743 + if (machine_is_assabet()) {
3744 +#ifdef CONFIG_SA1100_ASSABET
3745 + if (assabet_switches_ucb1x00_init() < 0)
3749 + if (machine_is_simpad()) {
3750 +#ifdef CONFIG_SA1100_SIMPAD
3751 + if (simpad_switches_ucb1x00_init() < 0)
3760 +void __exit switches_ucb1x00_exit(void)
3763 + /* Porting note: call a board-specific shutdown routine here. */
3765 + if (machine_is_assabet()) {
3766 +#ifdef CONFIG_SA1100_ASSABET
3767 + assabet_switches_ucb1x00_shutdown();
3770 + if (machine_is_simpad()) {
3771 +#ifdef CONFIG_SA1100_SIMPAD
3772 + simpad_switches_ucb1x00_shutdown();
3778 +++ linux-2.4.27/drivers/misc/switches.h
3781 + * linux/drivers/misc/switches.h
3783 + * Copyright (C) 2001 John Dorsey
3785 + * This program is free software; you can redistribute it and/or modify
3786 + * it under the terms of the GNU General Public License version 2 as
3787 + * published by the Free Software Foundation.
3789 + * 19 December 2001 - created.
3792 +#if !defined(_SWITCHES_H)
3793 +# define _SWITCHES_H
3795 +#include <linux/switches.h>
3797 +#define SWITCHES_NAME "switches"
3799 +extern int switches_event(switches_mask_t *mask);
3801 +extern int switches_sa1100_init(void);
3802 +extern void switches_sa1100_exit(void);
3804 +extern int switches_ucb1x00_init(void);
3805 +extern void switches_ucb1x00_exit(void);
3807 +#endif /* !defined(_SWITCHES_H) */
3809 +++ linux-2.4.27/drivers/misc/ucb1x00-assabet.c
3812 + * linux/drivers/misc/ucb1x00-assabet.c
3814 + * Copyright (C) 2001 Russell King, All Rights Reserved.
3816 + * This program is free software; you can redistribute it and/or modify
3817 + * it under the terms of the GNU General Public License as published by
3818 + * the Free Software Foundation; either version 2 of the License.
3820 + * We handle the machine-specific bits of the UCB1x00 driver here.
3822 +#include <linux/module.h>
3823 +#include <linux/init.h>
3824 +#include <linux/fs.h>
3825 +#include <linux/proc_fs.h>
3827 +#include <asm/dma.h>
3829 +#include "ucb1x00.h"
3831 +static struct proc_dir_entry *dir;
3832 +static struct ucb1x00 *ucb;
3834 +static int ucb1x00_assabet_read_vbatt(struct ucb1x00 *ucb)
3837 + ucb1x00_adc_enable(ucb);
3838 + val = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD1, UCB_NOSYNC);
3839 + ucb1x00_adc_disable(ucb);
3844 +static int ucb1x00_assabet_read_vcharger(struct ucb1x00 *ucb)
3847 + ucb1x00_adc_enable(ucb);
3848 + val = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD0, UCB_NOSYNC);
3849 + ucb1x00_adc_disable(ucb);
3854 +static int ucb1x00_assabet_read_batt_temp(struct ucb1x00 *ucb)
3857 + ucb1x00_adc_enable(ucb);
3858 + val = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD2, UCB_NOSYNC);
3859 + ucb1x00_adc_disable(ucb);
3864 +static int ucb_read(char *page, char **start, off_t off, int count, int *eof, void *data)
3867 + int (*fn)(struct ucb1x00 *) = data;
3872 + p += sprintf(p, "%d\n", v);
3874 + len = (p - page) - off;
3878 + *eof = (len <= count) ? 1 : 0;
3879 + *start = page + off;
3884 +static int __init ucb1x00_assabet_init(void)
3886 + struct proc_dir_entry *res;
3888 + ucb = ucb1x00_get();
3893 + dir = proc_mkdir("ucb1x00", NULL);
3897 + res = create_proc_read_entry("vbatt", S_IRUGO, dir, ucb_read, ucb1x00_assabet_read_vbatt);
3901 + res = create_proc_read_entry("vcharger", S_IRUGO, dir, ucb_read, ucb1x00_assabet_read_vcharger);
3905 + res = create_proc_read_entry("batt_temp", S_IRUGO, dir, ucb_read, ucb1x00_assabet_read_batt_temp);
3912 +static void __exit ucb1x00_assabet_exit(void)
3914 + remove_proc_entry("vbatt", dir);
3915 + remove_proc_entry("vcharger", dir);
3916 + remove_proc_entry("batt_temp", dir);
3919 +module_init(ucb1x00_assabet_init);
3920 +module_exit(ucb1x00_assabet_exit);
3922 +MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
3923 +MODULE_DESCRIPTION("Assabet noddy testing only example ADC driver");
3924 +MODULE_LICENSE("GPL");
3925 --- linux-2.4.27/drivers/misc/ucb1x00-audio.c~2.4.27-vrs1-pxa1-jpm1
3926 +++ linux-2.4.27/drivers/misc/ucb1x00-audio.c
3929 struct ucb1x00_audio *ucba;
3931 - ucba = kmalloc(sizeof(*ucba), GFP_KERNEL);
3932 + ucba = kmalloc(sizeof(*ucba), GFP_ATOMIC);
3934 memset(ucba, 0, sizeof(*ucba));
3936 --- linux-2.4.27/drivers/misc/ucb1x00-core.c~2.4.27-vrs1-pxa1-jpm1
3937 +++ linux-2.4.27/drivers/misc/ucb1x00-core.c
3939 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr);
3940 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
3941 ucb1x00_disable(ucb);
3942 +#ifdef CONFIG_SA1100_SIMPAD
3943 + simpad_switches_ucb1x00_reinit();
3948 @@ -561,8 +564,10 @@
3949 default_irq = IRQ_GPIO_UCB1300_IRQ;
3951 #ifdef CONFIG_SA1100_SIMPAD
3952 - if (machine_is_simpad())
3953 + if (machine_is_simpad()) {
3954 default_irq = IRQ_GPIO_UCB1300_IRQ;
3955 + irq_gpio_pin = GPIO_UCB1300_IRQ;
3958 #ifdef CONFIG_SA1100_SIMPUTER
3959 if (machine_is_simputer()) {
3961 if (id == UCB_ID_1400 && mcp_reg_read(mcp, 0x00) == 0x002a)
3962 id = UCB_ID_1400_BUGGY;
3964 - my_ucb = kmalloc(sizeof(struct ucb1x00), GFP_KERNEL);
3965 + my_ucb = kmalloc(sizeof(struct ucb1x00), GFP_ATOMIC);
3970 +++ linux-2.4.27/drivers/misc/ucb1x00-simpad.c
3973 + * linux/drivers/misc/ucb1x00-simpad.c
3975 + * Modified by Juergen Messerer for SIMpad
3976 + * Copyright (C) 2001 Russell King, All Rights Reserved.
3978 + * This program is free software; you can redistribute it and/or modify
3979 + * it under the terms of the GNU General Public License as published by
3980 + * the Free Software Foundation; either version 2 of the License.
3982 + * We handle the machine-specific bits of the UCB1x00 driver here.
3984 +#include <linux/module.h>
3985 +#include <linux/init.h>
3986 +#include <linux/fs.h>
3987 +#include <linux/proc_fs.h>
3989 +#include <asm/dma.h>
3991 +#include <asm/arch-sa1100/simpad_pm.h>
3993 +#include "ucb1x00.h"
3996 + * Conversion from AD -> mV
3997 + * 7.5V = 1023 7.3313mV/Digit
3999 + * 400 Units == 9.7V
4002 + * 12600 = Divident to get 2*7.3242
4003 + * 860 = Divider to get 2*7.3242
4004 + * 170 = Voltagedrop over
4006 +#define CALIBRATE_BATTERY(a) ((((a + 21)*12600)/860) + 170)
4009 + * We have two types of batteries a small and a large one
4010 + * To get the right value we to distinguish between those two
4011 + * 450 Units == 15 V
4013 +#ifdef SMALL_BATTERY
4014 +#define CALIBRATE_SUPPLY(a) (((a) * 1500) / 51)
4015 +#define MIN_SUPPLY 8500 /* Less then 8.5V means no powersupply */
4017 +#define CALIBRATE_SUPPLY(a) (((a) * 1500) / 45)
4018 +//#define MIN_SUPPLY 14000 /* Less then 14V means no powersupply */
4019 +#define MIN_SUPPLY 12000 /* Less then 12V means no powersupply */
4023 + * Charging Current
4024 + * if value is >= 50 then charging is on
4026 +#define CALIBRATE_CHARGING(a) (((a)* 1000)/(152/4)))
4027 +//#define CHARGING_LED_LEVEL 50
4029 +#ifdef CONFIG_SA1100_SIMPAD_SINUSPAD
4031 +#define CHARGING_LED_LEVEL 12
4032 +#define CHARGING_MAX_LEVEL 120
4033 +#define BATT_FULL 8100
4034 +#define BATT_LOW 7300
4035 +#define BATT_CRITICAL 6700
4036 +#define BATT_EMPTY 6400
4039 +#else // CONFIG_SA1100_SIMPAD_SINUSPAD
4041 +#define CHARGING_LED_LEVEL 28
4042 +#define CHARGING_MAX_LEVEL 265
4043 +#define BATT_FULL 8300
4044 +#define BATT_LOW 7400
4045 +#define BATT_CRITICAL 6800
4046 +#define BATT_EMPTY 6500
4048 +#endif // CONFIG_SA1100_SIMPAD_SINUSPAD
4051 +static struct proc_dir_entry *dir;
4052 +static struct ucb1x00 *ucb;
4054 +static int ucb1x00_simpad_read_vbatt(struct ucb1x00 *ucb)
4057 + ucb1x00_adc_enable(ucb);
4058 + val = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD1, UCB_NOSYNC);
4059 + ucb1x00_adc_disable(ucb);
4061 + return CALIBRATE_BATTERY(val);
4064 +static int ucb1x00_simpad_read_vcharger(struct ucb1x00 *ucb)
4067 + ucb1x00_adc_enable(ucb);
4068 + val = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD2, UCB_NOSYNC);
4069 + ucb1x00_adc_disable(ucb);
4071 + return CALIBRATE_SUPPLY(val);
4074 +static int ucb1x00_simpad_read_icharger(struct ucb1x00 *ucb)
4077 + ucb1x00_adc_enable(ucb);
4078 + val = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD3, UCB_NOSYNC);
4079 + ucb1x00_adc_disable(ucb);
4084 +static int ucb_read(char *page, char **start, off_t off, int count, int *eof, void *data)
4087 + int (*fn)(struct ucb1x00 *) = data;
4092 + p += sprintf(p, "%d\n", v);
4094 + len = (p - page) - off;
4098 + *eof = (len <= count) ? 1 : 0;
4099 + *start = page + off;
4104 +/****************************************************************************/
4105 +/* Functions exported for use by the kernel and kernel modules */
4106 +/****************************************************************************/
4108 +int simpad_get_battery(struct simpad_battery *bstat)
4110 + int icharger, vcharger, vbatt;
4113 + icharger = ucb1x00_simpad_read_icharger( ucb );
4114 + vcharger = ucb1x00_simpad_read_vcharger( ucb );
4115 + vbatt = ucb1x00_simpad_read_vbatt( ucb );
4117 + bstat->ac_status = SIMPAD_AC_STATUS_AC_UNKNOWN;
4118 + bstat->status = SIMPAD_BATT_STATUS_UNKNOWN;
4119 + bstat->percentage = 0x64; /* lets say 100% */
4120 + bstat->life = 360; /* lets say a long time */
4125 + bstat->ac_status = SIMPAD_AC_STATUS_AC_OFFLINE;
4126 + if ( vcharger>MIN_SUPPLY ) {
4127 + bstat->ac_status = SIMPAD_AC_STATUS_AC_ONLINE;
4131 + bstat->status = 0x0;
4132 + if ( icharger > CHARGING_LED_LEVEL ) {
4133 + bstat->status = SIMPAD_BATT_STATUS_CHARGING;
4136 + if ( vbatt > BATT_LOW )
4137 + bstat->status |= SIMPAD_BATT_STATUS_HIGH;
4138 + else if ( vbatt < BATT_CRITICAL )
4139 + bstat->status |= SIMPAD_BATT_STATUS_CRITICAL;
4141 + bstat->status |= SIMPAD_BATT_STATUS_LOW;
4143 + if (bstat->status & SIMPAD_BATT_STATUS_CHARGING) {
4144 + if (icharger > CHARGING_MAX_LEVEL) icharger = CHARGING_MAX_LEVEL;
4145 + if (icharger < CHARGING_LED_LEVEL) icharger = CHARGING_LED_LEVEL;
4146 + bstat->percentage = 100 - 100 * (icharger - CHARGING_LED_LEVEL) /
4147 + (CHARGING_MAX_LEVEL - CHARGING_LED_LEVEL);
4149 + if (vbatt > BATT_FULL) vbatt = BATT_FULL;
4150 + if (vbatt < BATT_EMPTY) vbatt = BATT_EMPTY;
4151 + bstat->percentage = 100 * (vbatt - BATT_EMPTY) / (BATT_FULL - BATT_EMPTY);
4154 + /* let's assume: full load is 7h */
4155 + /* bstat->life = 420*bstat->percentage/100; */
4159 + printk("get_battery: ac: %02x / ch: %02x / perc: %02x / life: %d\n",
4160 + bstat->ac_status, bstat->status,
4161 + bstat->percentage, bstat->life );
4167 +EXPORT_SYMBOL(simpad_get_battery);
4169 +/****************************************************************************/
4170 +/* sample proc interface */
4171 +/****************************************************************************/
4172 +static int __init ucb1x00_simpad_init(void)
4174 + struct proc_dir_entry *res;
4176 + ucb = ucb1x00_get();
4181 + dir = proc_mkdir("ucb1x00", NULL);
4185 + res = create_proc_read_entry("vbatt", S_IRUGO, dir, ucb_read, ucb1x00_simpad_read_vbatt);
4189 + res = create_proc_read_entry("vcharger", S_IRUGO, dir, ucb_read, ucb1x00_simpad_read_vcharger);
4193 + res = create_proc_read_entry("icharger", S_IRUGO, dir, ucb_read, ucb1x00_simpad_read_icharger);
4200 +static void __exit ucb1x00_simpad_exit(void)
4202 + remove_proc_entry("vbatt", dir);
4203 + remove_proc_entry("vcharger", dir);
4204 + remove_proc_entry("icharger", dir);
4207 +module_init(ucb1x00_simpad_init);
4208 +module_exit(ucb1x00_simpad_exit);
4210 +MODULE_AUTHOR("Juergen Messerer <juergen.messerer@freesurf.ch>");
4211 +MODULE_DESCRIPTION("SIMpad noddy testing only example ADC driver");
4212 +MODULE_LICENSE("GPL");
4213 --- linux-2.4.27/drivers/misc/ucb1x00-ts.c~2.4.27-vrs1-pxa1-jpm1
4214 +++ linux-2.4.27/drivers/misc/ucb1x00-ts.c
4216 UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
4217 UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
4220 + udelay(250); /*former 55*/
4222 return ucb1x00_adc_read(ts->ucb, UCB_ADC_INP_TSPY, ts->adcsync);
4225 UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
4226 UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
4229 + udelay(250); /*former 55*/
4231 return ucb1x00_adc_read(ts->ucb, UCB_ADC_INP_TSPX, ts->adcsync);
4233 --- linux-2.4.27/drivers/mtd/Config.in~2.4.27-vrs1-pxa1-jpm1
4234 +++ linux-2.4.27/drivers/mtd/Config.in
4236 if [ "$CONFIG_MTD_DEBUG" = "y" ]; then
4237 int ' Debugging verbosity (0 = quiet, 3 = noisy)' CONFIG_MTD_DEBUG_VERBOSE 0
4239 + if [ "$CONFIG_CRAMFS" = "y" ]; then
4240 + bool ' Cramfs root partition' CONFIG_ROOT_CRAMFS
4242 dep_tristate ' MTD partitioning support' CONFIG_MTD_PARTITIONS $CONFIG_MTD
4243 dep_tristate ' MTD concatenating support' CONFIG_MTD_CONCAT $CONFIG_MTD
4244 dep_tristate ' RedBoot partition table parsing' CONFIG_MTD_REDBOOT_PARTS $CONFIG_MTD_PARTITIONS
4245 --- linux-2.4.27/drivers/mtd/maps/sa1100-flash.c~2.4.27-vrs1-pxa1-jpm1
4246 +++ linux-2.4.27/drivers/mtd/maps/sa1100-flash.c
4247 @@ -767,40 +767,38 @@
4250 #ifdef CONFIG_SA1100_SIMPAD
4251 -#define SIMPAD_FLASH_SIZE 0x02000000
4252 -static struct mtd_partition simpad_partitions[] = {
4254 - name: "SIMpad boot firmware",
4257 - mask_flags: MTD_WRITEABLE, /* force read-only */
4259 - name: "SIMpad kernel",
4261 - offset: 0x00080000,
4263 -#ifdef CONFIG_JFFS2_FS
4264 - name: "SIMpad root jffs2",
4265 - size: MTDPART_SIZ_FULL,
4266 - offset: 0x00180000,
4268 +#ifdef CONFIG_SA1100_SIMPAD_SINUSPAD
4269 +#define SIMPAD_FLASH_SIZE 0x01000000
4271 - name: "SIMpad initrd",
4273 - offset: 0x00180000,
4275 - name: "SIMpad root cramfs",
4277 - offset: 0x00480000,
4279 - name: "SIMpad usr cramfs",
4281 - offset: 0x00780000,
4283 - name: "SIMpad usr local",
4284 - size: MTDPART_SIZ_FULL,
4285 - offset: 0x00d40000,
4286 +#define SIMPAD_FLASH_SIZE 0x02000000
4290 +static struct mtd_partition simpad_partitions[] = {
4292 + name: "SIMpad boot firmware",
4295 + mask_flags: MTD_WRITEABLE /* force read-only */
4297 + name: "SIMpad kernel",
4298 + offset: MTDPART_OFS_APPEND,
4301 +#ifdef CONFIG_ROOT_CRAMFS
4302 + name: "SIMpad root cramfs",
4303 + offset: MTDPART_OFS_APPEND,
4306 + name: "SIMpad local jffs",
4307 + offset: MTDPART_OFS_APPEND,
4308 + size: MTDPART_SIZ_FULL
4310 + name: "SIMpad root jffs2",
4311 + offset: MTDPART_OFS_APPEND,
4312 + size: MTDPART_SIZ_FULL
4313 +#endif /* CONFIG_CRAM_FS */
4316 #endif /* CONFIG_SA1100_SIMPAD */
4318 --- linux-2.4.27/drivers/pcmcia/sa1100_simpad.c~2.4.27-vrs1-pxa1-jpm1
4319 +++ linux-2.4.27/drivers/pcmcia/sa1100_simpad.c
4322 #include <asm/hardware.h>
4323 #include <asm/irq.h>
4324 +#include <asm/arch/simpad.h>
4326 #include "sa1100_generic.h"
4329 extern long get_cs3_shadow(void);
4330 -extern void set_cs3_bit(int value);
4331 +extern void set_cs3_bit(int value);
4332 extern void clear_cs3_bit(int value);
4335 static int simpad_pcmcia_init(struct pcmcia_init *init){
4338 - set_cs3_bit(PCMCIA_RESET);
4339 - clear_cs3_bit(PCMCIA_BUFF_DIS);
4340 - clear_cs3_bit(PCMCIA_RESET);
4342 clear_cs3_bit(VCC_3V_EN|VCC_5V_EN|EN0|EN1);
4344 /* Set transition detect */
4347 if(state_array->size<2) return -1;
4349 + memset(state_array->state, 0,
4350 + (state_array->size)*sizeof(struct pcmcia_state));
4354 state_array->state[1].detect=((levels & GPIO_CF_CD)==0)?1:0;
4355 @@ -100,13 +101,15 @@
4356 static int simpad_pcmcia_configure_socket(const struct pcmcia_configure
4359 - unsigned long value, flags;
4360 + static int irq_disabled = 0;
4362 - if(configure->sock>1) return -1;
4363 + if(configure->sock>1)
4366 - if(configure->sock==0) return 0;
4367 + if(configure->sock==0)
4370 - save_flags_cli(flags);
4371 + //local_irq_save(flags);
4373 /* Murphy: see table of MIC2562a-1 */
4379 - clear_cs3_bit(VCC_3V_EN|EN0);
4380 - set_cs3_bit(VCC_5V_EN|EN1);
4381 + clear_cs3_bit(VCC_3V_EN|EN1);
4382 + set_cs3_bit(VCC_5V_EN|EN0);
4386 @@ -129,26 +132,50 @@
4387 printk(KERN_ERR "%s(): unrecognized Vcc %u\n", __FUNCTION__,
4389 clear_cs3_bit(VCC_3V_EN|VCC_5V_EN|EN0|EN1);
4390 - restore_flags(flags);
4391 + //restore_flags(flags);
4395 - /* Silently ignore Vpp, output enable, speaker enable. */
4396 + if(configure->reset)
4397 + set_cs3_bit(PCMCIA_RESET);
4399 + clear_cs3_bit(PCMCIA_RESET);
4401 + if(configure->output)
4402 + clear_cs3_bit(PCMCIA_BUFF_DIS);
4404 + set_cs3_bit(PCMCIA_BUFF_DIS);
4406 - restore_flags(flags);
4407 + if(configure->irq) {
4408 + enable_irq(IRQ_GPIO_CF_IRQ);
4412 + if (!irq_disabled) {
4413 + disable_irq(IRQ_GPIO_CF_IRQ);
4418 + //local_irq_restore(flags);
4423 static int simpad_pcmcia_socket_init(int sock)
4425 - set_GPIO_IRQ_edge(GPIO_CF_CD, GPIO_BOTH_EDGES);
4427 + set_GPIO_IRQ_edge(GPIO_CF_CD, GPIO_BOTH_EDGES);
4431 static int simpad_pcmcia_socket_suspend(int sock)
4433 - set_GPIO_IRQ_edge(GPIO_CF_CD, GPIO_NO_EDGES);
4436 + set_GPIO_IRQ_edge(GPIO_CF_CD, GPIO_NO_EDGES);
4437 + set_cs3_bit(PCMCIA_RESET);
4442 --- linux-2.4.27/drivers/video/Config.in~2.4.27-vrs1-pxa1-jpm1
4443 +++ linux-2.4.27/drivers/video/Config.in
4447 dep_tristate ' CyberPro 2000/2010/5000 support' CONFIG_FB_CYBER2000 $CONFIG_PCI
4448 + if [ "$CONFIG_SA1100_SIMPAD" = "y" -o \
4449 + "$CONFIGG_SA1100_GDS2200" = "y" ]; then
4450 + bool ' MQ200 VGA support' CONFIG_FB_MQ200
4452 if [ "$CONFIG_APOLLO" = "y" ]; then
4453 define_bool CONFIG_FB_APOLLO y
4455 --- linux-2.4.27/drivers/video/Makefile~2.4.27-vrs1-pxa1-jpm1
4456 +++ linux-2.4.27/drivers/video/Makefile
4458 obj-$(CONFIG_FB_PVR2) += pvr2fb.o
4459 obj-$(CONFIG_FB_VOODOO1) += sstfb.o
4460 obj-$(CONFIG_FB_ANAKIN) += anakinfb.o
4461 +obj-$(CONFIG_FB_MQ200) += mq200fb.o
4463 # Generic Low Level Drivers
4466 +++ linux-2.4.27/drivers/video/mq200fb.c
4468 +/* MQ200 console frame buffer driver---mq200fb.c
4471 + * This file is subject to the terms and conditions of the GNU General Public
4472 + * License. See the file COPYING in the main directory of this archive for
4476 +#include <linux/config.h>
4477 +#include <linux/module.h>
4478 +#include <linux/kernel.h>
4479 +#include <linux/errno.h>
4480 +#include <linux/string.h>
4481 +#include <linux/mm.h>
4482 +#include <linux/tty.h>
4483 +#include <linux/slab.h>
4484 +#include <linux/vmalloc.h>
4485 +#include <linux/delay.h>
4486 +#include <linux/pm.h>
4487 +#include <linux/interrupt.h>
4488 +#include <linux/proc_fs.h> /* all the /proc functions */
4489 +#include <linux/ioport.h>
4490 +#include <asm/uaccess.h>
4491 +#include <linux/fb.h>
4492 +#include <linux/init.h>
4493 +#include <linux/pci.h>
4494 +#include <asm/io.h>
4496 +#include <linux/console.h>
4498 +#include <video/fbcon.h>
4499 +#ifdef CONFIG_FBCON_MFB
4500 +#include <video/fbcon-mfb.h>
4502 +#ifdef CONFIG_FBCON_CFB2
4503 +#include <video/fbcon-cfb2.h>
4505 +#ifdef CONFIG_FBCON_CFB4
4506 +#include <video/fbcon-cfb4.h>
4508 +#ifdef CONFIG_FBCON_CFB8
4509 +#include <video/fbcon-cfb8.h>
4511 +#ifdef CONFIG_FBCON_CFB16
4512 +#include <video/fbcon-cfb16.h>
4514 +#ifdef CONFIG_FBCON_CFB24
4515 +#include <video/fbcon-cfb24.h>
4517 +#ifdef CONFIG_FBCON_CFB32
4518 +#include <video/fbcon-cfb32.h>
4521 +#include <video/MQ200/mq2hw.h>
4522 +#include <video/MQ200/mqdata.h>
4523 +#include <video/MQ200/mqplat.h>
4525 +/* GPIO handling */
4526 +#include <asm/irq.h>
4527 +#include <asm/hardware.h>
4530 +#undef PDEBUG /* Safety */
4532 +#define PDEBUG(fmt, args...) printk(KERN_EMERG fmt, ##args)
4534 +#define PDEBUG(fmt, args...)
4537 +#define MQ200_DIRNAME "driver/mq200"
4538 +#define REG_DIRNAME "registers"
4540 +void enable_cursor(void *pMQMMIO);
4542 +static ssize_t proc_read_reg(struct file * file, char * buf,
4543 + size_t nbytes, loff_t *ppos);
4544 +static ssize_t proc_write_reg(struct file * file, const char * buffer,
4545 + size_t count, loff_t *ppos);
4547 +static struct file_operations proc_reg_operations = {
4548 + read: proc_read_reg,
4549 + write: proc_write_reg
4552 +typedef struct sa1110_reg_entry {
4555 + char* description;
4556 + unsigned short low_ino;
4557 +} sa1110_reg_entry_t;
4559 +#define CMAPSIZE 32
4560 +#define arraysize(x) (sizeof(x)/sizeof(*(x)))
4562 +#define mq200_p2v( x ) \
4563 + (((x) - 0x4b800000) + 0xf2800000)
4565 +/* The following is copied from mq2hw.c for initialization of MQ200 */
4567 +#define PLL1_83MHZ 0x0EF2082A
4568 +#define DEF_MIU2_83MHZ 0x4143E086
4569 +#define PLL1_50MHZ 0x0B200A2A
4570 +#define DEF_MIU2_50MHZ 0x40C30086
4572 +/* Miscellaneous default data */
4573 +#define DEF_D1 0x05000271
4574 +#define DEF_D2 0x00000271
4575 +#define DEF_MIU3 0x6D6AABFF
4576 +#define DEF_MIU4 0x00000001
4577 +#define DEF_MIU5 0x0000010D
4579 +#ifdef CONFIG_SA1100_GDS2200
4580 +#define DEF_GPO_CONTROL 0x00020054
4582 +#define DEF_GPO_CONTROL 0x00000000
4585 +#define DEF_GPIO_CONTROL 0x00000000
4586 +#define DEF_PWM_CONTROL 0x00A16c44
4587 +#define PWMOFFMASK 0xFF0FFF0F
4589 +struct fb_info_mq200 {
4590 + struct fb_info fb_info;
4591 + struct fb_fix_screeninfo fix;
4592 + struct fb_var_screeninfo var;
4593 + struct display disp;
4595 + __u8 red, green, blue;
4597 + struct fb_info_mq200 *next;
4598 + unsigned int mqMmioAddrVirt;
4599 + unsigned int mqFbAddrVirt;
4600 + unsigned int mqMmioAddrPhys;
4601 + unsigned int mqFbAddrPhys;
4603 + struct pm_dev *pm;
4608 +u32 mqMmioAddr, mqFbAddr;
4610 +/* Interface need to console.c. The following variable are defined in
4611 + drivers/char/console.c */
4613 +extern unsigned char color_table[];
4614 +extern int default_red[];
4615 +extern int default_grn[];
4616 +extern int default_blu[];
4618 +#ifdef CONFIG_SA1100_SIMPAD
4619 + extern void set_cs3_bit(int value);
4620 + extern void clear_cs3_bit(int value);
4621 + DISPLAY_CONFIG dc = {800, 600, 16, 60, 1600, 0x00130004};
4623 + DISPLAY_CONFIG dc = {800, 600, 32, 60, 3200, 0x0023000f};
4626 +static int currcon = 0;
4627 +static char mq200fb_name[16] = "MQ200FB";
4629 +static struct fb_var_screeninfo mq200fb_default = {
4630 + /* 800x600, 32 bpp */
4631 + 800, 600, 800, 600, 0, 0, 32, 0,
4632 + {0, 8, 0}, {8, 8, 0}, {16, 8, 0}, {24, 8, 0},
4633 + 0, 0, -1, -1, 0, MQ200_FB_SIZE, 64, 64, 32, 32, 64, 2,
4634 + 0, FB_VMODE_NONINTERLACED
4637 + u16 cfb16[CMAPSIZE];
4638 + u32 cfb24[CMAPSIZE];
4639 + u32 cfb32[CMAPSIZE];
4642 +static struct proc_dir_entry *regdir;
4643 +static struct proc_dir_entry *mq200dir;
4644 +static struct proc_dir_entry *driverdir;
4646 +/* Functions used to initialize MQ200 chip */
4647 +void setmqmode(PDISPLAY_CONFIG, void *);
4648 +void setup_cursor(void *);
4649 +void onoffdisplay(int, void *);
4650 +unsigned long getbppbits(int);
4651 +PDISPLAY_TIMING getgcparam(int, int, int);
4652 +void setpal(int, unsigned long, void *);
4653 +void setupfp(int, void *);
4654 +void setuphfbuffer(int, unsigned long, void *);
4655 +void setupgc(int, int, int, int, int, void *);
4656 +void setupgcmem(PDISPLAY_CONFIG, unsigned long, void *);
4657 +long idmqchip(void *pMQMMIO);
4658 +void turnoffMQ200(void * pMQMMIO);
4660 +/* Interface used by the world */
4661 +int mq200fb_setup(char*);
4662 +static int mq200fb_open(struct fb_info *info, int user);
4663 +static int mq200fb_release (struct fb_info *info, int user);
4664 +static int mq200fb_get_fix(struct fb_fix_screeninfo *fix, int con, \
4665 + struct fb_info *info);
4666 +static int mq200fb_get_var(struct fb_var_screeninfo *var, int con, \
4667 + struct fb_info *info);
4668 +static int mq200fb_set_var(struct fb_var_screeninfo *var, int con, \
4669 + struct fb_info *info);
4670 +static int mq200fb_pan_display(struct fb_var_screeninfo *var, int con, \
4671 + struct fb_info *info);
4672 +static int mq200fb_get_cmap(struct fb_cmap *cmap, int kspc, int con, \
4673 + struct fb_info *info);
4674 +static int mq200fb_set_cmap(struct fb_cmap *cmap, int kspc, int con, \
4675 + struct fb_info *info);
4676 +static int mq200fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
4677 + u_long arg, int con, struct fb_info *info);
4679 +/* Interface to the low level console driver */
4680 +int mq200fb_init(void);
4681 +static int mq200fbcon_switch(int con, struct fb_info *info);
4682 +static int mq200fbcon_updatevar(int con, struct fb_info *info);
4683 +static void mq200fbcon_blank(int blank, struct fb_info *info);
4685 +/* int sa1100fb_map_video_memory(void * pmem int memsize); */
4688 + *Internal routines
4691 +static u_long get_line_length(int xres_virtual, int bpp);
4692 +static void mq200fb_encode_fix(struct fb_fix_screeninfo *fix,
4693 + struct fb_var_screeninfo *var);
4694 +static void set_color_bitfields(struct fb_var_screeninfo *var);
4695 +static int mq200fb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
4696 + u_int *transp, struct fb_info *info);
4697 +static int mq200fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
4698 + u_int transp, struct fb_info *info);
4699 +static void do_install_cmap(int con, struct fb_info *info);
4702 +static int mq200fb_pm_callback(struct pm_dev *, pm_request_t, void *);
4705 +#if defined(CONFIG_SA1100_GDS2200) || defined(CONFIG_SA1100_SIMPAD)
4706 +static void mq200_backlight(void *, int);
4709 +#ifdef CONFIG_SA1100_SIMPAD
4710 +static void writeBrightness(void *, int);
4713 +static struct fb_ops mq200fb_ops = {
4714 + owner: THIS_MODULE,
4715 + fb_get_fix: mq200fb_get_fix,
4716 + fb_get_var: mq200fb_get_var,
4717 + fb_set_var: mq200fb_set_var,
4718 + fb_get_cmap: mq200fb_get_cmap,
4719 + fb_set_cmap: mq200fb_set_cmap,
4720 + fb_pan_display: mq200fb_pan_display,
4721 + fb_ioctl: mq200fb_ioctl,
4724 +typedef struct mq200_reg_entry {
4727 + char* description;
4728 + unsigned short low_ino;
4729 +} mq200_reg_entry_t;
4731 +static mq200_reg_entry_t mq200_regs[] =
4733 + { 0x4be00000, "PM_MISC", "MQ200 PM_MISC" },
4734 + { 0x4be00004, "D1_STATE", "MQ200 D1_STATE" },
4735 + { 0x4be00008, "D2_STATE", "MQ200 D2_STATE" },
4736 + { 0x4be00018, "PLL2_CONTROL", "MQ200 PLL2_CONTROL" },
4737 + { 0x4be0001c, "PLL3_CONTROL", "MQ200 PLL3_CONTROL" },
4738 + { 0x4be02000, "CPU_CONTROL", "MQ200 CPU_CONTROL" },
4739 + { 0x4be02004, "DRAW_STATUS", "MQ200 DRAW_STATUS" },
4740 + { 0x4be04000, "MIU_CONTROL1", "MQ200 MIU_CONTROL1" },
4741 + { 0x4be04004, "MIU_CONTROL2", "MQ200 MIU_CONTROL2" },
4742 + { 0x4be04008, "MIU_CONTROL3", "MQ200 MIU_CONTROL3" },
4743 + { 0x4be0400c, "MIU_CONTROL4", "MQ200 MIU_CONTROL4" },
4744 + { 0x4be04010, "MIU_CONTROL5", "MQ200 MIU_CONTROL5" },
4745 + { 0x4be0a000, "GC1_CONTROL", "MQ200 GC1_CONTROL" },
4746 + { 0x4be0a004, "GC1_CRT_CONTROL", "MQ200 GC1_CRT_CONTROL" },
4747 + { 0x4be0a008, "HD1_CONTROL", "MQ200 HD1_CONTROL" },
4748 + { 0x4be0a00c, "VD1_CONTROL", "MQ200 VD1_CONTROL" },
4749 + { 0x4be0a010, "HS1_CONTROL", "MQ200 HS1_CONTROL" },
4750 + { 0x4be0a014, "VS1_CONTROL", "MQ200 VS1_CONTROL" },
4751 + { 0x4be0a020, "HW1_CONTROL", "MQ200 HW1_CONTROL" },
4752 + { 0x4be0a024, "VW1_CONTROL", "MQ200 VW1_CONTROL" },
4753 + { 0x4be0a040, "HW_CURSOR1_POS", "MQ200 HW_CURSOR1_POS" },
4754 + { 0x4be0a044, "HW_CURSOR1_ADDR", "MQ200 HW_CURSOR1_ADDR" },
4755 + { 0x4be0e000, "FP_CONTROL", "MQ200 FP_CONTROL" },
4756 + { 0x4be0e004, "FP_PIN_CONTROL", "MQ200 FP_PIN_CONTROL" },
4757 + { 0x4be0e008, "FP_GPO_CONTROL", "MQ200 FP_GPO_CONTROL" },
4758 + { 0x4be0e00c, "FP_GPIO_CONTROL", "MQ200 FP_GPIO_CONTROL" },
4759 + { 0x4be0e010, "STN_CONTROL", "MQ200 STN_CONTROL" },
4760 + { 0x4be0e014, "DSTN_FB_CONTROL", "MQ200 DSTN_FB_CONTROL" },
4761 + { 0x4be0e03c, "PWM_CONTROL", "MQ200 PWM_CONTROL" },
4762 + { 0x4be14000, "DC_0", "MQ200 DC_1" },
4763 + { 0x4be14004, "DC_1", "MQ200 DC_2" },
4764 + { 0x4be14008, "DC_SW_0", "MQ200 DC_SW_0" },
4765 + { 0x4be1400c, "DC_SW_1", "MQ200 DC_SW_1" },
4766 + { 0x4be16040, "PMR", "MQ200 PMR" },
4767 + { 0x4be16044, "PMCSR", "MQ200 PMCSR" }
4770 +#define NUM_OF_MQ200_REG_ENTRY (sizeof(mq200_regs)/sizeof(mq200_reg_entry_t))
4772 +static int mq200fb_open(struct fb_info *info, int user)
4775 + * Nothing, only a usage count for the moment
4777 + MOD_INC_USE_COUNT;
4782 +/* Release console */
4783 +static int mq200fb_release (struct fb_info *info, int user)
4785 + struct fb_info_mq200 *p = (struct fb_info_mq200 *) info;
4786 + turnoffMQ200((void *) p->mqMmioAddrVirt);
4787 + MOD_DEC_USE_COUNT;
4790 +/* Get the Fixed Part of the Display */
4791 +static int mq200fb_get_fix(struct fb_fix_screeninfo *fix, int con,
4792 + struct fb_info *info)
4794 + struct fb_info_mq200 *p = (struct fb_info_mq200 *) info;
4796 + PDEBUG("mq200fb: %i---in mq200fb_get_fix.\n", __LINE__);
4805 + * Get the User Defined Part of the Display
4808 +static int mq200fb_get_var(struct fb_var_screeninfo *var, int con,
4809 + struct fb_info *info)
4811 + struct fb_info_mq200 *p = (struct fb_info_mq200 *) info;
4813 + PDEBUG("mq200fb: %i---in mq200fb_get_var.\n", __LINE__);
4821 + * Set the User Defined Part of the Display
4824 +static int mq200fb_set_var(struct fb_var_screeninfo *var, int con,
4825 + struct fb_info *info)
4827 + struct fb_info_mq200 * p = (struct fb_info_mq200 *) info;
4828 + int err, activate = var->activate;
4829 + int oldxres, oldyres, oldvxres, oldvyres, oldbpp;
4830 + u_long line_length;
4832 + struct display *display;
4834 + PDEBUG("mq200fb: %i---in mq200fb_set_var.\n", __LINE__);
4837 + display = &fb_display[con];
4839 + display = &(p->disp); /* used during initialization */
4842 + * FB_VMODE_CONUPDATE and FB_VMODE_SMOOTH_XPAN are equal!
4843 + * as FB_VMODE_SMOOTH_XPAN is only used internally
4846 + if (var->vmode & FB_VMODE_CONUPDATE) {
4847 + var->vmode |= FB_VMODE_YWRAP;
4848 + var->xoffset = display->var.xoffset;
4849 + var->yoffset = display->var.yoffset;
4855 + line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
4856 + if (line_length*var->yres_virtual > MQ200_FB_SIZE)
4859 + set_color_bitfields(var);
4861 + if ((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
4862 + oldxres = display->var.xres;
4863 + oldyres = display->var.yres;
4864 + oldvxres = display->var.xres_virtual;
4865 + oldvyres = display->var.yres_virtual;
4866 + oldbpp = display->var.bits_per_pixel;
4867 + display->var = *var;
4868 + if (oldxres != var->xres || oldyres != var->yres ||
4869 + oldvxres != var->xres_virtual || oldvyres != var->yres_virtual ||
4870 + oldbpp != var->bits_per_pixel) {
4872 + display->screen_base = (char *) p->mqFbAddrVirt;
4873 + display->visual = p->fix.visual;
4874 + display->type = p->fix.type;
4875 + display->type_aux = p->fix.type_aux;
4876 + display->ypanstep = p->fix.ypanstep;
4877 + display->ywrapstep = p->fix.ywrapstep;
4878 + display->line_length = p->fix.line_length;
4879 + display->can_soft_blank = 1;
4880 + display->inverse = 0;
4882 + switch (var->bits_per_pixel) {
4883 +#ifdef CONFIG_FBCON_MFB
4885 + display->dispsw = &fbcon_mfb;
4888 +#ifdef CONFIG_FBCON_CFB2
4890 + display->dispsw = &fbcon_cfb2;
4893 +#ifdef CONFIG_FBCON_CFB4
4895 + display->dispsw = &fbcon_cfb4;
4898 +#ifdef CONFIG_FBCON_CFB8
4900 + display->dispsw = &fbcon_cfb8;
4903 +#ifdef CONFIG_FBCON_CFB16
4905 + display->dispsw = &fbcon_cfb16;
4906 + display->dispsw_data = fbcon_cmap.cfb16;
4909 +#ifdef CONFIG_FBCON_CFB24
4911 + display->dispsw = &fbcon_cfb24;
4912 + display->dispsw_data = fbcon_cmap.cfb24;
4915 +#ifdef CONFIG_FBCON_CFB32
4917 + display->dispsw = &fbcon_cfb32;
4918 + display->dispsw_data = fbcon_cmap.cfb32;
4922 + display->dispsw = &fbcon_dummy;
4927 + if (p->fb_info.changevar)
4928 + (*p->fb_info.changevar)(con);
4931 + if (oldbpp != var->bits_per_pixel) {
4932 + if ((err = fb_alloc_cmap(&display->cmap, 0, 0)))
4934 + do_install_cmap(con, info);
4944 + * Pan or Wrap the Display
4946 + * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
4949 +static int mq200fb_pan_display(struct fb_var_screeninfo *var, int con,
4950 + struct fb_info *info)
4952 + PDEBUG("mq200fb: %i---mq200fb_pan_display.\n", __LINE__);
4954 + if (var->vmode & FB_VMODE_YWRAP) {
4955 + if (var->yoffset < 0 ||
4956 + var->yoffset >= fb_display[con].var.yres_virtual ||
4960 + if (var->xoffset+fb_display[con].var.xres >
4961 + fb_display[con].var.xres_virtual ||
4962 + var->yoffset+fb_display[con].var.yres >
4963 + fb_display[con].var.yres_virtual)
4966 + fb_display[con].var.xoffset = var->xoffset;
4967 + fb_display[con].var.yoffset = var->yoffset;
4968 + if (var->vmode & FB_VMODE_YWRAP)
4969 + fb_display[con].var.vmode |= FB_VMODE_YWRAP;
4971 + fb_display[con].var.vmode &= ~FB_VMODE_YWRAP;
4976 + * Get the Colormap
4979 +static int mq200fb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
4980 + struct fb_info *info)
4982 + PDEBUG("mq200fb: %i---mq200fb_get_cmap.\n", __LINE__);
4984 + if (con == currcon) /* current console? */
4985 + return fb_get_cmap(cmap, kspc, mq200fb_getcolreg, info);
4986 + else if (fb_display[con].cmap.len) /* non default colormap? */
4987 + fb_copy_cmap(&fb_display[con].cmap, cmap, kspc ? 0 : 2);
4990 + int size = (fb_display[con].var.bits_per_pixel <= 8) ? 256 : 16;
4991 + fb_copy_cmap(fb_default_cmap(size), cmap, kspc ? 0 : 2);
4997 + * Set the Colormap
5000 +static int mq200fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
5001 + struct fb_info *info)
5005 + PDEBUG("mq200fb: %i---mq200fb_set_cmap.\n", __LINE__);
5007 + if (!fb_display[con].cmap.len) { /* no colormap allocated? */
5008 + int size = (fb_display[con].var.bits_per_pixel <= 8) ? 256 : 16;
5009 + if ((err = fb_alloc_cmap(&fb_display[con].cmap, size, 0)))
5012 + if (con == currcon) /* current console? */
5013 + return fb_set_cmap(cmap, kspc, mq200fb_setcolreg, info);
5015 + fb_copy_cmap(cmap, &fb_display[con].cmap, kspc ? 0 : 1);
5020 +static int mq200fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
5021 + u_long arg, int con, struct fb_info *info)
5027 +int __init mq200fb_setup(char *options)
5029 + PDEBUG("mq200fb.c: %i---mq200fb_setup\n", __LINE__);
5034 + fb_info.fontname[0] = '\0';
5036 + if (!options || !*options)
5039 + for (this_opt = strtok(options, ","); this_opt;
5040 + this_opt = strtok(NULL, ",")) {
5041 + if (!strncmp(this_opt, "font:", 5))
5042 + strcpy(fb_info.fontname, this_opt+5);
5053 +int __init mq200fb_init(void)
5055 + struct fb_info_mq200 *p = NULL;
5056 + int i; /* used as loop counter */
5057 + struct proc_dir_entry *entry;
5059 + p = (struct fb_info_mq200 *) kmalloc(sizeof(*p), GFP_ATOMIC);
5062 + memset(p, 0, sizeof(*p));
5064 + mq200dir = proc_mkdir(MQ200_DIRNAME, NULL);
5065 + if (mq200dir == NULL) {
5066 + printk(KERN_ERR "mq200fb: can't create /proc/" MQ200_DIRNAME "\n");
5070 + regdir = proc_mkdir(REG_DIRNAME, mq200dir);
5071 + if (regdir == NULL) {
5072 + printk(KERN_ERR "mq200fb: can't create /proc/" MQ200_DIRNAME "/" REG_DIRNAME "\n");
5076 + for(i=0;i<NUM_OF_MQ200_REG_ENTRY;i++) {
5077 + entry = create_proc_entry(mq200_regs[i].name,
5078 + S_IWUSR |S_IRUSR | S_IRGRP | S_IROTH,
5081 + mq200_regs[i].low_ino = entry->low_ino;
5082 + entry->proc_fops = &proc_reg_operations;
5086 + "mq200fb: can't create /proc/" REG_DIRNAME
5087 + "/%s\n", mq200_regs[i].name);
5095 +#ifdef CONFIG_SA1100_ASSABET
5096 + pCPUReg=(u32 *)ioremap( MSC2, 4);
5097 + *pCPUReg = 0x42194449;
5098 + iounmap((void *) pCPUReg);
5100 + GPDR |= 0x08000000;
5101 + GAFR |= 0x08000000;
5102 + TUCR |= 0x20000000;
5104 + ASSABET_BCR_set(ASSABET_BCR_GFX_RST); /* ASSABET_BCR */
5107 + ASSABET_BCR_clear(ASSABET_BCR_GFX_RST);
5109 + ASSABET_BCR_set(ASSABET_BCR_GFX_RST); /* ASSABET_BCR */
5112 +#ifdef CONFIG_SA1100_SIMPAD
5118 + p->mqMmioAddrPhys=REGISTER_BASE;
5119 + p->mqFbAddrPhys=FB_BASE;
5121 + p->mqMmioAddrVirt = mqMmioAddr = 0xf2e00000;
5122 + p->mqFbAddrVirt = mqFbAddr = 0xf2800000;
5124 +#endif /* MQ_SA1110 */
5128 + PDEBUG("mq200fb.c: line %i, mqMmioAddr = 0X%08X, mqFbAddr = 0X%08X\n",\
5129 + __LINE__, mqMmioAddr, mqFbAddr);
5131 + /* Setmode for MQ200 chip */
5132 + setmqmode(&dc, (void *) mqMmioAddr);
5134 + /* Set fb_info_mq200.fix info */
5135 + strcpy(p->fix.id, mq200fb_name);
5136 + p->fix.smem_start = p->mqFbAddrPhys;
5137 + p->fix.smem_len = MQ200_FB_SIZE;
5138 + p->fix.mmio_start = p->mqMmioAddrPhys;
5139 + p->fix.mmio_len = MQ200_MMIO_SIZE;
5140 + p->fix.type = FB_TYPE_PACKED_PIXELS;
5143 + p->fix.visual = FB_VISUAL_PSEUDOCOLOR;
5144 + else if (dc.bpp >= 16)
5145 + p->fix.visual = FB_VISUAL_DIRECTCOLOR;
5147 + p->fix.line_length = dc.stride;
5149 + /* Set fb_info_mq200.var info */
5150 + p->var.xres = dc.x;
5151 + p->var.yres = dc.y;
5152 + p->var.xres_virtual = dc.x;
5153 + p->var.yres_virtual = dc.y;
5154 + p->var.bits_per_pixel = dc.bpp;
5157 + p->var.red.offset = 0;
5158 + p->var.green.offset = 0;
5159 + p->var.blue.offset = 0;
5160 + p->var.red.length = p->var.green.length = \
5161 + p->var.blue.length = dc.bpp;
5162 + p->var.transp.length = 0;
5163 + p->var.transp.offset = 0;
5165 + else if(dc.bpp == 16) {
5168 + p->var.red.offset = 2;
5169 + p->var.green.offset = -3;
5170 + p->var.blue.offset = 8;
5172 + p->var.red.offset = 11;
5173 + p->var.green.offset = 5;
5174 + p->var.blue.offset = 0;
5177 + p->var.red.length = 5;
5178 + p->var.green.length = 6;
5179 + p->var.blue.length = 5;
5181 + else if (dc.bpp == 24) {
5183 + p->var.red.offset = 8;
5184 + p->var.green.offset = 16;
5185 + p->var.blue.offset = 24;
5187 + p->var.red.offset = 16;
5188 + p->var.green.offset = 8;
5189 + p->var.blue.offset = 0;
5191 + p->var.red.length = 8;
5192 + p->var.green.length = 8;
5193 + p->var.blue.length = 8;
5195 + else if(dc.bpp == 32) {
5197 + p->var.red.offset = 8;
5198 + p->var.green.offset = 16;
5199 + p->var.blue.offset = 24;
5201 + p->var.red.offset = 0;
5202 + p->var.green.offset = 8;
5203 + p->var.blue.offset = 16;
5204 +#endif /* CONFIG_PREP */
5205 + p->var.red.length = 8;
5206 + p->var.green.length = 8;
5207 + p->var.blue.length = 8;
5210 + p->var.transp.length = 0;
5211 + p->var.transp.offset = 0;
5212 + p->var.height = p->var.width = -1;
5213 + p->var.vmode = FB_VMODE_NONINTERLACED;
5214 + p->var.pixclock = 10000;
5215 + p->var.left_margin = p->var.right_margin = 16;
5216 + p->var.upper_margin = p->var.lower_margin = 16;
5217 + p->var.hsync_len = p->var.vsync_len = 8;
5219 + /* Set fb_info_mq200.disp info */
5220 + p->disp.var = p->var;
5221 + p->disp.cmap.red = NULL;
5222 + p->disp.cmap.green = NULL;
5223 + p->disp.cmap.blue = NULL;
5224 + p->disp.cmap.transp = NULL;
5225 + p->disp.screen_base = (char *) p->mqFbAddrVirt;
5226 + p->disp.visual = p->fix.visual;
5227 + p->disp.type = p->fix.type;
5228 + p->disp.type_aux = p->fix.type_aux;
5229 + p->disp.line_length = p->fix.line_length;
5230 + p->disp.can_soft_blank = 1;
5233 +#ifdef CONFIG_FBCON_CFB8
5235 + p->disp.dispsw = &fbcon_cfb8;
5238 +#ifdef CONFIG_FBCON_CFB16
5240 + p->disp.dispsw = &fbcon_cfb16;
5241 + p->disp.dispsw_data = fbcon_cmap.cfb16;
5244 +#ifdef CONFIG_FBCON_CFB24
5246 + p->disp.dispsw = &fbcon_cfb24;
5247 + p->disp.dispsw_data = fbcon_cmap.cfb24;
5250 +#ifdef CONFIG_FBCON_CFB32
5252 + p->disp.dispsw = &fbcon_cfb32;
5253 + p->disp.dispsw_data = fbcon_cmap.cfb32;
5257 + PDEBUG("mq200fb.c: %i---Wrong configuration options", __LINE__);
5260 + p->disp.scrollmode = SCROLL_YREDRAW;
5262 + strcpy(p->fb_info.modename, p->fix.id);
5263 + p->fb_info.changevar = NULL;
5264 + p->fb_info.node = NODEV;
5266 + p->fb_info.fbops = &mq200fb_ops;
5267 + p->fb_info.disp = &(p->disp);
5268 + p->fb_info.switch_con = &mq200fbcon_switch;
5269 + p->fb_info.updatevar = &mq200fbcon_updatevar;
5270 + p->fb_info.blank = &mq200fbcon_blank;
5271 + p->fb_info.flags = FBINFO_FLAG_DEFAULT;
5273 + for (i = 0; i < 16; i++) {
5274 + int j = color_table[i];
5275 + p->palette[i].red = default_red[j];
5276 + p->palette[i].green = default_grn[j];
5277 + p->palette[i].blue = default_blu[j];
5280 + if (register_framebuffer(&p->fb_info) < 0) {
5281 + PDEBUG("Oops...register_framebuffer failed!\n");
5283 + iounmap((void *)mqMmioAddr);
5284 + iounmap((void *)mqFbAddr);
5290 + * Note that the console registers this as well, but we want to
5291 + * power down the display prior to sleeping.
5293 + p->pm = pm_register(PM_SYS_DEV, PM_SYS_VGA, mq200fb_pm_callback);
5297 + PDEBUG("fb%d: Virtual frame buffer device, using %ldK of video memory\n", \
5298 + GET_FB_IDX(p->fb_info.node), MQ200_FB_SIZE >> 10);
5302 +static int mq200fbcon_switch(int con, struct fb_info *info)
5304 + /* Do we have to save the colormap? */
5306 + PDEBUG("mq200fb: mq200fbcon_switch.\n");
5308 + if (fb_display[currcon].cmap.len)
5309 + fb_get_cmap(&fb_display[currcon].cmap, 1, mq200fb_getcolreg, info);
5312 + /* Install new colormap */
5313 + do_install_cmap(con, info);
5318 + * Update the `var' structure (called by fbcon.c)
5321 +static int mq200fbcon_updatevar(int con, struct fb_info *info)
5325 + PDEBUG("mq200fb: mq200fbcon_updatevar.\n");
5331 + * Blank the display.
5334 +static void mq200fbcon_blank(int blank, struct fb_info *info)
5336 + /*struct fb_info_mq200 *p = (struct fb_info_mq200 *) info;*/
5341 + onoffdisplay(DISABLE_LCD_GC1, (void *) p->mqMmioAddrVirt);
5343 + onoffdisplay(ENABLE_LCD_GC1, (void *) p->mqMmioAddrVirt);*/
5346 +static u_long get_line_length(int xres_virtual, int bpp)
5350 + PDEBUG("mq200fb: get_line_length.\n");
5352 + length = (xres_virtual+bpp-1)/bpp;
5353 + length = (length+31)&-32;
5358 +static void mq200fb_encode_fix(struct fb_fix_screeninfo *fix,
5359 + struct fb_var_screeninfo *var)
5362 + PDEBUG("mq200fb: mq200fb_encode_fix.\n");
5364 + memset(fix, 0, sizeof(struct fb_fix_screeninfo));
5365 + strcpy(fix->id, mq200fb_name);
5366 + fix->smem_start = mqFbAddr;
5367 + fix->smem_len = MQ200_FB_SIZE;
5368 + fix->type = FB_TYPE_PACKED_PIXELS;
5369 + fix->type_aux = 0;
5370 + switch (var->bits_per_pixel) {
5372 + fix->visual = FB_VISUAL_MONO01;
5377 + fix->visual = FB_VISUAL_PSEUDOCOLOR;
5382 + fix->visual = FB_VISUAL_DIRECTCOLOR;
5385 + fix->ywrapstep = 1;
5386 + fix->xpanstep = 1;
5387 + fix->ypanstep = 1;
5388 + fix->line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
5391 +static void set_color_bitfields(struct fb_var_screeninfo *var)
5394 + PDEBUG("mq200fb: set_color_bitfields.\n");
5396 + switch (var->bits_per_pixel) {
5399 + var->red.offset = 0;
5400 + var->red.length = 8;
5401 + var->green.offset = 0;
5402 + var->green.length = 8;
5403 + var->blue.offset = 0;
5404 + var->blue.length = 8;
5405 + var->transp.offset = 0;
5406 + var->transp.length = 0;
5408 + case 16: /* RGB 565 */
5410 + var->red.offset = 2;
5411 + var->green.offset = -3;
5412 + var->blue.offset = 8;
5414 + var->red.offset = 11;
5415 + var->green.offset = 5;
5416 + var->blue.offset = 0;
5418 + var->red.length = 5;
5419 + var->green.length = 6;
5420 + var->blue.length = 5;
5421 + var->transp.length = 0;
5422 + var->transp.offset = 0;
5424 + case 24: /* RGB 888 */
5426 + var->red.offset = 8;
5427 + var->green.offset = 16;
5428 + var->blue.offset = 24;
5430 + var->red.offset = 16;
5431 + var->green.offset = 8;
5432 + var->blue.offset = 0;
5434 + var->red.length = 8;
5435 + var->green.length = 8;
5436 + var->blue.length = 8;
5438 + case 32: /* RGBA 8888 */
5439 + var->red.offset = 0;
5440 + var->red.length = 8;
5441 + var->green.offset = 8;
5442 + var->green.length = 8;
5443 + var->blue.offset = 16;
5444 + var->blue.length = 8;
5445 + var->transp.offset = 24;
5446 + var->transp.length = 8;
5449 + var->red.msb_right = 0;
5450 + var->green.msb_right = 0;
5451 + var->blue.msb_right = 0;
5452 + var->transp.msb_right = 0;
5457 + * Read a single color register and split it into
5458 + * colors/transparent. Return != 0 for invalid regno.
5461 +static int mq200fb_getcolreg(u_int regno, u_int *red, u_int *green,
5462 + u_int *blue, u_int *transp, struct fb_info *info)
5464 + struct fb_info_mq200 *p = (struct fb_info_mq200 *) info;
5466 + /*PDEBUG("mq200fb: mq200fb_getcolreg.\n");*/
5470 + *red = (p->palette[regno].red<<8) | p->palette[regno].red;
5471 + *green = (p->palette[regno].green<<8) | p->palette[regno].green;
5472 + *blue = (p->palette[regno].blue<<8) | p->palette[regno].blue;
5479 + * Set a single color register. The values supplied are already
5480 + * rounded down to the hardware's capabilities (according to the
5481 + * entries in the var structure). Return != 0 for invalid regno.
5484 +static int mq200fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
5485 + u_int transp, struct fb_info *info)
5487 + struct fb_info_mq200 *p = (struct fb_info_mq200 *) info;
5488 + unsigned long color;
5493 + /*PDEBUG("In mq200fb_setcolreg, regno = %d, 0x%0x\n", regno, red);*/
5495 + /*PDEBUG("mq200fb: mq200fb_setcolreg.\n");*/
5497 + switch (p->var.bits_per_pixel) {
5498 +#ifdef CONFIG_FBCON_CFB16
5500 + if(regno < CMAPSIZE)
5502 + fbcon_cmap.cfb16[regno] =
5503 + ((red & 0xf800) >> 9) |
5504 + ((green & 0xf800) >> 14) |
5505 + ((green & 0xf800) << 2) | ((blue & 0xf800) >> 3);
5507 + fbcon_cmap.cfb16[regno] =
5508 + ((red & 0xf800) >> 0) |
5509 + ((green & 0xf800) >> 5) | ((blue & 0xf800) >> 11);
5511 +#endif /* CONFIG_PREP */
5514 +#ifdef CONFIG_FBCON_CFB24
5516 + if (regno < CMAPSIZE)
5518 + fbcon_cmap.cfb24[regno] =
5519 + ((red & 0xff00)) |
5520 + ((green & 0xff00) << 8) | ((blue & 0xff00) << 16);
5522 + fbcon_cmap.cfb24[regno] =
5523 + ((red & 0xff00) << 8) |
5524 + ((green & 0xff00)) | ((blue & 0xff00) >> 8);
5528 +#ifdef CONFIG_FBCON_CFB32
5530 + if(regno < CMAPSIZE)
5532 + fbcon_cmap.cfb32[regno] =
5533 + ((red & 0xff00)) |
5534 + ((green & 0xff00) << 8) | ((blue & 0xff00) << 16);
5536 + fbcon_cmap.cfb32[regno] =
5537 + ((red & 0xff00) >> 8) |
5538 + ((green & 0xff00)) | ((blue & 0xff00) << 8);
5551 + p->palette[regno].red = red;
5552 + p->palette[regno].green = green;
5553 + p->palette[regno].blue = blue;
5555 + color = red | (green << 8) | (blue << 16);
5556 + setpal(regno, color, (void *)p->mqMmioAddrVirt);
5562 +static void do_install_cmap(int con, struct fb_info *info)
5564 + if (con != currcon)
5567 + PDEBUG("mq200fb: do_install_cmap.\n");
5569 + if (fb_display[con].cmap.len)
5570 + fb_set_cmap(&fb_display[con].cmap, 1, mq200fb_setcolreg, info);
5572 + int size = (fb_display[con].var.bits_per_pixel <= 8) ? 256 : 16;
5573 + fb_set_cmap(fb_default_cmap(size), 1, mq200fb_setcolreg, info);
5579 +int init_module(void)
5581 + return mq200fb_init();
5584 +void cleanup_module(void)
5586 + unregister_framebuffer(&(fb_info_mq200.fb_info));
5587 + iounmap((void *)(fb_info_mq200.mqMmioAddrVirt));
5588 + iounmap((void *)(fb_info_mq200.mqFbAddrVirt));
5591 +#endif /* MODULE */
5593 +/* The following is copied from mq2hw.c for initialization of MQ200 */
5595 +long idmqchip(void *pMQMMIO)
5599 + id = READ32(PCI_VENDOR_DEVICE);
5603 +/* Setmode for MediaQ chip
5606 +void setmqmode(PDISPLAY_CONFIG pDC, void *pMQMMIO)
5608 + volatile unsigned long regdata, pmmisc;
5609 + int x=0, y=0, freq=0, paneltype; /* i is used as loop counter */
5610 + unsigned long screensize, gc_startaddr;
5612 + printk("mq200fb: setmqmode - before reset\n");
5613 + regdata = SW_CHIP_RESET;
5614 + REG32(DC_0, regdata);
5616 + /* use 50MHz for LCD only and 83MHz if CRT is on */
5617 + if (pDC->flag & CRT_ON)
5618 + regdata = PLL1_83MHZ;
5620 + regdata = PLL1_50MHZ;
5621 + REG32(DC_0, regdata);
5624 + /* Enter D0 state from reset D3 state */
5626 + REG32(PCI_PM_CNTL_STATUS, ENTER_D0);
5631 + if((READ32(PCI_PM_CNTL_STATUS) & POWER_STATE_MASK) == 0x0)
5635 + /* In stable D3 state here ... */
5637 + * Set up PMU misc registers
5638 + * - also PMCLK_2048CYCLE and FP_PMCLK_128K if SA1110
5640 + if ((READ32(DC_1) & BUS_MODE_MASK) == BUS_MODE_SA1110)
5641 + regdata = GE_ENABLE|GE_BY_PLL1|PMCLK_2048CYCLE|FP_PMCLK_512;
5643 + /* the rest of CPUs */
5644 + regdata = GE_ENABLE|GE_BY_PLL1;
5645 + REG32(PM_MISC, regdata);
5647 + REG32(D1_STATE, DEF_D1);
5648 + REG32(D2_STATE, DEF_D2);
5650 + /* To initialize MIU block ... */
5651 + REG32(MIU_CONTROL1, DRAM_RESET_DISABLE);
5654 + REG32(MIU_CONTROL1, 0x00);
5657 + if (pDC->flag & CRT_ON)
5658 + regdata = DEF_MIU2_83MHZ;
5660 + regdata = DEF_MIU2_50MHZ;
5661 + REG32(MIU_CONTROL2, regdata);
5662 + REG32(MIU_CONTROL3, DEF_MIU3);
5663 + /* MIU REG 5 MUST BE PROGRAMMED BEFORE MIU REG 4 */
5664 + REG32(MIU_CONTROL5, DEF_MIU5);
5665 + REG32(MIU_CONTROL4, DEF_MIU4);
5668 + REG32(MIU_CONTROL1, MIU_ENABLE | MIU_RESET_DISABLE);
5671 + /* Here, MIU is supposed to ready to serve ... */
5674 + /* Last 1KB is reserved for hardware cursor */
5675 + if (mqflag & ENA_HW_CURSOR)
5677 + printk("mq200fb: enabling hardware cursor\n");
5678 + setup_cursor(pMQMMIO);
5679 + enable_cursor(pMQMMIO);
5682 + /* Set up GE Base Address */
5683 + REG32(BASE_ADDRESS, gc_startaddr);
5684 + /* Set up flat panel parameters
5687 + paneltype = pDC->flag & PANEL_TYPE_MASK;
5690 + /* Panel is used as a display in the system */
5691 + setupfp(paneltype, pMQMMIO);
5693 + /* Set up DSTN half frame buffer */
5694 + screensize = pDC->x * pDC->y * pDC->bpp / 8 + gc_startaddr;
5695 + setuphfbuffer(paneltype, screensize, pMQMMIO);
5697 + /* Get flat panel frequency */
5698 + freq = fpControlData[paneltype].freq;
5701 + /* Based on display configuration, proper GC is set up .. */
5702 + if (pDC->flag & LARGE_DESKTOP)
5704 + switch (pDC->flag & LCDCRT_POS_MASK)
5706 + case HORI_CRT_LCD:
5707 + case HORI_LCD_CRT:
5712 + case VERT_CRT_LCD:
5713 + case VERT_LCD_CRT:
5721 + /* SAME_IMAGE and simultaneous LCD and/or CRT */
5726 + /* Set up GC memory configuration */
5727 + setupgcmem(pDC, gc_startaddr, pMQMMIO);
5729 + pmmisc = READ32(PM_MISC);
5731 + /* Set up 2 GCs */
5732 + if (pDC->flag & USE_2GCs)
5734 + /* Set up GC1 for CRT */
5735 + setupgc(IS_GC1, x, y, pDC->bpp, pDC->refresh, pMQMMIO);
5737 + /* Set up GC2 for flat panel */
5738 + setupgc(IS_GC2, x, y, pDC->bpp, freq, pMQMMIO);
5740 + /* PLL2 and PLL3 are both used ... */
5741 + /* to save a little bit power, can shut down PLL3 if both LCD
5742 + and CRT are the same frequency...
5744 + pmmisc |= (PLL2_ENABLE | PLL3_ENABLE);
5745 + REG32(PM_MISC, pmmisc);
5747 + /* Enable panel and CRT accordingly */
5748 + if (pDC->flag & LCD_ON)
5749 + onoffdisplay(ENABLE_LCD_GC2, pMQMMIO);
5751 + if (pDC->flag & CRT_ON)
5752 + onoffdisplay(ENABLE_CRT_GC1, pMQMMIO);
5756 + /* Simultaneous mode - set up GC1 only */
5758 + setupgc(IS_GC1, x, y, pDC->bpp, freq, pMQMMIO);
5760 + setupgc(IS_GC1, x, y, pDC->bpp, pDC->refresh, pMQMMIO);
5763 + pmmisc |= PLL2_ENABLE;
5764 + REG32(PM_MISC, pmmisc);
5766 + /* Enable panel and CRT accordingly */
5767 + if (pDC->flag & LCD_ON)
5768 + onoffdisplay(ENABLE_LCD_GC1, pMQMMIO);
5770 + if (pDC->flag & CRT_ON)
5771 + onoffdisplay(ENABLE_CRT_GC1, pMQMMIO);
5775 +/* Set up flat panel register depending on panel type
5778 +void setupfp(int panel, void *pMQMMIO)
5780 + PFPDATA_CONTROL pFP;
5781 + int frcaddr, frcidx, i;
5783 + /* Locate panel data pointer */
5784 + pFP = &fpControlData[panel];
5785 + printk("FP_PIN_CONTROL set to %x\n", (u_int)pFP->fpPinControl);
5786 + REG32(FP_CONTROL, pFP->fpControl);
5787 + REG32(FP_PIN_CONTROL, pFP->fpPinControl);
5788 + REG32(STN_CONTROL, pFP->stnControl);
5789 + REG32(FP_GPO_CONTROL, DEF_GPO_CONTROL);
5790 + REG32(FP_GPIO_CONTROL, DEF_GPIO_CONTROL);
5791 + REG32(PWM_CONTROL, DEF_PWM_CONTROL);
5793 + /* Program FRC registers for STN panel (DSTN and SSTN) */
5794 + frcidx = 0; /* DSTN */
5795 + if ( (pFP->fpControl & FP_TYPE_MASK) != FP_TYPE_TFT )
5797 + if ((pFP->fpControl & FP_TYPE_MASK) == FP_TYPE_SSTN)
5798 + frcidx++; /* SSTN index */
5800 + for ( i = frcaddr = 0; i < FRC_PATTERN_CNT; i++,frcaddr+=4 )
5801 + REG32((FRC_PATTERN + frcaddr),
5802 + FRCControlData[frcidx].frcPattern[i]);
5804 + for ( i = frcaddr = 0; i < FRC_WEIGHT_CNT; i++,frcaddr+=4 )
5805 + REG32((FRC_WEIGHT + frcaddr), FRCControlData[frcidx].frcWeight[i]);
5808 + /* Set up flat panel GPO and GPIO register from default */
5809 + REG32(FP_GPO_CONTROL, DEF_GPO_CONTROL);
5810 + REG32(FP_GPIO_CONTROL, DEF_GPIO_CONTROL);
5815 +/* Set up DSTN half frame buffer register depending on panel type
5817 + * panel : panel type
5818 + * sizeused : used (occupied) area of frame buffer
5821 +void setuphfbuffer(int panel, unsigned long sizeused, void *pMQMMIO)
5823 + PFPDATA_CONTROL pFP;
5824 + unsigned long dstnfbsize, dstnstart, dstnend;
5826 + /* Locate panel data pointer */
5827 + pFP = &fpControlData[panel];
5829 + /* Figure out half frame buffer for DSTN panel */
5830 + if ( (pFP->fpControl & FP_TYPE_MASK) == FP_TYPE_DSTN )
5832 + /* Color D-STN memory requirement - no need to *3 for mono dstn panel */
5833 + if (pFP->fpControl & FP_MONO)
5834 + dstnfbsize = pFP->x;
5836 + dstnfbsize = pFP->x * 3;
5837 + dstnfbsize = (((dstnfbsize + 127) >> 7) * pFP->y) << 3;
5839 + /* make it suitable for register bits definition */
5840 + dstnstart = (sizeused + 127) >> 7;
5841 + dstnend = (sizeused + dstnfbsize + 15) >> 4;
5842 + REG32(DSTN_FB_CONTROL, (dstnstart | ((dstnend - 1) << 16)));
5847 +/* Set up graphics controller (GC1 or GC2) timing registers and PLLx
5850 + * x : horizontal viewport size
5851 + * y : vertical viewport size
5852 + * refresh : refresh rate (mainly VESA-supported mode)
5855 +void setupgc(int gc, int x, int y, int bpp, int refresh, void *pMQMMIO)
5857 + PDISPLAY_TIMING pDT;
5858 + unsigned long gccontrol;
5860 + /* Locate GC timing parameters first */
5861 + pDT = getgcparam(x, y, refresh);
5863 + /* error checking for pDT here */
5865 + gccontrol = getbppbits(bpp) |
5866 + FDx_1 | (1L << 24) |
5871 + /* Set up GC window as display */
5872 + REG32(HW1_CONTROL, ((x - 1) << 16) | (1 << 28));
5873 + REG32(VW1_CONTROL, ((y - 1) << 16));
5875 + REG32(HD1_CONTROL, pDT->hd);
5876 + REG32(VD1_CONTROL, pDT->vd);
5877 + REG32(HS1_CONTROL, pDT->hs);
5878 + REG32(VS1_CONTROL, pDT->vs);
5879 + REG32(VS1_CONTROL, pDT->vs);
5880 + REG32(GC1_CRT_CONTROL, pDT->crtc);
5882 + /* Program PLL2 for GC1 */
5883 + REG32(PLL2_CONTROL, pDT->pll);
5885 + /* GC1 control register */
5886 + gccontrol |= GxRCLK_PLL2;
5887 + REG32(GC1_CONTROL, gccontrol);
5892 + /* Set up GC window as display */
5893 + REG32(HW2_CONTROL, ((x - 1) << 16));
5894 + REG32(VW2_CONTROL, ((y - 1) << 16));
5896 + REG32(HD2_CONTROL, pDT->hd);
5897 + REG32(VD2_CONTROL, pDT->vd);
5898 + REG32(HS2_CONTROL, pDT->hs);
5899 + REG32(VS2_CONTROL, pDT->vs);
5900 + REG32(VS2_CONTROL, pDT->vs);
5901 + REG32(GC1_CRT_CONTROL, pDT->crtc);
5903 + /* Program PLL3 for GC2 */
5904 + REG32(PLL3_CONTROL, pDT->pll);
5906 + /* GC2 control register */
5907 + gccontrol |= GxRCLK_PLL3;
5908 + REG32(GC2_CONTROL, gccontrol);
5913 +/* Set up graphics controller (GC1 or GC2) memory configuration (stride and
5914 + * starting address etc.)
5916 + * pDC : pointer to active DIPSLAY_CONFIG structure
5917 + * startaddr : starting address - 0 if starting from very beginning
5919 + * - use GC1 for Simultaneous mode (1 GC)
5920 + * - use GC1 for CRT and GC2 for LCD at QView mode
5923 +void setupgcmem(PDISPLAY_CONFIG pDC, unsigned long startaddr, void *pMQMMIO)
5925 + unsigned long stride=0, start1=0, start2=0;
5927 + if (pDC->flag & LARGE_DESKTOP)
5929 + /* 4 possible layouts */
5930 + switch (pDC->flag & LCDCRT_POS_MASK)
5932 + case HORI_CRT_LCD:
5933 + stride = (pDC->x / 2) * pDC->bpp / 8;
5934 + start1 = startaddr;
5935 + start2 = startaddr + stride;
5938 + case HORI_LCD_CRT:
5939 + stride = (pDC->x / 2) * pDC->bpp / 8;
5940 + start1 = startaddr + stride;
5941 + start2 = startaddr;
5944 + case VERT_CRT_LCD:
5945 + stride = pDC->x * pDC->bpp / 8;
5946 + start1 = startaddr;
5947 + start2 = startaddr + stride * pDC->y / 2;
5950 + case VERT_LCD_CRT:
5951 + stride = pDC->x * pDC->bpp / 8;
5952 + start1 = startaddr + stride * pDC->y / 2;
5953 + start2 = startaddr;
5957 + /* Program to the chip */
5958 + REG32(IW1_STRIDE, stride);
5959 + REG32(IW2_STRIDE, stride);
5961 + REG32(IW1_START_ADDR, start1);
5962 + REG32(IW2_START_ADDR, start2);
5966 + /* QView Same Image and Simultaneous LCD and/or CRT
5968 + * - set up 2 GCs in any cases ...
5969 + * - 2 addidtional registers write vs. code size
5973 + /* Calculate stride */
5974 + stride = pDC->x * pDC->bpp / 8;
5976 + REG32(IW1_STRIDE, stride);
5977 + REG32(IW2_STRIDE, stride);
5979 + REG32(IW1_START_ADDR, startaddr);
5980 + REG32(IW2_START_ADDR, startaddr);
5985 +/* Program palette entry
5988 +void setpal(int index, unsigned long color, void *pMQMMIO)
5990 + /*PDEBUG("mq200fb: setpal. %d %d\n", index, color);*/
5992 + REG32_PAL(index, color);
5995 +/* Vertical blank time is in progress ..
5998 +void invblank(void *pMQMMIO)
6000 + unsigned long *intstat = (unsigned long *)(pMQMMIO+INT_STATUS_REG);
6002 + /* Make sure int occurs first */
6003 + while ( !(*intstat & ST_GC1_VDE_F) );
6005 + /* Reset GC1 VDE F status bit - write 1 to clear the status */
6006 + REG32(INT_STATUS_REG,ST_GC1_VDE_F);
6008 + /* Wait for next VDE falling edge for DAC access */
6009 + while ( !(*intstat & ST_GC1_VDE_F) );
6011 + /* Here MQ200 should be in V blank period ... */
6015 +/* Retrive graphics controller parameters from supported table
6018 +PDISPLAY_TIMING getgcparam(int x, int y, int refresh)
6022 + for (i=0; i < MAX_MQMODE; i++)
6024 + if ( TimingParam[i].x == x
6025 + && TimingParam[i].y == y
6026 + && TimingParam[i].refresh == refresh )
6027 + return ( (PDISPLAY_TIMING)&TimingParam[i] );
6029 + return (NULL); /* not existed */
6032 +/* Return color depth setting for GC
6035 +unsigned long getbppbits(int bpp)
6037 + unsigned long bppbits = 0;
6041 + case 8UL: bppbits = GC_8BPP; break;
6042 + case 16UL: bppbits = GC_16BPP_BP; break;
6043 + case 24UL: bppbits = GC_24BPP_BP; break;
6044 + case 32UL: bppbits = GC_32BPP_ARGB_BP; break;
6045 + case 4UL: bppbits = GC_4BPP; break;
6046 + case 2UL: bppbits = GC_2BPP; break;
6047 + case 1UL: bppbits = GC_1BPP; break;
6052 +/* Turn on/off LCD or CRT driven by either GC1 or GC2
6055 +void onoffdisplay(int display_flag, void *pMQMMIO)
6057 + unsigned long fpcontrol, gccontrol, crtcontrol;
6059 + switch (display_flag)
6061 + case ENABLE_LCD_GC1:
6062 + /* Obtain current setting */
6063 + fpcontrol = READ32(FP_CONTROL) & FPI_BY_GCxMASK;
6064 + gccontrol = READ32(GC1_CONTROL);
6066 + /* Turn on GC1 first if remain disabled */
6067 + if (!(gccontrol & GC_ENABLE))
6068 + REG32(GC1_CONTROL, gccontrol | GC_ENABLE);
6070 + /* Flat panel controlled by GC1 */
6071 + REG32(FP_CONTROL, fpcontrol | FPI_BY_GC1);
6073 +#if defined(CONFIG_SA1100_GDS2200) || defined(CONFIG_SA1100_SIMPAD)
6074 + mq200_backlight(pMQMMIO, 1);
6079 + case ENABLE_LCD_GC2:
6080 + /* Obtain current setting */
6081 + fpcontrol = READ32(FP_CONTROL) & FPI_BY_GCxMASK;
6082 + gccontrol = READ32(GC2_CONTROL);
6084 + /* Turn on GC1 first if remain disabled */
6085 + if (!(gccontrol & GC_ENABLE))
6086 + REG32(GC2_CONTROL, gccontrol | GC_ENABLE);
6088 + /* Flat panel controlled by GC1 */
6089 + REG32(FP_CONTROL, fpcontrol | FPI_BY_GC2);
6092 + case DISABLE_LCD_GC1:
6093 + /* Disable flat panel first */
6094 + fpcontrol = READ32(FP_CONTROL) & FPI_BY_GCxMASK;
6095 + REG32(FP_CONTROL, fpcontrol);
6097 + crtcontrol = READ32(GC1_CRT_CONTROL) & (~CRT_BY_GCxMASK);
6098 +#if defined(CONFIG_SA1100_GDS2200) || defined(CONFIG_SA1100_SIMPAD)
6099 + mq200_backlight(pMQMMIO, 0);
6102 + /* Disable GC1 if not used for CRT */
6103 + if (!(crtcontrol == CRT_BY_GC1))
6105 + gccontrol = READ32(GC1_CONTROL);
6106 + REG32(GC1_CONTROL, gccontrol & GC_DISABLE);
6110 + case DISABLE_LCD_GC2:
6111 + /* Disable flat panel first */
6112 + fpcontrol = READ32(FP_CONTROL) & FPI_BY_GCxMASK;
6113 + REG32(FP_CONTROL, fpcontrol);
6115 + crtcontrol = READ32(GC1_CRT_CONTROL) & (~CRT_BY_GCxMASK);
6117 + /* Disable GC2 if not used for CRT */
6118 + if (!(crtcontrol == CRT_BY_GC2))
6120 + gccontrol = READ32(GC2_CONTROL);
6121 + REG32(GC2_CONTROL, gccontrol & GC_DISABLE);
6125 + case ENABLE_CRT_GC1:
6126 + /* Enable GC1 if not yet enabled */
6127 + gccontrol = READ32(GC1_CONTROL);
6128 + if (!(gccontrol & GC_ENABLE))
6129 + REG32(GC1_CONTROL, gccontrol | GC_ENABLE);
6131 + /* Enable CRT by GC1 */
6132 + crtcontrol = READ32(GC1_CRT_CONTROL) & CRT_BY_GCxMASK;
6133 + REG32(GC1_CRT_CONTROL, crtcontrol | CRT_BY_GC1);
6136 + case ENABLE_CRT_GC2:
6137 + /* Enable GC2 if not yet enabled */
6138 + gccontrol = READ32(GC2_CONTROL);
6139 + if (!(gccontrol & GC_ENABLE))
6140 + REG32(GC2_CONTROL, gccontrol | GC_ENABLE);
6142 + /* Enable CRT by GC2 */
6143 + crtcontrol = READ32(GC1_CRT_CONTROL) & CRT_BY_GCxMASK;
6144 + REG32(GC1_CRT_CONTROL, crtcontrol | CRT_BY_GC2);
6147 + case DISABLE_CRT_GC1:
6148 + /* Disable CRT first */
6149 + crtcontrol = READ32(GC1_CRT_CONTROL) & CRT_BY_GCxMASK;
6150 + REG32(GC1_CRT_CONTROL, crtcontrol);
6152 + fpcontrol = READ32(FP_CONTROL) & (~FPI_BY_GCxMASK);
6154 + /* Disable GC1 if not used for CRT */
6155 + if (!(crtcontrol == CRT_BY_GC1))
6157 + gccontrol = READ32(GC1_CONTROL);
6158 + REG32(GC1_CONTROL, gccontrol & GC_DISABLE);
6162 + case DISABLE_CRT_GC2:
6163 + /* Disable CRT first */
6164 + crtcontrol = READ32(GC1_CRT_CONTROL) & CRT_BY_GCxMASK;
6165 + REG32(GC1_CRT_CONTROL, crtcontrol);
6167 + fpcontrol = READ32(FP_CONTROL) & (~FPI_BY_GCxMASK);
6169 + /* Disable GC2 if not used for CRT */
6170 + if (!(crtcontrol == CRT_BY_GC2))
6172 + gccontrol = READ32(GC2_CONTROL);
6173 + REG32(GC2_CONTROL, gccontrol & GC_DISABLE);
6180 +/* Setup hardware cursor data area start address in the frame buffer
6183 +void setup_cursor(void *pMQMMIO)
6185 + REG32(HW_CURSOR1_FGCLR, CURSOR_FGCLR);
6186 + REG32(HW_CURSOR2_FGCLR, CURSOR_FGCLR);
6187 + REG32(HW_CURSOR1_BGCLR, CURSOR_BGCLR);
6188 + REG32(HW_CURSOR2_BGCLR, CURSOR_BGCLR);
6189 + REG32(HW_CURSOR1_ADDR, 0x000007ff);
6190 + REG32(HW_CURSOR2_ADDR, 0x000007ff);
6193 +/* Move cursor position and adjust hot spot offset
6196 +void move_cursor(unsigned long pos, unsigned long addr, void *pMQMMIO)
6198 + REG32(HW_CURSOR1_POS, pos);
6199 + REG32(HW_CURSOR2_POS, pos);
6202 +/* Enable hardware cursor
6205 +void enable_cursor(void *pMQMMIO)
6209 + temp = READ32(GC1_CONTROL) | HC_ENABLE;
6210 + REG32(GC1_CONTROL, temp);
6211 + if (mqflag & USE_2GCs)
6213 + temp = READ32(GC2_CONTROL) | HC_ENABLE;
6214 + REG32(GC2_CONTROL, temp);
6218 +/* Disable hardware cursor
6221 +void disable_cursor(void *pMQMMIO)
6225 + temp = READ32(GC1_CONTROL) & HC_DISABLE;
6226 + REG32(GC1_CONTROL, temp);
6227 + if (mqflag & USE_2GCs)
6229 + temp = READ32(GC2_CONTROL) & HC_DISABLE;
6230 + REG32(GC2_CONTROL, temp);
6233 +/* The above is copied from mq2hw.c for initialization of MQ200 */
6235 +void turnoffMQ200(void * pMQMMIO)
6237 + volatile u32 temp;
6239 + temp = READ32(FP_CONTROL);
6240 + temp &=0xfffffffc;
6241 + REG32(FP_CONTROL, temp);
6243 + temp =READ32(FP_CONTROL) & 0x3;
6245 + PDEBUG("FP_CONTROL is not cleared properly");
6247 + PDEBUG("FP_CONTROL is cleared properly");
6249 + temp = READ32(FP_PIN_CONTROL);
6251 + REG32(FP_PIN_CONTROL, temp);
6254 + temp = READ32(GC1_CONTROL);
6255 + temp &=0xfffffffe;
6256 + REG32(GC1_CONTROL, temp);
6258 + temp = READ32(GC1_CONTROL) & 0x1;
6260 + PDEBUG("GC1_CONTROL is not cleared properly");
6262 + PDEBUG("GC1_CONTROL is cleared properly");
6264 + temp = READ32(GC1_CRT_CONTROL);
6265 + temp &=0xfffffffe;
6266 + REG32(GC1_CRT_CONTROL, temp);
6269 + temp = READ32(GC2_CONTROL);
6270 + temp &=0xfffffffe;
6271 + REG32(GC2_CONTROL, temp);
6273 + temp = READ32(GC2_CONTROL) & 0x1;
6275 + PDEBUG("GC2_CONTROL is not cleared properly");
6277 + PDEBUG("GC2_CONTROL is cleared properly");
6284 + * Power management hook. Note that we won't be called from IRQ context,
6285 + * unlike the blank functions above, so we may sleep.
6288 +mq200fb_pm_callback(struct pm_dev *pm_dev, pm_request_t req, void *data)
6290 + struct fb_info_mq200 *p = (struct fb_info_mq200 *) pm_dev->data;
6291 + void * pMQMMIO = (void *) p->mqMmioAddrVirt;
6293 + if (req == PM_SUSPEND){
6295 + onoffdisplay(DISABLE_LCD_GC1, pMQMMIO);
6296 + REG32(PCI_PM_CNTL_STATUS, ENTER_D3);
6299 + if( req == PM_RESUME){
6300 + setmqmode(&dc, pMQMMIO);
6301 + onoffdisplay(ENABLE_LCD_GC1, pMQMMIO);
6302 + REG32(PCI_PM_CNTL_STATUS, ENTER_D0);
6310 +#if defined(CONFIG_SA1100_GDS2200) || defined(CONFIG_SA1100_SIMPAD)
6312 +static void mq200_backlight(void *pMQMMIO, int flag)
6315 +#ifdef CONFIG_SA1100_GDS2200
6316 + unsigned long gpiocontrol, data;
6319 + gpiocontrol = READ32(FP_GPIO_CONTROL) & 0x3f;
6320 + data = (flag ? GPIO2_OUT_HIGH : 0);
6321 + for(i = 0 ; i < 128 ; i++) {
6322 + REG32(FP_GPIO_CONTROL, gpiocontrol | data);
6324 + REG32(FP_GPIO_CONTROL, gpiocontrol | GPIO1_OUT_HIGH | data);
6326 + REG32(FP_GPIO_CONTROL, gpiocontrol);
6330 +#endif /* CONFIG_SA1100_GDS2200 */
6332 +#ifdef CONFIG_SA1100_SIMPAD
6335 + set_cs3_bit(DISPLAY_ON);
6337 + clear_cs3_bit(DISPLAY_ON);
6339 +#endif /* CONFIG_SA1100_SIMPAD */
6342 +#endif /* CONFIG_SA1100_GDS2200 || CONFIG_SA1100_SIMPAD */
6344 +#ifdef CONFIG_SA1100_SIMPAD
6346 +static void writeBrightness(void *pMQMMIO, int brightness)
6348 + unsigned long dutyCycle, pwmcontrol;
6349 + int MAX_BRIGHT_REG = 0x000000fc; /* int 254 */
6351 + if(brightness > MAX_BRIGHT_REG)
6356 + *Determine dutyCycle.
6357 + *Note: the lower the value, the brighter the display!
6360 + dutyCycle = MAX_BRIGHT_REG - brightness;
6363 + *Configure PWM0 (source clock = oscillator clock, pwm always enabled,
6364 + *zero, clock pre-divider = 4) pwm frequency = 12.0kHz
6366 + pwmcontrol = READ32(PWM_CONTROL);
6367 + REG32(PWM_CONTROL, 0x00000044 | (pwmcontrol & 0xffffff00));
6370 + /* Write to pwm duty cycle register. */
6372 + REG32(PWM_CONTROL, ((dutyCycle << 8) & 0x0000ff00) |
6373 + (pwmcontrol & 0xffff00ff));
6377 +#endif /* CONFIG_SA1100_SIMPAD */
6379 +static int proc_read_reg(struct file * file, char * buf,
6380 + size_t nbytes, loff_t *ppos)
6382 + int i_ino = (file->f_dentry->d_inode)->i_ino;
6383 + char outputbuf[15];
6386 + mq200_reg_entry_t* current_reg=NULL;
6387 + if (*ppos>0) /* Assume reading completed in previous read*/
6389 + for (i=0;i<NUM_OF_MQ200_REG_ENTRY;i++) {
6390 + if (mq200_regs[i].low_ino==i_ino) {
6391 + current_reg = &mq200_regs[i];
6395 + if (current_reg==NULL)
6398 + count = sprintf(outputbuf, "0x%08X\n",
6399 + *((volatile *) mq200_p2v(current_reg->phyaddr)));
6401 + if (count>nbytes) /* Assume output can be read at one time */
6403 + if (copy_to_user(buf, outputbuf, count))
6408 +static ssize_t proc_write_reg(struct file * file, const char * buffer,
6409 + size_t count, loff_t *ppos)
6411 + int i_ino = (file->f_dentry->d_inode)->i_ino;
6412 + mq200_reg_entry_t* current_reg=NULL;
6414 + unsigned long newRegValue;
6417 + for (i=0;i<NUM_OF_MQ200_REG_ENTRY;i++) {
6418 + if (mq200_regs[i].low_ino==i_ino) {
6419 + current_reg = &mq200_regs[i];
6423 + if (current_reg==NULL)
6426 + newRegValue = simple_strtoul(buffer,&endp,0);
6427 + *((volatile *) mq200_p2v(current_reg->phyaddr))=newRegValue;
6428 + return (count+endp-buffer);
6431 --- linux-2.4.27/include/asm-arm/arch-sa1100/simpad.h~2.4.27-vrs1-pxa1-jpm1
6432 +++ linux-2.4.27/include/asm-arm/arch-sa1100/simpad.h
6434 #define GPIO_UART3_DCD GPIO_GPIO18
6435 #define GPIO_UART3_DSR GPIO_GPIO17
6437 +#define GPIO_POWER_BUTTON GPIO_GPIO0
6438 #define GPIO_UCB1300_IRQ GPIO_GPIO (22) /* UCB GPIO and touchscreen */
6440 #define IRQ_UART1_CTS IRQ_GPIO15
6442 #define IRQ_UART3_DCD GPIO_GPIO18
6443 #define IRQ_UART3_DSR GPIO_GPIO17
6445 -#define IRQ_GPIO_UCB1300_IRQ IRQ_GPIO22
6446 +#define IRQ_GPIO_UCB1300_IRQ IRQ_GPIO22
6447 +#define IRQ_GPIO_POWER_BUTTON IRQ_GPIO0
6449 +/*--- SmartCard ---*/
6450 +#define GPIO_SMART_CARD GPIO_GPIO10
6451 +#define IRQ_GPIO_SMART_CARD IRQ_GPIO10
6454 #define GPIO_CF_CD GPIO_GPIO24
6456 #define LED2_ON 0x1000
6457 #define IRDA_MODE 0x2000 // Fast/Slow IrDA mode
6458 #define ENABLE_5V 0x4000 // Enable 5V circuit
6459 -#define RESET_SIMCARD 0x8000
6460 +#define nRESET_SIMCARD 0x8000
6462 #define RS232_ENABLE 0x0440
6463 #define PCMCIAMASK 0x402f
6465 +++ linux-2.4.27/include/asm-arm/arch-sa1100/simpad_pm.h
6468 +* Abstraction interface for microcontroller connection to rest of system
6470 +* Copyright 2003 Peter Pregler
6471 +* Copyright 2000,1 Compaq Computer Corporation.
6473 +* Use consistent with the GNU GPL is permitted,
6474 +* provided that this copyright notice is
6475 +* preserved in its entirety in all copies and derived works.
6477 +* COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
6478 +* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
6479 +* FITNESS FOR ANY PARTICULAR PURPOSE.
6481 +* Author: Peter Pregler (based on work for ipaq by Andrew Christian)
6485 +#ifndef __SIMPAD_HAL_H
6486 +#define __SIMPAD_HAL_H
6488 +extern int simpad_apm_get_power_status(unsigned char *ac_line_status, unsigned char *battery_status,
6489 + unsigned char *battery_flag, unsigned char *battery_percentage,
6490 + unsigned short *battery_life);
6493 +struct simpad_battery {
6494 + unsigned char ac_status; /* line connected yes/no */
6495 + unsigned char status; /* battery loading yes/no */
6496 + unsigned char percentage; /* percentage loaded */
6497 + unsigned short life; /* life till empty */
6500 +extern int simpad_get_battery(struct simpad_battery *bstat);
6502 +/* These should match the apm_bios.h definitions */
6503 +#define SIMPAD_AC_STATUS_AC_OFFLINE 0x00
6504 +#define SIMPAD_AC_STATUS_AC_ONLINE 0x01
6505 +#define SIMPAD_AC_STATUS_AC_BACKUP 0x02 /* What does this mean? */
6506 +#define SIMPAD_AC_STATUS_AC_UNKNOWN 0xff
6508 +/* These bitfields are rarely "or'd" together */
6509 +#define SIMPAD_BATT_STATUS_HIGH 0x01
6510 +#define SIMPAD_BATT_STATUS_LOW 0x02
6511 +#define SIMPAD_BATT_STATUS_CRITICAL 0x04
6512 +#define SIMPAD_BATT_STATUS_CHARGING 0x08
6513 +#define SIMPAD_BATT_STATUS_CHARGE_MAIN 0x10
6514 +#define SIMPAD_BATT_STATUS_DEAD 0x20 /* Battery will not charge */
6515 +#define SIMPAD_BATT_NOT_INSTALLED 0x20 /* For expansion pack batteries */
6516 +#define SIMPAD_BATT_STATUS_FULL 0x40 /* Battery fully charged (and connected to AC) */
6517 +#define SIMPAD_BATT_STATUS_NOBATT 0x80
6518 +#define SIMPAD_BATT_STATUS_UNKNOWN 0xff
6521 +#include <linux/simpad_ts.h>
6523 +enum simpad_asset_type {
6529 +#define TTYPE(_type) (((unsigned int)_type) << 8)
6530 +#define TCHAR(_len) (TTYPE(ASSET_TCHAR) | (_len))
6531 +#define TSHORT TTYPE(ASSET_SHORT)
6532 +#define TLONG TTYPE(ASSET_LONG)
6533 +#define ASSET(_type,_num) ((((unsigned int)_type)<<16) | (_num))
6535 +#define ASSET_HM_VERSION ASSET( TCHAR(10), 0 ) /* 1.1, 1.2 */
6536 +#define ASSET_SERIAL_NUMBER ASSET( TCHAR(40), 1 ) /* Unique iPAQ serial number */
6537 +#define ASSET_MODULE_ID ASSET( TCHAR(20), 2 ) /* E.g., "iPAQ 3700" */
6538 +#define ASSET_PRODUCT_REVISION ASSET( TCHAR(10), 3 ) /* 1.0, 2.0 */
6539 +#define ASSET_PRODUCT_ID ASSET( TSHORT, 4 ) /* 2 = Palm-sized computer */
6540 +#define ASSET_FRAME_RATE ASSET( TSHORT, 5 )
6541 +#define ASSET_PAGE_MODE ASSET( TSHORT, 6 ) /* 0 = Flash memory */
6542 +#define ASSET_COUNTRY_ID ASSET( TSHORT, 7 ) /* 0 = USA */
6543 +#define ASSET_IS_COLOR_DISPLAY ASSET( TSHORT, 8 ) /* Boolean, 1 = yes */
6544 +#define ASSET_ROM_SIZE ASSET( TSHORT, 9 ) /* 16, 32 */
6545 +#define ASSET_RAM_SIZE ASSET( TSHORT, 10 ) /* 32768 */
6546 +#define ASSET_HORIZONTAL_PIXELS ASSET( TSHORT, 11 ) /* 240 */
6547 +#define ASSET_VERTICAL_PIXELS ASSET( TSHORT, 12 ) /* 320 */
6549 +#define ASSET_TYPE(_asset) (((_asset)&0xff000000)>>24)
6550 +#define ASSET_TCHAR_LEN(_asset) (((_asset)&0x00ff0000)>>16)
6551 +#define ASSET_NUMBER(_asset) ((_asset)&0x0000ffff)
6553 +#define MAX_TCHAR_LEN 40
6555 +struct simpad_asset {
6556 + unsigned int type;
6558 + unsigned char tchar[ MAX_TCHAR_LEN ];
6559 + unsigned short vshort;
6560 + unsigned long vlong;
6564 +/********************************************************************
6565 + * Interface to the hardware-type specific functions
6567 + * get_version Read the version number of the microcontroller on the option pack SPI bus
6568 + * spi_read Reads from the serial EEPROM memory on the option pack SPI bus
6569 + * spi_write Write to the serial EEPROM memory on the option pack SPI bus
6570 + * get_option_detect Returns whether or not an option pack is present
6572 + * get_thermal_sensor Return measured temperature of the unit, in units of 0.125 deg C
6573 + * set_notify_led Turns on, off, or blinks the Green LED
6574 + * read_light_sensor Returns the value of the front light sensor
6575 + * get_battery Returns the current voltage and charging state of all batteries
6576 + * audio_clock Sets the audio CODEC to run at a particular rate
6577 + * audio_power Turns on/off audio CODEC (internally calls audio_clock)
6578 + * audio_mute Mutes the audio CODEC
6579 + * asset_read Extracts PocketPC-style asset information from persistent memory
6580 + * backlight_control Adjusts the backlight level (only on/off for 3100)
6585 + * codec_control Reset/mute/control level of 3100 audio codec
6586 + * contrast_control Adjusts the contrast level (only for 3100)
6588 + * iPAQ 3600, 3700 only
6589 + * ====================
6590 + * eeprom_read Reads from the asset information on the eeprom of a 3600 (deprecated)
6591 + * eeprom_write Writes to the asset information on the eeprom (deprecated)
6593 + * The interfaces to the EEPROM functions are maintained only because the simpad_ts driver has
6594 + * a deprecated ioctl call for them. They are used internally by the "asset_read" function.
6596 + * iPAQ 3800, 3900 only
6597 + * ====================
6598 + * set_ebat Tells enhanced PCMCIA sleeves that this iPAQ can handle
6599 + * a wider voltage range (applies to 3800, 3900)
6601 + *********************************************************************/
6603 +struct simpad_hal_ops {
6604 + /* Functions provided by the underlying hardware */
6605 + int (*get_version)( struct simpad_ts_version * );
6606 + int (*eeprom_read)( unsigned short address, unsigned char *data, unsigned short len );
6607 + int (*eeprom_write)( unsigned short address, unsigned char *data, unsigned short len );
6608 + int (*get_thermal_sensor)( unsigned short * );
6609 + int (*set_notify_led)( unsigned char mode, unsigned char duration,
6610 + unsigned char ontime, unsigned char offtime );
6611 + int (*read_light_sensor)( unsigned char *result );
6612 + int (*get_battery)( struct simpad_battery * );
6613 + int (*spi_read)( unsigned short address, unsigned char *data, unsigned short len );
6614 + int (*spi_write)( unsigned short address, unsigned char *data, unsigned short len );
6615 + int (*codec_control)( unsigned char, unsigned char );
6616 + int (*get_option_detect)( int *result );
6617 + int (*audio_clock)( long samplerate );
6618 + int (*audio_power)( long samplerate );
6619 + int (*audio_mute)( int mute );
6620 + int (*asset_read)( struct simpad_asset *asset );
6621 + int (*set_ebat)( void );
6623 + /* Functions indirectly provided by the underlying hardware */
6624 + int (*backlight_control)( enum flite_pwr power, unsigned char level );
6625 + int (*contrast_control)( unsigned char level );
6627 + /* for module use counting */
6628 + struct module *owner;
6631 +/* Used by the device-specific hardware module to register itself */
6632 +extern int simpad_hal_register_interface( struct simpad_hal_ops *ops );
6633 +extern void simpad_hal_unregister_interface( struct simpad_hal_ops *ops );
6636 + * Calls into HAL from the device-specific hardware module
6637 + * These run at interrupt time
6639 +extern void simpad_hal_keypress( unsigned char key );
6640 +extern void simpad_hal_touchpanel( unsigned short x, unsigned short y, int down );
6641 +extern void simpad_hal_option_detect( int present );
6643 +/* Callbacks registered by device drivers */
6644 +struct simpad_driver_ops {
6645 + void (*keypress)( unsigned char key );
6646 + void (*touchpanel)( unsigned short x, unsigned short y, int down );
6647 + void (*option_detect)( int present );
6650 +extern int simpad_hal_register_driver( struct simpad_driver_ops * );
6651 +extern void simpad_hal_unregister_driver( struct simpad_driver_ops * );
6654 +/* Calls into HAL from device drivers and other kernel modules */
6655 +extern void simpad_get_flite( struct simpad_ts_backlight *bl );
6656 +extern void simpad_get_contrast( unsigned char *contrast );
6657 +extern int simpad_set_flite( enum flite_pwr pwr, unsigned char brightness );
6658 +extern int simpad_set_contrast( unsigned char contrast );
6659 +extern int simpad_toggle_frontlight( void );
6661 +extern int simpad_apm_get_power_status(unsigned char *ac_line_status, unsigned char *battery_status,
6662 + unsigned char *battery_flag, unsigned char *battery_percentage,
6663 + unsigned short *battery_life);
6665 +extern struct simpad_hal_ops *simpad_hal_ops;
6667 +/* Do not use this macro in driver files - instead, use the inline functions defined below */
6668 +#define CALL_HAL( f, args... ) \
6669 + { int __result = -EIO; \
6670 + if ( simpad_hal_ops && simpad_hal_ops->f ) { \
6671 + __MOD_INC_USE_COUNT(simpad_hal_ops->owner); \
6672 + __result = simpad_hal_ops->f(args); \
6673 + __MOD_DEC_USE_COUNT(simpad_hal_ops->owner); \
6675 + return __result; }
6677 +#define HFUNC static __inline__ int
6679 +/* The eeprom_read/write address + len has a maximum value of 512. Both must be even numbers */
6680 +HFUNC simpad_eeprom_read( u16 addr, u8 *data, u16 len ) CALL_HAL(eeprom_read,addr,data,len)
6681 +HFUNC simpad_eeprom_write( u16 addr, u8 *data, u16 len) CALL_HAL(eeprom_write,addr,data,len)
6682 +HFUNC simpad_spi_read( u8 addr, u8 *data, u16 len) CALL_HAL(spi_read,addr,data,len)
6683 +HFUNC simpad_spi_write( u8 addr, u8 *data, u16 len) CALL_HAL(spi_write,addr,data,len)
6684 +HFUNC simpad_get_version( struct simpad_ts_version *v ) CALL_HAL(get_version,v)
6685 +HFUNC simpad_get_thermal_sensor( u16 *thermal ) CALL_HAL(get_thermal_sensor,thermal)
6686 +HFUNC simpad_set_led( u8 mode, u8 dur, u8 ont, u8 offt ) CALL_HAL(set_notify_led, mode, dur, ont, offt)
6687 +HFUNC simpad_get_light_sensor( u8 *result ) CALL_HAL(read_light_sensor,result)
6688 +HFUNC simpad_get_battery( struct simpad_battery *bat ) CALL_HAL(get_battery,bat)
6689 +HFUNC simpad_get_option_detect( int *result) CALL_HAL(get_option_detect,result)
6690 +HFUNC simpad_audio_clock( long samplerate ) CALL_HAL(audio_clock,samplerate)
6691 +HFUNC simpad_audio_power( long samplerate ) CALL_HAL(audio_power,samplerate)
6692 +HFUNC simpad_audio_mute( int mute ) CALL_HAL(audio_mute,mute)
6693 +HFUNC simpad_asset_read( struct simpad_asset *asset ) CALL_HAL(asset_read,asset)
6694 +HFUNC simpad_set_ebat( void ) CALL_HAL(set_ebat)
6696 +/* Don't use these functions directly - rather, call {get,set}_{flite,contrast} */
6697 + /* Functions indirectly provided by the underlying hardware */
6698 +HFUNC simpad_backlight_control( enum flite_pwr p, u8 v ) CALL_HAL(backlight_control,p,v)
6699 +HFUNC simpad_contrast_control( u8 level ) CALL_HAL(contrast_control,level)
6703 --- linux-2.4.27/include/linux/apm_bios.h~2.4.27-vrs1-pxa1-jpm1
6704 +++ linux-2.4.27/include/linux/apm_bios.h
6705 @@ -216,4 +216,19 @@
6706 #define APM_IOC_STANDBY _IO('A', 1)
6707 #define APM_IOC_SUSPEND _IO('A', 2)
6709 +#define APM_AC_OFFLINE 0
6710 +#define APM_AC_ONLINE 1
6711 +#define APM_AC_BACKUP 2
6712 +#define APM_AC_UNKNOWN 0xFF
6714 +#define APM_BATTERY_STATUS_HIGH 0
6715 +#define APM_BATTERY_STATUS_LOW 1
6716 +#define APM_BATTERY_STATUS_CRITICAL 2
6717 +#define APM_BATTERY_STATUS_CHARGING 3
6718 +#define APM_BATTERY_STATUS_UNKNOWN 0xFF
6720 +#define APM_BATTERY_LIFE_UNKNOWN 0xFFFF
6721 +#define APM_BATTERY_LIFE_MINUTES 0x8000
6722 +#define APM_BATTERY_LIFE_VALUE_MASK 0x7FFF
6724 #endif /* LINUX_APM_H */
6726 +++ linux-2.4.27/include/linux/switches.h
6729 + * linux/include/linux/switches.h
6731 + * Copyright (C) 2000 John Dorsey
6733 + * This program is free software; you can redistribute it and/or modify
6734 + * it under the terms of the GNU General Public License version 2 as
6735 + * published by the Free Software Foundation.
6737 + * 23 October 2000 - created.
6740 +#if !defined(_LINUX_SWITCHES_H)
6741 +#define _LINUX_SWITCHES_H
6743 +#define SWITCHES_MASK_SIZE (128)
6745 +typedef unsigned long switches_bitfield;
6747 +#define SWITCHES_BITS (sizeof(switches_bitfield) * 8)
6748 +#define SWITCHES_NUM_FIELDS (SWITCHES_MASK_SIZE / SWITCHES_BITS)
6749 +#define SWITCHES_FIELD_SELECT(i) ((i) / SWITCHES_BITS)
6750 +#define SWITCHES_FIELD_MASK(i) ((switches_bitfield)(1 << (i) % \
6753 +typedef struct switches_mask_t {
6754 + unsigned int count;
6755 + switches_bitfield events[SWITCHES_NUM_FIELDS];
6756 + switches_bitfield states[SWITCHES_NUM_FIELDS];
6759 +#define SWITCHES_ZERO(m) \
6761 + unsigned int sz_i; \
6763 + for(sz_i = 0; sz_i < SWITCHES_NUM_FIELDS; ++sz_i) \
6764 + (m)->events[sz_i] = (m)->states[sz_i] = 0; \
6767 +/* `s' is the state of the switch, either 0 or non-zero: */
6768 +#define SWITCHES_SET(m, i, s) \
6770 + ((m)->events[SWITCHES_FIELD_SELECT((i))] |= \
6771 + SWITCHES_FIELD_MASK((i))); \
6773 + ((m)->states[SWITCHES_FIELD_SELECT((i))] |= \
6774 + SWITCHES_FIELD_MASK((i))); \
6776 + ((m)->states[SWITCHES_FIELD_SELECT((i))] &= \
6777 + ~SWITCHES_FIELD_MASK((i))); \
6781 +/* Should only use to clear an event set by SWITCHES_SET(): */
6782 +#define SWITCHES_CLEAR(m, i) \
6784 + ((m)->events[SWITCHES_FIELD_SELECT((i))] &= \
6785 + ~SWITCHES_FIELD_MASK((i))); \
6786 + ((m)->states[SWITCHES_FIELD_SELECT((i))] &= \
6787 + ~SWITCHES_FIELD_MASK((i))); \
6791 +#define SWITCHES_COUNT(m) ((m)->count)
6793 +/* Returns 0 or non-zero: */
6794 +#define SWITCHES_EVENT(m, i) \
6795 +((m)->events[SWITCHES_FIELD_SELECT((i))] & SWITCHES_FIELD_MASK((i)))
6797 +/* Returns 0 or non-zero: */
6798 +#define SWITCHES_STATE(m, i) \
6799 +((m)->states[SWITCHES_FIELD_SELECT((i))] & SWITCHES_FIELD_MASK((i)))
6801 +#endif /* !defined(_LINUX_SWITCHES_H) */
6803 +++ linux-2.4.27/include/video/MQ200/mq2ge.h
6805 +#ifndef _VIDEO_MQ200_MQ2GE_H
6806 +#define _VIDEO_MQ200_MQ2GE_H
6809 +/* Misc. GE Function Macro */
6810 +#undef CHECK_SRCFIFO
6811 +#define RGB_RASTER_CHECK
6812 +#define INCLUDE_GENERIC_CODE
6814 +#ifdef CHECK_SRCFIFO
6815 +#define geWAITSRCFIFO(cnt) geWaitSrcFIFO(cnt)
6816 +#define geWAITCMDFIFO(cnt) geWaitCmdFIFO(cnt)
6817 +#define geWAITNOTBUSY() geWaitNotBusy()
6819 +#define geWAITSRCFIFO(cnt)
6820 +#define geWAITCMDFIFO(cnt)
6821 +#define geWAITNOTBUSY()
6824 +/* Additional UGL Raster Ops */
6825 +#define UGL_RASTER_OP_NOP 0x00000000L
6827 +#define UGL_RASTER_OP_BLACKNESS 0x00000001L
6828 +#define UGL_RASTER_OP_BSRC_BLACK 0x00000002L
6829 +#define UGL_RASTER_OP_BSRC_OCOPY 0x00000003L
6830 +#define UGL_RASTER_OP_BSRC_XCOPY 0x00000004L
6832 +#define UGL_RASTER_OP_WHITENESS 0x00010001L
6833 +#define UGL_RASTER_OP_WSRC_COPY 0x00010002L
6834 +#define UGL_RASTER_OP_WSRC_WHITE 0x00010003L
6835 +#define UGL_RASTER_OP_WSRC_INVERT 0x00010004L
6837 +#define UGL_RASTER_OP_SRC_COPY 0x00020001L
6838 +#define UGL_RASTER_OP_SRCDEST_AND 0x00020002L
6839 +#define UGL_RASTER_OP_SRCDEST_OR 0x00020003L
6840 +#define UGL_RASTER_OP_SRCDEST_XOR 0x00020004L
6842 +#define UGL_RASTER_OP_DEST_COPY 0x00030001L
6843 +#define UGL_RASTER_OP_DESTSRC_AND 0x00030002L
6844 +#define UGL_RASTER_OP_DESTSRC_OR 0x00030003L
6845 +#define UGL_RASTER_OP_DESTSRC_XOR 0x00030004L
6847 +/* MediaQ Raster Ops */
6848 +#define MQ200_SOURCE_ROP 0x01
6849 +#define MQ200_PATTERN_ROP 0x02
6850 +#define MQ200_GE_NOP 0x000000AAL
6851 +#define MQ200_GE_BLACKNESS 0x00000000L
6852 +#define MQ200_GE_WHITENESS 0x000000FFL
6853 +#define MQ200_GE_SRC_INVERT 0x00000033L
6854 +#define MQ200_GE_SRC_COPY 0x000000CCL
6855 +#define MQ200_GE_SRCDEST_XOR 0x00000066L
6856 +#define MQ200_GE_SRCDEST_AND 0x00000088L
6857 +#define MQ200_GE_SRCDEST_OR 0x000000EEL
6858 +#define MQ200_GE_PATTERN_INVERT 0x0000000FL
6859 +#define MQ200_GE_PATTERN_COPY 0x000000F0L
6860 +#define MQ200_GE_PATDEST_XOR 0x0000005AL
6861 +#define MQ200_GE_PATDEST_AND 0x000000A0L
6862 +#define MQ200_GE_PATDEST_OR 0x000000FAL
6863 +/* MediaQ Raster Ops mapping table */
6864 +#define UGL_NR_OPERAND 4
6865 +#define UGL_NR_OPERATION 5
6867 +#define geREG_2( idx1, val1, idx2, val2 ) \
6868 + geREG( idx2, val2 ); \
6869 + geREG( idx1, val1 )
6870 +#define geREG_3( idx1, val1, idx2, val2, idx3, val3 ) \
6871 + geREG_2( idx2, val2, idx3, val3 ); \
6872 + geREG( idx1, val1 )
6873 +#define geREG_4( idx1, val1, idx2, val2, idx3, val3, idx4, val4 ) \
6874 + geREG_3( idx2, val2, idx3, val3, idx4, val4 ); \
6875 + geREG( idx1, val1 )
6876 +#define geREG_5( idx1, val1, idx2, val2, idx3, val3, idx4, val4, idx5, val5 ) \
6877 + geREG_4( idx2, val2, idx3, val3, idx4, val4, idx5, val5 ); \
6878 + geREG( idx1, val1 )
6880 +/* Declare MQ200 GE Utility Functions */
6881 +void geWaitNotBusy(void);
6882 +void geWaitCmdFIFO(u32 cnt);
6883 +void geWaitSrcFIFO(u32 cnt);
6885 +#endif /* _VIDEO_MQ200_MQ2GE_H */
6887 +++ linux-2.4.27/include/video/MQ200/mq2hw.h
6889 +/***************************************************************************
6892 + MQ200 chip definition file
6894 + Copyright (c) 2000 by MediaQ, Incorporated.
6895 + All Rights Reserved.
6897 +***************************************************************************/
6898 +#ifndef _VIDEO_MQ200_MQ2HW_H
6899 +#define _VIDEO_MQ200_MQ2HW_H
6901 +#define MQ200_VENDOR_ID 0x4D51
6902 +#define MQ200_DEVICE_ID 0x0200
6903 +#define MQ200_ID 0x02004D51
6904 +#define PM_ID_CAP 0x06210001 /* Power management ID/capability */
6907 +#define MQ200_REV_0X 0x00
6908 +#define MQ200_REV_1A 0x01
6909 +#define MQ200_REV_1B1C 0x11
6910 +#define MQ200_REV_1D 0x10
6912 +/* Some useful defines */
6914 +#define ULONG unsigned long
6917 +#define USHORT unsigned short
6920 +#define BYTE unsigned char
6923 +/* To access MediaQ memory-mapped IO register (32bit in size) */
6924 +#define REG32(addr,val) (*(volatile ULONG *)((ULONG)pMQMMIO+addr)=(val))
6925 +#define READ32(addr) (*((volatile ULONG *)((ULONG)pMQMMIO+addr)))
6926 +#define geREG(addr,val) (*(volatile ULONG *)(mqMmioAddr+addr)=(val))
6927 +#define geREAD(addr) (*((volatile ULONG *)(mqMmioAddr+addr)))
6928 +#define gcREG(addr,val) geREG(addr,val)
6929 +#define gcREAD(addr) geREAD(addr)
6930 +#define cpuREG(addr,val) geREG(addr,val)
6931 +#define cpuREAD(addr) geREAD(addr)
6932 +#define pmuREG(addr,val) geREG(addr,val)
6933 +#define pmuREAD(addr) geREAD(addr)
6934 +#define pciREG(addr,val) geREG(addr,val)
6935 +#define pciREAD(addr) geREAD(addr)
6937 +/* To access MediaQ DAC - index-based */
6938 +#define REG32_PAL(idx,val) (*(ULONG *)((ULONG)pMQMMIO+C1_BASE+idx*4)=(val))
6939 +#define READ32_PAL(idx) (*(ULONG *)((ULONG)pMQMMIO+C1_BASE+idx*4))
6941 +/* MQ200 module offset */
6942 +#define PM_BASE (0) /* Power Management + Clk Gen */
6943 +#define CC_BASE (0x2000) /* CPU interface */
6944 +#define MM_BASE (0x4000) /* Memory Controller (m1/m2) */
6945 +#define VI_BASE (0x6000) /* Video-in controller */
6946 +#define IN_BASE (0x8000) /* Interrupt controller */
6947 +#define GC_BASE (0xA000) /* Graphics Controller 1/2 */
6948 +#define GE_BASE (0xC000) /* Graphics engine */
6949 +#define GE2_BASE (0xC200) /* Graphics engine (GE2) */
6950 +#define FP_BASE (0xE000) /* Flat panel interface */
6951 +#define C1_BASE (0x10000) /* Color palette 1 */
6952 +#define C2_BASE (0x12000) /* Color palette 2 */
6953 +#define DC_BASE (0x14000) /* Device Configuration Space */
6954 +#define PC_BASE (0x16000) /* PCI Configuration Header */
6955 +#define PSF_BASE (0x18000) /* Primary Source FIFO Space */
6956 +#define SSF_BASE (0x1A000) /* Secondary Source FIFO Space */
6958 +#define MQ200_MMIO_SIZE (0x1C0000L)
6959 +#define MQ200_FB_SIZE (0x200000L) /* 2MB memory */
6960 +#define GC_OFFSET (0x80)
6962 +/* Interrupt Controller */
6963 +#define INT_CONTROL_REG (IN_BASE + 0x00) /* Global interrupt ctrl reg */
6964 +#define INT_MASK_REG (IN_BASE + 0x04) /* Interrupt mask reg */
6965 +#define INT_STATUS_REG (IN_BASE + 0x08) /* Interrupt status reg */
6966 +#define INT_RAW_STATUS_REG (IN_BASE + 0x0C) /* Interrupt pin raw */
6969 +/* INT_CONTROL_REG - Global Interrupt Control Register */
6970 +#define INT_ENABLE 0x00000001 /* Interrupt to CPU enabled */
6971 +#define INT_PORLARITY_HIGH 0x00000002 /* Interrupt is active high */
6972 +#define INT_GPIO1_0To1 0x00000004 /* Interrupt as xition 0 to 1 */
6973 +#define INT_GPIO2_0To1 0x00000008 /* Interrupt as xition 0 to 1 */
6974 +#define INT_GPIO3_0To1 0x00000010 /* Interrupt as xtion 0 to 1 */
6976 +/* INT_MASK_REG -- Interrupt Mask Register */
6977 +#define UM_GC1_VSE_R 0x00000001 /* GC1 VSE - Rising edge */
6978 +#define UM_GC1_VSE_F 0x00000002 /* GC1 VSE - Falling edge */
6979 +#define UM_GC1_VDE_R 0x00000004 /* GC1 VDE - Rising edge */
6980 +#define UM_GC1_VDE_F 0x00000008 /* GC1 VDE - Falling edge */
6981 +#define UM_GC2_VSE_R 0x00000010 /* GC2 VSE - Rising edge */
6982 +#define UM_GC2_VSE_F 0x00000020 /* GC2 VSE - Falling edge */
6983 +#define UM_GC2_VDE_R 0x00000040 /* GC2 VDE - Rising edge */
6984 +#define UM_GC2_VDE_F 0x00000080 /* GC2 VDE - Falling edge */
6985 +#define UM_CFIFO_HALF_EMPTY 0x00000100 /* Command fifo half empty */
6986 +#define UM_CFIFO_EMPTY 0x00000200 /* Command fifo empty */
6987 +#define UM_SFIFO_HALF_EMPTY 0x00000400 /* Source fifo half empty */
6988 +#define UM_SFIFO_EMPTY 0x00000800 /* Source fifo empty */
6989 +#define UM_GE_IDLE 0x00001000 /* GE is idle */
6990 +#define UM_GPIO_1 0x00002000 /* GPIO pin 1 */
6991 +#define UM_GPIO_2 0x00004000 /* GPIO pin 2 */
6992 +#define UM_GPIO_3 0x00008000 /* GPIO pin 3 */
6994 +/* INT_STATUS_REG -- Interrupt Status Register */
6995 +#define ST_GC1_VSE_R 0x00000001 /* GC1 VSE - Rising edge */
6996 +#define ST_GC1_VSE_F 0x00000002 /* GC1 VSE - Falling edge */
6997 +#define ST_GC1_VDE_R 0x00000004 /* GC1 VDE - Rising edge */
6998 +#define ST_GC1_VDE_F 0x00000008 /* GC1 VDE - Falling edge */
6999 +#define ST_GC2_VSE_R 0x00000010 /* GC2 VSE - Rising edge */
7000 +#define ST_GC2_VSE_F 0x00000020 /* GC2 VSE - Falling edge */
7001 +#define ST_GC2_VDE_R 0x00000040 /* GC2 VDE - Rising edge */
7002 +#define ST_GC2_VDE_F 0x00000080 /* GC2 VDE - Falling edge */
7003 +#define ST_CFIFO_HALF_EMPTY 0x00000100 /* Command fifo half empty */
7004 +#define ST_CFIFO_EMPTY 0x00000200 /* Command fifo empty */
7005 +#define ST_SFIFO_HALF_EMPTY 0x00000400 /* Source fifo half empty */
7006 +#define ST_SFIFO_EMPTY 0x00000800 /* Source fifo empty */
7007 +#define ST_GE_IDLE 0x00001000 /* GE is idle */
7008 +#define ST_GPIO_1 0x00002000 /* GPIO pin 1 */
7009 +#define ST_GPIO_2 0x00004000 /* GPIO pin 2 */
7010 +#define ST_GPIO_3 0x00008000 /* GPIO pin 3 */
7012 +/* INT_RAW_STATUA_REG -- Interrupt Pin Raw Status Register */
7013 +#define GC1_VSE 0x00000001 /* GC1 - VSE */
7014 +#define GC1_VDE 0x00000004 /* GC1 - VDE */
7015 +#define GC2_VSE 0x00000010 /* GC2 - VSE */
7016 +#define GC2_VDE 0x00000040 /* GC2 - VDE */
7017 +#define INT_GE_BUSY 0x00000100 /* GE busy */
7018 +#define SFIFO_EMPTY 0x00000200 /* Source fifo empty */
7019 +#define SFIFO_HEMPTY 0x00000400 /* Source fifo half empty */
7020 +#define CFIFO_EMPTY 0x00000800 /* Command fifo empty */
7021 +#define CFIFO_HEMPTY 0x00001000 /* Command fifo half empty */
7022 +#define GPIO_PIN_1 0x00002000 /* GPIO pin 1 */
7023 +#define GPIO_PIN_2 0x00004000 /* GPIO pin 2 */
7024 +#define GPIO_PIN_3 0x00008000 /* GPIO pin 3 */
7026 +/* 2D Engine registers - GE1 (0x00 - 0x7F) */
7027 +#define DRAW_CMD (GE_BASE + 0x00) /* Drawing command register */
7028 +#define WIDTH_HEIGHT (GE_BASE + 0x04) /* Width/height register */
7029 +#define LINE_DRAW WIDTH_HEIGHT /* Bresenham Line Draw reg */
7030 +#define DEST_XY (GE_BASE + 0x08) /* Destination X/Y register */
7031 +#define LINE_MAJOR_X DEST_XY /* Bresenham Line Start X/Y reg */
7032 +#define PAT_OFFSET DEST_XY /* Pattern Offset register */
7033 +#define SRC_XY (GE_BASE + 0x0C) /* Source X/Y register */
7034 +#define LINE_MINOR_Y SRC_XY /* Bresenham Line Delta register */
7035 +#define COLOR_COMPARE (GE_BASE + 0x10) /* Color compare register */
7036 +#define CLIP_LeftT (GE_BASE + 0x14) /* Clip Left/Top register */
7037 +#define CLIP_RightB (GE_BASE + 0x18) /* Clip Right/Bottom register */
7038 +#define FG_COLOR (GE_BASE + 0x1C) /* Fg color for Mono src reg */
7039 +#define BG_COLOR (GE_BASE + 0x20) /* Bg color for Mono src reg */
7040 +#define SRC_STRIDE_OFFSET (GE_BASE + 0x24) /* Source Stride & Offset Reg */
7041 +#define DEST_STRIDE (GE_BASE + 0x28) /* Base address register */
7042 +#define BASE_ADDRESS (GE_BASE + 0x2C) /* Base address register */
7043 +#define TEST_RESULT_REG (GE_BASE + 0x7C) /* Test result register */
7044 +#define COLOR_PATTERN (GE_BASE + 0x100) /* Color pattern registers */
7045 +#define MONO_PATTERN0 COLOR_PATTERN /* Mono Pattern register 0 */
7046 +#define MONO_PATTERN1 (GE_BASE + 0x104) /* Mono Pattern register 1 */
7047 +#define PAT_FG_COLOR (GE_BASE + 0x108) /* Mono Pattern Fg color reg */
7048 +#define PAT_BG_COLOR (GE_BASE + 0x10C) /* Mono Pattern Bg color reg */
7049 +#define _FIRST_GE DRAW_CMD
7050 +#define _LAST_GE (COLOR_PATTERN + 0x80)
7051 +#define SRC_IMAGE_DATA (GE_BASE + 0xC000) /* Source Data register */
7053 +/* 2D Engine registers - GE2 (0x80 to 0xFF) */
7054 +#define DRAW_CMD2 (GE2_BASE + 0x00) /* Drawing command register */
7055 +#define WIDTH_HEIGHT2 (GE2_BASE + 0x04) /* Width/height register */
7056 +#define LINE_DRAW2 WIDTH_HEIGHT2 /* Bresenham Line Draw register */
7057 +#define DEST_XY2 (GE2_BASE + 0x08) /* Destination X/Y register */
7058 +#define LINE_MAJOR_X2 DEST_XY2 /* Bresenham Line Start X/Y reg */
7059 +#define PAT_OFFSET2 DEST_XY2 /* Pattern Offset register */
7060 +#define SRC_XY2 (GE2_BASE + 0x0C) /* Source X/Y register */
7061 +#define LINE_MINOR_Y2 SRC_XY2 /* Bresenham Line Delta register */
7062 +#define COLOR_COMPARE2 (GE2_BASE + 0x10) /* Color compare register */
7063 +#define CLIP_LeftT2 (GE2_BASE + 0x14) /* Clip Left/Top register */
7064 +#define CLIP_RightB2 (GE2_BASE + 0x18) /* Clip Right/Bottom register */
7065 +#define FG_COLOR2 (GE2_BASE + 0x1C) /* Fg color for Mono src reg */
7066 +#define BG_COLOR2 (GE2_BASE + 0x20) /* Bg color for Mono src reg */
7067 +#define SRC_STRIDE_OFFSET2 (GE2_BASE + 0x24) /* Source Stride & Offset Reg */
7068 +#define DEST_STRIDE2 (GE2_BASE + 0x28) /* Base address register */
7069 +#define BASE_ADDRESS2 (GE2_BASE + 0x2C) /* Base address register */
7070 +#define TEST_RESULT_REG2 (GE2_BASE + 0x7C) /* Test result register */
7071 +#define COLOR_PATTERN2 (GE2_BASE + 0x100) /* Color pattern registers */
7072 +#define MONO_PATTERN02 COLOR_PATTERN2 /* Mono Pattern register 0 */
7073 +#define MONO_PATTERN12 (GE2_BASE + 0x104) /* Mono Pattern register 1 */
7074 +#define PAT_FG_COLOR2 (GE2_BASE + 0x108) /* Mono Pattern Fg color reg */
7075 +#define PAT_BG_COLOR2 (GE2_BASE + 0x10C) /* Mono Pattern Bg color reg */
7076 +#define _FIRST_GE2 DRAW_CMD2
7077 +#define _LAST_GE2 (COLOR_PATTERN2 + 0x80)
7078 +#define SRC_IMAGE_DATA2 (GE2_BASE + 0xC000) /* Source Data register */
7081 +/* DEST_STRIDE color depth */
7082 +#define GE_8BPP 0x00000000 /* 8BPP mode */
7083 +#define GE_16BPP 0x40000000 /* 16BPP mode */
7084 +#define GE_24BPP 0x80000000 /* 24BPP mode */
7085 +#define GE_32BPP 0xC0000000 /* 24BPP mode */
7088 +#define GE_TEST_MODE_ENABLE 0x20000000 /* Test mode enabled */
7089 +#define GE_TEST_MASK 0xc0000000 /* Test mode read path select */
7090 +#define SEL_CLIP_LR 0x40000000 /* Select clipping left/right */
7091 +#define SEL_CLIP_TB 0x80000000 /* Select clipping top/bottom */
7093 +/* Draw command register bits */
7094 +#define DO_BITBLT 0x00000200
7095 +#define DO_AAFONT 0x00000300
7096 +#define DO_LINEDRAW 0x00000400
7097 +#define X_DIR 0x00000800 /* Negative X direction */
7098 +#define Y_DIR 0x00001000 /* Negative Y direction */
7099 +#define SRC_IS_MEMORY 0x00002000 /* Source is in system memory */
7100 +#define MONO_SRC 0x00004000 /* Source is mono bitmap */
7101 +#define MONO_PATTERN 0x00008000 /* Pattern is monochrome */
7102 +#define TRANS_COLOR 0x00010000 /* Transparency is enabled */
7103 +#define TRANS_NOT_EQUAL 0x00020000 /* Polarity for color */
7104 +#define TRANS_MONO 0x00040000 /* Mono xparency is enabled */
7105 +#define TRANS_MONO_FG 0x00080000 /* Polarity for mono */
7106 +#define PACKED_MODE 0x00100000 /* Memory xfer mode select */
7107 +#define ALPHA_BYTE_MASK 0x00600000 /* Alpha Byte mask for 32bpp */
7108 +#define MONO_SOLID 0x00800000 /* Solid Mono Pattern */
7109 +#define SRC_NE_DEST_STRIDE 0x01000000 /* Src Not Equal Dest Stride */
7110 +#define ROP2_ENABLE 0x02000000 /* Use Rop2 code */
7111 +#define CLIP_ENABLE 0x04000000 /* Clipping is enabled */
7112 +#define AUTO_EXEC 0x08000000 /* Auto execute at dest X/Y */
7113 +#define VDE_GC2_ENABLE 0x10000000 /* Enable falling edge check */
7114 +#define VDE_GC1_ENABLE 0x20000000 /* Enable falling edge check */
7115 +#define COLOR_DEPTH_MASK 0xC0000000 /* Color Depth mask */
7116 +#define GE_8BPP 0x00000000 /* 8BPP mode */
7117 +#define GE_16BPP 0x40000000 /* 16BPP mode */
7118 +#define GE_24BPP 0x80000000 /* 24BPP mode */
7120 +/* Graphics Controller 1 Registers */
7121 +#define GC1_CONTROL (GC_BASE + 0x00) /* Graphics Controll 1 Control Reg */
7122 +#define GC1_CRT_CONTROL (GC_BASE + 0x04) /* CRT controll register */
7123 +#define HD1_CONTROL (GC_BASE + 0x08) /* Horizontal Display 1 Control */
7124 +#define VD1_CONTROL (GC_BASE + 0x0C) /* Vertical Display 1 Control */
7125 +#define HS1_CONTROL (GC_BASE + 0x10) /* Horizontal Sync 1 Control */
7126 +#define VS1_CONTROL (GC_BASE + 0x14) /* Vertical Sync 1 Control */
7127 +#define HW1_CONTROL (GC_BASE + 0x20) /* Horizontal Window 1 Control */
7128 +#define VW1_CONTROL (GC_BASE + 0x24) /* Vertical Window 1 Control */
7129 +#define AHW1_CONTROL (GC_BASE + 0x28) /* Alt Horizontal Window 1 Control */
7130 +#define AVW1_CONTROL (GC_BASE + 0x2C) /* Alt Vertical Window 1 Control */
7131 +#define IW1_START_ADDR (GC_BASE + 0x30) /* Image Window 1 Start Address */
7132 +#define AIW1_START_ADDR (GC_BASE + 0x34) /* Alt Image Window 1 Start Address */
7133 +#define IW1_STRIDE (GC_BASE + 0x38) /* (Alt) Image Window 1 Stride */
7134 +#define IW1_LINE_SIZE (GC_BASE + 0x3C) /* (Alt) Image Window 1 Line Size */
7135 +#define HW_CURSOR1_POS (GC_BASE + 0x40) /* Hardware cursor 1 position */
7136 +#define HW_CURSOR1_ADDR (GC_BASE + 0x44) /* Start address and offset */
7137 +#define HW_CURSOR1_FGCLR (GC_BASE + 0x48) /* Foreground color */
7138 +#define HW_CURSOR1_BGCLR (GC_BASE + 0x4C) /* Background color */
7140 +/* Graphics Controller 2 Registers */
7141 +#define GC2_CONTROL (GC_BASE + 0x80) /* Graphics Controll 2 Control Reg */
7142 +#define GC2_CRC_CONTROL (GC_BASE + 0x84) /* CRC Control */
7143 +#define HD2_CONTROL (GC_BASE + 0x88) /* Horizontal Display 2 Control */
7144 +#define VD2_CONTROL (GC_BASE + 0x8C) /* Vertical Display 2 Control */
7145 +#define HS2_CONTROL (GC_BASE + 0x90) /* Horizontal Sync 2 Control */
7146 +#define VS2_CONTROL (GC_BASE + 0x94) /* Vertical Sync 2 Control */
7147 +#define HW2_CONTROL (GC_BASE + 0xA0) /* Horizontal Window 2 Control */
7148 +#define VW2_CONTROL (GC_BASE + 0xA4) /* Vertical Window 2 Control */
7149 +#define AHW2_CONTROL (GC_BASE + 0xA8) /* Alt Horizontal Window 2 Control */
7150 +#define AVW2_CONTROL (GC_BASE + 0xAC) /* Alt Vertical Window 2 Control */
7151 +#define IW2_START_ADDR (GC_BASE + 0xB0) /* Image Window 2 Start Address */
7152 +#define AIW2_START_ADDR (GC_BASE + 0xB4) /* Alt Image Window 2 Start Address */
7153 +#define IW2_STRIDE (GC_BASE + 0xB8) /* (Alt) Image Window 2 Stride */
7154 +#define IW2_LINE_SIZE (GC_BASE + 0xBC) /* (Alt) Image Window 2 Line Size */
7155 +#define HW_CURSOR2_POS (GC_BASE + 0xC0) /* Hardware cursor 2 position */
7156 +#define HW_CURSOR2_ADDR (GC_BASE + 0xC4) /* Start address and offset */
7157 +#define HW_CURSOR2_FGCLR (GC_BASE + 0xC8) /* Foreground color */
7158 +#define HW_CURSOR2_BGCLR (GC_BASE + 0xCC) /* Background color */
7160 +/* GC1_CONTROL/GC2_CONTROL register */
7161 +#define GC_ENABLE 0x00000001UL /* Controll 1/2 enabled */
7162 +#define GC_DISABLE 0xfffffffeUL /* Controll 1/2 disabled */
7163 +#define HORZ_COUNT_RESET 0x00000002UL /* Horiz counter 1/2 reset */
7164 +#define VERT_COUNT_RESET 0x00000004UL /* Vertical counter 1/2 reset */
7165 +#define IM_ENABLE 0x00000008UL /* Image Window 1/2 Enable */
7166 +#define IM_DISABLE 0xfffffff7UL /* Image Window 1/2 Disable */
7168 +#define GC_1BPP 0x00000000UL /* GC1/2 color depth */
7169 +#define GC_2BPP 0x00000010UL
7170 +#define GC_4BPP 0x00000020UL
7171 +#define GC_8BPP 0x00000030UL
7172 +#define GC_16BPP 0x00000040UL /* with color palette enabled */
7173 +#define GC_24BPP_NBP 0x00000050UL /* with color palette enabled */
7174 +#define GC_32BPP_ABGR 0x00000060UL /* with color palette enabled */
7175 +#define GC_32BPP_ARGB 0x00000070UL /* with color palette enabled */
7176 +#define GC_16BPP_BP 0x000000C0UL /* with color pal bypassed */
7177 +#define GC_24BPP_BP 0x000000D0UL /* with color pal bypassed */
7178 +#define GC_32BPP_ABGR_BP 0x000000E0UL /* with color pal bypassed */
7179 +#define GC_32BPP_ARGB_BP 0x000000F0UL /* with color pal bypassed */
7180 +#define GC_32BPP GC_32BPP_ARGB /* Default 32bpp with ARGB */
7181 +#define GC_24BPP GC_24BPP_NBP
7183 +#define HC_ENABLE 0x00000100UL /* Hardware cursor enable */
7184 +#define HC_DISABLE 0xfffffeffUL /* And mask to disable HC */
7185 +#define AIM_ENABLE 0x00000800UL /* Alt Image Win 1/2 Enable */
7187 +#define AGC_1BPP 0x00000000UL /* Alt GC1/2 color depth */
7188 +#define AGC_2BPP 0x00001000UL
7189 +#define AGC_4BPP 0x00002000UL
7190 +#define AGC_8BPP 0x00003000UL
7191 +#define AGC_16BPP 0x00004000UL
7192 +#define AGC_24BPP 0x00005000UL
7193 +#define AGC_32BPP_ABGR 0x00006000UL
7194 +#define AGC_32BPP_ARGB 0x00007000UL
7195 +#define AGC_16BPP_BP 0x0000C000UL
7196 +#define AGC_24BPP_BP 0x0000D000UL
7197 +#define AGC_32BPP_ABGR_BP 0x0000E000UL
7198 +#define AGC_32BPP_ARGB_BP 0x0000F000UL
7199 +#define AGC_32BPP AGC_32BPP_ARGB_BP /* Default 32bpp w/ ARGB_BP */
7201 +#define GxRCLK_BUSCLK 0x00000000UL /* G1RCLK source is bus clock */
7202 +#define GxRCLK_PLL1 0x00010000UL /* G1RCLK source is PLL1 */
7203 +#define GxRCLK_PLL2 0x00020000UL /* G1RCLK source is PLL2 */
7204 +#define GxRCLK_PLL3 0x00030000UL /* G1RCLK source is PLL3 */
7205 +#define GxRCLK_PLL_MASK 0x00030000UL /* G1RCLK source mask */
7206 +#define GC_TEST_MODE0 0x00040000UL /* Test mode 0 enabled */
7207 +#define GC_TEST_MODE1 0x00080000UL /* Test mode 1 enabled */
7209 +#define FDx_1 0x00000000UL /* FD1 = 1 */
7210 +#define FDx_15 0x00100000UL /* FD1 = 1.5 */
7211 +#define FDx_25 0x00200000UL /* FD1 = 2.5 */
7212 +#define FDx_35 0x00300000UL /* FD1 = 3.5 */
7213 +#define FDx_45 0x00400000UL /* FD1 = 4.5 */
7214 +#define FDx_55 0x00500000UL /* FD1 = 5.5 */
7215 +#define FDx_65 0x00600000UL /* FD1 = 6.5 */
7217 +/* GC1_CRT_CONTROL register */
7218 +#define CRT_ENABLE 0x00000001UL /* CRT DAC enabled */
7219 +#define CRT_DISABLE 0xfffffffeUL /* CRT DAC disabled -and mask */
7220 +#define CRT_BY_GC1 0x00000001UL /* CRT DAC driven by GC1 */
7221 +#define CRT_BY_GC2 0x00000003UL /* CRT DAC driven by GC2 */
7222 +#define CRT_BY_GCxMASK 0xfffffffcUL /* Mask for CRT DAC */
7223 +#define VSYNC_OUT_PMCLK 0x00000004UL /* CRT VSYNC output PMCLK
7225 +#define HSYNC_OUT_PMCLK 0x00000008UL /* CRT HSYNC output PMCLK
7227 +#define HSYNC_OUT_LOW 0x00000010UL /* CRT HSYNC output pin low */
7228 +#define HSYNC_OUT_HIGH 0x00000020UL /* CRT HSYNC output pin high */
7229 +#define VSYNC_OUT_LOW 0x00000040UL /* CRT VSYNC output pin low */
7230 +#define VSYNC_OUT_HIGH 0x00000080UL /* CRT VSYNC output pin high */
7231 +#define HSYNC_POLARITY_LOW 0x00000100UL /* active low */
7232 +#define VSYNC_POLARITY_LOW 0x00000200UL /* active low */
7233 +#define SYNC_PED_ENABLE 0x00000400UL /* Sync pedestal enable */
7234 +#define BLANK_PED_ENABLE 0x00000800UL /* Blank pedestal enable */
7235 +#define CSYNC_ENABLE 0x00001000UL /* Composite Sync Enable */
7236 +#define VREF_EXTERNAL 0x00002000UL /* Select external VREF */
7237 +#define MON_SENSE_ENABLE 0x00004000UL /* CRT DAC monitor sense
7239 +#define CONST_OUT_ENABLE 0x00008000UL /* Constant output enable */
7240 +#define BLUE_NOT_LOADED 0x01000000UL /* Blue DAC is not loaded */
7241 +#define GREEN_NOT_LOADED 0x02000000UL /* Green DAC is not loaded */
7242 +#define RED_NOT_LOADED 0x04000000UL /* Red DAC is not loaded */
7244 +/* GC2_CRC_CONTROL */
7245 +#define CRC_ENABLE 0x00000001UL /* Enable CRC logic */
7246 +#define CRC_2_VSYNC 0x00000002UL /* Wait for 2 vsync */
7247 +#define CRC_READ_BLUE 0x00000000UL /* Read CRC result for blue */
7248 +#define CRC_READ_GREEN 0x00000004UL /* Read CRC result for green */
7249 +#define CRC_READ_RED 0x00000008UL /* Read CRC result for red */
7250 +#define CRC_RESULT_MASK 0x3fffff00UL /* CRC result mask */
7252 +/* Flat Panel Interface Registers */
7253 +#define FP_CONTROL (FP_BASE + 0x00) /* Flat panel control */
7254 +#define FP_PIN_CONTROL (FP_BASE + 0x04) /* Flat panel pin control */
7255 +#define FP_GPO_CONTROL (FP_BASE + 0x08) /* FP Gen. purpose output ctrl */
7256 +#define FP_GPIO_CONTROL (FP_BASE + 0x0C) /* FP Gen. purpose I/O control */
7257 +#define STN_CONTROL (FP_BASE + 0x10) /* STN panel control */
7258 +#define DSTN_FB_CONTROL (FP_BASE + 0x14) /* D-STN frame buffer control */
7259 +#define PWM_CONTROL (FP_BASE + 0x3C) /* PWM control */
7260 +#define FRC_PATTERN (FP_BASE + 0x40) /* FRC pattern starting index */
7261 +#define FRC_WEIGHT (FP_BASE + 0xC0) /* FRC weight starting index */
7264 +#define FPI_ENABLE 0x00000001UL /* Trigger fp power up sequence */
7265 +#define FPI_DISABLE 0xfffffffeUL /* Trigger fp power down sequence */
7266 +#define FPI_BY_GC1 0x00000001UL /* FPI enabled & driven by GC1 */
7267 +#define FPI_BY_GC2 0x00000003UL /* FPI enabled & driven by GC2 */
7268 +#define FPI_BY_GCxMASK 0xfffffffcUL /* mask */
7269 +#define FP_TYPE_TFT 0x00000000UL /* Flat panel type TFT */
7270 +#define FP_TYPE_SSTN 0x00000004UL /* Flat panel type S-STN */
7271 +#define FP_TYPE_DSTN 0x00000008UL /* Flat panel type D-STN */
7272 +#define FP_TYPE_MASK 0x0000000cUL /* Flat panel type mask */
7273 +#define FP_COLOR 0x00000000UL /* Color flat panel */
7274 +#define FP_MONO 0x00000010UL /* Mono flat panel */
7275 +#define TFT_4BITS_MONO 0x00000000UL /* Specify num of bits/pixel */
7276 +#define TFT_12BITS_COLOR 0x00000000UL /* Specify num of bits/pixel */
7277 +#define SSTN_4BITS_MONOCLR 0x00000000UL /* Specify num of bits/pixel */
7278 +#define DSTN_8BITS_MONOCLR 0x00000000UL /* Specify num of bits/pixel */
7279 +#define TFT_6BITS_MONO 0x00000020UL /* Specify num of bits/pixel */
7280 +#define TFT_18BITS_COLOR 0x00000020UL /* Specify num of bits/pixel */
7281 +#define SSTN_8BITS_MONOCLR 0x00000020UL /* Specify num of bits/pixel */
7282 +#define DSTN_16BITS_MONOCLR 0x00000020UL /* Specify num of bits/pixel */
7283 +#define TFT_8BITS_MONO 0x00000040UL /* Specify num of bits/pixel */
7284 +#define TFT_24BITS_COLOR 0x00000040UL /* Specify num of bits/pixel */
7285 +#define SSTN_12BITS_COLOR 0x00000040UL /* Specify num of bits/pixel */
7286 +#define DSTN_24BITS_COLOR 0x00000040UL /* Specify num of bits/pixel */
7287 +#define SSTN_16BITS_MONOCLR 0x00000060UL /* Specify num of bits/pixel */
7288 +#define SSTN_24BITS_COLOR 0x00000080UL /* Specify num of bits/pixel */
7289 +#define DITHER_PATTERN_0 0x00000000UL /* Dither pattern */
7290 +#define DITHER_PATTERN_1 0x00000100UL /* Dither pattern */
7291 +#define DITHER_PATTERN_2 0x00000200UL /* Dither pattern */
7292 +#define DITHER_PATTERN_3 0x00000300UL /* Dither pattern */
7293 +#define DITHER_BASE_8BITS 0x00000000UL /* No dithering */
7294 +#define DITHER_BASE_2BITS 0x00002000UL /* Num of bits to be dithered */
7295 +#define DITHER_BASE_3BITS 0x00003000UL /* Num of bits to be dithered */
7296 +#define DITHER_BASE_4BITS 0x00004000UL /* Num of bits to be dithered */
7297 +#define DITHER_BASE_6BITS 0x00006000UL /* Num of bits to be dithered */
7298 +#define FRC_ALTWIN_DISABLE 0x00008000UL /* Disable Dither/FRC if Alt enabled */
7299 +#define FRC_2LEVEL 0x00000000UL /* Disable FRC */
7300 +#define FRC_4LEVEL 0x00010000UL /* 4-level FRC */
7301 +#define FRC_8LEVEL 0x00020000UL /* 8-level FRC */
7302 +#define FRC_16LEVEL 0x00030000UL /* 16-level FRC */
7303 +#define DITHER_PATTERN_ADJ1 0x00fc0000UL /* Dither pattern adjust 1 */
7304 +#define DITHER_PATTERN_ADJ2 0x07000000UL /* Dither pattern adjust 2 */
7305 +#define DITHER_PATTERN_ADJ3 0x08000000UL /* Dither pattern adjust 3 */
7306 +#define TEST_MODE0_ENABLE 0x10000000UL /* Enable test mode 0 */
7307 +#define TEST_MODE1_ENABLE 0x20000000UL /* Enable test mode 1 */
7308 +#define TEST_MODE2_ENABLE 0x40000000UL /* Enable test mode 2 */
7309 +#define TEST_MODE3_ENABLE 0x80000000UL /* Enable test mode 3 */
7311 +/* FP_PIN_CONTROL */
7312 +#define FP_PIN_DISABLE 0x00000001UL /* Disable flat panel pins */
7313 +#define DATA_INV_ENABLE 0x00000002UL /* TFT fp data inversion enabled */
7314 +#define FP_DISP_ENABLE 0x00000004UL /* FP Display enable control */
7315 +#define FMOD_ENABLE 0x00000008UL /* Flat panel AC mod enable */
7316 +#define FD2_SCLK 0x00000010UL /* STN output shift clk on FD2 pin*/
7317 +#define FSCLK_OUTPUT_ENABLE 0x00000020UL /* FSCLK output enable */
7318 +#define TFT_SCLK_SELECT 0x00000040UL /* TFT shift clock select */
7319 +#define SCLK_MASK 0x00000080UL /* Shift clock mask */
7320 +#define STN_LP_DISABLE 0x00000100UL /* STN LP control */
7321 +#define SCLK_DISABLE 0x00000200UL /* STN shift clock control */
7322 +#define STN_ExtraLP_ENABLE 0x00000400UL /* STN extra LP control */
7323 +#define FP_FD2_MAX 0x00000000UL /* FD2 drive strength - max (16mA)*/
7324 +#define FP_FD2_MEDIUM 0x00001000UL /* FD2 drive strength - medium */
7325 +#define FP_FD2_MEDIUM2 0x00002000UL /* FD2 drive strength - medium 2 */
7326 +#define FP_FD2_MIN 0x00003000UL /* FD2 drive strength - min */
7327 +#define FP_DATA_MAX 0x00000000UL /* Data drv strength - max (16mA) */
7328 +#define FP_DATA_MEDIUM 0x00004000UL /* Data drive strength - medium */
7329 +#define FP_DATA_MEDIUM2 0x00008000UL /* Data drive strength - medium 2 */
7330 +#define FP_DATA_MIN 0x0000c000UL /* Data drive strength - min */
7331 +#define FD2_ACTIVE_L 0x00010000UL /* Flat panel data bit 2 polarity */
7332 +#define FD_ACTIVE_L 0x00020000UL /* Flat panel data polarity */
7333 +#define FDE_ACTIVE_L 0x00040000UL /* Data enable polarity */
7334 +#define FHSYNC_ACTIVE_L 0x00080000UL /* Horz sync polarity */
7335 +#define FVSYNC_ACTIVE_L 0x00100000UL /* Vert sync polarity */
7336 +#define FSCLK_ACTIVE_L 0x00200000UL /* Shift clock polarity */
7337 +#define FP_FSCLK_MAX 0x00000000UL /* Sh clk drv strength -max (16mA)*/
7338 +#define FP_FSCLK_MEDIUM 0x00400000UL /* Sh clk drv strength -medium */
7339 +#define FP_FSCLK_MEDIUM2 0x00800000UL /* Sh clk drv strength -medium 2 */
7340 +#define FP_FSCLK_MIN 0x00c00000UL /* Sh clk drv strength -min */
7341 +#define FSCLK_DELAY 0x07000000UL /* Shift clock delay */
7343 +/* FP_GPO_CONTROL */
7344 +#define ENCTL_AS_GPO0 0x00000001UL /* ENCTL used as GPO 0 */
7345 +#define ENCTL_AS_OSC 0x00000002UL /* ENCTL used as Oscillator clock */
7346 +#define ENCTL_AS_PLL3 0x00000003UL /* ENCTL used as PLL3 clock */
7347 +#define ENVEE_AS_GPO1 0x00000004UL /* ENVEE used as GPO 1 */
7348 +#define PWM0_AS_GPO2 0x00000010UL /* PWM0 pin used as GPO 2 */
7349 +#define PWM1_AS_GPO3 0x00000040UL /* PWM1 pin used as GPO 3 */
7350 +#define ENVDD_AS_GPO4 0x00000100UL /* ENVDD pin used as GPO 4 */
7351 +#define FP_PWM_MAX 0x00000000UL /* PWM0/1 drv strength -max (16mA)*/
7352 +#define FP_PWM_MEDIUM 0x00000400UL /* PWM0/1 drv strength -medium */
7353 +#define FP_PWM_MEDIUM2 0x00000800UL /* PWM0/1 drv strength -medium 2 */
7354 +#define FP_PWM_MIN 0x00000c00UL /* PWM0/1 drv strength -min */
7355 +#define FP_GPIO_MAX 0x00000000UL /* GPIO0/1/2 drv strgth. -max 16mA*/
7356 +#define FP_GPIO_MEDIUM 0x00001000UL /* GPIO0/1/2 drv strgth. -medium */
7357 +#define FP_GPIO_MEDIUM2 0x00002000UL /* GPIO0/1/2 drv strgth. -medium 2*/
7358 +#define FP_GPIO_MIN 0x00003000UL /* GPIO0/1/2 drv strgth. -min */
7359 +#define FP_EN_MAX 0x00000000UL /* ENVDD/ENCTL/ENVEE -max (16mA) */
7360 +#define FP_EN_MEDIUM 0x00004000UL /* ENVDD/ENCTL/ENVEE -medium */
7361 +#define FP_EN_MEDIUM2 0x00008000UL /* ENVDD/ENCTL/ENVEE -medium 2 */
7362 +#define FP_EN_MIN 0x0000c000UL /* ENVDD/ENCTL/ENVEE -min */
7363 +#define GPO0_DATA_HIGH 0x00010000UL /* ENCTL is driven high */
7364 +#define GPO1_DATA_HIGH 0x00020000UL /* ENVEE is driven high */
7365 +#define GPO2_DATA_HIGH 0x00040000UL /* PWM0 is driven high */
7366 +#define GPO3_DATA_HIGH 0x00080000UL /* PWM1 is driven high */
7367 +#define GPO4_DATA_HIGH 0x00100000UL /* ENVDD is driven high */
7369 +/* FP_GPIO_CONTROL */
7370 +#define GPIO0_IN 0x00000000UL /* General-purpose input */
7371 +#define GPIO0_OUT 0x00000001UL /* General-purpose output */
7372 +#define GPIO0_PLL1 0x00000002UL /* GPIO0 used to output PLL 1 clk */
7373 +#define GPIO0_CRC_B 0x00000003UL /* GPIO0 used to output CRC Blue */
7374 +#define GPIO1_IN 0x00000000UL /* General-purpose input */
7375 +#define GPIO1_OUT 0x00000004UL /* General-purpose output */
7376 +#define GPIO1_PLL2 0x00000008UL /* GPIO1 used to output PLL 2 clk */
7377 +#define GPIO1_CRC_G 0x0000000cUL /* GPIO1 used to output CRC Green */
7378 +#define GPIO2_IN 0x00000000UL /* General-purpose input */
7379 +#define GPIO2_OUT 0x00000010UL /* General-purpose output */
7380 +#define GPIO2_PLL3 0x00000020UL /* GPIO2 used to output PLL 3 clk */
7381 +#define GPIO2_CRC_R 0x00000030UL /* GPIO2 used to output CRC Red */
7382 +#define GPIO0_OUT_HIGH 0x00010000UL /* GOIO0 output data */
7383 +#define GPIO1_OUT_HIGH 0x00020000UL /* GOIO1 output data */
7384 +#define GPIO2_OUT_HIGH 0x00040000UL /* GOIO2 output data */
7385 +#define GPIO0_IN_HIGH 0x01000000UL /* GOIO0 input data */
7386 +#define GPIO1_IN_HIGH 0x02000000UL /* GOIO1 input data */
7387 +#define GPIO2_IN_HIGH 0x04000000UL /* GOIO2 input data */
7390 +#define FMOD_FRAMECLK 0x00000000UL /* FMOD generated using frame clock */
7391 +#define FMOD_LINECLK 0x80000000UL /* FMOD generated using line clock */
7394 +#define PWM0_BY_PLL 0x00000000UL /* PWM 0 signal by PLL */
7395 +#define PWM0_BY_BUS 0x00000001UL /* PWM 0 signal using bus clk */
7396 +#define PWM0_BY_PMC 0x00000002UL /* PWM 0 signal by power mgt clock */
7397 +#define PWM0_ALWAYS_ON 0x00000004UL /* PWM 0 signal always generated */
7398 +#define PWM0_DC_MASK 0xffff00ffUL /* PWM 0 duty cycle mask */
7399 +#define PWM0_MASK 0xffff0000UL /* PWM 0 mask */
7400 +#define PWM1_BY_PLL 0x00000000UL /* PWM 1 signal by PLL */
7401 +#define PWM1_BY_BUS 0x00010000UL /* PWM 1 signal using bus clk */
7402 +#define PWM1_BY_PMC 0x00020000UL /* PWM 1 signal by power mgt clock */
7403 +#define PWM1_ALWAYS_ON 0x00040000UL /* PWM 1 signal always generated */
7404 +#define PWM1_DC_MASK 0x00ffffffUL /* PWM 0 duty cycle mask */
7405 +#define PWM1_MASK 0x0000ffffUL /* PWM 1 mask */
7407 +/* PCI Power Management Interface Registers */
7408 +#ifndef PCI_VENDOR_DEVICE
7409 +#define PCI_VENDOR_DEVICE (PC_BASE + 0x00)
7412 +#ifndef PCI_CMD_STATUS
7413 +#define PCI_CMD_STATUS (PC_BASE + 0x04)
7416 +#ifndef PCI_REV_CLASS
7417 +#define PCI_REV_CLASS (PC_BASE + 0x08)
7420 +#ifndef PCI_HEADER_TYPE
7421 +#define PCI_HEADER_TYPE (PC_BASE + 0x0c)
7425 +#define PCI_SUB_ID (PC_BASE + 0x2c)
7428 +#ifndef PCI_ROM_BASE
7429 +#define PCI_ROM_BASE (PC_BASE + 0x30)
7432 +#ifndef PCI_CAP_PTR
7433 +#define PCI_CAP_PTR (PC_BASE + 0x34)
7436 +#ifndef PCI_INTERRUPT
7437 +#define PCI_INTERRUPT (PC_BASE + 0x3c)
7440 +#ifndef PCI_PM_REGISTER
7441 +#define PCI_PM_REGISTER (PC_BASE + 0x40)
7444 +#ifndef PCI_PM_CNTL_STATUS
7445 +#define PCI_PM_CNTL_STATUS (PC_BASE + 0x44)
7449 +#define POWER_STATE_MASK 0x00000003UL /* Device power state mask */
7450 +#define ENTER_D0 0x00000000UL /* Enter D0 state */
7451 +#define ENTER_D1 0x00000001UL /* Enter D1 state */
7452 +#define ENTER_D2 0x00000002UL /* Enter D2 state */
7453 +#define ENTER_D3 0x00000003UL /* Enter D3 state */
7455 +/* DC (Device Configuration Unit) Registers */
7456 +#define DC_0 (DC_BASE + 0x00) /* Device Configruation Register 0 */
7457 +#define DC_1 (DC_BASE + 0x04) /* Device Configruation Register 1 */
7458 +#define DC_SW_0 (DC_BASE + 0x08) /* Software Register 0 */
7459 +#define DC_SW_1 (DC_BASE + 0x0C) /* Software Register 1 */
7462 +#define OSC_BYPASSED 0x00000001UL /* Oscillator bypassed, powered down */
7463 +#define OSC_ENABLE 0x00000002UL /* Oscillator control can be enabled */
7464 +#define PLL1_BYPASSED 0x00000004UL /* PLL1 bypassed */
7465 +#define PLL1_ENABLE 0x00000008UL /* PLL1 can be enabled */
7466 +#define PLL1_DIVBY1 0x00000000UL /* PLL1 P output divisor by 1 */
7467 +#define PLL1_DIVBY2 0x00000010UL /* PLL1 P output divisor by 2 */
7468 +#define PLL1_DIVBY4 0x00000020UL /* PLL1 P output divisor by 4 */
7469 +#define PLL1_DIVBY8 0x00000030UL /* PLL1 P output divisor by 8 */
7470 +#define PLL1_DIVBY16 0x00000040UL /* PLL1 P output divisor by 16 */
7471 +#define PLL1_DIV_MASK 0x00000070UL /* PLL1 P output divisor mask */
7472 +#define CIF_DIVBY1 0x00000000UL /* CPU Interface clk divisor by 1 */
7473 +#define CIF_DIVBY2 0x00000080UL /* CPU Interface clk divisor by 2 */
7474 +#define STRONGARM_SYNC_F 0x00002000UL /* StrongARM bus intrf at fall edge */
7475 +#define SW_CHIP_RESET 0x00004000UL /* Software chip reset */
7476 +#define MEM_STANDBY_DISABLE 0x00008000UL /* Memory Power unit Standby disab. */
7477 +#define OSC_SHAPER_DISABLE 0x01000000UL /* Oscillator waveform shaper disab. */
7478 +#define FAST_POWER_DISABLE 0x02000000UL /* Fast Power Sequencing disable */
7479 +#define OSC_FREQ_SEL_0 0x00000000UL /* Osc frequency select range 0 */
7480 +#define OSC_FREQ_SEL_1 0x04000000UL /* Osc frequency select range 1 */
7481 +#define OSC_FREQ_SEL_2 0x08000000UL /* Osc frequency select range 2 */
7482 +#define OSC_FREQ_SEL_3 0x0c000000UL /* Osc frequency select range 3 */
7485 +#define BUS_MODE_MASK 0x0000003FUL /* Bus interface mode mask */
7486 +#define BUS_MODE_SH7709 0x00000001UL /* Bus interface mode - SH7709 */
7487 +#define BUS_MODE_SH7750 0x00000002UL /* Bus interface mode - SH7750 */
7488 +#define BUS_MODE_VR41xx 0x00000004UL /* Bus interface mode - VR4111/21 */
7489 +#define BUS_MODE_SA1110 0x00000008UL /* Bus interface mode - SA1110 */
7490 +#define BUS_MODE_TX3922 0x00000010UL /* Bus interface mode - TX3922 */
7491 +#define BUS_MODE_PCI 0x00000020UL /* Bus interface mode - PCI */
7493 +/* PMU (Power Management Unit) Registers */
7494 +#define PM_MISC (PM_BASE + 0x00) /* Power management misc ctrl */
7495 +#define D1_STATE (PM_BASE + 0x04) /* D1 state control */
7496 +#define D2_STATE (PM_BASE + 0x08) /* D2 state control */
7497 +#define PLL2_CONTROL (PM_BASE + 0x18) /* PLL2 programming */
7498 +#define PLL3_CONTROL (PM_BASE + 0x1C) /* PLL3 programming */
7501 +#define PLL1_N_BIT5 0x00000001UL /* Bit 5 of PLL1 N parameter */
7502 +#define PLL2_ENABLE 0x00000004UL /* PLL2 can be enabled */
7503 +#define PLL3_ENABLE 0x00000008UL /* PLL3 can be enabled */
7504 +#define FORCE_POWER_STATE 0x00000020UL /* For testing */
7505 +#define GE_ENABLE 0x00000100UL /* GE can be enabled */
7506 +#define GE_CLOCK_ON 0x00000200UL /* GE clock is always running */
7507 +#define GE_PIPELINE_ON 0x00000400UL /* GE pipeline always running */
7508 +#define GE_BY_BUS 0x00000000UL /* GE driven by bus intf clk */
7509 +#define GE_BY_PLL1 0x00000800UL /* GE driven by PLL1 */
7510 +#define GE_BY_PLL2 0x00001000UL /* GE driven by PLL2 */
7511 +#define GE_BY_PLL3 0x00001800UL /* GE driven by PLL3 */
7512 +#define GE_BY_MASK 0x00001800UL /* GE clock select mask */
7513 +#define GE_CMDFIFO_RESET 0x00002000UL /* GE command FIFO is reset */
7514 +#define GE_SRCFIFO_RESET 0x00004000UL /* GE CPU src FIFO is reset */
7515 +#define POWER_ON_IF_MIU_ON 0x00008000UL /* Pwr seq on when MIU enab.*/
7516 +#define D3_MEM_REFRESF 0x00010000UL /* FrameBuf refreshed in D3 */
7517 +#define D4_MEM_REFRESF 0x00020000UL /* FrameBuf refreshed in D4 */
7518 +#define PMCLK_4CYCLE 0x00000000UL /* Power sequencing interval */
7519 +#define PMCLK_8CYCLE 0x00040000UL /* Power sequencing interval */
7520 +#define PMCLK_16CYCLE 0x00080000UL /* Power sequencing interval */
7521 +#define PMCLK_2048CYCLE 0x000c0000UL /* Power sequencing interval */
7522 +#define FP_PMCLK_512 0x00000000UL /* FP power seq interval */
7523 +#define FP_PMCLK_1024 0x00100000UL /* FP power seq interval */
7524 +#define FP_PMCLK_2048 0x00200000UL /* FP power seq interval */
7525 +#define FP_PMCLK_128K 0x00300000UL /* FP power seq interval */
7526 +#define POWER_SEQ_ALL 0x00400000UL /* General power seq interval */
7527 +#define PMU_TEST_MODE 0x008000UL /* PMU test mode */
7528 +#define PM_POWER_MASK 0x03000000UL /* Power state mask */
7529 +#define PM_D0_STATE 0x00000000UL /* Power state D0 */
7530 +#define PM_D1_STATE 0x01000000UL /* Power state D1 */
7531 +#define PM_D2_STATE 0x02000000UL /* Power state D2 */
7532 +#define PM_D3_STATE 0x03000000UL /* Power state D3 */
7533 +#define POWER_IN_PROGRESS 0x04000000UL /* Power seq. active status */
7535 +/* D1_STATE and D2_STATE */
7536 +#define DxOSC_ENABLE 0x00000001UL /* Oscillator can be enabled in D1/2 */
7537 +#define DxPLL1_ENABLE 0x00000002UL /* PLL1 can be enabled in D1/2 */
7538 +#define DxPLL2_ENABLE 0x00000004UL /* PLL2 can be enabled in D1/2 */
7539 +#define DxPLL3_ENABLE 0x00000008UL /* PLL3 can be enabled in D1/2 */
7540 +#define DxMIU_ENABLE 0x00000010UL /* MIU can be enabled in D1/2 */
7541 +#define DxMEM_REFRESH 0x00000020UL /* Memory is refreshed in D1/2 */
7542 +#define DxGE_ENABLE 0x00000040UL /* GE can be enabled in D1/2 */
7543 +#define DxCRT_ENABLE 0x00000100UL /* CRT can be enabled in D1/2 */
7544 +#define DxFP_ENABLE 0x00000200UL /* Flat panel can be enabled in D1/2 */
7545 +#define DxGC1_ENABLE 0x00010000UL /* GC1 can be enabled in D1/2 */
7546 +#define DxW1_ENABLE 0x00020000UL /* Window 1 can be enabled in D1/2 */
7547 +#define DxAW1_ENABLE 0x00040000UL /* Alt window 1 enabled in D1/2 */
7548 +#define DxHC1_ENABLE 0x00080000UL /* Cursor 1 enabled in D1/2 */
7549 +#define DxGC2_ENABLE 0x01000000UL /* GC2 can be enabled in D1/2 */
7550 +#define DxW2_ENABLE 0x02000000UL /* Window 2 can be enabled in D1/2 */
7551 +#define DxAW2_ENABLE 0x04000000UL /* Alt window 2 enabled in D1/2 */
7552 +#define DxHC2_ENABLE 0x08000000UL /* Cursor 2 enabled in D1/2 */
7554 +/* PLL2_CONTROL/PLL3_CONTROL */
7555 +#define PLL_FROM_OSC 0x00000000UL /* PLL2/3 ref clock from OSCCLK */
7556 +#define PLL_FROM_PxCLK 0x00000001UL /* PLL2/3 ref clock from P2CLK */
7557 +#define PLL_BYPASSED 0x00000002UL /* PLL2/3 is bypassed */
7558 +#define PLL_DIVBY1 0x00000000UL /* PLL2/3 P output divisor by 1 */
7559 +#define PLL_DIVBY2 0x00000010UL /* PLL2/3 P output divisor by 2 */
7560 +#define PLL_DIVBY4 0x00000020UL /* PLL2/3 P output divisor by 4 */
7561 +#define PLL_DIVBY8 0x00000030UL /* PLL2/3 P output divisor by 8 */
7562 +#define PLL_DIVBY16 0x00000040UL /* PLL2/3 P output divisor by 16 */
7563 +#define PLL_DIV_MASK 0x00000070UL /* PLL2/3 P output divisor mask */
7565 +/* CPU Interface Registers */
7566 +#define CPU_CONTROL (CC_BASE + 0x00) /* CPU control register */
7567 +#define DRAW_STATUS (CC_BASE + 0x04) /* Drawing status register */
7570 +#define SW_RESET 0x00000002UL /* Reset all modules except CIF */
7571 +#define MIU_READ_REQ 0x00000004UL /* MIU read request */
7572 +#define CLKRUN_ENABLE 0x00000008UL /* CLKRUN enabled. On Pwr-on, disab. */
7575 +#define CMD_FIFO_MASK 0x0000001fUL /* Command FIFO entries mask */
7576 +#define SRC_FIFO_MASK 0x00000f00UL /* Source FIFO entry mask */
7577 +#define GE_BUSY 0x00010000UL /* Any command in Comm FIFO */
7578 +#define CMD_FIFO_FULL 0x00000000UL /* Cmd fifo full bit */
7579 +#define CMD_FIFO_EMPTY 0x00000010UL /* Cmd fifo empty, 16x32 bits free */
7580 +#define SRC_FIFO_FULL 0x00000000UL /* Src fifo full bit */
7581 +#define SRC_FIFO_EMPTY 0x00000800UL /* Src fifo empty, 8x128 bits free */
7583 +#define CMD_FIFO_CNT 16 /* Command FIFO full entry */
7584 +#define CMD_FIFO_MAX_INDEX 64
7585 +#define SRC_FIFO_MAX_BYTES 128 /* max pixels in src fifo - 8bits */
7586 +#define SRC_FIFO_MAX_WORDS 64 /* max pixels in src fifo - 16bits */
7587 +#define SRC_FIFO_MAX_DWORDS 32 /* max dwords in src fifo - 32bits */
7589 +/* MIU (Memory Interface Unit) Registers */
7590 +#define MIU_CONTROL1 (MM_BASE + 0x00) /* Memory interface control 1 */
7591 +#define MIU_CONTROL2 (MM_BASE + 0x04) /* Memory interface control 2 */
7592 +#define MIU_CONTROL3 (MM_BASE + 0x08) /* Memory interface control 3 */
7593 +#define MIU_CONTROL4 (MM_BASE + 0x0C) /* Memory interface control 4 */
7594 +#define MIU_CONTROL5 (MM_BASE + 0x10) /* Memory interface control 5 */
7597 +#define MIU_ENABLE 0x00000001UL /* Enable MIU */
7598 +#define MIU_RESET_DISABLE 0x00000002UL /* MIU reset is disabled */
7599 +#define DRAM_RESET_DISABLE 0x00000004UL /* DRAM reset is disabled */
7602 +#define CLK_FROM_BUS 0x00000001UL /* Bus clk for mem clk src */
7603 +#define CLK_FROM_PLL2 0x00000001UL /* PLL2 for mem clock source */
7604 +#define MEM_REFRESH_ENABLE 0x00000002UL /* Mem ref disab at pwr dw mod*/
7605 +#define CPU_PB_ENABLE 0x00000004UL /* Page Break enab after CPU mem cyc */
7606 +#define GC1_PB_ENABLE 0x00000008UL /* Page Break after GC1 mem cycles */
7607 +#define GC2_PB_ENABLE 0x00000010UL /* Page Break after GC2 mem cycles */
7608 +#define STN_R_PB_ENABLE 0x00000020UL /* Page Break after STN read mem cyc */
7609 +#define STN_W_PB_ENABLE 0x00000040UL /* Page Break after STN wr. mem cyc */
7610 +#define GE_PB_ENABLE 0x00000080UL /* Page Break after GE memory cycles */
7611 +#define AUTO_REF_ENABLE 0x40000000UL /* Standby sig enab. when MIU active */
7612 +#define STANDBY_ENABLE 0x80000000UL /* Standby sig enab. when MIU active */
7615 +#define DISPLAY_BURST2 0x00000000UL /* Burst size for disp mem refresh */
7616 +#define DISPLAY_BURST4 0x00000001UL
7617 +#define DISPLAY_BURST6 0x00000002UL
7618 +#define DISPLAY_BURST8 0x00000003UL
7619 +#define STN_R_BURST2 0x00000000UL /* Burst size for STN read mem cycle */
7620 +#define STN_R_BURST4 0x00000004UL
7621 +#define STN_R_BURST6 0x00000008UL
7622 +#define STN_R_BURST8 0x0000000cUL
7623 +#define STN_W_BURST2 0x00000000UL /* Burst size for STN write mem cyc */
7624 +#define STN_W_BURST4 0x00000010UL
7625 +#define STN_W_BURST6 0x00000020UL
7626 +#define STN_W_BURST8 0x00000030UL
7627 +#define GE_RW_BURST2 0x00000000UL /* Burst size for GE r/w mem cycle */
7628 +#define GE_RW_BURST4 0x00000040UL
7629 +#define GE_RW_BURST6 0x00000080UL
7630 +#define GE_RW_BURST8 0x000000c0UL
7631 +#define CPU_RW_BURST2 0x00000000UL /* Burst size for CPU r/w mem cycle */
7632 +#define CPU_RW_BURST4 0x00000100UL
7633 +#define CPU_RW_BURST6 0x00000200UL
7634 +#define CPU_RW_BURST8 0x00000300UL
7637 +#define R_LATENCY_REQUEST 0x00000001UL /* Read Latency Request */
7640 +#define LATENCY_1 0x00000001UL /* EDRAM Latency 1 */
7641 +#define LATENCY_2 0x00000005UL /* EDRAM Latency 2 */
7642 +#define LATENCY_3 0x00000007UL /* EDRAM Latency 3 */
7643 +#define DUMMY_IN_COMMANDS 0x00000008UL /* Dummy cycle insertion betw cmds */
7644 +#define DUMMY_IN_PRECHARGE 0x00000010UL /* Dummy cyc between precharge cyc */
7645 +#define DELAY_1ns 0x00000000UL /* Internal memory clock delay */
7646 +#define ACT_TO_CLOSE_3 0x00000100UL /* Bank activate to close - 3 mclk */
7647 +#define ACT_TO_CLOSE_4 0x00000200UL /* Bank activate to close - 4 mclk */
7648 +#define ACT_TO_CLOSE_5 0x00000300UL /* Bank activate to close - 5 mclk */
7649 +#define ACT_TO_COMMAND_2 0x00000000UL /* Bank activate to cmd r/w - 2 mclk */
7650 +#define ACT_TO_COMMAND_3 0x00000400UL /* Bank activate to cmd r/w - 3 mclk */
7651 +#define CLOSE_TO_ACT_2 0x00000000UL /* Bank close to activate - 2 mclk */
7652 +#define CLOSE_TO_ACT_3 0x00000800UL /* Bank close to activate - 3 mclk */
7653 +#define ROW_CYCLE_6 0x00000000UL /* Row Cycle time - 6 memory clock */
7654 +#define ROW_CYCLE_8 0x00001000UL /* Row Cycle time - 8 memory clock */
7655 +#define DELAY_R_CLOCK_0_0 0x00000000UL /* Delay for read clock - no delay */
7656 +#define DELAY_R_CLOCK_0_5 0x00010000UL /* Delay for read clock - 0.5ns */
7657 +#define DELAY_R_CLOCK_1_0 0x00020000UL /* Delay for read clock - 1.0ns */
7658 +#define DELAY_R_CLOCK_1_5 0x00030000UL /* Delay for read clock - 1.5ns */
7659 +#define DELAY_M_CLOCK_0_0 0x00000000UL /* Delay for memory clock - no delay */
7660 +#define DELAY_M_CLOCK_0_5 0x00020000UL /* Delay for memory clock - 0.5ns */
7661 +#define DELAY_M_CLOCK_1_0 0x00080000UL /* Delay for memory clock - 1.0ns */
7662 +#define DELAY_M_CLOCK_1_5 0x000c0000UL /* Delay for memory clock - 1.5ns */
7666 + * Data structure and defines for MQ chip and driver interface
7669 +/* Display configuration structure - for interface */
7670 +typedef struct DisplayConfig
7672 + int x; /* x resolution */
7673 + int y; /* y resolution */
7674 + int bpp; /* color depth */
7675 + int refresh; /* CRT refresh rate */
7676 + int stride; /* memory stride */
7677 + unsigned long flag; /* display flag */
7678 +} DISPLAY_CONFIG, *PDISPLAY_CONFIG;
7680 +/* Flag definition */
7681 +#define PANEL_TYPE_MASK 0x000000ff /* Panel type mask */
7682 +#define PROCESSOR_MASK 0x00003f00 /* Mask of processor type */
7683 +#define IS_SH3 0x00000000
7684 +#define IS_SH4 0x00000100
7685 +#define IS_NEC 0x00000200
7686 +#define IS_SARM 0x00000300
7687 +#define IS_TOSHIBA 0x00000400
7688 +#define IS_PCI 0x00000500
7689 +#define LCD_ON 0x00010000 /* LCD mode */
7690 +#define CRT_ON 0x00020000 /* CRT mode */
7691 +#define LARGE_DESKTOP 0x00040000 /* Large desktop mode is on */
7692 +#define INDEP_DISPLAY 0x00080000 /* Independent display */
7693 +#define SAME_IMAGE 0x00100000 /* Use 2 GC but same image */
7694 +#define USE_2GCs 0x001C0000 /* 2 GCs are used */
7695 +#define USE_2GCs_MASK 0x001C0000 /* mask for 2 GCs */
7696 +#define ENA_HW_CURSOR 0x00200000 /* Enable hw cursor */
7697 +#define HORI_LCD_CRT 0x00000000 /* QView hori arrangement */
7698 +#define HORI_CRT_LCD 0x10000000 /* QView hori arrangement */
7699 +#define VERT_CRT_LCD 0x20000000 /* QView vert arrangement */
7700 +#define VERT_LCD_CRT 0x30000000 /* QView vert arrangement */
7701 +#define LCDCRT_POS_MASK 0x30000000 /* mask for QV orientation */
7703 +/* Display timing structure */
7704 +typedef struct DisplayTiming
7706 + int x; /* x resolution */
7707 + int y; /* y resolution */
7708 + int refresh; /* refresh rate */
7709 + unsigned long hd; /* hori display control */
7710 + unsigned long vd; /* vert display control */
7711 + unsigned long hs; /* hori sync control */
7712 + unsigned long vs; /* vert sync control */
7713 + unsigned long crtc; /* crt control */
7714 + unsigned long pll; /* PLL2 or PLL3 setting */
7715 +} DISPLAY_TIMING, *PDISPLAY_TIMING;
7717 +/* Flat panel register */
7718 +typedef struct FPControl
7720 + int x; /* panel size x */
7721 + int y; /* panel size y */
7722 + int freq; /* panel freq */
7723 + unsigned long fpControl; /* flat panel control */
7724 + unsigned long fpPinControl; /* flat panel pin control */
7725 + unsigned long stnControl; /* stn panel control */
7726 +} FPDATA_CONTROL, *PFPDATA_CONTROL;
7728 +/* Frame rate control */
7729 +#define FRC_PATTERN_CNT 32
7730 +#define FRC_WEIGHT_CNT 8
7731 +typedef struct FRCControl
7733 + ULONG frcPattern[FRC_PATTERN_CNT]; /* FRC pattern control */
7734 + ULONG frcWeight[FRC_WEIGHT_CNT]; /* FRC weight control */
7735 +} FRC_CONTROL, *PFRC_CONTROL;
7737 +/* Miscellaneous defines */
7741 +/* Turn on/off display */
7742 +#define ENABLE_LCD_GC1 0
7743 +#define ENABLE_LCD_GC2 1
7744 +#define DISABLE_LCD_GC1 2
7745 +#define DISABLE_LCD_GC2 3
7746 +#define ENABLE_CRT_GC1 4
7747 +#define ENABLE_CRT_GC2 5
7748 +#define DISABLE_CRT_GC1 6
7749 +#define DISABLE_CRT_GC2 7
7756 +#define CHECK_IF_STATE_D(s) {\
7757 + unsigned long ulState = (s);\
7758 + unsigned long ulPMReg;\
7761 + ulPMReg = READ32(PCI_PM_CNTL_STATUS);\
7762 + if((ulPMReg &0x03) == ulState)\
7766 +#endif /* _VIDEO_MQ200_MQ2HW_H */
7769 +++ linux-2.4.27/include/video/MQ200/mqdata.h
7771 +/***************************************************************************
7774 + This file contains timing and flat panel parameters for MediaQ graphics
7777 + Copyright (c) 2000 by MediaQ, Incorporated.
7778 + All Rights Reserved.
7780 +***************************************************************************/
7781 +#ifndef _VIDEO_MQ200_MQDATA_H
7782 +#define _VIDEO_MQ200_MQDATA_H
7783 +/* LCD/CRT timing parameters for each resolution - VESA modes
7785 + * . the first entry is reserved to provide customized panel timing support
7786 + * . OEM can fill in proper timing for non-VESA LCD (or CRT)
7789 +DISPLAY_TIMING TimingParam[] =
7791 + { /* customized refresh rate - reserved for non-VESA panel timing */
7792 + 0,0,0, /* X/Y/Freq */
7793 + 0, /* HD Total + HD End */
7794 + 0, /* VD Total + VD End */
7795 + 0, /* HS Start + HS End */
7796 + 0, /* VS Start + VS End */
7797 + 0x00000000, /* CRT control */
7798 + 0x00000000, /* PLLx multiplier and control */
7801 + { /* 640 x 240 90Hz (25.175 MHz) */
7802 + 640,240,90, /* X/Y/Freq */
7803 + (793-2) | (640L << 16), /* HD Total + HD End */
7804 + (262-1) | ((240L-1) << 16), /* VD Total + VD End */
7805 + 647 | (704L << 16), /* HS Start + HS End */
7806 + 245 | (246L << 16), /* VS Start + VS End */
7807 + HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
7809 + 0x00a30930, /* PLLx multiplier and control */
7812 + { /* 640 x 480 60Hz (25.175 MHz) */
7813 + 640,480,60, /* X/Y/Freq */
7814 + (800-2) | (640L << 16), /* HD Total + HD End */
7815 + (525-1) | ((480L-1) << 16), /* VD Total + VD End */
7816 + 656 | (752L << 16), /* HS Start + HS End */
7817 + 490 | (492L << 16), /* VS Start + VS End */
7818 + HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
7820 + 0x00a30930, /* PLLx multiplier and control */
7823 + { /* 640 x 480 72Hz (31.5 MHz) */
7824 + 640,480,72, /* X/Y/Freq */
7825 + (832-2) | (640L << 16), /* HD Total + HD End */
7826 + (520-1) | ((480L-1) << 16), /* VD Total + VD End */
7827 + 688 | (728L << 16), /* HS Start + HS End */
7828 + 489 | (492L << 16), /* VS Start + VS End */
7829 + HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
7831 + 0x00f50b30, /* PLLx multiplier and control */
7834 + { /* 640 x 480 75Hz (31.5 MHz) */
7835 + 640,480,75, /* X/Y/Freq */
7836 + (840-2) | (640L << 16), /* HD Total + HD End */
7837 + (500-1) | ((480L-1) << 16), /* VD Total + VD End */
7838 + 680 | (744L << 16), /* HS Start + HS End */
7839 + 481 | (484L << 16), /* VS Start + VS End */
7840 + HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
7842 + 0x00f50b30, /* PLLx multiplier and control */
7845 + { /* 640 x 480 85Hz (36 MHz) */
7846 + 640,480,85, /* X/Y/Freq */
7847 + (832-2) | (640L << 16), /* HD Total + HD End */
7848 + (509-1) | ((480L-1) << 16), /* VD Total + VD End */
7849 + 696 | (752L << 16), /* HS Start + HS End */
7850 + 481 | (484L << 16), /* VS Start + VS End */
7851 + HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
7853 + 0x00d20830, /* PLLx multiplier and control */
7856 + { /* 800 x 600 60Hz (40 MHz) */
7857 + 800,600,60, /* X/Y/Freq */
7858 + (1056-2) | (800L << 16), /* HD Total + HD End */
7859 + (628-1) | ((600L-1) << 16), /* VD Total + VD End */
7860 + 839 | (967L << 16), /* HS Start + HS End */
7861 + 601 | (605L << 16), /* VS Start + VS End */
7862 + BLANK_PED_ENABLE, /* CRT control */
7863 + 0x00e90830, /* PLLx multiplier and control */
7866 + { /* 800 x 600 72Hz 50 MHz) */
7867 + 800,600,72, /* X/Y/Freq */
7868 + (1040-2) | (800L << 16), /* HD Total + HD End */
7869 + (666-1) | ((600L-1) << 16), /* VD Total + VD End */
7870 + 856 | (976L << 16), /* HS Start + HS End */
7871 + 637 | (643L << 16), /* VS Start + VS End */
7872 + BLANK_PED_ENABLE, /* CRT control */
7873 + 0x00b20a20, /* PLLx multiplier and control */
7876 + { /* 800 x 600 75Hz (49.5 MHz) */
7877 + 800,600,75, /* X/Y/Freq */
7878 + (1056-2) | (800L << 16), /* HD Total + HD End */
7879 + (625-1) | ((600L-1) << 16), /* VD Total + VD End */
7880 + 816 | (896L << 16), /* HS Start + HS End */
7881 + 601 | (604L << 16), /* VS Start + VS End */
7882 + BLANK_PED_ENABLE, /* CRT control */
7883 + 0x00900820, /* PLLx multiplier and control */
7886 + { /* 800 x 600 85Hz (56.25 MHz) */
7887 + 800,600,85, /* X/Y/Freq */
7888 + (1047-2) | (800L << 16), /* HD Total + HD End */
7889 + (631-1) | ((600L-1) << 16), /* VD Total + VD End */
7890 + 832 | (896L << 16), /* HS Start + HS End */
7891 + 601 | (604L << 16), /* VS Start + VS End */
7892 + BLANK_PED_ENABLE, /* CRT control */
7893 + 0x00b60920, /* PLLx multiplier and control */
7896 + { /* 1024 x 768 60Hz (65 MHz) */
7897 + 1024,768,60, /* X/Y/Freq */
7898 + (1344-2) | (1024L << 16), /* HD Total + HD End */
7899 + (806-1) | ((768L-1) << 16), /* VD Total + VD End */
7900 + 1048 | (1184L << 16), /* HS Start + HS End */
7901 + 771 | (777L << 16), /* VS Start + VS End */
7902 + HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
7904 + 0x00fd0b20, /* PLLx multiplier and control */
7907 + { /* 1024 x 768 70Hz (75 MHz) */
7908 + 1024,768,70, /* X/Y/Freq */
7909 + (1327-2) | (1024L << 16), /* HD Total + HD End */
7910 + (806-1) | ((768L-1) << 16), /* VD Total + VD End */
7911 + 1047 | (1183L << 16), /* HS Start + HS End */
7912 + 771 | (777L << 16), /* VS Start + VS End */
7913 + HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
7915 + 0x00f30920, /* PLLx multiplier and control */
7918 + { /* 1024 x 768 75Hz (78.750 MHz) */
7919 + 1024,768,75, /* X/Y/Freq */
7920 + (1312-2) | (1024L << 16), /* HD Total + HD End */
7921 + (806-1) | ((768L-1) << 16), /* VD Total + VD End */
7922 + 1040 | (1136L << 16), /* HS Start + HS End */
7923 + 769 | (772L << 16), /* VS Start + VS End */
7924 + BLANK_PED_ENABLE, /* CRT control */
7925 + 0x00cc0720, /* PLLx multiplier and control */
7928 + { /* 1024 x 768 85Hz (94.5 MHz) */
7929 + 1024,768,85, /* X/Y/Freq */
7930 + (1375-2) | (1024L << 16), /* HD Total + HD End */
7931 + (808-1) | ((768L-1) << 16), /* VD Total + VD End */
7932 + 1072 | (1168L << 16), /* HS Start + HS End */
7933 + 769 | (772L << 16), /* VS Start + VS End */
7934 + BLANK_PED_ENABLE, /* CRT control */
7935 + 0x007a0710, /* PLLx multiplier and control */
7938 +#define MAX_MQMODE (sizeof(TimingParam) / sizeof(TimingParam[0]))
7940 +/* Flat panel control registers
7942 +FPDATA_CONTROL fpControlData[] =
7944 + /* Type 0 : OEM Specific panel
7946 + { /* Flat panel info */
7949 + /* Flat panel Control */
7953 + /* Flat panel pin control */
7957 + /* STN panel control */
7960 + /* Type 1 : SSTN VGA 8Bit Color - 72Hz
7961 + * - Sanyo SSTN 640x480 8-bit color interface
7963 + { /* Flat panel info */
7966 + /* Flat panel Control */
7969 + | SSTN_8BITS_MONOCLR
7970 + | DITHER_PATTERN_3
7971 + | DITHER_BASE_4BITS
7976 + /* Flat panel pin control */
7977 + FSCLK_OUTPUT_ENABLE
7982 + /* STN panel control */
7986 + /* Type 2 : DSTN 16 Bit VGA Color - 72Hz
7987 + * - Hitachi 8.2" SX21V001
7988 + * - Sanyo 10.4" LM-CJ53-22NTK
7989 + * - Sharp 10.4" LM64C35P
7991 + { /* Flat panel info */
7994 + /* Flat panel Control */
7997 + | DSTN_16BITS_MONOCLR
7998 + | DITHER_PATTERN_3
7999 + | DITHER_BASE_4BITS
8004 + /* Flat panel pin control */
8005 + FSCLK_OUTPUT_ENABLE
8010 + /* STN panel control */
8014 + /* Type 3 : TFT 18 Bit VGA - 60Hz
8015 + * - NEC 10.4" NL6448AC33-24
8017 + { /* Flat panel info */
8020 + /* Flat panel Control */
8023 + | TFT_18BITS_COLOR
8024 + | DITHER_PATTERN_3
8025 + | DITHER_BASE_6BITS
8028 + /* Flat panel pin control */
8029 + FSCLK_OUTPUT_ENABLE
8032 + /* STN panel control */
8036 + /* Type 4 : TFT 18 Bit SVGA - 60Hz
8037 + * - Hitachi 12.1" 800x600 TX31D24VC1CAA
8039 + { /* Flat panel info */
8042 + /* Flat panel Control */
8045 + | TFT_18BITS_COLOR
8046 + | DITHER_PATTERN_3
8047 + | DITHER_BASE_6BITS
8050 + /* Flat panel pin control */
8051 + FSCLK_OUTPUT_ENABLE
8054 + /* STN panel control */
8058 + /* Type 5 : DSTN 16Bit SVGA Color Panel - 72Hz
8059 + * - Hitachi 10.0" SX25S001
8060 + * - Hitachi 12.1" SX25S003
8062 + { /* Flat panel info */
8065 + /* Flat panel Control */
8068 + | DSTN_16BITS_MONOCLR
8069 + | DITHER_PATTERN_3
8070 + | DITHER_BASE_4BITS
8075 + /* Flat panel pin control */
8076 + FSCLK_OUTPUT_ENABLE
8081 + /* STN panel control */
8085 + /* Type 6 : DSTN 8 Bit VGA Color - 72Hz
8087 + { /* Flat panel info */
8090 + /* Flat panel Control */
8093 + | DSTN_8BITS_MONOCLR
8094 + | DITHER_PATTERN_3
8095 + | DITHER_BASE_4BITS
8100 + /* Flat panel pin control */
8101 + FSCLK_OUTPUT_ENABLE
8106 + /* STN panel control */
8110 + /* Type 7 : SSTN VGA 16Bit Color - 72Hz
8112 + { /* Flat panel info */
8115 + /* Flat panel Control */
8118 + | SSTN_16BITS_MONOCLR
8119 + | DITHER_PATTERN_3
8120 + | DITHER_BASE_4BITS
8125 + /* Flat panel pin control */
8126 + FSCLK_OUTPUT_ENABLE
8131 + /* STN panel control */
8135 + /* Type 8 : SSTN VGA 8Bit Color - 60Hz
8136 + * - Sanyo SSTN 640x480 8-bit color interface
8138 + { /* Flat panel info */
8141 + /* Flat panel Control */
8144 + | SSTN_8BITS_MONOCLR
8145 + | DITHER_PATTERN_3
8146 + | DITHER_BASE_4BITS
8151 + /* Flat panel pin control */
8152 + FSCLK_OUTPUT_ENABLE
8157 + /* STN panel control */
8161 + /* Type 9 : DSTN 16 Bit VGA Color - 60Hz
8162 + * - Hitachi 8.2" SX21V001
8163 + * - Sanyo 10.4" LM-CJ53-22NTK
8164 + * - Sharp 10.4" LM64C35P
8166 + { /* Flat panel info */
8169 + /* Flat panel Control */
8172 + | DSTN_16BITS_MONOCLR
8173 + | DITHER_PATTERN_1
8174 + | DITHER_BASE_4BITS
8179 + /* Flat panel pin control */
8180 + FSCLK_OUTPUT_ENABLE
8185 + /* STN panel control */
8189 + /* Type 10 : DSTN 16Bit SVGA Color Panel - 60Hz
8190 + * - Hitachi 10.0" SX25S001
8191 + * - Hitachi 12.1" SX25S003
8192 + * - Sanyo LM-FC53-22NTK
8194 + { /* Flat panel info */
8197 + /* Flat panel Control */
8203 + | DSTN_16BITS_MONOCLR
8204 + | DITHER_PATTERN_3
8205 + | DITHER_BASE_4BITS
8211 + /* Flat panel pin control */
8212 + FSCLK_OUTPUT_ENABLE
8217 + /* STN panel control */
8221 + /* Type 11 : DSTN 24Bit XGA Color Panel - 60Hz
8222 + * - Hitachi 12.1" SX25S003
8224 + { /* Flat panel info */
8227 + /* Flat panel Control */
8230 + | DSTN_24BITS_COLOR
8231 + | DITHER_PATTERN_3
8232 + | DITHER_BASE_4BITS
8237 + /* Flat panel pin control */
8238 + FSCLK_OUTPUT_ENABLE
8243 + /* STN panel control */
8247 + /* Type 12 : DSTN 16Bit XGA Color Panel - 60Hz
8248 + * - Hitachi 12.1" SX25S003
8250 + { /* Flat panel info */
8253 + /* Flat panel Control */
8256 + | DSTN_16BITS_MONOCLR
8257 + | DITHER_PATTERN_3
8258 + | DITHER_BASE_4BITS
8263 + /* Flat panel pin control */
8264 + FSCLK_OUTPUT_ENABLE
8269 + /* STN panel control */
8273 + /* Type 13 : TFT 18Bit XGA - 60Hz
8274 + * - Hitachi 12.1" 800x600 TX31D24VC1CAA
8276 + { /* Flat panel info */
8279 + /* Flat panel Control */
8282 + | TFT_18BITS_COLOR
8283 + | DITHER_PATTERN_3
8284 + | DITHER_BASE_6BITS
8287 + /* Flat panel pin control */
8288 + FSCLK_OUTPUT_ENABLE
8293 + /* STN panel control */
8297 + /* Type 14 : TFT 24Bit XGA - 60Hz
8298 + * - Hitachi 12.1" 800x600 TX31D24VC1CAA
8300 + { /* Flat panel info */
8303 + /* Flat panel Control */
8306 + | TFT_24BITS_COLOR
8307 + | DITHER_PATTERN_3
8308 + | DITHER_BASE_6BITS
8311 + /* Flat panel pin control */
8312 + FSCLK_OUTPUT_ENABLE
8317 + /* STN panel control */
8321 + /* Type 15 : TFT 18 Bit SVGA - 60Hz (Similar to type 4)
8322 + * - NEC 12.1" 800x600 TX31D24VC1CAA
8324 + { /* Flat panel control */
8327 + /* Flat panel Control */
8330 + | TFT_18BITS_COLOR
8331 + | DITHER_PATTERN_3
8332 + | DITHER_BASE_6BITS
8335 + /* Flat panel pin control */
8336 + FSCLK_OUTPUT_ENABLE
8342 + /* STN panel control */
8346 + /* Type 16 : SSTN VGA 8Bit Color - 90Hz
8347 + * - Sharp LM8M64 SSTN 640x240 8-bit color interface
8349 + { /* Flat panel control */
8354 + | SSTN_8BITS_MONOCLR
8355 + | DITHER_PATTERN_1
8356 + | DITHER_BASE_4BITS
8361 + FSCLK_OUTPUT_ENABLE
8366 + /* STN panel control */
8371 +/* Flat panel FRC weight/pattern registers - for SSTN and DSTN panel only
8374 +FRC_CONTROL FRCControlData[] =
8413 + /* FRC weight data */
8425 + /* FRC Pattern Data - 2FCA (for SSTN) */
8463 + /* FRC weight data */
8475 + /* FRC Pattern Data - (for Panletype 4-> Simpad) */
8512 + /* FRC weight data */
8524 +#endif /* _VIDEO_MQ200_MQDATA_H */
8526 +++ linux-2.4.27/include/video/MQ200/mqmacros.h
8528 +#ifndef _VIDEO_MQ200_MQMACROS_H
8529 +#define _VIDEO_MQ200_MQMACROS_H
8531 +#ifdef CHECK_SRCFIFO
8533 +#define PUMP_PACKED_SRCFIFO(pSrcData,srcStride,nDwords,height,extras) \
8537 + while( height-- ) \
8539 + pData = (u32 *)((u32)(pSrcData + 3UL) & ~0x03UL); \
8541 + while ( j >= SRC_FIFO_MAX_DWORDS ) \
8543 + geWAITSRCFIFO( SRC_FIFO_MAX_DWORDS ); \
8544 + for ( i = 0; i < SRC_FIFO_MAX_DWORDS; i++ ) \
8545 + geREG(SRC_IMAGE_DATA, *pData++); \
8546 + j -= SRC_FIFO_MAX_DWORDS; \
8548 + geWAITSRCFIFO( j ); \
8550 + geREG(SRC_IMAGE_DATA, *pData++); \
8551 + pSrcData += srcStride; \
8553 + geWAITSRCFIFO( extras ); \
8554 + while( extras-- ) \
8555 + geREG(SRC_IMAGE_DATA, 0UL); \
8559 +#define PUMP_REAL_PACKED_SRCFIFO(pSrcData,nDwords,extras) \
8561 + u32 *pData =(u32 *)pSrcData; \
8565 + if (nDwords >= SRC_FIFO_MAX_DWORDS) \
8567 + geWAITSRCFIFO( SRC_FIFO_MAX_DWORDS ); \
8568 + for (i = SRC_FIFO_MAX_DWORDS; i > 0; i--) \
8569 + geREG(SRC_IMAGE_DATA, *pData++); \
8570 + nDwords -= SRC_FIFO_MAX_DWORDS; \
8574 + geWAITSRCFIFO( nDwords ); \
8575 + for (i = nDwords; i > 0; i--) \
8576 + geREG(SRC_IMAGE_DATA, *pData++); \
8577 + nDwords -= nDwords; \
8580 + geWAITSRCFIFO(extras); \
8581 + while( extras-- ) \
8582 + geREG(SRC_IMAGE_DATA, 0UL); \
8585 +#else /* CHECK_SRCFIFO */
8587 +#define PUMP_PACKED_SRCFIFO(pSrcData,srcStride,nDwords,height,extras) \
8591 + while( height-- ) \
8593 + pData = (u32 *)((u32)(pSrcData + 3UL) & ~0x03UL); \
8594 + for ( i = 0; i < nDwords; i++ ) \
8595 + geREG(SRC_IMAGE_DATA, *pData++); \
8596 + pSrcData += srcStride; \
8598 + while( extras-- ) \
8599 + geREG(SRC_IMAGE_DATA, 0UL); \
8602 +#define PUMP_REAL_PACKED_SRCFIFO(pSrcData,nDwords,extras) \
8604 + u32 *pData =(u32 *)pSrcData; \
8605 + while(nDwords--) \
8606 + geREG(SRC_IMAGE_DATA, *pData++); \
8607 + while( extras-- ) \
8608 + geREG(SRC_IMAGE_DATA, 0UL); \
8613 +#endif /* _VIDEO_MQ200_MQMACROS_H */
8615 +++ linux-2.4.27/include/video/MQ200/mqplat.h
8617 +/***************************************************************************
8620 + MQ200 platform, system or OS specific header file
8622 + Copyright (c) 2000 by MediaQ, Incorporated.
8623 + All Rights Reserved.
8625 +***************************************************************************/
8626 +#ifndef _VIDEO_MQ200_MQPLAT_H
8627 +#define _VIDEO_MQ200_MQPLAT_H
8629 +/* OS variation - ONLY define one */
8636 +/* CPU variation - ONLY define one */
8640 +#undef MQ_MIPS_TOSHIBA
8643 +/* PCI support - undef accordingly */
8646 + #warning "MQ200 driver compiled for PCI !"
8649 +/* Derived equates from CPU type */
8651 + #warning "MQ200 driver compiled for SHx !"
8652 + #define FB_BASE 0x93800000L /* MQ200 frame buffer adddr */
8656 + #warning "MQ200 driver compiled for NEC MIPS !"
8657 + #define CHECK_FIFO_REQUIRED /* GE fifo checking required */
8658 + #define FB_BASE 0xAA000000L
8661 + #define IOREGS_BASE 0xAF000000L /* for VR4122 */
8662 + #define IOREGS_SIZE 0x00002000L
8664 + #define IOREGS_BASE 0xAB000000L /* for VR 4111/21 */
8665 + #define IOREGS_SIZE 0x00001000L
8666 + #define CHECK_NOTBUSY /* Needed for NEC MIPS */
8667 + #define CHECK_CMDFIFO /* Needed for NEC MIPS */
8668 + #endif /* MQ_PCI */
8671 +#ifdef MQ_MIPS_TOSHIBA
8672 + #warning "MQ200 driver compiled for TOSHIBA MIPS !"
8673 + #define FB_BASE 0x6D800000L
8677 + #warning "MQ200 driver compiled for Intel SA1110 !"
8678 + #define FB_BASE_CS3 0x1b800000L /* configured as CS3 */
8679 + #define FB_BASE_CS4 0x43800000L /* configured as CS4 */
8680 +#define FB_BASE_CS5 0x4b800000L /* configured as CS5 */
8681 +#define FB_BASE FB_BASE_CS5 /* change accordingly! */
8682 +#define REGISTER_BASE 0x4be00000L
8685 +/* OS-derived misc defines */
8687 + #warning "MQ200 driver compiled for VxWorks !"
8688 + #define MQ_DELAY(cnt) taskDelay(cnt*30);
8689 + #define MQ_COLOR_RGB /* Color (32bit):ARGB */
8693 + #warning "MQ200 driver compiled for Window CE !"
8694 + #define MQ_DELAY(cnt) Sleep(cnt)
8698 + #warning "MQ200 driver compiled for Linux !"
8699 +/* #define MQ_DELAY(cnt) {volatile int delay; for (delay=0; delay<10000*cnt; delay++); } */
8701 +#define MQ_DELAY(cnt) mdelay(cnt * 10)
8704 +/* Further derivation
8705 +#ifdef MQ_COLOR_RGB
8706 + #define GETR(color) (unsigned char)(color >> 16)
8707 + #define GETG(color) (unsigned char)((unsigned short)(color) >> 8)
8708 + #define GETB(color) (unsigned char)(color)
8709 + #define MAKERGB(r,g,b) ((unsigned long)(((unsigned char)(r)|\
8710 + ((unsigned short)((unsigned char)(g))<<8))|\
8711 + (((unsigned long)(unsigned char)(b))<<16)))
8716 +#ifndef CURSOR_FGCLR
8717 + #define CURSOR_FGCLR 0x0000FFFF /* Yellow */
8719 +#ifndef CURSOR_BGCLR
8720 + #define CURSOR_BGCLR 0x00000000 /* Black */
8722 +#endif /* _VIDEO_MQ200_MQPLAT_H */
8724 +++ linux-2.4.27/include/video/MQ200/mqproto.h
8726 +/***************************************************************************
8729 + MQ200 common function prototypes
8731 + Copyright (c) 2000 by MediaQ, Incorporated.
8732 + All Rights Reserved.
8734 +***************************************************************************/
8741 +extern FPDATA_CONTROL fpControlData[];
8742 +extern DISPLAY_TIMING TimingParam[];
8744 +#endif /* MQPROTO_H */
8745 --- linux-2.4.27/init/do_mounts.c~2.4.27-vrs1-pxa1-jpm1
8746 +++ linux-2.4.27/init/do_mounts.c
8747 @@ -789,7 +789,13 @@
8750 printk(KERN_ERR "VFS: Unable to mount root fs via NFS, trying floppy.\n");
8751 +#ifdef CONFIG_SA1100_SIMPAD
8752 + /* no floppy -> cramfs */
8753 + printk(KERN_ERR "VFS: Unable to mount root fs via NFS, trying cramfs.\n");
8754 + ROOT_DEV = MKDEV(31, 2);
8756 ROOT_DEV = MKDEV(FLOPPY_MAJOR, 0);
8760 devfs_make_root(root_device_name);