3 # Patch managed by http://www.holgerschurig.de/patcher.html
6 --- linux-2.4.27/Documentation/Configure.help~2.4.27-vrs1-pxa1
7 +++ linux-2.4.27/Documentation/Configure.help
9 building a kernel for install/rescue disks or your system is very
12 +Kernel Execute-In-Place from ROM
14 + Execute-In-Place allows the kernel to run directly from
15 + non-volatile storage, such as flash. This saves RAM space since
16 + the text section of the kernel is not loaded from flash to
17 + RAM. Read-write sections, such as the data section and stack,
18 + are still copied to RAM. The XIP kernel is not compressed since it
19 + has to run directly from flash, so it will take more space to store
20 + it. The flash address where the kernel is linked to run from and
21 + is stored is board dependent. Therefore, if you say Y, you must
22 + know the proper physical address where to store the kernel image.
24 + Also note that the make target becomes "make xipImage" rather than
25 + "make zImage" or "make Image". The final kernel binary to put in
26 + ROM memory will be arch/arm/boot/xipImage.
31 Kernel core (/proc/kcore) format
33 @@ -13609,6 +13627,30 @@
35 If you don't know what this all is, saying Y is a safe choice.
37 +Workaround for XScale cache errata
38 +CONFIG_XSCALE_CACHE_ERRATA
39 + There are couple errata that say that the cache may get confused
40 + whether some cache lines are dirty or not, resulting in some memory
41 + corruptions. The workaround (using the cache only in write through
42 + mode) is performance impairing, and the bug _might_ just not be
43 + that visible or critical to you depending on many esoteric
46 + Not using the workaround makes Linux unreliable. If you're used
47 + to some other OSes which requires to be rebooted once in a while
48 + then this won't look so bad to you. On the other hand you may
49 + stress test the system for hours without seeing any effect of this
52 + So this is configurable. Let's hope a future core revision will tell
53 + this was just a bad dream. But in the mean time the risk and
54 + trade-off is yours to decide.
56 + This should apply to all PXA250 up to rev B2 (erratum #120) and
57 + possibly other current XScale cores as well.
59 + If you don't know what to answer, say Y.
61 Support CD-ROM drives that are not SCSI or IDE/ATAPI
63 If you have a CD-ROM drive that is neither SCSI nor IDE/ATAPI, say Y
64 @@ -16812,6 +16854,40 @@
68 +Use linear addressing for cramfs
70 + This option tells the cramfs driver to load data directly from a linear
71 + adressed memory range (usually non volatile memory like flash) instead
72 + of going through the block device layer. This saves some memory since
73 + no intermediate buffering is necessary.
75 + This is also a prerequisite for XIP of binaries stored on the filesystem.
77 + The location of the cramfs image in memory is board dependent. Therefore,
78 + if you say Y, you must know the proper physical address where to store
79 + the cramfs image and specify it using the physaddr=0x******** mount
80 + option (for example: "mount -t cramfs -o physaddr=0x100000 none /mnt").
84 +Support XIP on linear cramfs
85 +CONFIG_CRAMFS_LINEAR_XIP
86 + You must say Y to this option if you want to be able to run applications
87 + directly from non-volatile memory. XIP applications are marked by
88 + setting the sticky bit (ie, "chmod +t <app name>"). A cramfs file system
89 + then needs to be created using mkcramfs (with XIP cramfs support
90 + in it). Applications marked for XIP execution will not be compressed
91 + since they have to run directly from flash.
93 +Root file system on linear cramfs
94 +CONFIG_ROOT_CRAMFS_LINEAR
95 + Say Y if you have enabled linear cramfs, and you want to be able to use
96 + the linear cramfs image as a root file system. To actually have the
97 + kernel mount this cramfs image as a root file system, you must also pass
98 + the command line parameter "root=/dev/null rootflags=physaddr=0x********"
99 + to the kernel (replace 0x******** with the physical address location
100 + of the linear cramfs image to boot with).
102 CMS file system support
104 Read only support for CMS minidisk file systems found on IBM
106 +++ linux-2.4.27/Documentation/arm/XScale/PXA/USB-client
108 +Date: Wed, 05 Jun 2002 13:38:53 -0700
109 +From: Frank Becker <fbecker@intrinsyc.com>
110 +To: Nicolas Pitre <nico@cam.org>
111 +Subject: [PATCH] PXA-USB
117 +This patch adds minimal USB client (UDC) support.
120 +It adds just enough to get usb-eth working. I.e.
121 +endpoints 0-2, no dma. Performance isn't stellar
122 +partially due to UDC bug workarounds...
123 +(~350K @ 100Mhz, ~550K @ 200Mhz).
125 +Endpoint 1&2 have changed direction compared to
126 +the SA, so the host side requires a change to
127 +usbnet.c to flip endpoints (in:2/out:1 -> in:1/out:2).
129 +usb-eth and usb-char for PXA are almost identical
130 +to the SA versions, so they could probably be merged at
131 +one point. I made some minor changes to the eth driver
132 +to grab the usb resources at open, rather than at init
133 +and allow eth&char to be loaded at the same time.
135 +Stuart Lynne was working on his own USB client driver
136 +(and he was getting higher throughput than my driver).
137 +Assuming you guys have something in the oven for USB
138 +as well, there should be good selection for best of
144 +Frank Becker - Intrinsyc Software, Inc. - http://www.intrinsyc.com/
145 +Need a break? http://criticalmass.sf.net/
146 --- linux-2.4.27/Makefile~2.4.27-vrs1-pxa1
147 +++ linux-2.4.27/Makefile
152 -EXTRAVERSION = -vrs1
153 +EXTRAVERSION =-vrs1-pxa1
155 KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
158 DRIVERS-$(CONFIG_SOUND) += drivers/sound/sounddrivers.o
159 DRIVERS-$(CONFIG_PCI) += drivers/pci/driver.o
160 DRIVERS-$(CONFIG_MTD) += drivers/mtd/mtdlink.o
161 +DRIVERS-$(CONFIG_MMC) += drivers/mmc/mmcdrivers.o
162 DRIVERS-$(CONFIG_PCMCIA) += drivers/pcmcia/pcmcia.o
163 DRIVERS-$(CONFIG_NET_PCMCIA) += drivers/net/pcmcia/pcmcia_net.o
164 DRIVERS-$(CONFIG_NET_WIRELESS) += drivers/net/wireless/wireless_net.o
165 --- linux-2.4.27/arch/arm/Makefile~2.4.27-vrs1-pxa1
166 +++ linux-2.4.27/arch/arm/Makefile
168 CFLAGS +=-Uarm -fno-common -pipe
170 ifeq ($(CONFIG_FRAME_POINTER),y)
171 -CFLAGS :=$(CFLAGS:-fomit-frame-pointer=-mapcs -mno-sched-prolog)
172 +CFLAGS :=$(CFLAGS:-fomit-frame-pointer=)
173 +CFLAGS +=-fno-omit-frame-pointer -mapcs -mno-sched-prolog
176 -CFLAGS :=$(CFLAGS:-O2=-Os)
177 +#CFLAGS :=$(CFLAGS:-O2=-Os)
179 ifeq ($(CONFIG_DEBUG_INFO),y)
182 arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3
183 arch-$(CONFIG_CPU_32v4) :=-D__LINUX_ARM_ARCH__=4 -march=armv4
184 arch-$(CONFIG_CPU_32v5) :=-D__LINUX_ARM_ARCH__=5 -march=armv5
185 +#arch-$(CONFIG_CPU_XSCALE) :=-D__LINUX_ARM_ARCH__=5 -mcpu=xscale
186 +arch-$(CONFIG_CPU_XSCALE) :=-D__LINUX_ARM_ARCH__=5 -march=armv4 -Wa,-mxscale
188 # This selects how we optimise for the processor.
191 tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi
192 tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110
193 tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100
194 +#tune-$(CONFIG_CPU_XSCALE) :=-mtune=xscale
195 +tune-$(CONFIG_CPU_XSCALE) :=-mtune=strongarm
197 CFLAGS_BOOT :=$(apcs-y) $(arch-y) $(tune-y) -mshort-load-bytes -msoft-float -Uarm
198 CFLAGS +=$(apcs-y) $(arch-y) $(tune-y) -mshort-load-bytes -msoft-float -Uarm
203 +ifeq ($(CONFIG_ARCH_PXA),y)
207 ifeq ($(CONFIG_ARCH_L7200),y)
214 +ifeq ($(CONFIG_XIP_KERNEL),y)
215 + DATAADDR := $(TEXTADDR)
216 + # Replace phys addr with virt addr while keeping offset from base.
217 + # Virt base addr also defined in include/asm-arm/arch-*/hardware.h
218 + TEXTADDR = $(shell echo 0x`echo $(CONFIG_XIP_PHYS_ADDR)|sed -e's/^0x//'` |\
219 + awk --non-decimal-data '/[:xdigit:]/ \
220 + {printf("0x%x\n",and($$0,0x001fffff)+0xe8000000)}' )
221 + LDSCRIPT = arch/arm/vmlinux-armv-xip.lds.in
225 export MACHINE PROCESSOR TEXTADDR GZFLAGS CFLAGS_BOOT OBJCOPYFLAGS
227 # Only set INCDIR if its not already defined above
229 arch/arm/kernel arch/arm/mm arch/arm/lib: dummy
230 $(MAKE) CFLAGS="$(CFLAGS) $(CFLAGS_KERNEL)" $(subst $@, _dir_$@, $@)
232 -bzImage zImage zinstall Image bootpImage install: vmlinux
233 +bzImage zImage zinstall Image xipImage bootpImage install: vmlinux
237 --- linux-2.4.27/arch/arm/boot/Makefile~2.4.27-vrs1-pxa1
238 +++ linux-2.4.27/arch/arm/boot/Makefile
243 +ifeq ($(CONFIG_ARCH_PXA),y)
244 +ZRELADDR = 0xa0008000
247 ifeq ($(CONFIG_ARCH_ANAKIN),y)
248 ZRELADDR = 0x20008000
251 zImage: compressed/vmlinux
252 $(OBJCOPY) $(OBJCOPYFLAGS) $< $@
254 +ifeq ($(CONFIG_XIP_KERNEL),y)
255 +xipImage: $(CONFIGURE) $(SYSTEM)
256 + $(OBJCOPY) -S -O binary -R .data $(SYSTEM) vmlinux-text.bin
257 + $(OBJCOPY) -S -O binary -R .init -R .text -R __ex_table -R __ksymtab $(SYSTEM) vmlinux-data.bin
258 + cat vmlinux-text.bin vmlinux-data.bin > $@
259 + $(RM) -f vmlinux-text.bin vmlinux-data.bin
262 bootpImage: bootp/bootp
263 $(OBJCOPY) $(OBJCOPYFLAGS) $< $@
266 sh ./install.sh $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) zImage $(TOPDIR)/System.map "$(INSTALL_PATH)"
269 - $(RM) Image zImage bootpImage
270 + $(RM) Image xipImage zImage bootpImage
271 @$(MAKE) -C compressed clean
272 @$(MAKE) -C bootp clean
274 --- linux-2.4.27/arch/arm/boot/compressed/Makefile~2.4.27-vrs1-pxa1
275 +++ linux-2.4.27/arch/arm/boot/compressed/Makefile
277 OBJS += head-sa1100.o
280 +ifeq ($(CONFIG_CPU_XSCALE),y)
281 +OBJS += head-xscale.o
284 SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/LOAD_ADDR/$(ZRELADDR)/;s/BSS_START/$(ZBSSADDR)/
286 LIBGCC := $(shell $(CC) $(CFLAGS) --print-libgcc-file-name)
288 +++ linux-2.4.27/arch/arm/boot/compressed/head-xscale.S
291 + * linux/arch/arm/boot/compressed/head-xscale.S
293 + * XScale specific tweaks. This is merged into head.S by the linker.
297 +#include <linux/config.h>
298 +#include <linux/linkage.h>
299 +#include <asm/mach-types.h>
301 + .section ".start", #alloc, #execinstr
305 + @ Preserve r8/r7 i.e. kernel entry values
307 + @ Data cache might be active.
308 + @ Be sure to flush kernel binary out of the cache,
309 + @ whatever state it is, before it is turned off.
310 + @ This is done by fetching through currently executed
311 + @ memory to be sure we hit the same cache.
313 + add r3, r2, #0x10000 @ 64 kb is quite enough...
314 +1: ldr r0, [r2], #32
317 + mcr p15, 0, r0, c7, c10, 4 @ drain WB
318 + mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
320 + @ disabling MMU and caches
321 + mrc p15, 0, r0, c1, c0, 0 @ read control reg
322 + bic r0, r0, #0x05 @ clear DC, MMU
323 + bic r0, r0, #0x1000 @ clear Icache
324 + mcr p15, 0, r0, c1, c0, 0
326 +#ifdef CONFIG_ARCH_LUBBOCK
327 + mov r7, #MACH_TYPE_LUBBOCK
330 +#ifdef CONFIG_ARCH_PXA_IDP
331 + mov r7, #MACH_TYPE_PXA_IDP
334 +#ifdef CONFIG_ARCH_TRIZEPS2
335 + mov r7, #(MACH_TYPE_TRIZEPS2 & 0xFF00)
336 + add r7, r7, #(MACH_TYPE_TRIZEPS2 & 0xFF)
340 --- linux-2.4.27/arch/arm/boot/compressed/head.S~2.4.27-vrs1-pxa1
341 +++ linux-2.4.27/arch/arm/boot/compressed/head.S
345 1: cmp r1, r8 @ if virt > start of RAM
346 +#ifdef CONFIG_XSCALE_CACHE_ERRATA
347 + orrhs r1, r1, #0x08 @ set cacheable, not bufferable
349 orrhs r1, r1, #0x0c @ set cacheable, bufferable
351 cmp r1, r9 @ if virt > end of RAM
352 bichs r1, r1, #0x0c @ clear cacheable, bufferable
353 str r1, [r0], #4 @ 1:1 mapping
355 * so there is no map overlap problem for up to 1 MB compressed kernel.
356 * If the execution is in RAM then we would only be duplicating the above.
358 +#ifdef CONFIG_XSCALE_CACHE_ERRATA
365 orr r1, r1, r2, lsl #20
366 --- linux-2.4.27/arch/arm/config.in~2.4.27-vrs1-pxa1
367 +++ linux-2.4.27/arch/arm/config.in
369 Cirrus-CL-PS7500FE CONFIG_ARCH_CLPS7500 \
370 CLPS711x/EP721x-based CONFIG_ARCH_CLPS711X \
371 Co-EBSA285 CONFIG_ARCH_CO285 \
372 + PXA250/210-based CONFIG_ARCH_PXA \
373 EBSA-110 CONFIG_ARCH_EBSA110 \
374 Excalibur-ARM CONFIG_ARCH_CAMELOT \
375 FootBridge CONFIG_ARCH_FOOTBRIDGE \
379 mainmenu_option next_comment
380 +comment 'Intel PXA250/210 Implementations'
381 +dep_bool ' Intel DBPXA250 Development Platform' CONFIG_ARCH_LUBBOCK $CONFIG_ARCH_PXA
382 +dep_bool ' Accelent Xscale IDP' CONFIG_ARCH_PXA_IDP $CONFIG_ARCH_PXA
383 +dep_bool ' Intrinsyc CerfBoard' CONFIG_ARCH_PXA_CERF $CONFIG_ARCH_PXA
384 +dep_bool ' Trizeps-II MT6N' CONFIG_ARCH_TRIZEPS2 $CONFIG_ARCH_PXA
386 +if [ "$CONFIG_ARCH_PXA_CERF" = "y" ]; then
387 + define_bool CONFIG_PXA_CERF y
389 + choice 'CerfBoard Style' \
390 + "PDA CONFIG_PXA_CERF_PDA \
391 + BOARD CONFIG_PXA_CERF_BOARD" PDA
393 + choice 'CerfBoard RAM Available' \
394 + "128MB CONFIG_PXA_CERF_RAM_128MB \
395 + 64MB CONFIG_PXA_CERF_RAM_64MB \
396 + 32MB CONFIG_PXA_CERF_RAM_32MB \
397 + 16MB CONFIG_PXA_CERF_RAM_16MB" 64MB
399 + choice 'CerfBoard Flash Available' \
400 + "64MB CONFIG_PXA_CERF_FLASH_64MB \
401 + 32MB CONFIG_PXA_CERF_FLASH_32MB \
402 + 16MB CONFIG_PXA_CERF_FLASH_16MB \
403 + 8MB CONFIG_PXA_CERF_FLASH_8MB" 32MB
406 +if [ "$CONFIG_ARCH_LUBBOCK" = "y" ]; then
407 + define_bool CONFIG_SA1111 y
410 +if [ "$CONFIG_ARCH_TRIZEPS2" = "y" ]; then
411 + define_bool CONFIG_TRIZEPS2 y
414 +dep_tristate 'PXA USB function support' CONFIG_PXA_USB $CONFIG_ARCH_PXA
415 +dep_tristate ' Support for PXA USB network link function' CONFIG_PXA_USB_NETLINK $CONFIG_PXA_USB
416 +dep_tristate ' Support for PXA USB character device emulation' CONFIG_PXA_USB_CHAR $CONFIG_PXA_USB
420 +mainmenu_option next_comment
421 comment 'CLPS711X/EP721X Implementations'
422 dep_bool ' AUTCPU12' CONFIG_ARCH_AUTCPU12 $CONFIG_ARCH_CLPS711X
423 dep_bool ' CDB89712' CONFIG_ARCH_CDB89712 $CONFIG_ARCH_CLPS711X
425 define_bool CONFIG_CPU_SA1100 n
428 +if [ "$CONFIG_ARCH_PXA" = "y" ]; then
429 + define_bool CONFIG_CPU_32v5 y
430 + define_bool CONFIG_CPU_XSCALE y
431 + bool 'Workaround for XScale cache errata (see help)' CONFIG_XSCALE_CACHE_ERRATA
434 # Figure out what processor architecture version we should be using.
435 # This defines the compiler instruction set which depends on the machine type.
438 hex 'Compressed ROM boot loader BSS address' CONFIG_ZBOOT_ROM_BSS 0
440 if [ "$CONFIG_ARCH_SA1100" = "y" -o \
441 + "$CONFIG_ARCH_PXA" = "y" -o \
442 "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
443 dep_bool 'Support CPU clock change (EXPERIMENTAL)' CONFIG_CPU_FREQ $CONFIG_EXPERIMENTAL
446 bool 'Support for hot-pluggable devices' CONFIG_HOTPLUG
447 if [ "$CONFIG_HOTPLUG" = "y" ]; then
448 source drivers/pcmcia/Config.in
449 + source drivers/mmc/Config.in
451 define_bool CONFIG_PCMCIA n
452 + define_bool CONFIG_MMC n
454 if [ "$CONFIG_SA1100_ACCELENT" = "y" ]; then
455 if [ "$CONFIG_PCMCIA" != "n" ]; then
457 bool 'System V IPC' CONFIG_SYSVIPC
458 bool 'BSD Process Accounting' CONFIG_BSD_PROCESS_ACCT
459 bool 'Sysctl support' CONFIG_SYSCTL
461 +if [ "$CONFIG_ARCH_PXA" = "y" ]; then
462 + dep_bool 'Kernel Execute-In-Place from ROM (EXPERIMENTAL)' CONFIG_XIP_KERNEL $CONFIG_EXPERIMENTAL
463 + if [ "$CONFIG_XIP_KERNEL" = "y" ]; then
464 + hex ' Kernel .text physical address' CONFIG_XIP_PHYS_ADDR 0
468 comment 'At least one math emulation must be selected'
469 tristate 'NWFPE math emulation' CONFIG_FPE_NWFPE
470 if [ "$CONFIG_FPE_NWFPE" != "n" ]; then
472 "$CONFIG_ARCH_SHARK" = "y" -o \
473 "$CONFIG_ARCH_CO285" = "y" -o \
474 "$CONFIG_ARCH_SA1100" = "y" -o \
475 + "$CONFIG_ARCH_LUBBOCK" = "y" -o \
476 + "$CONFIG_ARCH_PXA_IDP" = "y" -o \
477 + "$CONFIG_ARCH_PXA_CERF" = "y" -o \
478 "$CONFIG_ARCH_INTEGRATOR" = "y" -o \
479 "$CONFIG_ARCH_CDB89712" = "y" -o \
480 "$CONFIG_ARCH_P720T" = "y" -o \
482 "$CONFIG_ARCH_SHARK" = "y" -o \
483 "$CONFIG_ARCH_CO285" = "y" -o \
484 "$CONFIG_ARCH_SA1100" = "y" -o \
485 + "$CONFIG_ARCH_LUBBOCK" = "y" -o \
486 "$CONFIG_ARCH_INTEGRATOR" = "y" -o \
487 "$CONFIG_ARCH_P720T" = "y" -o \
488 "$CONFIG_ARCH_OMAHA" = "y" -o \
489 + "$CONFIG_ARCH_PXA_CERF" = "y" -o \
490 + "$CONFIG_ARCH_PXA_IDP" = "y" -o \
491 "$CONFIG_ARCH_AT91RM9200" = "y" ]; then
492 bool ' Timer LED' CONFIG_LEDS_TIMER
493 bool ' CPU usage LED' CONFIG_LEDS_CPU
495 if [ "$CONFIG_FOOTBRIDGE_HOST" = "y" -o \
496 "$CONFIG_ARCH_SHARK" = "y" -o \
497 "$CONFIG_ARCH_SA1100" = "y" -o \
498 + "$CONFIG_ARCH_PXA" = "y" -o \
499 "$CONFIG_ARCH_INTEGRATOR" = "y" -o \
500 "$CONFIG_ARCH_TBOX" = "y" -o \
501 "$CONFIG_ARCH_CLPS7500" = "y" -o \
503 "$CONFIG_ARCH_TBOX" = "y" -o \
504 "$CONFIG_ARCH_SHARK" = "y" -o \
505 "$CONFIG_ARCH_SA1100" = "y" -o \
506 + "$CONFIG_ARCH_PXA" = "y" -o \
507 "$CONFIG_PCI" = "y" ]; then
508 mainmenu_option next_comment
511 +++ linux-2.4.27/arch/arm/def-configs/cerfboard_pxa
514 +# Automatically generated by make menuconfig: don't edit
517 +# CONFIG_EISA is not set
518 +# CONFIG_SBUS is not set
519 +# CONFIG_MCA is not set
521 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
522 +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
523 +# CONFIG_GENERIC_BUST_SPINLOCK is not set
524 +# CONFIG_GENERIC_ISA_DMA is not set
527 +# Code maturity level options
529 +CONFIG_EXPERIMENTAL=y
530 +# CONFIG_OBSOLETE is not set
533 +# Loadable module support
536 +# CONFIG_MODVERSIONS is not set
542 +# CONFIG_ARCH_ANAKIN is not set
543 +# CONFIG_ARCH_ARCA5K is not set
544 +# CONFIG_ARCH_CLPS7500 is not set
545 +# CONFIG_ARCH_CLPS711X is not set
546 +# CONFIG_ARCH_CO285 is not set
548 +# CONFIG_ARCH_EBSA110 is not set
549 +# CONFIG_ARCH_CAMELOT is not set
550 +# CONFIG_ARCH_FOOTBRIDGE is not set
551 +# CONFIG_ARCH_INTEGRATOR is not set
552 +# CONFIG_ARCH_OMAHA is not set
553 +# CONFIG_ARCH_L7200 is not set
554 +# CONFIG_ARCH_MX1ADS is not set
555 +# CONFIG_ARCH_RPC is not set
556 +# CONFIG_ARCH_RISCSTATION is not set
557 +# CONFIG_ARCH_SA1100 is not set
558 +# CONFIG_ARCH_SHARK is not set
561 +# Archimedes/A5000 Implementations
563 +# CONFIG_ARCH_ARC is not set
564 +# CONFIG_ARCH_A5K is not set
567 +# Footbridge Implementations
569 +# CONFIG_ARCH_CATS is not set
570 +# CONFIG_ARCH_PERSONAL_SERVER is not set
571 +# CONFIG_ARCH_EBSA285_ADDIN is not set
572 +# CONFIG_ARCH_EBSA285_HOST is not set
573 +# CONFIG_ARCH_NETWINDER is not set
576 +# SA11x0 Implementations
578 +# CONFIG_SA1100_ACCELENT is not set
579 +# CONFIG_SA1100_ASSABET is not set
580 +# CONFIG_ASSABET_NEPONSET is not set
581 +# CONFIG_SA1100_ADSBITSY is not set
582 +# CONFIG_SA1100_BRUTUS is not set
583 +# CONFIG_SA1100_CEP is not set
584 +# CONFIG_SA1100_CERF is not set
585 +# CONFIG_SA1100_H3100 is not set
586 +# CONFIG_SA1100_H3600 is not set
587 +# CONFIG_SA1100_H3800 is not set
588 +# CONFIG_SA1100_H3XXX is not set
589 +# CONFIG_SA1100_EXTENEX1 is not set
590 +# CONFIG_SA1100_FLEXANET is not set
591 +# CONFIG_SA1100_FREEBIRD is not set
592 +# CONFIG_SA1100_FRODO is not set
593 +# CONFIG_SA1100_GRAPHICSCLIENT is not set
594 +# CONFIG_SA1100_GRAPHICSMASTER is not set
595 +# CONFIG_SA1100_BADGE4 is not set
596 +# CONFIG_SA1100_JORNADA720 is not set
597 +# CONFIG_SA1100_HUW_WEBPANEL is not set
598 +# CONFIG_SA1100_ITSY is not set
599 +# CONFIG_SA1100_LART is not set
600 +# CONFIG_SA1100_NANOENGINE is not set
601 +# CONFIG_SA1100_OMNIMETER is not set
602 +# CONFIG_SA1100_PANGOLIN is not set
603 +# CONFIG_SA1100_PLEB is not set
604 +# CONFIG_SA1100_PT_SYSTEM3 is not set
605 +# CONFIG_SA1100_SHANNON is not set
606 +# CONFIG_SA1100_SHERMAN is not set
607 +# CONFIG_SA1100_SIMPAD is not set
608 +# CONFIG_SA1100_SIMPUTER is not set
609 +# CONFIG_SA1100_PFS168 is not set
610 +# CONFIG_SA1100_VICTOR is not set
611 +# CONFIG_SA1100_XP860 is not set
612 +# CONFIG_SA1100_YOPY is not set
613 +# CONFIG_SA1100_USB is not set
614 +# CONFIG_SA1100_USB_NETLINK is not set
615 +# CONFIG_SA1100_USB_CHAR is not set
616 +# CONFIG_H3600_SLEEVE is not set
619 +# Intel PXA250/210 Implementations
621 +# CONFIG_ARCH_LUBBOCK is not set
622 +# CONFIG_ARCH_PXA_IDP is not set
623 +CONFIG_ARCH_PXA_CERF=y
625 +# CONFIG_PXA_CERF_PDA is not set
626 +CONFIG_PXA_CERF_BOARD=y
627 +# CONFIG_PXA_CERF_RAM_128MB is not set
628 +CONFIG_PXA_CERF_RAM_64MB=y
629 +# CONFIG_PXA_CERF_RAM_32MB is not set
630 +# CONFIG_PXA_CERF_RAM_16MB is not set
631 +# CONFIG_PXA_CERF_FLASH_64MB is not set
632 +CONFIG_PXA_CERF_FLASH_32MB=y
633 +# CONFIG_PXA_CERF_FLASH_16MB is not set
634 +# CONFIG_PXA_CERF_FLASH_8MB is not set
636 +CONFIG_PXA_USB_NETLINK=y
637 +CONFIG_PXA_USB_CHAR=m
640 +# CLPS711X/EP721X Implementations
642 +# CONFIG_ARCH_AUTCPU12 is not set
643 +# CONFIG_ARCH_CDB89712 is not set
644 +# CONFIG_ARCH_CLEP7312 is not set
645 +# CONFIG_ARCH_EDB7211 is not set
646 +# CONFIG_ARCH_P720T is not set
647 +# CONFIG_ARCH_FORTUNET is not set
648 +# CONFIG_ARCH_EP7211 is not set
649 +# CONFIG_ARCH_EP7212 is not set
650 +# CONFIG_ARCH_ACORN is not set
651 +# CONFIG_FOOTBRIDGE is not set
652 +# CONFIG_FOOTBRIDGE_HOST is not set
653 +# CONFIG_FOOTBRIDGE_ADDIN is not set
655 +# CONFIG_CPU_26 is not set
656 +# CONFIG_CPU_ARM610 is not set
657 +# CONFIG_CPU_ARM710 is not set
658 +# CONFIG_CPU_ARM720T is not set
659 +# CONFIG_CPU_ARM920T is not set
660 +# CONFIG_CPU_ARM922T is not set
661 +# CONFIG_PLD is not set
662 +# CONFIG_CPU_ARM926T is not set
663 +# CONFIG_CPU_ARM1020 is not set
664 +# CONFIG_CPU_ARM1026 is not set
665 +# CONFIG_CPU_SA110 is not set
666 +# CONFIG_CPU_SA1100 is not set
669 +CONFIG_XSCALE_CACHE_ERRATA=y
670 +# CONFIG_CPU_32v3 is not set
671 +# CONFIG_CPU_32v4 is not set
672 +# CONFIG_DISCONTIGMEM is not set
677 +# CONFIG_PCI is not set
678 +# CONFIG_ISA is not set
679 +# CONFIG_ISA_DMA is not set
680 +# CONFIG_ZBOOT_ROM is not set
681 +CONFIG_ZBOOT_ROM_TEXT=0
682 +CONFIG_ZBOOT_ROM_BSS=0
687 +# PCMCIA/CardBus support
690 +# CONFIG_I82092 is not set
691 +# CONFIG_I82365 is not set
692 +# CONFIG_TCIC is not set
693 +# CONFIG_PCMCIA_CLPS6700 is not set
694 +# CONFIG_PCMCIA_SA1100 is not set
698 +CONFIG_BSD_PROCESS_ACCT=y
701 +# CONFIG_FPE_FASTFPE is not set
703 +# CONFIG_KCORE_AOUT is not set
704 +# CONFIG_BINFMT_AOUT is not set
706 +# CONFIG_BINFMT_MISC is not set
707 +# CONFIG_PM is not set
708 +# CONFIG_ARTHUR is not set
709 +CONFIG_CMDLINE="root=1f03 rw console=tty0 console=ttyS0,38400 init=/linuxrc"
711 +# CONFIG_LEDS_TIMER is not set
713 +CONFIG_ALIGNMENT_TRAP=y
716 +# Parallel port support
718 +# CONFIG_PARPORT is not set
721 +# Memory Technology Devices (MTD)
724 +# CONFIG_MTD_DEBUG is not set
725 +CONFIG_MTD_PARTITIONS=y
726 +# CONFIG_MTD_CONCAT is not set
727 +CONFIG_MTD_REDBOOT_PARTS=y
728 +# CONFIG_MTD_CMDLINE_PARTS is not set
729 +# CONFIG_MTD_AFS_PARTS is not set
732 +# CONFIG_FTL is not set
733 +# CONFIG_NFTL is not set
736 +# RAM/ROM/Flash chip drivers
739 +# CONFIG_MTD_JEDECPROBE is not set
740 +CONFIG_MTD_GEN_PROBE=y
741 +CONFIG_MTD_CFI_ADV_OPTIONS=y
742 +CONFIG_MTD_CFI_NOSWAP=y
743 +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
744 +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
745 +CONFIG_MTD_CFI_GEOMETRY=y
746 +# CONFIG_MTD_CFI_B1 is not set
747 +# CONFIG_MTD_CFI_B2 is not set
749 +# CONFIG_MTD_CFI_B8 is not set
750 +# CONFIG_MTD_CFI_I1 is not set
752 +# CONFIG_MTD_CFI_I4 is not set
753 +# CONFIG_MTD_CFI_I8 is not set
754 +CONFIG_MTD_CFI_INTELEXT=y
755 +# CONFIG_MTD_CFI_AMDSTD is not set
756 +# CONFIG_MTD_RAM is not set
757 +# CONFIG_MTD_ROM is not set
758 +# CONFIG_MTD_ABSENT is not set
759 +# CONFIG_MTD_OBSOLETE_CHIPS is not set
760 +# CONFIG_MTD_AMDSTD is not set
761 +# CONFIG_MTD_SHARP is not set
762 +# CONFIG_MTD_JEDEC is not set
765 +# Mapping drivers for chip access
767 +# CONFIG_MTD_PHYSMAP is not set
768 +# CONFIG_MTD_LUBBOCK is not set
769 +# CONFIG_MTD_NORA is not set
770 +# CONFIG_MTD_ARM_INTEGRATOR is not set
771 +# CONFIG_MTD_CDB89712 is not set
772 +# CONFIG_MTD_SA1100 is not set
773 +# CONFIG_MTD_DC21285 is not set
774 +# CONFIG_MTD_IQ80310 is not set
775 +# CONFIG_MTD_FORTUNET is not set
776 +CONFIG_MTD_PXA_CERF=y
777 +# CONFIG_MTD_EPXA10DB is not set
778 +# CONFIG_MTD_AUTCPU12 is not set
779 +# CONFIG_MTD_EDB7312 is not set
780 +# CONFIG_MTD_IMPA7 is not set
781 +# CONFIG_MTD_PCI is not set
784 +# Self-contained MTD device drivers
786 +# CONFIG_MTD_PMC551 is not set
787 +# CONFIG_MTD_SLRAM is not set
788 +# CONFIG_MTD_MTDRAM is not set
789 +# CONFIG_MTD_BLKMTD is not set
790 +# CONFIG_MTD_DOC1000 is not set
791 +# CONFIG_MTD_DOC2000 is not set
792 +# CONFIG_MTD_DOC2001 is not set
793 +# CONFIG_MTD_DOCPROBE is not set
796 +# NAND Flash Device Drivers
798 +# CONFIG_MTD_NAND is not set
801 +# Plug and Play configuration
803 +# CONFIG_PNP is not set
804 +# CONFIG_ISAPNP is not set
809 +# CONFIG_BLK_DEV_FD is not set
810 +# CONFIG_BLK_DEV_XD is not set
811 +# CONFIG_PARIDE is not set
812 +# CONFIG_BLK_CPQ_DA is not set
813 +# CONFIG_BLK_CPQ_CISS_DA is not set
814 +# CONFIG_CISS_SCSI_TAPE is not set
815 +# CONFIG_BLK_DEV_DAC960 is not set
816 +# CONFIG_BLK_DEV_UMEM is not set
817 +CONFIG_BLK_DEV_LOOP=m
818 +# CONFIG_BLK_DEV_NBD is not set
819 +CONFIG_BLK_DEV_RAM=y
820 +CONFIG_BLK_DEV_RAM_SIZE=4096
821 +CONFIG_BLK_DEV_INITRD=y
824 +# Multi-device support (RAID and LVM)
826 +# CONFIG_MD is not set
827 +# CONFIG_BLK_DEV_MD is not set
828 +# CONFIG_MD_LINEAR is not set
829 +# CONFIG_MD_RAID0 is not set
830 +# CONFIG_MD_RAID1 is not set
831 +# CONFIG_MD_RAID5 is not set
832 +# CONFIG_MD_MULTIPATH is not set
833 +# CONFIG_BLK_DEV_LVM is not set
836 +# Networking options
839 +# CONFIG_PACKET_MMAP is not set
840 +# CONFIG_NETLINK_DEV is not set
841 +# CONFIG_NETFILTER is not set
845 +# CONFIG_IP_MULTICAST is not set
846 +# CONFIG_IP_ADVANCED_ROUTER is not set
848 +CONFIG_IP_PNP_DHCP=y
849 +CONFIG_IP_PNP_BOOTP=y
850 +CONFIG_IP_PNP_RARP=y
851 +# CONFIG_NET_IPIP is not set
852 +# CONFIG_NET_IPGRE is not set
853 +# CONFIG_ARPD is not set
854 +# CONFIG_INET_ECN is not set
855 +# CONFIG_SYN_COOKIES is not set
856 +# CONFIG_IPV6 is not set
857 +# CONFIG_KHTTPD is not set
858 +# CONFIG_ATM is not set
859 +# CONFIG_VLAN_8021Q is not set
860 +# CONFIG_IPX is not set
861 +# CONFIG_ATALK is not set
866 +# CONFIG_DEV_APPLETALK is not set
867 +# CONFIG_DECNET is not set
868 +# CONFIG_BRIDGE is not set
869 +# CONFIG_X25 is not set
870 +# CONFIG_LAPB is not set
871 +# CONFIG_LLC is not set
872 +# CONFIG_NET_DIVERT is not set
873 +# CONFIG_ECONET is not set
874 +# CONFIG_WAN_ROUTER is not set
875 +# CONFIG_NET_FASTROUTE is not set
876 +# CONFIG_NET_HW_FLOWCONTROL is not set
879 +# QoS and/or fair queueing
881 +# CONFIG_NET_SCHED is not set
886 +# CONFIG_NET_PKTGEN is not set
889 +# Network device support
896 +# CONFIG_ARCNET is not set
897 +# CONFIG_DUMMY is not set
898 +# CONFIG_BONDING is not set
899 +# CONFIG_EQUALIZER is not set
900 +# CONFIG_TUN is not set
901 +# CONFIG_ETHERTAP is not set
904 +# Ethernet (10 or 100Mbit)
906 +CONFIG_NET_ETHERNET=y
907 +# CONFIG_ARM_AM79C961A is not set
908 +# CONFIG_ARM_CIRRUS is not set
909 +# CONFIG_SUNLANCE is not set
910 +# CONFIG_SUNBMAC is not set
911 +# CONFIG_SUNQE is not set
912 +# CONFIG_SUNGEM is not set
913 +# CONFIG_NET_VENDOR_3COM is not set
914 +# CONFIG_LANCE is not set
915 +CONFIG_NET_VENDOR_SMC=y
916 +# CONFIG_WD80x3 is not set
917 +# CONFIG_ULTRAMCA is not set
918 +# CONFIG_ULTRA is not set
919 +# CONFIG_ULTRA32 is not set
920 +# CONFIG_SMC9194 is not set
921 +# CONFIG_NET_VENDOR_RACAL is not set
922 +# CONFIG_NET_ISA is not set
923 +# CONFIG_NET_PCI is not set
924 +# CONFIG_NET_POCKET is not set
927 +# Ethernet (1000 Mbit)
929 +# CONFIG_ACENIC is not set
930 +# CONFIG_DL2K is not set
931 +# CONFIG_MYRI_SBUS is not set
932 +# CONFIG_NS83820 is not set
933 +# CONFIG_HAMACHI is not set
934 +# CONFIG_YELLOWFIN is not set
935 +# CONFIG_SK98LIN is not set
936 +# CONFIG_TIGON3 is not set
937 +# CONFIG_FDDI is not set
938 +# CONFIG_HIPPI is not set
939 +# CONFIG_PLIP is not set
941 +# CONFIG_PPP_MULTILINK is not set
942 +# CONFIG_PPP_FILTER is not set
944 +# CONFIG_PPP_SYNC_TTY is not set
945 +CONFIG_PPP_DEFLATE=m
946 +CONFIG_PPP_BSDCOMP=m
947 +# CONFIG_PPPOE is not set
948 +# CONFIG_SLIP is not set
951 +# Wireless LAN (non-hamradio)
953 +# CONFIG_NET_RADIO is not set
956 +# Token Ring devices
958 +# CONFIG_TR is not set
959 +# CONFIG_NET_FC is not set
960 +# CONFIG_RCPCI is not set
961 +# CONFIG_SHAPER is not set
966 +# CONFIG_WAN is not set
969 +# PCMCIA network device support
972 +CONFIG_PCMCIA_3C589=m
973 +CONFIG_PCMCIA_3C574=m
974 +CONFIG_PCMCIA_FMVJ18X=m
975 +CONFIG_PCMCIA_PCNET=m
976 +CONFIG_PCMCIA_AXNET=m
977 +CONFIG_PCMCIA_NMCLAN=m
978 +CONFIG_PCMCIA_SMC91C92=m
979 +CONFIG_PCMCIA_XIRC2PS=m
980 +# CONFIG_ARCNET_COM20020_CS is not set
981 +# CONFIG_PCMCIA_IBMTR is not set
982 +CONFIG_NET_PCMCIA_RADIO=y
983 +CONFIG_PCMCIA_RAYCS=m
984 +CONFIG_PCMCIA_NETWAVE=m
985 +CONFIG_PCMCIA_WAVELAN=m
986 +CONFIG_AIRONET4500_CS=m
989 +# Amateur Radio support
991 +# CONFIG_HAMRADIO is not set
994 +# IrDA (infrared) support
996 +# CONFIG_IRDA is not set
999 +# ATA/ATAPI/MFM/RLL support
1004 +# IDE, ATA and ATAPI Block devices
1006 +CONFIG_BLK_DEV_IDE=y
1007 +# CONFIG_BLK_DEV_HD_IDE is not set
1008 +# CONFIG_BLK_DEV_HD is not set
1009 +CONFIG_BLK_DEV_IDEDISK=y
1010 +# CONFIG_IDEDISK_MULTI_MODE is not set
1011 +# CONFIG_IDEDISK_STROKE is not set
1012 +# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
1013 +# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
1014 +# CONFIG_BLK_DEV_IDEDISK_IBM is not set
1015 +# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
1016 +# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
1017 +# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
1018 +# CONFIG_BLK_DEV_IDEDISK_WD is not set
1019 +# CONFIG_BLK_DEV_COMMERIAL is not set
1020 +# CONFIG_BLK_DEV_TIVO is not set
1021 +CONFIG_BLK_DEV_IDECS=m
1022 +# CONFIG_BLK_DEV_IDECD is not set
1023 +# CONFIG_BLK_DEV_IDETAPE is not set
1024 +# CONFIG_BLK_DEV_IDEFLOPPY is not set
1025 +# CONFIG_BLK_DEV_IDESCSI is not set
1026 +# CONFIG_IDE_TASK_IOCTL is not set
1027 +# CONFIG_BLK_DEV_CMD640 is not set
1028 +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
1029 +# CONFIG_BLK_DEV_ISAPNP is not set
1030 +# CONFIG_IDE_CHIPSETS is not set
1031 +# CONFIG_IDEDMA_AUTO is not set
1032 +# CONFIG_DMA_NONPCI is not set
1033 +# CONFIG_BLK_DEV_IDE_MODES is not set
1034 +# CONFIG_BLK_DEV_ATARAID is not set
1035 +# CONFIG_BLK_DEV_ATARAID_PDC is not set
1036 +# CONFIG_BLK_DEV_ATARAID_HPT is not set
1041 +# CONFIG_SCSI is not set
1044 +# I2O device support
1046 +# CONFIG_I2O is not set
1047 +# CONFIG_I2O_BLOCK is not set
1048 +# CONFIG_I2O_LAN is not set
1049 +# CONFIG_I2O_SCSI is not set
1050 +# CONFIG_I2O_PROC is not set
1055 +# CONFIG_ISDN is not set
1058 +# Input core support
1060 +# CONFIG_INPUT is not set
1061 +# CONFIG_INPUT_KEYBDEV is not set
1062 +# CONFIG_INPUT_MOUSEDEV is not set
1063 +# CONFIG_INPUT_JOYDEV is not set
1064 +# CONFIG_INPUT_EVDEV is not set
1067 +# Character devices
1070 +CONFIG_VT_CONSOLE=y
1072 +CONFIG_SERIAL_CONSOLE=y
1073 +# CONFIG_SERIAL_EXTENDED is not set
1074 +# CONFIG_SERIAL_NONSTANDARD is not set
1079 +# CONFIG_SERIAL_ANAKIN is not set
1080 +# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
1081 +# CONFIG_SERIAL_AMBA is not set
1082 +# CONFIG_SERIAL_AMBA_CONSOLE is not set
1083 +# CONFIG_SERIAL_CLPS711X is not set
1084 +# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
1085 +# CONFIG_SERIAL_21285 is not set
1086 +# CONFIG_SERIAL_21285_OLD is not set
1087 +# CONFIG_SERIAL_21285_CONSOLE is not set
1088 +# CONFIG_SERIAL_UART00 is not set
1089 +# CONFIG_SERIAL_UART00_CONSOLE is not set
1090 +# CONFIG_SERIAL_SA1100 is not set
1091 +# CONFIG_SERIAL_SA1100_CONSOLE is not set
1092 +# CONFIG_SERIAL_OMAHA is not set
1093 +# CONFIG_SERIAL_OMAHA_CONSOLE is not set
1094 +# CONFIG_SERIAL_8250 is not set
1095 +# CONFIG_SERIAL_8250_CONSOLE is not set
1096 +# CONFIG_SERIAL_8250_EXTENDED is not set
1097 +# CONFIG_SERIAL_8250_MANY_PORTS is not set
1098 +# CONFIG_SERIAL_8250_SHARE_IRQ is not set
1099 +# CONFIG_SERIAL_8250_DETECT_IRQ is not set
1100 +# CONFIG_SERIAL_8250_MULTIPORT is not set
1101 +# CONFIG_SERIAL_8250_HUB6 is not set
1102 +CONFIG_UNIX98_PTYS=y
1103 +CONFIG_UNIX98_PTY_COUNT=256
1109 +# CONFIG_I2C_ALGOBIT is not set
1110 +# CONFIG_I2C_ALGOPCF is not set
1111 +CONFIG_I2C_PXA_ALGO=y
1112 +CONFIG_I2C_PXA_ADAP=y
1113 +# CONFIG_I2C_CHARDEV is not set
1114 +# CONFIG_I2C_PROC is not set
1115 +# CONFIG_I2C_DS1307 is not set
1118 +# L3 serial bus support
1120 +# CONFIG_L3 is not set
1121 +# CONFIG_L3_ALGOBIT is not set
1122 +# CONFIG_L3_BIT_SA1100_GPIO is not set
1123 +# CONFIG_L3_SA1111 is not set
1124 +# CONFIG_BIT_SA1100_GPIO is not set
1129 +# CONFIG_BUSMOUSE is not set
1130 +# CONFIG_MOUSE is not set
1135 +# CONFIG_INPUT_GAMEPORT is not set
1136 +# CONFIG_QIC02_TAPE is not set
1142 +# CONFIG_WATCHDOG_NOWAYOUT is not set
1143 +# CONFIG_ACQUIRE_WDT is not set
1144 +# CONFIG_ADVANTECH_WDT is not set
1145 +# CONFIG_ALIM7101_WDT is not set
1146 +# CONFIG_SC520_WDT is not set
1147 +# CONFIG_PCWATCHDOG is not set
1148 +# CONFIG_21285_WATCHDOG is not set
1149 +# CONFIG_977_WATCHDOG is not set
1150 +# CONFIG_SA1100_WATCHDOG is not set
1151 +CONFIG_PXA_WATCHDOG=m
1152 +# CONFIG_OMAHA_WATCHDOG is not set
1153 +# CONFIG_EUROTECH_WDT is not set
1154 +# CONFIG_IB700_WDT is not set
1155 +# CONFIG_WAFER_WDT is not set
1156 +# CONFIG_I810_TCO is not set
1157 +# CONFIG_MIXCOMWD is not set
1158 +# CONFIG_60XX_WDT is not set
1159 +# CONFIG_SC1200_WDT is not set
1160 +# CONFIG_SOFT_WATCHDOG is not set
1161 +# CONFIG_W83877F_WDT is not set
1162 +# CONFIG_WDT is not set
1163 +# CONFIG_WDTPCI is not set
1164 +# CONFIG_MACHZ_WDT is not set
1165 +# CONFIG_NVRAM is not set
1166 +# CONFIG_RTC is not set
1167 +# CONFIG_PXA_RTC is not set
1168 +# CONFIG_DTLK is not set
1169 +# CONFIG_R3964 is not set
1170 +# CONFIG_APPLICOM is not set
1173 +# Ftape, the floppy tape device driver
1175 +# CONFIG_FTAPE is not set
1176 +# CONFIG_AGP is not set
1177 +# CONFIG_DRM is not set
1180 +# PCMCIA character devices
1182 +CONFIG_PCMCIA_SERIAL_CS=y
1183 +CONFIG_PCMCIA_CHRDEV=y
1186 +# Multimedia devices
1188 +# CONFIG_VIDEO_DEV is not set
1193 +# CONFIG_QUOTA is not set
1195 +CONFIG_AUTOFS4_FS=y
1196 +# CONFIG_REISERFS_FS is not set
1197 +# CONFIG_REISERFS_CHECK is not set
1198 +# CONFIG_REISERFS_PROC_INFO is not set
1199 +# CONFIG_ADFS_FS is not set
1200 +# CONFIG_ADFS_FS_RW is not set
1201 +# CONFIG_AFFS_FS is not set
1202 +# CONFIG_HFS_FS is not set
1203 +# CONFIG_BFS_FS is not set
1204 +# CONFIG_EXT3_FS is not set
1205 +# CONFIG_JBD is not set
1206 +# CONFIG_JBD_DEBUG is not set
1211 +# CONFIG_EFS_FS is not set
1212 +# CONFIG_JFFS_FS is not set
1214 +CONFIG_JFFS2_FS_DEBUG=0
1215 +# CONFIG_CRAMFS is not set
1218 +# CONFIG_ISO9660_FS is not set
1219 +# CONFIG_JOLIET is not set
1220 +# CONFIG_ZISOFS is not set
1221 +# CONFIG_MINIX_FS is not set
1222 +# CONFIG_VXFS_FS is not set
1223 +# CONFIG_NTFS_FS is not set
1224 +# CONFIG_NTFS_RW is not set
1225 +# CONFIG_HPFS_FS is not set
1227 +# CONFIG_DEVFS_FS is not set
1228 +# CONFIG_DEVFS_MOUNT is not set
1229 +# CONFIG_DEVFS_DEBUG is not set
1231 +# CONFIG_QNX4FS_FS is not set
1232 +# CONFIG_QNX4FS_RW is not set
1235 +# CONFIG_SYSV_FS is not set
1236 +# CONFIG_UDF_FS is not set
1237 +# CONFIG_UDF_RW is not set
1238 +# CONFIG_UFS_FS is not set
1239 +# CONFIG_UFS_FS_WRITE is not set
1242 +# Network File Systems
1244 +# CONFIG_CODA_FS is not set
1245 +# CONFIG_INTERMEZZO_FS is not set
1249 +# CONFIG_NFSD is not set
1250 +# CONFIG_NFSD_V3 is not set
1254 +# CONFIG_SMB_FS is not set
1255 +# CONFIG_NCP_FS is not set
1256 +# CONFIG_NCPFS_PACKET_SIGNING is not set
1257 +# CONFIG_NCPFS_IOCTL_LOCKING is not set
1258 +# CONFIG_NCPFS_STRONG is not set
1259 +# CONFIG_NCPFS_NFS_NS is not set
1260 +# CONFIG_NCPFS_OS2_NS is not set
1261 +# CONFIG_NCPFS_SMALLDOS is not set
1262 +# CONFIG_NCPFS_NLS is not set
1263 +# CONFIG_NCPFS_EXTRAS is not set
1264 +# CONFIG_ZISOFS_FS is not set
1265 +# CONFIG_ZLIB_FS_INFLATE is not set
1270 +# CONFIG_PARTITION_ADVANCED is not set
1271 +CONFIG_MSDOS_PARTITION=y
1272 +# CONFIG_SMB_NLS is not set
1276 +# Native Language Support
1278 +CONFIG_NLS_DEFAULT="iso8859-1"
1279 +CONFIG_NLS_CODEPAGE_437=m
1280 +# CONFIG_NLS_CODEPAGE_737 is not set
1281 +# CONFIG_NLS_CODEPAGE_775 is not set
1282 +CONFIG_NLS_CODEPAGE_850=m
1283 +CONFIG_NLS_CODEPAGE_852=m
1284 +# CONFIG_NLS_CODEPAGE_855 is not set
1285 +# CONFIG_NLS_CODEPAGE_857 is not set
1286 +# CONFIG_NLS_CODEPAGE_860 is not set
1287 +# CONFIG_NLS_CODEPAGE_861 is not set
1288 +# CONFIG_NLS_CODEPAGE_862 is not set
1289 +CONFIG_NLS_CODEPAGE_863=m
1290 +# CONFIG_NLS_CODEPAGE_864 is not set
1291 +# CONFIG_NLS_CODEPAGE_865 is not set
1292 +# CONFIG_NLS_CODEPAGE_866 is not set
1293 +# CONFIG_NLS_CODEPAGE_869 is not set
1294 +# CONFIG_NLS_CODEPAGE_936 is not set
1295 +# CONFIG_NLS_CODEPAGE_950 is not set
1296 +# CONFIG_NLS_CODEPAGE_932 is not set
1297 +# CONFIG_NLS_CODEPAGE_949 is not set
1298 +# CONFIG_NLS_CODEPAGE_874 is not set
1299 +# CONFIG_NLS_ISO8859_8 is not set
1300 +# CONFIG_NLS_CODEPAGE_1250 is not set
1301 +# CONFIG_NLS_CODEPAGE_1251 is not set
1302 +CONFIG_NLS_ISO8859_1=m
1303 +CONFIG_NLS_ISO8859_2=m
1304 +CONFIG_NLS_ISO8859_3=m
1305 +CONFIG_NLS_ISO8859_4=m
1306 +# CONFIG_NLS_ISO8859_5 is not set
1307 +# CONFIG_NLS_ISO8859_6 is not set
1308 +# CONFIG_NLS_ISO8859_7 is not set
1309 +# CONFIG_NLS_ISO8859_9 is not set
1310 +# CONFIG_NLS_ISO8859_13 is not set
1311 +# CONFIG_NLS_ISO8859_14 is not set
1312 +# CONFIG_NLS_ISO8859_15 is not set
1313 +# CONFIG_NLS_KOI8_R is not set
1314 +# CONFIG_NLS_KOI8_U is not set
1315 +# CONFIG_NLS_UTF8 is not set
1321 +# CONFIG_VGA_CONSOLE is not set
1324 +# Frame-buffer support
1326 +# CONFIG_FB is not set
1331 +# CONFIG_SOUND is not set
1334 +# Multimedia Capabilities Port drivers
1336 +# CONFIG_MCP is not set
1337 +# CONFIG_MCP_SA1100 is not set
1338 +# CONFIG_MCP_UCB1200 is not set
1339 +# CONFIG_MCP_UCB1200_AUDIO is not set
1340 +# CONFIG_MCP_UCB1200_TS is not set
1341 +# CONFIG_MCP_UCB1400_TS is not set
1346 +# CONFIG_USB is not set
1349 +# Bluetooth support
1351 +# CONFIG_BLUEZ is not set
1356 +CONFIG_FRAME_POINTER=y
1357 +CONFIG_DEBUG_USER=y
1358 +# CONFIG_DEBUG_INFO is not set
1359 +# CONFIG_NO_PGT_CACHE is not set
1360 +CONFIG_DEBUG_KERNEL=y
1361 +# CONFIG_DEBUG_SLAB is not set
1362 +CONFIG_MAGIC_SYSRQ=y
1363 +# CONFIG_DEBUG_SPINLOCK is not set
1364 +# CONFIG_DEBUG_WAITQ is not set
1365 +CONFIG_DEBUG_BUGVERBOSE=y
1366 +CONFIG_DEBUG_ERRORS=y
1368 +# CONFIG_DEBUG_DC21285_PORT is not set
1369 +# CONFIG_DEBUG_CLPS711X_UART2 is not set
1371 +++ linux-2.4.27/arch/arm/def-configs/cerfpda_pxa
1374 +# Automatically generated by make menuconfig: don't edit
1377 +# CONFIG_EISA is not set
1378 +# CONFIG_SBUS is not set
1379 +# CONFIG_MCA is not set
1381 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
1382 +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
1383 +# CONFIG_GENERIC_BUST_SPINLOCK is not set
1384 +# CONFIG_GENERIC_ISA_DMA is not set
1387 +# Code maturity level options
1389 +CONFIG_EXPERIMENTAL=y
1390 +# CONFIG_OBSOLETE is not set
1393 +# Loadable module support
1396 +# CONFIG_MODVERSIONS is not set
1402 +# CONFIG_ARCH_ANAKIN is not set
1403 +# CONFIG_ARCH_ARCA5K is not set
1404 +# CONFIG_ARCH_CLPS7500 is not set
1405 +# CONFIG_ARCH_CLPS711X is not set
1406 +# CONFIG_ARCH_CO285 is not set
1408 +# CONFIG_ARCH_EBSA110 is not set
1409 +# CONFIG_ARCH_CAMELOT is not set
1410 +# CONFIG_ARCH_FOOTBRIDGE is not set
1411 +# CONFIG_ARCH_INTEGRATOR is not set
1412 +# CONFIG_ARCH_L7200 is not set
1413 +# CONFIG_ARCH_MX1ADS is not set
1414 +# CONFIG_ARCH_RPC is not set
1415 +# CONFIG_ARCH_SA1100 is not set
1416 +# CONFIG_ARCH_SHARK is not set
1419 +# Archimedes/A5000 Implementations
1421 +# CONFIG_ARCH_ARC is not set
1422 +# CONFIG_ARCH_A5K is not set
1425 +# Footbridge Implementations
1427 +# CONFIG_ARCH_CATS is not set
1428 +# CONFIG_ARCH_PERSONAL_SERVER is not set
1429 +# CONFIG_ARCH_EBSA285_ADDIN is not set
1430 +# CONFIG_ARCH_EBSA285_HOST is not set
1431 +# CONFIG_ARCH_NETWINDER is not set
1434 +# SA11x0 Implementations
1436 +# CONFIG_SA1100_ASSABET is not set
1437 +# CONFIG_ASSABET_NEPONSET is not set
1438 +# CONFIG_SA1100_ADSBITSY is not set
1439 +# CONFIG_SA1100_BRUTUS is not set
1440 +# CONFIG_SA1100_CEP is not set
1441 +# CONFIG_SA1100_CERF is not set
1442 +# CONFIG_SA1100_H3100 is not set
1443 +# CONFIG_SA1100_H3600 is not set
1444 +# CONFIG_SA1100_H3800 is not set
1445 +# CONFIG_SA1100_H3XXX is not set
1446 +# CONFIG_SA1100_EXTENEX1 is not set
1447 +# CONFIG_SA1100_FLEXANET is not set
1448 +# CONFIG_SA1100_FREEBIRD is not set
1449 +# CONFIG_SA1100_FRODO is not set
1450 +# CONFIG_SA1100_GRAPHICSCLIENT is not set
1451 +# CONFIG_SA1100_GRAPHICSMASTER is not set
1452 +# CONFIG_SA1100_BADGE4 is not set
1453 +# CONFIG_SA1100_JORNADA720 is not set
1454 +# CONFIG_SA1100_HUW_WEBPANEL is not set
1455 +# CONFIG_SA1100_ITSY is not set
1456 +# CONFIG_SA1100_LART is not set
1457 +# CONFIG_SA1100_NANOENGINE is not set
1458 +# CONFIG_SA1100_OMNIMETER is not set
1459 +# CONFIG_SA1100_PANGOLIN is not set
1460 +# CONFIG_SA1100_PLEB is not set
1461 +# CONFIG_SA1100_PT_SYSTEM3 is not set
1462 +# CONFIG_SA1100_SHANNON is not set
1463 +# CONFIG_SA1100_SHERMAN is not set
1464 +# CONFIG_SA1100_SIMPAD is not set
1465 +# CONFIG_SA1100_PFS168 is not set
1466 +# CONFIG_SA1100_VICTOR is not set
1467 +# CONFIG_SA1100_XP860 is not set
1468 +# CONFIG_SA1100_YOPY is not set
1469 +# CONFIG_SA1100_USB is not set
1470 +# CONFIG_SA1100_USB_NETLINK is not set
1471 +# CONFIG_SA1100_USB_CHAR is not set
1472 +# CONFIG_H3600_SLEEVE is not set
1475 +# Intel PXA250/210 Implementations
1477 +# CONFIG_ARCH_LUBBOCK is not set
1478 +# CONFIG_ARCH_PXA_IDP is not set
1479 +CONFIG_ARCH_PXA_CERF=y
1481 +CONFIG_PXA_CERF_PDA=y
1482 +# CONFIG_PXA_CERF_BOARD is not set
1483 +# CONFIG_PXA_CERF_RAM_128MB is not set
1484 +CONFIG_PXA_CERF_RAM_64MB=y
1485 +# CONFIG_PXA_CERF_RAM_32MB is not set
1486 +# CONFIG_PXA_CERF_RAM_16MB is not set
1487 +# CONFIG_PXA_CERF_FLASH_64MB is not set
1488 +CONFIG_PXA_CERF_FLASH_32MB=y
1489 +# CONFIG_PXA_CERF_FLASH_16MB is not set
1490 +# CONFIG_PXA_CERF_FLASH_8MB is not set
1492 +CONFIG_PXA_USB_NETLINK=y
1493 +CONFIG_PXA_USB_CHAR=y
1496 +# CLPS711X/EP721X Implementations
1498 +# CONFIG_ARCH_AUTCPU12 is not set
1499 +# CONFIG_ARCH_CDB89712 is not set
1500 +# CONFIG_ARCH_CLEP7312 is not set
1501 +# CONFIG_ARCH_EDB7211 is not set
1502 +# CONFIG_ARCH_P720T is not set
1503 +# CONFIG_ARCH_FORTUNET is not set
1504 +# CONFIG_ARCH_EP7211 is not set
1505 +# CONFIG_ARCH_EP7212 is not set
1506 +# CONFIG_ARCH_ACORN is not set
1507 +# CONFIG_FOOTBRIDGE is not set
1508 +# CONFIG_FOOTBRIDGE_HOST is not set
1509 +# CONFIG_FOOTBRIDGE_ADDIN is not set
1511 +# CONFIG_CPU_26 is not set
1512 +# CONFIG_CPU_32v3 is not set
1513 +# CONFIG_CPU_32v4 is not set
1514 +# CONFIG_CPU_ARM610 is not set
1515 +# CONFIG_CPU_ARM710 is not set
1516 +# CONFIG_CPU_ARM720T is not set
1517 +# CONFIG_CPU_ARM920T is not set
1518 +# CONFIG_CPU_ARM922T is not set
1519 +# CONFIG_PLD is not set
1520 +# CONFIG_CPU_ARM926T is not set
1521 +# CONFIG_CPU_ARM1020 is not set
1522 +# CONFIG_CPU_SA110 is not set
1523 +# CONFIG_CPU_SA1100 is not set
1525 +CONFIG_CPU_XSCALE=y
1526 +# CONFIG_XSCALE_CACHE_ERRATA is not set
1527 +# CONFIG_ARM_THUMB is not set
1528 +# CONFIG_DISCONTIGMEM is not set
1533 +# CONFIG_PCI is not set
1534 +# CONFIG_ISA is not set
1535 +# CONFIG_ISA_DMA is not set
1536 +# CONFIG_ZBOOT_ROM is not set
1537 +CONFIG_ZBOOT_ROM_TEXT=0
1538 +CONFIG_ZBOOT_ROM_BSS=0
1542 +# PCMCIA/CardBus support
1545 +# CONFIG_I82092 is not set
1546 +# CONFIG_I82365 is not set
1547 +# CONFIG_TCIC is not set
1548 +# CONFIG_PCMCIA_CLPS6700 is not set
1549 +# CONFIG_PCMCIA_SA1100 is not set
1550 +CONFIG_PCMCIA_PXA=y
1553 +CONFIG_BSD_PROCESS_ACCT=y
1556 +# CONFIG_FPE_FASTFPE is not set
1558 +# CONFIG_KCORE_AOUT is not set
1559 +# CONFIG_BINFMT_AOUT is not set
1560 +CONFIG_BINFMT_ELF=y
1561 +# CONFIG_BINFMT_MISC is not set
1562 +# CONFIG_PM is not set
1563 +# CONFIG_ARTHUR is not set
1564 +CONFIG_CMDLINE="root=1f03 rw console=tty0 console=ttyS0,38400 init=/linuxrc"
1566 +# CONFIG_LEDS_TIMER is not set
1568 +CONFIG_ALIGNMENT_TRAP=y
1571 +# Parallel port support
1573 +# CONFIG_PARPORT is not set
1576 +# Memory Technology Devices (MTD)
1579 +# CONFIG_MTD_DEBUG is not set
1580 +CONFIG_MTD_PARTITIONS=y
1581 +# CONFIG_MTD_CONCAT is not set
1582 +CONFIG_MTD_REDBOOT_PARTS=y
1583 +# CONFIG_MTD_CMDLINE_PARTS is not set
1584 +# CONFIG_MTD_AFS_PARTS is not set
1587 +# CONFIG_FTL is not set
1588 +# CONFIG_NFTL is not set
1591 +# RAM/ROM/Flash chip drivers
1594 +# CONFIG_MTD_JEDECPROBE is not set
1595 +CONFIG_MTD_GEN_PROBE=y
1596 +CONFIG_MTD_CFI_ADV_OPTIONS=y
1597 +CONFIG_MTD_CFI_NOSWAP=y
1598 +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
1599 +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
1600 +CONFIG_MTD_CFI_GEOMETRY=y
1601 +# CONFIG_MTD_CFI_B1 is not set
1602 +# CONFIG_MTD_CFI_B2 is not set
1603 +CONFIG_MTD_CFI_B4=y
1604 +# CONFIG_MTD_CFI_B8 is not set
1605 +# CONFIG_MTD_CFI_I1 is not set
1606 +CONFIG_MTD_CFI_I2=y
1607 +# CONFIG_MTD_CFI_I4 is not set
1608 +# CONFIG_MTD_CFI_I8 is not set
1609 +CONFIG_MTD_CFI_INTELEXT=y
1610 +# CONFIG_MTD_CFI_AMDSTD is not set
1611 +# CONFIG_MTD_RAM is not set
1612 +# CONFIG_MTD_ROM is not set
1613 +# CONFIG_MTD_ABSENT is not set
1614 +# CONFIG_MTD_OBSOLETE_CHIPS is not set
1615 +# CONFIG_MTD_AMDSTD is not set
1616 +# CONFIG_MTD_SHARP is not set
1617 +# CONFIG_MTD_JEDEC is not set
1620 +# Mapping drivers for chip access
1622 +# CONFIG_MTD_PHYSMAP is not set
1623 +# CONFIG_MTD_LUBBOCK is not set
1624 +# CONFIG_MTD_NORA is not set
1625 +# CONFIG_MTD_ARM_INTEGRATOR is not set
1626 +# CONFIG_MTD_CDB89712 is not set
1627 +# CONFIG_MTD_SA1100 is not set
1628 +# CONFIG_MTD_DC21285 is not set
1629 +# CONFIG_MTD_IQ80310 is not set
1630 +# CONFIG_MTD_FORTUNET is not set
1631 +CONFIG_MTD_PXA_CERF=y
1632 +# CONFIG_MTD_EPXA10DB is not set
1633 +# CONFIG_MTD_AUTCPU12 is not set
1634 +# CONFIG_MTD_EDB7312 is not set
1635 +# CONFIG_MTD_IMPA7 is not set
1636 +# CONFIG_MTD_PCI is not set
1639 +# Self-contained MTD device drivers
1641 +# CONFIG_MTD_PMC551 is not set
1642 +# CONFIG_MTD_SLRAM is not set
1643 +# CONFIG_MTD_MTDRAM is not set
1644 +# CONFIG_MTD_BLKMTD is not set
1645 +# CONFIG_MTD_DOC1000 is not set
1646 +# CONFIG_MTD_DOC2000 is not set
1647 +# CONFIG_MTD_DOC2001 is not set
1648 +# CONFIG_MTD_DOCPROBE is not set
1651 +# NAND Flash Device Drivers
1653 +# CONFIG_MTD_NAND is not set
1656 +# Plug and Play configuration
1658 +# CONFIG_PNP is not set
1659 +# CONFIG_ISAPNP is not set
1664 +# CONFIG_BLK_DEV_FD is not set
1665 +# CONFIG_BLK_DEV_XD is not set
1666 +# CONFIG_PARIDE is not set
1667 +# CONFIG_BLK_CPQ_DA is not set
1668 +# CONFIG_BLK_CPQ_CISS_DA is not set
1669 +# CONFIG_BLK_DEV_DAC960 is not set
1670 +CONFIG_BLK_DEV_LOOP=m
1671 +# CONFIG_BLK_DEV_NBD is not set
1672 +CONFIG_BLK_DEV_RAM=y
1673 +CONFIG_BLK_DEV_RAM_SIZE=4096
1674 +CONFIG_BLK_DEV_INITRD=y
1677 +# Multi-device support (RAID and LVM)
1679 +# CONFIG_MD is not set
1680 +# CONFIG_BLK_DEV_MD is not set
1681 +# CONFIG_MD_LINEAR is not set
1682 +# CONFIG_MD_RAID0 is not set
1683 +# CONFIG_MD_RAID1 is not set
1684 +# CONFIG_MD_RAID5 is not set
1685 +# CONFIG_MD_MULTIPATH is not set
1686 +# CONFIG_BLK_DEV_LVM is not set
1689 +# Networking options
1692 +# CONFIG_PACKET_MMAP is not set
1693 +# CONFIG_NETLINK_DEV is not set
1694 +# CONFIG_NETFILTER is not set
1698 +# CONFIG_IP_MULTICAST is not set
1699 +# CONFIG_IP_ADVANCED_ROUTER is not set
1701 +CONFIG_IP_PNP_DHCP=y
1702 +CONFIG_IP_PNP_BOOTP=y
1703 +CONFIG_IP_PNP_RARP=y
1704 +# CONFIG_NET_IPIP is not set
1705 +# CONFIG_NET_IPGRE is not set
1706 +# CONFIG_ARPD is not set
1707 +# CONFIG_INET_ECN is not set
1708 +# CONFIG_SYN_COOKIES is not set
1709 +# CONFIG_IPV6 is not set
1710 +# CONFIG_KHTTPD is not set
1711 +# CONFIG_ATM is not set
1712 +# CONFIG_VLAN_8021Q is not set
1713 +# CONFIG_IPX is not set
1714 +# CONFIG_ATALK is not set
1715 +# CONFIG_DECNET is not set
1716 +# CONFIG_BRIDGE is not set
1717 +# CONFIG_X25 is not set
1718 +# CONFIG_LAPB is not set
1719 +# CONFIG_LLC is not set
1720 +# CONFIG_NET_DIVERT is not set
1721 +# CONFIG_ECONET is not set
1722 +# CONFIG_WAN_ROUTER is not set
1723 +# CONFIG_NET_FASTROUTE is not set
1724 +# CONFIG_NET_HW_FLOWCONTROL is not set
1727 +# QoS and/or fair queueing
1729 +# CONFIG_NET_SCHED is not set
1732 +# Network device support
1734 +CONFIG_NETDEVICES=y
1739 +# CONFIG_ARCNET is not set
1740 +# CONFIG_DUMMY is not set
1741 +# CONFIG_BONDING is not set
1742 +# CONFIG_EQUALIZER is not set
1743 +# CONFIG_TUN is not set
1744 +# CONFIG_ETHERTAP is not set
1747 +# Ethernet (10 or 100Mbit)
1749 +CONFIG_NET_ETHERNET=y
1750 +# CONFIG_ARM_AM79C961A is not set
1751 +# CONFIG_SUNLANCE is not set
1752 +# CONFIG_SUNBMAC is not set
1753 +# CONFIG_SUNQE is not set
1754 +# CONFIG_SUNGEM is not set
1755 +# CONFIG_NET_VENDOR_3COM is not set
1756 +# CONFIG_LANCE is not set
1757 +# CONFIG_NET_VENDOR_SMC is not set
1758 +# CONFIG_NET_VENDOR_RACAL is not set
1759 +# CONFIG_NET_ISA is not set
1760 +# CONFIG_NET_PCI is not set
1761 +# CONFIG_NET_POCKET is not set
1764 +# Ethernet (1000 Mbit)
1766 +# CONFIG_ACENIC is not set
1767 +# CONFIG_DL2K is not set
1768 +# CONFIG_MYRI_SBUS is not set
1769 +# CONFIG_NS83820 is not set
1770 +# CONFIG_HAMACHI is not set
1771 +# CONFIG_YELLOWFIN is not set
1772 +# CONFIG_SK98LIN is not set
1773 +# CONFIG_FDDI is not set
1774 +# CONFIG_HIPPI is not set
1775 +# CONFIG_PLIP is not set
1777 +# CONFIG_PPP_MULTILINK is not set
1778 +# CONFIG_PPP_FILTER is not set
1780 +# CONFIG_PPP_SYNC_TTY is not set
1781 +CONFIG_PPP_DEFLATE=m
1782 +CONFIG_PPP_BSDCOMP=m
1783 +# CONFIG_PPPOE is not set
1784 +# CONFIG_SLIP is not set
1787 +# Wireless LAN (non-hamradio)
1789 +# CONFIG_NET_RADIO is not set
1792 +# Token Ring devices
1794 +# CONFIG_TR is not set
1795 +# CONFIG_NET_FC is not set
1796 +# CONFIG_RCPCI is not set
1797 +# CONFIG_SHAPER is not set
1802 +# CONFIG_WAN is not set
1805 +# PCMCIA network device support
1807 +CONFIG_NET_PCMCIA=y
1808 +CONFIG_PCMCIA_3C589=m
1809 +CONFIG_PCMCIA_3C574=m
1810 +CONFIG_PCMCIA_FMVJ18X=m
1811 +CONFIG_PCMCIA_PCNET=m
1812 +CONFIG_PCMCIA_AXNET=m
1813 +CONFIG_PCMCIA_NMCLAN=m
1814 +CONFIG_PCMCIA_SMC91C92=m
1815 +CONFIG_PCMCIA_XIRC2PS=m
1816 +# CONFIG_ARCNET_COM20020_CS is not set
1817 +# CONFIG_PCMCIA_IBMTR is not set
1818 +# CONFIG_NET_PCMCIA_RADIO is not set
1821 +# Amateur Radio support
1823 +# CONFIG_HAMRADIO is not set
1826 +# IrDA (infrared) support
1830 +# CONFIG_IRNET is not set
1832 +CONFIG_IRDA_ULTRA=y
1833 +# CONFIG_IRDA_CACHE_LAST_LSAP is not set
1834 +# CONFIG_IRDA_FAST_RR is not set
1835 +CONFIG_IRDA_DEBUG=y
1838 +# Infrared-port device drivers
1841 +# CONFIG_IRPORT_SIR is not set
1842 +# CONFIG_DONGLE is not set
1843 +# CONFIG_USB_IRDA is not set
1844 +# CONFIG_NSC_FIR is not set
1845 +# CONFIG_WINBOND_FIR is not set
1846 +# CONFIG_TOSHIBA_FIR is not set
1847 +# CONFIG_SMC_IRCC_FIR is not set
1848 +# CONFIG_ALI_FIR is not set
1849 +# CONFIG_VLSI_FIR is not set
1852 +# ATA/IDE/MFM/RLL support
1857 +# IDE, ATA and ATAPI Block devices
1859 +CONFIG_BLK_DEV_IDE=y
1860 +# CONFIG_BLK_DEV_HD_IDE is not set
1861 +# CONFIG_BLK_DEV_HD is not set
1862 +CONFIG_BLK_DEV_IDEDISK=y
1863 +# CONFIG_IDEDISK_MULTI_MODE is not set
1864 +# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
1865 +# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
1866 +# CONFIG_BLK_DEV_IDEDISK_IBM is not set
1867 +# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
1868 +# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
1869 +# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
1870 +# CONFIG_BLK_DEV_IDEDISK_WD is not set
1871 +# CONFIG_BLK_DEV_COMMERIAL is not set
1872 +# CONFIG_BLK_DEV_TIVO is not set
1873 +CONFIG_BLK_DEV_IDECS=m
1874 +# CONFIG_BLK_DEV_IDECD is not set
1875 +# CONFIG_BLK_DEV_IDETAPE is not set
1876 +# CONFIG_BLK_DEV_IDEFLOPPY is not set
1877 +# CONFIG_BLK_DEV_IDESCSI is not set
1878 +# CONFIG_BLK_DEV_CMD640 is not set
1879 +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
1880 +# CONFIG_BLK_DEV_ISAPNP is not set
1881 +# CONFIG_IDE_CHIPSETS is not set
1882 +# CONFIG_IDEDMA_AUTO is not set
1883 +# CONFIG_DMA_NONPCI is not set
1884 +# CONFIG_BLK_DEV_IDE_MODES is not set
1885 +# CONFIG_BLK_DEV_ATARAID is not set
1886 +# CONFIG_BLK_DEV_ATARAID_PDC is not set
1887 +# CONFIG_BLK_DEV_ATARAID_HPT is not set
1892 +# CONFIG_SCSI is not set
1895 +# I2O device support
1897 +# CONFIG_I2O is not set
1898 +# CONFIG_I2O_BLOCK is not set
1899 +# CONFIG_I2O_LAN is not set
1900 +# CONFIG_I2O_SCSI is not set
1901 +# CONFIG_I2O_PROC is not set
1906 +# CONFIG_ISDN is not set
1909 +# Input core support
1912 +# CONFIG_INPUT_KEYBDEV is not set
1913 +# CONFIG_INPUT_MOUSEDEV is not set
1914 +# CONFIG_INPUT_JOYDEV is not set
1915 +CONFIG_INPUT_EVDEV=y
1918 +# Character devices
1921 +CONFIG_VT_CONSOLE=y
1923 +CONFIG_SERIAL_CONSOLE=y
1924 +# CONFIG_SERIAL_EXTENDED is not set
1925 +# CONFIG_SERIAL_NONSTANDARD is not set
1930 +# CONFIG_SERIAL_ANAKIN is not set
1931 +# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
1932 +# CONFIG_SERIAL_AMBA is not set
1933 +# CONFIG_SERIAL_AMBA_CONSOLE is not set
1934 +# CONFIG_SERIAL_CLPS711X is not set
1935 +# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
1936 +# CONFIG_SERIAL_21285 is not set
1937 +# CONFIG_SERIAL_21285_OLD is not set
1938 +# CONFIG_SERIAL_21285_CONSOLE is not set
1939 +# CONFIG_SERIAL_UART00 is not set
1940 +# CONFIG_SERIAL_UART00_CONSOLE is not set
1941 +# CONFIG_SERIAL_SA1100 is not set
1942 +# CONFIG_SERIAL_SA1100_CONSOLE is not set
1943 +# CONFIG_SERIAL_8250 is not set
1944 +# CONFIG_SERIAL_8250_CONSOLE is not set
1945 +# CONFIG_SERIAL_8250_EXTENDED is not set
1946 +# CONFIG_SERIAL_8250_MANY_PORTS is not set
1947 +# CONFIG_SERIAL_8250_SHARE_IRQ is not set
1948 +# CONFIG_SERIAL_8250_DETECT_IRQ is not set
1949 +# CONFIG_SERIAL_8250_MULTIPORT is not set
1950 +# CONFIG_SERIAL_8250_HUB6 is not set
1951 +CONFIG_UNIX98_PTYS=y
1952 +CONFIG_UNIX98_PTY_COUNT=256
1957 +# CONFIG_I2C is not set
1960 +# L3 serial bus support
1962 +# CONFIG_L3 is not set
1963 +# CONFIG_L3_ALGOBIT is not set
1964 +# CONFIG_L3_BIT_SA1100_GPIO is not set
1965 +# CONFIG_L3_SA1111 is not set
1966 +# CONFIG_BIT_SA1100_GPIO is not set
1971 +# CONFIG_BUSMOUSE is not set
1972 +# CONFIG_MOUSE is not set
1977 +# CONFIG_INPUT_GAMEPORT is not set
1978 +# CONFIG_INPUT_NS558 is not set
1979 +# CONFIG_INPUT_LIGHTNING is not set
1980 +# CONFIG_INPUT_PCIGAME is not set
1981 +# CONFIG_INPUT_CS461X is not set
1982 +# CONFIG_INPUT_EMU10K1 is not set
1983 +# CONFIG_INPUT_SERIO is not set
1984 +# CONFIG_INPUT_SERPORT is not set
1985 +# CONFIG_INPUT_ANALOG is not set
1986 +# CONFIG_INPUT_A3D is not set
1987 +# CONFIG_INPUT_ADI is not set
1988 +# CONFIG_INPUT_COBRA is not set
1989 +# CONFIG_INPUT_GF2K is not set
1990 +# CONFIG_INPUT_GRIP is not set
1991 +# CONFIG_INPUT_INTERACT is not set
1992 +# CONFIG_INPUT_TMDC is not set
1993 +# CONFIG_INPUT_SIDEWINDER is not set
1994 +# CONFIG_INPUT_IFORCE_USB is not set
1995 +# CONFIG_INPUT_IFORCE_232 is not set
1996 +# CONFIG_INPUT_WARRIOR is not set
1997 +# CONFIG_INPUT_MAGELLAN is not set
1998 +# CONFIG_INPUT_SPACEORB is not set
1999 +# CONFIG_INPUT_SPACEBALL is not set
2000 +# CONFIG_INPUT_STINGER is not set
2001 +# CONFIG_INPUT_DB9 is not set
2002 +# CONFIG_INPUT_GAMECON is not set
2003 +# CONFIG_INPUT_TURBOGRAFX is not set
2004 +# CONFIG_QIC02_TAPE is not set
2009 +# CONFIG_WATCHDOG is not set
2010 +# CONFIG_INTEL_RNG is not set
2011 +# CONFIG_NVRAM is not set
2012 +# CONFIG_RTC is not set
2013 +# CONFIG_DTLK is not set
2014 +# CONFIG_R3964 is not set
2015 +# CONFIG_APPLICOM is not set
2018 +# Ftape, the floppy tape device driver
2020 +# CONFIG_FTAPE is not set
2021 +# CONFIG_AGP is not set
2022 +# CONFIG_DRM is not set
2025 +# PCMCIA character devices
2027 +CONFIG_PCMCIA_SERIAL_CS=y
2028 +CONFIG_PCMCIA_CHRDEV=y
2031 +# Multimedia devices
2033 +# CONFIG_VIDEO_DEV is not set
2038 +# CONFIG_QUOTA is not set
2040 +CONFIG_AUTOFS4_FS=y
2041 +# CONFIG_REISERFS_FS is not set
2042 +# CONFIG_REISERFS_CHECK is not set
2043 +# CONFIG_REISERFS_PROC_INFO is not set
2044 +# CONFIG_ADFS_FS is not set
2045 +# CONFIG_ADFS_FS_RW is not set
2046 +# CONFIG_AFFS_FS is not set
2047 +# CONFIG_HFS_FS is not set
2048 +# CONFIG_BFS_FS is not set
2049 +# CONFIG_EXT3_FS is not set
2050 +# CONFIG_JBD is not set
2051 +# CONFIG_JBD_DEBUG is not set
2056 +# CONFIG_EFS_FS is not set
2057 +# CONFIG_JFFS_FS is not set
2059 +CONFIG_JFFS2_FS_DEBUG=0
2060 +# CONFIG_CRAMFS is not set
2063 +# CONFIG_ISO9660_FS is not set
2064 +# CONFIG_JOLIET is not set
2065 +# CONFIG_ZISOFS is not set
2066 +# CONFIG_MINIX_FS is not set
2067 +# CONFIG_VXFS_FS is not set
2068 +# CONFIG_NTFS_FS is not set
2069 +# CONFIG_NTFS_RW is not set
2070 +# CONFIG_HPFS_FS is not set
2072 +# CONFIG_DEVFS_FS is not set
2073 +# CONFIG_DEVFS_MOUNT is not set
2074 +# CONFIG_DEVFS_DEBUG is not set
2076 +# CONFIG_QNX4FS_FS is not set
2077 +# CONFIG_QNX4FS_RW is not set
2080 +# CONFIG_SYSV_FS is not set
2081 +# CONFIG_UDF_FS is not set
2082 +# CONFIG_UDF_RW is not set
2083 +# CONFIG_UFS_FS is not set
2084 +# CONFIG_UFS_FS_WRITE is not set
2087 +# Network File Systems
2089 +# CONFIG_CODA_FS is not set
2090 +# CONFIG_INTERMEZZO_FS is not set
2094 +# CONFIG_NFSD is not set
2095 +# CONFIG_NFSD_V3 is not set
2099 +# CONFIG_SMB_FS is not set
2100 +# CONFIG_NCP_FS is not set
2101 +# CONFIG_NCPFS_PACKET_SIGNING is not set
2102 +# CONFIG_NCPFS_IOCTL_LOCKING is not set
2103 +# CONFIG_NCPFS_STRONG is not set
2104 +# CONFIG_NCPFS_NFS_NS is not set
2105 +# CONFIG_NCPFS_OS2_NS is not set
2106 +# CONFIG_NCPFS_SMALLDOS is not set
2107 +# CONFIG_NCPFS_NLS is not set
2108 +# CONFIG_NCPFS_EXTRAS is not set
2109 +# CONFIG_ZISOFS_FS is not set
2110 +# CONFIG_ZLIB_FS_INFLATE is not set
2115 +# CONFIG_PARTITION_ADVANCED is not set
2116 +CONFIG_MSDOS_PARTITION=y
2117 +# CONFIG_SMB_NLS is not set
2121 +# Native Language Support
2123 +CONFIG_NLS_DEFAULT="iso8859-1"
2124 +CONFIG_NLS_CODEPAGE_437=m
2125 +# CONFIG_NLS_CODEPAGE_737 is not set
2126 +# CONFIG_NLS_CODEPAGE_775 is not set
2127 +CONFIG_NLS_CODEPAGE_850=m
2128 +CONFIG_NLS_CODEPAGE_852=m
2129 +# CONFIG_NLS_CODEPAGE_855 is not set
2130 +# CONFIG_NLS_CODEPAGE_857 is not set
2131 +# CONFIG_NLS_CODEPAGE_860 is not set
2132 +# CONFIG_NLS_CODEPAGE_861 is not set
2133 +# CONFIG_NLS_CODEPAGE_862 is not set
2134 +CONFIG_NLS_CODEPAGE_863=m
2135 +# CONFIG_NLS_CODEPAGE_864 is not set
2136 +# CONFIG_NLS_CODEPAGE_865 is not set
2137 +# CONFIG_NLS_CODEPAGE_866 is not set
2138 +# CONFIG_NLS_CODEPAGE_869 is not set
2139 +# CONFIG_NLS_CODEPAGE_936 is not set
2140 +# CONFIG_NLS_CODEPAGE_950 is not set
2141 +# CONFIG_NLS_CODEPAGE_932 is not set
2142 +# CONFIG_NLS_CODEPAGE_949 is not set
2143 +# CONFIG_NLS_CODEPAGE_874 is not set
2144 +# CONFIG_NLS_ISO8859_8 is not set
2145 +# CONFIG_NLS_CODEPAGE_1250 is not set
2146 +# CONFIG_NLS_CODEPAGE_1251 is not set
2147 +CONFIG_NLS_ISO8859_1=m
2148 +CONFIG_NLS_ISO8859_2=m
2149 +CONFIG_NLS_ISO8859_3=m
2150 +CONFIG_NLS_ISO8859_4=m
2151 +# CONFIG_NLS_ISO8859_5 is not set
2152 +# CONFIG_NLS_ISO8859_6 is not set
2153 +# CONFIG_NLS_ISO8859_7 is not set
2154 +# CONFIG_NLS_ISO8859_9 is not set
2155 +# CONFIG_NLS_ISO8859_13 is not set
2156 +# CONFIG_NLS_ISO8859_14 is not set
2157 +# CONFIG_NLS_ISO8859_15 is not set
2158 +# CONFIG_NLS_KOI8_R is not set
2159 +# CONFIG_NLS_KOI8_U is not set
2160 +# CONFIG_NLS_UTF8 is not set
2166 +# CONFIG_VGA_CONSOLE is not set
2169 +# Frame-buffer support
2172 +CONFIG_DUMMY_CONSOLE=y
2173 +# CONFIG_FB_ACORN is not set
2174 +# CONFIG_FB_ANAKIN is not set
2175 +# CONFIG_FB_CLPS711X is not set
2176 +# CONFIG_FB_SA1100 is not set
2178 +# CONFIG_FB_PXA_8BPP is not set
2179 +CONFIG_FB_PXA_16BPP=y
2180 +# CONFIG_FB_CYBER2000 is not set
2181 +# CONFIG_FB_VIRTUAL is not set
2182 +# CONFIG_FBCON_ADVANCED is not set
2183 +CONFIG_FBCON_CFB2=y
2184 +CONFIG_FBCON_CFB4=y
2185 +CONFIG_FBCON_CFB8=y
2186 +CONFIG_FBCON_CFB16=y
2187 +# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
2188 +CONFIG_FBCON_FONTS=y
2189 +# CONFIG_FONT_8x8 is not set
2190 +# CONFIG_FONT_8x16 is not set
2191 +# CONFIG_FONT_SUN8x16 is not set
2192 +# CONFIG_FONT_SUN12x22 is not set
2193 +# CONFIG_FONT_6x11 is not set
2194 +# CONFIG_FONT_PEARL_8x8 is not set
2195 +CONFIG_FONT_ACORN_8x8=y
2201 +# CONFIG_SOUND_BT878 is not set
2202 +# CONFIG_SOUND_CMPCI is not set
2203 +# CONFIG_SOUND_EMU10K1 is not set
2204 +# CONFIG_MIDI_EMU10K1 is not set
2205 +# CONFIG_SOUND_FUSION is not set
2206 +# CONFIG_SOUND_CS4281 is not set
2207 +# CONFIG_SOUND_ES1370 is not set
2208 +# CONFIG_SOUND_ES1371 is not set
2209 +# CONFIG_SOUND_ESSSOLO1 is not set
2210 +# CONFIG_SOUND_MAESTRO is not set
2211 +# CONFIG_SOUND_MAESTRO3 is not set
2212 +# CONFIG_SOUND_ICH is not set
2213 +# CONFIG_SOUND_RME96XX is not set
2214 +# CONFIG_SOUND_SONICVIBES is not set
2215 +# CONFIG_SOUND_TRIDENT is not set
2216 +# CONFIG_SOUND_MSNDCLAS is not set
2217 +# CONFIG_SOUND_MSNDPIN is not set
2218 +# CONFIG_SOUND_VIA82CXXX is not set
2219 +# CONFIG_MIDI_VIA82CXXX is not set
2220 +# CONFIG_SOUND_OSS is not set
2221 +# CONFIG_SOUND_WAVEARTIST is not set
2222 +CONFIG_SOUND_PXA_AC97=y
2223 +# CONFIG_SOUND_TVMIXER is not set
2226 +# Multimedia Capabilities Port drivers
2228 +# CONFIG_MCP is not set
2229 +# CONFIG_MCP_SA1100 is not set
2230 +# CONFIG_MCP_UCB1200 is not set
2231 +# CONFIG_MCP_UCB1200_AUDIO is not set
2232 +# CONFIG_MCP_UCB1200_TS is not set
2233 +CONFIG_MCP_UCB1400_TS=y
2238 +# CONFIG_USB is not set
2239 +# CONFIG_USB_UHCI is not set
2240 +# CONFIG_USB_UHCI_ALT is not set
2241 +# CONFIG_USB_OHCI is not set
2242 +# CONFIG_USB_OHCI_SA1111 is not set
2243 +# CONFIG_USB_AUDIO is not set
2244 +# CONFIG_USB_BLUETOOTH is not set
2245 +# CONFIG_USB_STORAGE is not set
2246 +# CONFIG_USB_STORAGE_DEBUG is not set
2247 +# CONFIG_USB_STORAGE_DATAFAB is not set
2248 +# CONFIG_USB_STORAGE_FREECOM is not set
2249 +# CONFIG_USB_STORAGE_ISD200 is not set
2250 +# CONFIG_USB_STORAGE_DPCM is not set
2251 +# CONFIG_USB_STORAGE_HP8200e is not set
2252 +# CONFIG_USB_STORAGE_SDDR09 is not set
2253 +# CONFIG_USB_STORAGE_JUMPSHOT is not set
2254 +# CONFIG_USB_ACM is not set
2255 +# CONFIG_USB_PRINTER is not set
2256 +# CONFIG_USB_HID is not set
2257 +# CONFIG_USB_HIDDEV is not set
2258 +# CONFIG_USB_KBD is not set
2259 +# CONFIG_USB_MOUSE is not set
2260 +# CONFIG_USB_WACOM is not set
2261 +# CONFIG_USB_DC2XX is not set
2262 +# CONFIG_USB_MDC800 is not set
2263 +# CONFIG_USB_SCANNER is not set
2264 +# CONFIG_USB_MICROTEK is not set
2265 +# CONFIG_USB_HPUSBSCSI is not set
2266 +# CONFIG_USB_PEGASUS is not set
2267 +# CONFIG_USB_KAWETH is not set
2268 +# CONFIG_USB_CATC is not set
2269 +# CONFIG_USB_CDCETHER is not set
2270 +# CONFIG_USB_USBNET is not set
2271 +# CONFIG_USB_USS720 is not set
2274 +# USB Serial Converter support
2276 +# CONFIG_USB_SERIAL is not set
2277 +# CONFIG_USB_SERIAL_GENERIC is not set
2278 +# CONFIG_USB_SERIAL_BELKIN is not set
2279 +# CONFIG_USB_SERIAL_WHITEHEAT is not set
2280 +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
2281 +# CONFIG_USB_SERIAL_EMPEG is not set
2282 +# CONFIG_USB_SERIAL_FTDI_SIO is not set
2283 +# CONFIG_USB_SERIAL_VISOR is not set
2284 +# CONFIG_USB_SERIAL_IPAQ is not set
2285 +# CONFIG_USB_SERIAL_IR is not set
2286 +# CONFIG_USB_SERIAL_EDGEPORT is not set
2287 +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
2288 +# CONFIG_USB_SERIAL_KEYSPAN is not set
2289 +# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
2290 +# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
2291 +# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
2292 +# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
2293 +# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
2294 +# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
2295 +# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
2296 +# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
2297 +# CONFIG_USB_SERIAL_MCT_U232 is not set
2298 +# CONFIG_USB_SERIAL_KLSI is not set
2299 +# CONFIG_USB_SERIAL_PL2303 is not set
2300 +# CONFIG_USB_SERIAL_CYBERJACK is not set
2301 +# CONFIG_USB_SERIAL_XIRCOM is not set
2302 +# CONFIG_USB_SERIAL_OMNINET is not set
2303 +# CONFIG_USB_RIO500 is not set
2306 +# Bluetooth support
2309 +CONFIG_BLUEZ_L2CAP=y
2312 +# Bluetooth device drivers
2314 +# CONFIG_BLUEZ_HCIUSB is not set
2315 +CONFIG_BLUEZ_HCIUART=y
2316 +CONFIG_BLUEZ_HCIVHCI=y
2321 +CONFIG_FRAME_POINTER=y
2322 +CONFIG_DEBUG_USER=y
2323 +CONFIG_DEBUG_INFO=y
2324 +# CONFIG_NO_PGT_CACHE is not set
2325 +CONFIG_DEBUG_KERNEL=y
2326 +# CONFIG_DEBUG_SLAB is not set
2327 +CONFIG_MAGIC_SYSRQ=y
2328 +# CONFIG_DEBUG_SPINLOCK is not set
2329 +# CONFIG_DEBUG_WAITQ is not set
2330 +CONFIG_DEBUG_BUGVERBOSE=y
2331 +CONFIG_DEBUG_ERRORS=y
2333 +# CONFIG_DEBUG_DC21285_PORT is not set
2334 +# CONFIG_DEBUG_CLPS711X_UART2 is not set
2336 +++ linux-2.4.27/arch/arm/def-configs/csb226
2339 +# Automatically generated by make menuconfig: don't edit
2342 +# CONFIG_EISA is not set
2343 +# CONFIG_SBUS is not set
2344 +# CONFIG_MCA is not set
2346 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
2347 +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
2348 +# CONFIG_GENERIC_BUST_SPINLOCK is not set
2349 +# CONFIG_GENERIC_ISA_DMA is not set
2352 +# Code maturity level options
2354 +CONFIG_EXPERIMENTAL=y
2355 +# CONFIG_OBSOLETE is not set
2358 +# Loadable module support
2361 +# CONFIG_MODVERSIONS is not set
2367 +# CONFIG_ARCH_ANAKIN is not set
2368 +# CONFIG_ARCH_ARCA5K is not set
2369 +# CONFIG_ARCH_CLPS7500 is not set
2370 +# CONFIG_ARCH_CLPS711X is not set
2371 +# CONFIG_ARCH_CO285 is not set
2373 +# CONFIG_ARCH_EBSA110 is not set
2374 +# CONFIG_ARCH_CAMELOT is not set
2375 +# CONFIG_ARCH_FOOTBRIDGE is not set
2376 +# CONFIG_ARCH_INTEGRATOR is not set
2377 +# CONFIG_ARCH_OMAHA is not set
2378 +# CONFIG_ARCH_L7200 is not set
2379 +# CONFIG_ARCH_MX1ADS is not set
2380 +# CONFIG_ARCH_RPC is not set
2381 +# CONFIG_ARCH_RISCSTATION is not set
2382 +# CONFIG_ARCH_SA1100 is not set
2383 +# CONFIG_ARCH_SHARK is not set
2384 +# CONFIG_ARCH_AT91RM9200DK is not set
2387 +# Archimedes/A5000 Implementations
2389 +# CONFIG_ARCH_ARC is not set
2390 +# CONFIG_ARCH_A5K is not set
2393 +# Footbridge Implementations
2395 +# CONFIG_ARCH_CATS is not set
2396 +# CONFIG_ARCH_PERSONAL_SERVER is not set
2397 +# CONFIG_ARCH_EBSA285_ADDIN is not set
2398 +# CONFIG_ARCH_EBSA285_HOST is not set
2399 +# CONFIG_ARCH_NETWINDER is not set
2402 +# SA11x0 Implementations
2404 +# CONFIG_SA1100_ACCELENT is not set
2405 +# CONFIG_SA1100_ASSABET is not set
2406 +# CONFIG_ASSABET_NEPONSET is not set
2407 +# CONFIG_SA1100_ADSBITSY is not set
2408 +# CONFIG_SA1100_BRUTUS is not set
2409 +# CONFIG_SA1100_CEP is not set
2410 +# CONFIG_SA1100_CERF is not set
2411 +# CONFIG_SA1100_H3100 is not set
2412 +# CONFIG_SA1100_H3600 is not set
2413 +# CONFIG_SA1100_H3800 is not set
2414 +# CONFIG_SA1100_H3XXX is not set
2415 +# CONFIG_SA1100_EXTENEX1 is not set
2416 +# CONFIG_SA1100_FLEXANET is not set
2417 +# CONFIG_SA1100_FREEBIRD is not set
2418 +# CONFIG_SA1100_FRODO is not set
2419 +# CONFIG_SA1100_GRAPHICSCLIENT is not set
2420 +# CONFIG_SA1100_GRAPHICSMASTER is not set
2421 +# CONFIG_SA1100_HACKKIT is not set
2422 +# CONFIG_SA1100_BADGE4 is not set
2423 +# CONFIG_SA1100_JORNADA720 is not set
2424 +# CONFIG_SA1100_HUW_WEBPANEL is not set
2425 +# CONFIG_SA1100_ITSY is not set
2426 +# CONFIG_SA1100_LART is not set
2427 +# CONFIG_SA1100_NANOENGINE is not set
2428 +# CONFIG_SA1100_OMNIMETER is not set
2429 +# CONFIG_SA1100_PANGOLIN is not set
2430 +# CONFIG_SA1100_PLEB is not set
2431 +# CONFIG_SA1100_PT_SYSTEM3 is not set
2432 +# CONFIG_SA1100_SHANNON is not set
2433 +# CONFIG_SA1100_SHERMAN is not set
2434 +# CONFIG_SA1100_SIMPAD is not set
2435 +# CONFIG_SA1100_SIMPUTER is not set
2436 +# CONFIG_SA1100_PFS168 is not set
2437 +# CONFIG_SA1100_VICTOR is not set
2438 +# CONFIG_SA1100_XP860 is not set
2439 +# CONFIG_SA1100_YOPY is not set
2440 +# CONFIG_SA1100_USB is not set
2441 +# CONFIG_SA1100_USB_NETLINK is not set
2442 +# CONFIG_SA1100_USB_CHAR is not set
2443 +# CONFIG_H3600_SLEEVE is not set
2446 +# Intel PXA250/210 Board
2448 +# CONFIG_ARCH_PXA_IDP is not set
2449 +# CONFIG_ARCH_INNOKOM is not set
2450 +CONFIG_ARCH_CSB226=y
2451 +# CONFIG_ARCH_LUBBOCK is not set
2452 +# CONFIG_ARCH_PXA_CERF is not set
2453 +# CONFIG_PXA_USB is not set
2454 +# CONFIG_PXA_USB_NETLINK is not set
2455 +# CONFIG_PXA_USB_CHAR is not set
2458 +# CLPS711X/EP721X Implementations
2460 +# CONFIG_ARCH_AUTCPU12 is not set
2461 +# CONFIG_ARCH_CDB89712 is not set
2462 +# CONFIG_ARCH_CLEP7312 is not set
2463 +# CONFIG_ARCH_EDB7211 is not set
2464 +# CONFIG_ARCH_P720T is not set
2465 +# CONFIG_ARCH_FORTUNET is not set
2466 +# CONFIG_ARCH_EP7211 is not set
2467 +# CONFIG_ARCH_EP7212 is not set
2468 +# CONFIG_ARCH_ACORN is not set
2469 +# CONFIG_FOOTBRIDGE is not set
2470 +# CONFIG_FOOTBRIDGE_HOST is not set
2471 +# CONFIG_FOOTBRIDGE_ADDIN is not set
2473 +# CONFIG_CPU_26 is not set
2474 +# CONFIG_CPU_ARM610 is not set
2475 +# CONFIG_CPU_ARM710 is not set
2476 +# CONFIG_CPU_ARM720T is not set
2477 +# CONFIG_CPU_ARM920T is not set
2478 +# CONFIG_CPU_ARM922T is not set
2479 +# CONFIG_PLD is not set
2480 +# CONFIG_CPU_ARM926T is not set
2481 +# CONFIG_CPU_ARM1020 is not set
2482 +# CONFIG_CPU_ARM1026 is not set
2483 +# CONFIG_CPU_SA110 is not set
2484 +# CONFIG_CPU_SA1100 is not set
2486 +CONFIG_CPU_XSCALE=y
2487 +CONFIG_XSCALE_CACHE_ERRATA=y
2488 +# CONFIG_CPU_32v3 is not set
2489 +# CONFIG_CPU_32v4 is not set
2490 +# CONFIG_DISCONTIGMEM is not set
2495 +# CONFIG_PCI is not set
2496 +# CONFIG_ISA is not set
2497 +# CONFIG_ISA_DMA is not set
2498 +# CONFIG_ZBOOT_ROM is not set
2499 +CONFIG_ZBOOT_ROM_TEXT=0
2500 +CONFIG_ZBOOT_ROM_BSS=0
2501 +# CONFIG_CPU_FREQ is not set
2502 +# CONFIG_HOTPLUG is not set
2503 +# CONFIG_PCMCIA is not set
2504 +# CONFIG_MMC is not set
2507 +# CONFIG_BSD_PROCESS_ACCT is not set
2509 +# CONFIG_XIP_KERNEL is not set
2511 +# CONFIG_FPE_FASTFPE is not set
2513 +# CONFIG_KCORE_AOUT is not set
2514 +# CONFIG_BINFMT_AOUT is not set
2515 +CONFIG_BINFMT_ELF=y
2516 +# CONFIG_BINFMT_MISC is not set
2517 +# CONFIG_PM is not set
2518 +# CONFIG_ARTHUR is not set
2519 +CONFIG_CMDLINE="console=ttyS0,19200"
2520 +CONFIG_ALIGNMENT_TRAP=y
2521 +CONFIG_ARM_HWTIMER=y
2524 +# Parallel port support
2526 +# CONFIG_PARPORT is not set
2529 +# Memory Technology Devices (MTD)
2531 +# CONFIG_MTD is not set
2534 +# Plug and Play configuration
2536 +# CONFIG_PNP is not set
2537 +# CONFIG_ISAPNP is not set
2542 +# CONFIG_BLK_DEV_FD is not set
2543 +# CONFIG_BLK_DEV_XD is not set
2544 +# CONFIG_PARIDE is not set
2545 +# CONFIG_BLK_CPQ_DA is not set
2546 +# CONFIG_BLK_CPQ_CISS_DA is not set
2547 +# CONFIG_CISS_SCSI_TAPE is not set
2548 +# CONFIG_BLK_DEV_DAC960 is not set
2549 +# CONFIG_BLK_DEV_UMEM is not set
2550 +# CONFIG_BLK_DEV_LOOP is not set
2551 +# CONFIG_BLK_DEV_NBD is not set
2552 +# CONFIG_BLK_DEV_RAM is not set
2553 +# CONFIG_BLK_DEV_INITRD is not set
2556 +# Multi-device support (RAID and LVM)
2558 +# CONFIG_MD is not set
2559 +# CONFIG_BLK_DEV_MD is not set
2560 +# CONFIG_MD_LINEAR is not set
2561 +# CONFIG_MD_RAID0 is not set
2562 +# CONFIG_MD_RAID1 is not set
2563 +# CONFIG_MD_RAID5 is not set
2564 +# CONFIG_MD_MULTIPATH is not set
2565 +# CONFIG_BLK_DEV_LVM is not set
2568 +# Networking options
2570 +# CONFIG_PACKET is not set
2571 +# CONFIG_NETLINK_DEV is not set
2572 +# CONFIG_NETFILTER is not set
2573 +# CONFIG_FILTER is not set
2576 +# CONFIG_IP_MULTICAST is not set
2577 +# CONFIG_IP_ADVANCED_ROUTER is not set
2579 +# CONFIG_IP_PNP_DHCP is not set
2580 +CONFIG_IP_PNP_BOOTP=y
2581 +# CONFIG_IP_PNP_RARP is not set
2582 +# CONFIG_NET_IPIP is not set
2583 +# CONFIG_NET_IPGRE is not set
2584 +# CONFIG_ARPD is not set
2585 +# CONFIG_INET_ECN is not set
2586 +# CONFIG_SYN_COOKIES is not set
2587 +# CONFIG_IPV6 is not set
2588 +# CONFIG_KHTTPD is not set
2589 +# CONFIG_ATM is not set
2590 +# CONFIG_VLAN_8021Q is not set
2591 +# CONFIG_IPX is not set
2592 +# CONFIG_ATALK is not set
2595 +# Appletalk devices
2597 +# CONFIG_DEV_APPLETALK is not set
2598 +# CONFIG_DECNET is not set
2599 +# CONFIG_BRIDGE is not set
2600 +# CONFIG_X25 is not set
2601 +# CONFIG_LAPB is not set
2602 +# CONFIG_LLC is not set
2603 +# CONFIG_NET_DIVERT is not set
2604 +# CONFIG_ECONET is not set
2605 +# CONFIG_WAN_ROUTER is not set
2606 +# CONFIG_NET_FASTROUTE is not set
2607 +# CONFIG_NET_HW_FLOWCONTROL is not set
2610 +# QoS and/or fair queueing
2612 +# CONFIG_NET_SCHED is not set
2617 +# CONFIG_NET_PKTGEN is not set
2620 +# Network device support
2622 +CONFIG_NETDEVICES=y
2627 +# CONFIG_ARCNET is not set
2628 +# CONFIG_DUMMY is not set
2629 +# CONFIG_BONDING is not set
2630 +# CONFIG_EQUALIZER is not set
2631 +# CONFIG_TUN is not set
2632 +# CONFIG_ETHERTAP is not set
2635 +# Ethernet (10 or 100Mbit)
2637 +CONFIG_NET_ETHERNET=y
2638 +# CONFIG_ARM_AM79C961A is not set
2639 +CONFIG_ARM_CIRRUS=y
2640 +# CONFIG_SUNLANCE is not set
2641 +# CONFIG_SUNBMAC is not set
2642 +# CONFIG_SUNQE is not set
2643 +# CONFIG_SUNGEM is not set
2644 +# CONFIG_NET_VENDOR_3COM is not set
2645 +# CONFIG_LANCE is not set
2646 +# CONFIG_NET_VENDOR_SMC is not set
2647 +# CONFIG_NET_VENDOR_RACAL is not set
2648 +# CONFIG_NET_ISA is not set
2649 +# CONFIG_NET_PCI is not set
2650 +# CONFIG_NET_POCKET is not set
2653 +# Ethernet (1000 Mbit)
2655 +# CONFIG_ACENIC is not set
2656 +# CONFIG_DL2K is not set
2657 +# CONFIG_MYRI_SBUS is not set
2658 +# CONFIG_NS83820 is not set
2659 +# CONFIG_HAMACHI is not set
2660 +# CONFIG_YELLOWFIN is not set
2661 +# CONFIG_SK98LIN is not set
2662 +# CONFIG_TIGON3 is not set
2663 +# CONFIG_FDDI is not set
2664 +# CONFIG_HIPPI is not set
2665 +# CONFIG_PLIP is not set
2666 +# CONFIG_PPP is not set
2667 +# CONFIG_SLIP is not set
2670 +# Wireless LAN (non-hamradio)
2672 +# CONFIG_NET_RADIO is not set
2675 +# Token Ring devices
2677 +# CONFIG_TR is not set
2678 +# CONFIG_NET_FC is not set
2679 +# CONFIG_RCPCI is not set
2680 +# CONFIG_SHAPER is not set
2685 +# CONFIG_WAN is not set
2688 +# Amateur Radio support
2690 +# CONFIG_HAMRADIO is not set
2693 +# IrDA (infrared) support
2695 +# CONFIG_IRDA is not set
2698 +# ATA/ATAPI/MFM/RLL support
2700 +# CONFIG_IDE is not set
2701 +# CONFIG_BLK_DEV_IDE_MODES is not set
2702 +# CONFIG_BLK_DEV_HD is not set
2707 +# CONFIG_SCSI is not set
2710 +# I2O device support
2712 +# CONFIG_I2O is not set
2713 +# CONFIG_I2O_BLOCK is not set
2714 +# CONFIG_I2O_LAN is not set
2715 +# CONFIG_I2O_SCSI is not set
2716 +# CONFIG_I2O_PROC is not set
2721 +# CONFIG_ISDN is not set
2724 +# Input core support
2726 +# CONFIG_INPUT is not set
2727 +# CONFIG_INPUT_KEYBDEV is not set
2728 +# CONFIG_INPUT_MOUSEDEV is not set
2729 +# CONFIG_INPUT_JOYDEV is not set
2730 +# CONFIG_INPUT_EVDEV is not set
2733 +# Character devices
2735 +# CONFIG_VT is not set
2737 +CONFIG_SERIAL_CONSOLE=y
2738 +# CONFIG_SERIAL_EXTENDED is not set
2739 +# CONFIG_SERIAL_NONSTANDARD is not set
2744 +# CONFIG_SERIAL_ANAKIN is not set
2745 +# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
2746 +# CONFIG_SERIAL_AMBA is not set
2747 +# CONFIG_SERIAL_AMBA_CONSOLE is not set
2748 +# CONFIG_SERIAL_CLPS711X is not set
2749 +# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
2750 +# CONFIG_SERIAL_21285 is not set
2751 +# CONFIG_SERIAL_21285_OLD is not set
2752 +# CONFIG_SERIAL_21285_CONSOLE is not set
2753 +# CONFIG_SERIAL_UART00 is not set
2754 +# CONFIG_SERIAL_UART00_CONSOLE is not set
2755 +# CONFIG_SERIAL_SA1100 is not set
2756 +# CONFIG_SERIAL_SA1100_CONSOLE is not set
2757 +# CONFIG_SERIAL_OMAHA is not set
2758 +# CONFIG_SERIAL_OMAHA_CONSOLE is not set
2759 +# CONFIG_SERIAL_8250 is not set
2760 +# CONFIG_SERIAL_8250_CONSOLE is not set
2761 +# CONFIG_SERIAL_8250_EXTENDED is not set
2762 +# CONFIG_SERIAL_8250_MANY_PORTS is not set
2763 +# CONFIG_SERIAL_8250_SHARE_IRQ is not set
2764 +# CONFIG_SERIAL_8250_DETECT_IRQ is not set
2765 +# CONFIG_SERIAL_8250_MULTIPORT is not set
2766 +# CONFIG_SERIAL_8250_HUB6 is not set
2767 +CONFIG_UNIX98_PTYS=y
2768 +CONFIG_UNIX98_PTY_COUNT=256
2773 +# CONFIG_I2C is not set
2776 +# L3 serial bus support
2778 +# CONFIG_L3 is not set
2779 +# CONFIG_L3_ALGOBIT is not set
2780 +# CONFIG_L3_BIT_SA1100_GPIO is not set
2781 +# CONFIG_L3_SA1111 is not set
2782 +# CONFIG_BIT_SA1100_GPIO is not set
2787 +# CONFIG_BUSMOUSE is not set
2788 +# CONFIG_MOUSE is not set
2793 +# CONFIG_INPUT_GAMEPORT is not set
2794 +# CONFIG_QIC02_TAPE is not set
2799 +# CONFIG_WATCHDOG is not set
2800 +# CONFIG_NVRAM is not set
2801 +# CONFIG_RTC is not set
2802 +# CONFIG_PXA_RTC is not set
2803 +# CONFIG_DTLK is not set
2804 +# CONFIG_R3964 is not set
2805 +# CONFIG_APPLICOM is not set
2808 +# Ftape, the floppy tape device driver
2810 +# CONFIG_FTAPE is not set
2811 +# CONFIG_AGP is not set
2812 +# CONFIG_DRM is not set
2815 +# Multimedia devices
2817 +# CONFIG_VIDEO_DEV is not set
2822 +# CONFIG_QUOTA is not set
2823 +# CONFIG_AUTOFS_FS is not set
2824 +# CONFIG_AUTOFS4_FS is not set
2825 +# CONFIG_REISERFS_FS is not set
2826 +# CONFIG_REISERFS_CHECK is not set
2827 +# CONFIG_REISERFS_PROC_INFO is not set
2828 +# CONFIG_ADFS_FS is not set
2829 +# CONFIG_ADFS_FS_RW is not set
2830 +# CONFIG_AFFS_FS is not set
2831 +# CONFIG_HFS_FS is not set
2832 +# CONFIG_BFS_FS is not set
2833 +# CONFIG_EXT3_FS is not set
2834 +# CONFIG_JBD is not set
2835 +# CONFIG_JBD_DEBUG is not set
2836 +# CONFIG_FAT_FS is not set
2837 +# CONFIG_MSDOS_FS is not set
2838 +# CONFIG_UMSDOS_FS is not set
2839 +# CONFIG_VFAT_FS is not set
2840 +# CONFIG_EFS_FS is not set
2841 +# CONFIG_JFFS_FS is not set
2842 +# CONFIG_JFFS2_FS is not set
2843 +# CONFIG_CRAMFS is not set
2844 +# CONFIG_TMPFS is not set
2846 +# CONFIG_ISO9660_FS is not set
2847 +# CONFIG_JOLIET is not set
2848 +# CONFIG_ZISOFS is not set
2849 +# CONFIG_MINIX_FS is not set
2850 +# CONFIG_VXFS_FS is not set
2851 +# CONFIG_NTFS_FS is not set
2852 +# CONFIG_NTFS_RW is not set
2853 +# CONFIG_HPFS_FS is not set
2855 +# CONFIG_DEVFS_FS is not set
2856 +# CONFIG_DEVFS_MOUNT is not set
2857 +# CONFIG_DEVFS_DEBUG is not set
2859 +# CONFIG_QNX4FS_FS is not set
2860 +# CONFIG_QNX4FS_RW is not set
2861 +# CONFIG_ROMFS_FS is not set
2862 +# CONFIG_EXT2_FS is not set
2863 +# CONFIG_SYSV_FS is not set
2864 +# CONFIG_UDF_FS is not set
2865 +# CONFIG_UDF_RW is not set
2866 +# CONFIG_UFS_FS is not set
2867 +# CONFIG_UFS_FS_WRITE is not set
2870 +# Network File Systems
2872 +# CONFIG_CODA_FS is not set
2873 +# CONFIG_INTERMEZZO_FS is not set
2875 +# CONFIG_NFS_V3 is not set
2877 +# CONFIG_NFSD is not set
2878 +# CONFIG_NFSD_V3 is not set
2881 +# CONFIG_SMB_FS is not set
2882 +# CONFIG_NCP_FS is not set
2883 +# CONFIG_NCPFS_PACKET_SIGNING is not set
2884 +# CONFIG_NCPFS_IOCTL_LOCKING is not set
2885 +# CONFIG_NCPFS_STRONG is not set
2886 +# CONFIG_NCPFS_NFS_NS is not set
2887 +# CONFIG_NCPFS_OS2_NS is not set
2888 +# CONFIG_NCPFS_SMALLDOS is not set
2889 +# CONFIG_NCPFS_NLS is not set
2890 +# CONFIG_NCPFS_EXTRAS is not set
2891 +# CONFIG_ZISOFS_FS is not set
2892 +# CONFIG_ZLIB_FS_INFLATE is not set
2897 +CONFIG_PARTITION_ADVANCED=y
2898 +# CONFIG_ACORN_PARTITION is not set
2899 +# CONFIG_OSF_PARTITION is not set
2900 +# CONFIG_AMIGA_PARTITION is not set
2901 +# CONFIG_ATARI_PARTITION is not set
2902 +# CONFIG_MAC_PARTITION is not set
2903 +# CONFIG_MSDOS_PARTITION is not set
2904 +# CONFIG_LDM_PARTITION is not set
2905 +# CONFIG_SGI_PARTITION is not set
2906 +# CONFIG_ULTRIX_PARTITION is not set
2907 +# CONFIG_SUN_PARTITION is not set
2908 +# CONFIG_SMB_NLS is not set
2909 +# CONFIG_NLS is not set
2914 +# CONFIG_SOUND is not set
2917 +# Multimedia Capabilities Port drivers
2919 +# CONFIG_MCP is not set
2920 +# CONFIG_MCP_SA1100 is not set
2921 +# CONFIG_MCP_UCB1200 is not set
2922 +# CONFIG_MCP_UCB1200_AUDIO is not set
2923 +# CONFIG_MCP_UCB1200_TS is not set
2924 +# CONFIG_MCP_UCB1400_TS is not set
2929 +# CONFIG_USB is not set
2932 +# Bluetooth support
2934 +# CONFIG_BLUEZ is not set
2939 +CONFIG_FRAME_POINTER=y
2940 +CONFIG_DEBUG_USER=y
2941 +CONFIG_DEBUG_INFO=y
2942 +# CONFIG_NO_PGT_CACHE is not set
2943 +CONFIG_DEBUG_KERNEL=y
2944 +CONFIG_DEBUG_SLAB=y
2945 +CONFIG_MAGIC_SYSRQ=y
2946 +CONFIG_DEBUG_SPINLOCK=y
2947 +CONFIG_DEBUG_WAITQ=y
2948 +CONFIG_DEBUG_BUGVERBOSE=y
2949 +CONFIG_DEBUG_ERRORS=y
2951 +# CONFIG_DEBUG_DC21285_PORT is not set
2952 +# CONFIG_DEBUG_CLPS711X_UART2 is not set
2954 +++ linux-2.4.27/arch/arm/def-configs/innokom
2957 +# Automatically generated by make menuconfig: don't edit
2960 +# CONFIG_EISA is not set
2961 +# CONFIG_SBUS is not set
2962 +# CONFIG_MCA is not set
2964 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
2965 +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
2966 +# CONFIG_GENERIC_BUST_SPINLOCK is not set
2967 +# CONFIG_GENERIC_ISA_DMA is not set
2970 +# Code maturity level options
2972 +CONFIG_EXPERIMENTAL=y
2973 +# CONFIG_OBSOLETE is not set
2976 +# Loadable module support
2979 +# CONFIG_MODVERSIONS is not set
2985 +# CONFIG_ARCH_ANAKIN is not set
2986 +# CONFIG_ARCH_ARCA5K is not set
2987 +# CONFIG_ARCH_CLPS7500 is not set
2988 +# CONFIG_ARCH_CLPS711X is not set
2989 +# CONFIG_ARCH_CO285 is not set
2991 +# CONFIG_ARCH_EBSA110 is not set
2992 +# CONFIG_ARCH_CAMELOT is not set
2993 +# CONFIG_ARCH_FOOTBRIDGE is not set
2994 +# CONFIG_ARCH_INTEGRATOR is not set
2995 +# CONFIG_ARCH_OMAHA is not set
2996 +# CONFIG_ARCH_L7200 is not set
2997 +# CONFIG_ARCH_MX1ADS is not set
2998 +# CONFIG_ARCH_RPC is not set
2999 +# CONFIG_ARCH_RISCSTATION is not set
3000 +# CONFIG_ARCH_SA1100 is not set
3001 +# CONFIG_ARCH_SHARK is not set
3002 +# CONFIG_ARCH_AT91RM9200DK is not set
3005 +# Archimedes/A5000 Implementations
3007 +# CONFIG_ARCH_ARC is not set
3008 +# CONFIG_ARCH_A5K is not set
3011 +# Footbridge Implementations
3013 +# CONFIG_ARCH_CATS is not set
3014 +# CONFIG_ARCH_PERSONAL_SERVER is not set
3015 +# CONFIG_ARCH_EBSA285_ADDIN is not set
3016 +# CONFIG_ARCH_EBSA285_HOST is not set
3017 +# CONFIG_ARCH_NETWINDER is not set
3020 +# SA11x0 Implementations
3022 +# CONFIG_SA1100_ACCELENT is not set
3023 +# CONFIG_SA1100_ASSABET is not set
3024 +# CONFIG_ASSABET_NEPONSET is not set
3025 +# CONFIG_SA1100_ADSBITSY is not set
3026 +# CONFIG_SA1100_BRUTUS is not set
3027 +# CONFIG_SA1100_CEP is not set
3028 +# CONFIG_SA1100_CERF is not set
3029 +# CONFIG_SA1100_H3100 is not set
3030 +# CONFIG_SA1100_H3600 is not set
3031 +# CONFIG_SA1100_H3800 is not set
3032 +# CONFIG_SA1100_H3XXX is not set
3033 +# CONFIG_SA1100_EXTENEX1 is not set
3034 +# CONFIG_SA1100_FLEXANET is not set
3035 +# CONFIG_SA1100_FREEBIRD is not set
3036 +# CONFIG_SA1100_FRODO is not set
3037 +# CONFIG_SA1100_GRAPHICSCLIENT is not set
3038 +# CONFIG_SA1100_GRAPHICSMASTER is not set
3039 +# CONFIG_SA1100_HACKKIT is not set
3040 +# CONFIG_SA1100_BADGE4 is not set
3041 +# CONFIG_SA1100_JORNADA720 is not set
3042 +# CONFIG_SA1100_HUW_WEBPANEL is not set
3043 +# CONFIG_SA1100_ITSY is not set
3044 +# CONFIG_SA1100_LART is not set
3045 +# CONFIG_SA1100_NANOENGINE is not set
3046 +# CONFIG_SA1100_OMNIMETER is not set
3047 +# CONFIG_SA1100_PANGOLIN is not set
3048 +# CONFIG_SA1100_PLEB is not set
3049 +# CONFIG_SA1100_PT_SYSTEM3 is not set
3050 +# CONFIG_SA1100_SHANNON is not set
3051 +# CONFIG_SA1100_SHERMAN is not set
3052 +# CONFIG_SA1100_SIMPAD is not set
3053 +# CONFIG_SA1100_SIMPUTER is not set
3054 +# CONFIG_SA1100_PFS168 is not set
3055 +# CONFIG_SA1100_VICTOR is not set
3056 +# CONFIG_SA1100_XP860 is not set
3057 +# CONFIG_SA1100_YOPY is not set
3058 +# CONFIG_SA1100_USB is not set
3059 +# CONFIG_SA1100_USB_NETLINK is not set
3060 +# CONFIG_SA1100_USB_CHAR is not set
3061 +# CONFIG_H3600_SLEEVE is not set
3064 +# Intel PXA250/210 Board
3066 +# CONFIG_ARCH_PXA_IDP is not set
3067 +CONFIG_ARCH_INNOKOM=y
3068 +# CONFIG_ARCH_CSB226 is not set
3069 +# CONFIG_ARCH_LUBBOCK is not set
3070 +# CONFIG_ARCH_PXA_CERF is not set
3071 +# CONFIG_PXA_USB is not set
3072 +# CONFIG_PXA_USB_NETLINK is not set
3073 +# CONFIG_PXA_USB_CHAR is not set
3076 +# CLPS711X/EP721X Implementations
3078 +# CONFIG_ARCH_AUTCPU12 is not set
3079 +# CONFIG_ARCH_CDB89712 is not set
3080 +# CONFIG_ARCH_CLEP7312 is not set
3081 +# CONFIG_ARCH_EDB7211 is not set
3082 +# CONFIG_ARCH_P720T is not set
3083 +# CONFIG_ARCH_FORTUNET is not set
3084 +# CONFIG_ARCH_EP7211 is not set
3085 +# CONFIG_ARCH_EP7212 is not set
3086 +# CONFIG_ARCH_ACORN is not set
3087 +# CONFIG_FOOTBRIDGE is not set
3088 +# CONFIG_FOOTBRIDGE_HOST is not set
3089 +# CONFIG_FOOTBRIDGE_ADDIN is not set
3091 +# CONFIG_CPU_26 is not set
3092 +# CONFIG_CPU_ARM610 is not set
3093 +# CONFIG_CPU_ARM710 is not set
3094 +# CONFIG_CPU_ARM720T is not set
3095 +# CONFIG_CPU_ARM920T is not set
3096 +# CONFIG_CPU_ARM922T is not set
3097 +# CONFIG_PLD is not set
3098 +# CONFIG_CPU_ARM926T is not set
3099 +# CONFIG_CPU_ARM1020 is not set
3100 +# CONFIG_CPU_ARM1026 is not set
3101 +# CONFIG_CPU_SA110 is not set
3102 +# CONFIG_CPU_SA1100 is not set
3104 +CONFIG_CPU_XSCALE=y
3105 +CONFIG_XSCALE_CACHE_ERRATA=y
3106 +# CONFIG_CPU_32v3 is not set
3107 +# CONFIG_CPU_32v4 is not set
3108 +# CONFIG_DISCONTIGMEM is not set
3113 +# CONFIG_PCI is not set
3114 +# CONFIG_ISA is not set
3115 +# CONFIG_ISA_DMA is not set
3116 +# CONFIG_ZBOOT_ROM is not set
3117 +CONFIG_ZBOOT_ROM_TEXT=0
3118 +CONFIG_ZBOOT_ROM_BSS=0
3119 +# CONFIG_CPU_FREQ is not set
3120 +# CONFIG_HOTPLUG is not set
3121 +# CONFIG_PCMCIA is not set
3122 +# CONFIG_MMC is not set
3125 +# CONFIG_BSD_PROCESS_ACCT is not set
3127 +# CONFIG_XIP_KERNEL is not set
3129 +# CONFIG_FPE_FASTFPE is not set
3131 +# CONFIG_KCORE_AOUT is not set
3132 +# CONFIG_BINFMT_AOUT is not set
3133 +CONFIG_BINFMT_ELF=y
3134 +# CONFIG_BINFMT_MISC is not set
3135 +# CONFIG_PM is not set
3136 +# CONFIG_ARTHUR is not set
3137 +CONFIG_CMDLINE="root=/dev/nfs mem=32M ip=dhcp console=ttyS0,19200"
3138 +CONFIG_ALIGNMENT_TRAP=y
3139 +CONFIG_ARM_HWTIMER=y
3142 +# Parallel port support
3144 +# CONFIG_PARPORT is not set
3147 +# Memory Technology Devices (MTD)
3150 +# CONFIG_MTD_DEBUG is not set
3151 +CONFIG_MTD_PARTITIONS=y
3152 +# CONFIG_MTD_CONCAT is not set
3153 +# CONFIG_MTD_REDBOOT_PARTS is not set
3154 +CONFIG_MTD_CMDLINE_PARTS=y
3155 +# CONFIG_MTD_AFS_PARTS is not set
3158 +# CONFIG_FTL is not set
3159 +# CONFIG_NFTL is not set
3162 +# RAM/ROM/Flash chip drivers
3165 +# CONFIG_MTD_JEDECPROBE is not set
3166 +CONFIG_MTD_GEN_PROBE=y
3167 +# CONFIG_MTD_CFI_ADV_OPTIONS is not set
3168 +CONFIG_MTD_CFI_INTELEXT=y
3169 +CONFIG_MTD_CFI_AMDSTD=y
3170 +# CONFIG_MTD_CFI_STAA is not set
3171 +# CONFIG_MTD_RAM is not set
3172 +# CONFIG_MTD_ROM is not set
3173 +# CONFIG_MTD_ABSENT is not set
3174 +# CONFIG_MTD_OBSOLETE_CHIPS is not set
3175 +# CONFIG_MTD_AMDSTD is not set
3176 +# CONFIG_MTD_SHARP is not set
3177 +# CONFIG_MTD_JEDEC is not set
3180 +# Mapping drivers for chip access
3182 +# CONFIG_MTD_PHYSMAP is not set
3183 +# CONFIG_MTD_NORA is not set
3184 +# CONFIG_MTD_ARM_INTEGRATOR is not set
3185 +# CONFIG_MTD_CDB89712 is not set
3186 +# CONFIG_MTD_SA1100 is not set
3187 +# CONFIG_MTD_DC21285 is not set
3188 +# CONFIG_MTD_IQ80310 is not set
3189 +# CONFIG_MTD_LUBBOCK is not set
3190 +# CONFIG_MTD_EPXA10DB is not set
3191 +# CONFIG_MTD_FORTUNET is not set
3192 +CONFIG_MTD_INNOKOM=y
3193 +CONFIG_MTD_INNOKOM_16MB=y
3194 +# CONFIG_MTD_INNOKOM_64MB is not set
3195 +# CONFIG_MTD_AUTCPU12 is not set
3196 +# CONFIG_MTD_EDB7312 is not set
3197 +# CONFIG_MTD_IMPA7 is not set
3198 +# CONFIG_MTD_CEIVA is not set
3199 +# CONFIG_MTD_PCI is not set
3200 +# CONFIG_MTD_PCMCIA is not set
3203 +# Self-contained MTD device drivers
3205 +# CONFIG_MTD_PMC551 is not set
3206 +# CONFIG_MTD_SLRAM is not set
3207 +# CONFIG_MTD_MTDRAM is not set
3208 +# CONFIG_MTD_BLKMTD is not set
3209 +# CONFIG_MTD_DOC1000 is not set
3210 +# CONFIG_MTD_DOC2000 is not set
3211 +# CONFIG_MTD_DOC2001 is not set
3212 +# CONFIG_MTD_DOCPROBE is not set
3215 +# NAND Flash Device Drivers
3217 +# CONFIG_MTD_NAND is not set
3220 +# Plug and Play configuration
3222 +# CONFIG_PNP is not set
3223 +# CONFIG_ISAPNP is not set
3228 +# CONFIG_BLK_DEV_FD is not set
3229 +# CONFIG_BLK_DEV_XD is not set
3230 +# CONFIG_PARIDE is not set
3231 +# CONFIG_BLK_CPQ_DA is not set
3232 +# CONFIG_BLK_CPQ_CISS_DA is not set
3233 +# CONFIG_CISS_SCSI_TAPE is not set
3234 +# CONFIG_BLK_DEV_DAC960 is not set
3235 +# CONFIG_BLK_DEV_UMEM is not set
3236 +# CONFIG_BLK_DEV_LOOP is not set
3237 +# CONFIG_BLK_DEV_NBD is not set
3238 +# CONFIG_BLK_DEV_RAM is not set
3239 +# CONFIG_BLK_DEV_INITRD is not set
3242 +# Multi-device support (RAID and LVM)
3244 +# CONFIG_MD is not set
3245 +# CONFIG_BLK_DEV_MD is not set
3246 +# CONFIG_MD_LINEAR is not set
3247 +# CONFIG_MD_RAID0 is not set
3248 +# CONFIG_MD_RAID1 is not set
3249 +# CONFIG_MD_RAID5 is not set
3250 +# CONFIG_MD_MULTIPATH is not set
3251 +# CONFIG_BLK_DEV_LVM is not set
3254 +# Networking options
3256 +# CONFIG_PACKET is not set
3257 +# CONFIG_NETLINK_DEV is not set
3258 +# CONFIG_NETFILTER is not set
3259 +# CONFIG_FILTER is not set
3262 +# CONFIG_IP_MULTICAST is not set
3263 +# CONFIG_IP_ADVANCED_ROUTER is not set
3265 +CONFIG_IP_PNP_DHCP=y
3266 +# CONFIG_IP_PNP_BOOTP is not set
3267 +# CONFIG_IP_PNP_RARP is not set
3268 +# CONFIG_NET_IPIP is not set
3269 +# CONFIG_NET_IPGRE is not set
3270 +# CONFIG_ARPD is not set
3271 +# CONFIG_INET_ECN is not set
3272 +# CONFIG_SYN_COOKIES is not set
3273 +# CONFIG_IPV6 is not set
3274 +# CONFIG_KHTTPD is not set
3275 +# CONFIG_ATM is not set
3276 +# CONFIG_VLAN_8021Q is not set
3277 +# CONFIG_IPX is not set
3278 +# CONFIG_ATALK is not set
3281 +# Appletalk devices
3283 +# CONFIG_DEV_APPLETALK is not set
3284 +# CONFIG_DECNET is not set
3285 +# CONFIG_BRIDGE is not set
3286 +# CONFIG_X25 is not set
3287 +# CONFIG_LAPB is not set
3288 +# CONFIG_LLC is not set
3289 +# CONFIG_NET_DIVERT is not set
3290 +# CONFIG_ECONET is not set
3291 +# CONFIG_WAN_ROUTER is not set
3292 +# CONFIG_NET_FASTROUTE is not set
3293 +# CONFIG_NET_HW_FLOWCONTROL is not set
3296 +# QoS and/or fair queueing
3298 +# CONFIG_NET_SCHED is not set
3303 +# CONFIG_NET_PKTGEN is not set
3306 +# Network device support
3308 +CONFIG_NETDEVICES=y
3313 +# CONFIG_ARCNET is not set
3314 +# CONFIG_DUMMY is not set
3315 +# CONFIG_BONDING is not set
3316 +# CONFIG_EQUALIZER is not set
3317 +# CONFIG_TUN is not set
3318 +# CONFIG_ETHERTAP is not set
3321 +# Ethernet (10 or 100Mbit)
3323 +CONFIG_NET_ETHERNET=y
3324 +# CONFIG_ARM_AM79C961A is not set
3325 +# CONFIG_ARM_CIRRUS is not set
3326 +# CONFIG_SUNLANCE is not set
3327 +# CONFIG_SUNBMAC is not set
3328 +# CONFIG_SUNQE is not set
3329 +# CONFIG_SUNGEM is not set
3330 +# CONFIG_NET_VENDOR_3COM is not set
3331 +# CONFIG_LANCE is not set
3332 +CONFIG_NET_VENDOR_SMC=y
3333 +# CONFIG_WD80x3 is not set
3334 +# CONFIG_ULTRAMCA is not set
3335 +# CONFIG_ULTRA is not set
3336 +# CONFIG_ULTRA32 is not set
3337 +# CONFIG_SMC9194 is not set
3339 +# CONFIG_NET_VENDOR_RACAL is not set
3340 +# CONFIG_NET_ISA is not set
3341 +# CONFIG_NET_PCI is not set
3342 +# CONFIG_NET_POCKET is not set
3345 +# Ethernet (1000 Mbit)
3347 +# CONFIG_ACENIC is not set
3348 +# CONFIG_DL2K is not set
3349 +# CONFIG_MYRI_SBUS is not set
3350 +# CONFIG_NS83820 is not set
3351 +# CONFIG_HAMACHI is not set
3352 +# CONFIG_YELLOWFIN is not set
3353 +# CONFIG_SK98LIN is not set
3354 +# CONFIG_TIGON3 is not set
3355 +# CONFIG_FDDI is not set
3356 +# CONFIG_HIPPI is not set
3357 +# CONFIG_PLIP is not set
3358 +# CONFIG_PPP is not set
3359 +# CONFIG_SLIP is not set
3362 +# Wireless LAN (non-hamradio)
3364 +# CONFIG_NET_RADIO is not set
3367 +# Token Ring devices
3369 +# CONFIG_TR is not set
3370 +# CONFIG_NET_FC is not set
3371 +# CONFIG_RCPCI is not set
3372 +# CONFIG_SHAPER is not set
3377 +# CONFIG_WAN is not set
3380 +# Amateur Radio support
3382 +# CONFIG_HAMRADIO is not set
3385 +# IrDA (infrared) support
3387 +# CONFIG_IRDA is not set
3390 +# ATA/ATAPI/MFM/RLL support
3392 +# CONFIG_IDE is not set
3393 +# CONFIG_BLK_DEV_IDE_MODES is not set
3394 +# CONFIG_BLK_DEV_HD is not set
3399 +# CONFIG_SCSI is not set
3402 +# I2O device support
3404 +# CONFIG_I2O is not set
3405 +# CONFIG_I2O_BLOCK is not set
3406 +# CONFIG_I2O_LAN is not set
3407 +# CONFIG_I2O_SCSI is not set
3408 +# CONFIG_I2O_PROC is not set
3413 +# CONFIG_ISDN is not set
3416 +# Input core support
3418 +# CONFIG_INPUT is not set
3419 +# CONFIG_INPUT_KEYBDEV is not set
3420 +# CONFIG_INPUT_MOUSEDEV is not set
3421 +# CONFIG_INPUT_JOYDEV is not set
3422 +# CONFIG_INPUT_EVDEV is not set
3425 +# Character devices
3427 +# CONFIG_VT is not set
3429 +CONFIG_SERIAL_CONSOLE=y
3430 +# CONFIG_SERIAL_EXTENDED is not set
3431 +# CONFIG_SERIAL_NONSTANDARD is not set
3436 +# CONFIG_SERIAL_ANAKIN is not set
3437 +# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
3438 +# CONFIG_SERIAL_AMBA is not set
3439 +# CONFIG_SERIAL_AMBA_CONSOLE is not set
3440 +# CONFIG_SERIAL_CLPS711X is not set
3441 +# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
3442 +# CONFIG_SERIAL_21285 is not set
3443 +# CONFIG_SERIAL_21285_OLD is not set
3444 +# CONFIG_SERIAL_21285_CONSOLE is not set
3445 +# CONFIG_SERIAL_UART00 is not set
3446 +# CONFIG_SERIAL_UART00_CONSOLE is not set
3447 +# CONFIG_SERIAL_SA1100 is not set
3448 +# CONFIG_SERIAL_SA1100_CONSOLE is not set
3449 +# CONFIG_SERIAL_OMAHA is not set
3450 +# CONFIG_SERIAL_OMAHA_CONSOLE is not set
3451 +# CONFIG_SERIAL_8250 is not set
3452 +# CONFIG_SERIAL_8250_CONSOLE is not set
3453 +# CONFIG_SERIAL_8250_EXTENDED is not set
3454 +# CONFIG_SERIAL_8250_MANY_PORTS is not set
3455 +# CONFIG_SERIAL_8250_SHARE_IRQ is not set
3456 +# CONFIG_SERIAL_8250_DETECT_IRQ is not set
3457 +# CONFIG_SERIAL_8250_MULTIPORT is not set
3458 +# CONFIG_SERIAL_8250_HUB6 is not set
3459 +CONFIG_UNIX98_PTYS=y
3460 +CONFIG_UNIX98_PTY_COUNT=256
3466 +# CONFIG_I2C_ALGOBIT is not set
3467 +# CONFIG_I2C_ALGOPCF is not set
3468 +CONFIG_I2C_PXA_ALGO=y
3469 +CONFIG_I2C_PXA_ADAP=y
3470 +CONFIG_I2C_CHARDEV=y
3472 +# CONFIG_I2C_DS1307 is not set
3475 +# L3 serial bus support
3477 +# CONFIG_L3 is not set
3478 +# CONFIG_L3_ALGOBIT is not set
3479 +# CONFIG_L3_BIT_SA1100_GPIO is not set
3480 +# CONFIG_L3_SA1111 is not set
3481 +# CONFIG_BIT_SA1100_GPIO is not set
3486 +# CONFIG_BUSMOUSE is not set
3487 +# CONFIG_MOUSE is not set
3492 +# CONFIG_INPUT_GAMEPORT is not set
3493 +# CONFIG_QIC02_TAPE is not set
3498 +# CONFIG_WATCHDOG is not set
3499 +# CONFIG_NVRAM is not set
3500 +# CONFIG_RTC is not set
3501 +# CONFIG_PXA_RTC is not set
3502 +# CONFIG_DTLK is not set
3503 +# CONFIG_R3964 is not set
3504 +# CONFIG_APPLICOM is not set
3507 +# Ftape, the floppy tape device driver
3509 +# CONFIG_FTAPE is not set
3510 +# CONFIG_AGP is not set
3511 +# CONFIG_DRM is not set
3514 +# Multimedia devices
3516 +# CONFIG_VIDEO_DEV is not set
3521 +# CONFIG_QUOTA is not set
3522 +# CONFIG_AUTOFS_FS is not set
3523 +# CONFIG_AUTOFS4_FS is not set
3524 +# CONFIG_REISERFS_FS is not set
3525 +# CONFIG_REISERFS_CHECK is not set
3526 +# CONFIG_REISERFS_PROC_INFO is not set
3527 +# CONFIG_ADFS_FS is not set
3528 +# CONFIG_ADFS_FS_RW is not set
3529 +# CONFIG_AFFS_FS is not set
3530 +# CONFIG_HFS_FS is not set
3531 +# CONFIG_BFS_FS is not set
3532 +# CONFIG_EXT3_FS is not set
3533 +# CONFIG_JBD is not set
3534 +# CONFIG_JBD_DEBUG is not set
3535 +# CONFIG_FAT_FS is not set
3536 +# CONFIG_MSDOS_FS is not set
3537 +# CONFIG_UMSDOS_FS is not set
3538 +# CONFIG_VFAT_FS is not set
3539 +# CONFIG_EFS_FS is not set
3540 +# CONFIG_JFFS_FS is not set
3542 +CONFIG_JFFS2_FS_DEBUG=0
3543 +# CONFIG_JFFS2_FS_NAND is not set
3544 +# CONFIG_CRAMFS is not set
3545 +# CONFIG_TMPFS is not set
3547 +# CONFIG_ISO9660_FS is not set
3548 +# CONFIG_JOLIET is not set
3549 +# CONFIG_ZISOFS is not set
3550 +# CONFIG_MINIX_FS is not set
3551 +# CONFIG_VXFS_FS is not set
3552 +# CONFIG_NTFS_FS is not set
3553 +# CONFIG_NTFS_RW is not set
3554 +# CONFIG_HPFS_FS is not set
3557 +CONFIG_DEVFS_MOUNT=y
3558 +# CONFIG_DEVFS_DEBUG is not set
3560 +# CONFIG_QNX4FS_FS is not set
3561 +# CONFIG_QNX4FS_RW is not set
3562 +# CONFIG_ROMFS_FS is not set
3563 +# CONFIG_EXT2_FS is not set
3564 +# CONFIG_SYSV_FS is not set
3565 +# CONFIG_UDF_FS is not set
3566 +# CONFIG_UDF_RW is not set
3567 +# CONFIG_UFS_FS is not set
3568 +# CONFIG_UFS_FS_WRITE is not set
3571 +# Network File Systems
3573 +# CONFIG_CODA_FS is not set
3574 +# CONFIG_INTERMEZZO_FS is not set
3578 +# CONFIG_NFSD is not set
3579 +# CONFIG_NFSD_V3 is not set
3583 +# CONFIG_SMB_FS is not set
3584 +# CONFIG_NCP_FS is not set
3585 +# CONFIG_NCPFS_PACKET_SIGNING is not set
3586 +# CONFIG_NCPFS_IOCTL_LOCKING is not set
3587 +# CONFIG_NCPFS_STRONG is not set
3588 +# CONFIG_NCPFS_NFS_NS is not set
3589 +# CONFIG_NCPFS_OS2_NS is not set
3590 +# CONFIG_NCPFS_SMALLDOS is not set
3591 +# CONFIG_NCPFS_NLS is not set
3592 +# CONFIG_NCPFS_EXTRAS is not set
3593 +# CONFIG_ZISOFS_FS is not set
3594 +# CONFIG_ZLIB_FS_INFLATE is not set
3599 +CONFIG_PARTITION_ADVANCED=y
3600 +# CONFIG_ACORN_PARTITION is not set
3601 +# CONFIG_OSF_PARTITION is not set
3602 +# CONFIG_AMIGA_PARTITION is not set
3603 +# CONFIG_ATARI_PARTITION is not set
3604 +# CONFIG_MAC_PARTITION is not set
3605 +# CONFIG_MSDOS_PARTITION is not set
3606 +# CONFIG_LDM_PARTITION is not set
3607 +# CONFIG_SGI_PARTITION is not set
3608 +# CONFIG_ULTRIX_PARTITION is not set
3609 +# CONFIG_SUN_PARTITION is not set
3610 +# CONFIG_SMB_NLS is not set
3611 +# CONFIG_NLS is not set
3616 +# CONFIG_SOUND is not set
3619 +# Multimedia Capabilities Port drivers
3621 +# CONFIG_MCP is not set
3622 +# CONFIG_MCP_SA1100 is not set
3623 +# CONFIG_MCP_UCB1200 is not set
3624 +# CONFIG_MCP_UCB1200_AUDIO is not set
3625 +# CONFIG_MCP_UCB1200_TS is not set
3626 +# CONFIG_MCP_UCB1400_TS is not set
3631 +# CONFIG_USB is not set
3634 +# Bluetooth support
3636 +# CONFIG_BLUEZ is not set
3641 +CONFIG_FRAME_POINTER=y
3642 +CONFIG_DEBUG_USER=y
3643 +CONFIG_DEBUG_INFO=y
3644 +# CONFIG_NO_PGT_CACHE is not set
3645 +CONFIG_DEBUG_KERNEL=y
3646 +CONFIG_DEBUG_SLAB=y
3647 +CONFIG_MAGIC_SYSRQ=y
3648 +CONFIG_DEBUG_SPINLOCK=y
3649 +CONFIG_DEBUG_WAITQ=y
3650 +CONFIG_DEBUG_BUGVERBOSE=y
3651 +CONFIG_DEBUG_ERRORS=y
3653 +# CONFIG_DEBUG_DC21285_PORT is not set
3654 +# CONFIG_DEBUG_CLPS711X_UART2 is not set
3656 +++ linux-2.4.27/arch/arm/def-configs/lubbock
3659 +# Automatically generated make config: don't edit
3662 +# CONFIG_EISA is not set
3663 +# CONFIG_SBUS is not set
3664 +# CONFIG_MCA is not set
3666 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
3667 +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
3668 +# CONFIG_GENERIC_BUST_SPINLOCK is not set
3669 +# CONFIG_GENERIC_ISA_DMA is not set
3672 +# Code maturity level options
3674 +CONFIG_EXPERIMENTAL=y
3675 +# CONFIG_OBSOLETE is not set
3678 +# Loadable module support
3681 +# CONFIG_MODVERSIONS is not set
3682 +# CONFIG_KMOD is not set
3687 +# CONFIG_ARCH_ANAKIN is not set
3688 +# CONFIG_ARCH_ARCA5K is not set
3689 +# CONFIG_ARCH_CLPS7500 is not set
3690 +# CONFIG_ARCH_CLPS711X is not set
3691 +# CONFIG_ARCH_CO285 is not set
3693 +# CONFIG_ARCH_EBSA110 is not set
3694 +# CONFIG_ARCH_CAMELOT is not set
3695 +# CONFIG_ARCH_FOOTBRIDGE is not set
3696 +# CONFIG_ARCH_INTEGRATOR is not set
3697 +# CONFIG_ARCH_OMAHA is not set
3698 +# CONFIG_ARCH_L7200 is not set
3699 +# CONFIG_ARCH_MX1ADS is not set
3700 +# CONFIG_ARCH_RPC is not set
3701 +# CONFIG_ARCH_RISCSTATION is not set
3702 +# CONFIG_ARCH_SA1100 is not set
3703 +# CONFIG_ARCH_SHARK is not set
3704 +# CONFIG_ARCH_AT91RM9200 is not set
3707 +# Archimedes/A5000 Implementations
3711 +# Archimedes/A5000 Implementations (select only ONE)
3713 +# CONFIG_ARCH_ARC is not set
3714 +# CONFIG_ARCH_A5K is not set
3717 +# Footbridge Implementations
3719 +# CONFIG_ARCH_CATS is not set
3720 +# CONFIG_ARCH_PERSONAL_SERVER is not set
3721 +# CONFIG_ARCH_EBSA285_ADDIN is not set
3722 +# CONFIG_ARCH_EBSA285_HOST is not set
3723 +# CONFIG_ARCH_NETWINDER is not set
3726 +# SA11x0 Implementations
3728 +# CONFIG_SA1100_ACCELENT is not set
3729 +# CONFIG_SA1100_ASSABET is not set
3730 +# CONFIG_ASSABET_NEPONSET is not set
3731 +# CONFIG_SA1100_ADSAGC is not set
3732 +# CONFIG_SA1100_ADSBITSY is not set
3733 +# CONFIG_SA1100_ADSBITSYPLUS is not set
3734 +# CONFIG_SA1100_BRUTUS is not set
3735 +# CONFIG_SA1100_CEP is not set
3736 +# CONFIG_SA1100_CERF is not set
3737 +# CONFIG_SA1100_H3100 is not set
3738 +# CONFIG_SA1100_H3600 is not set
3739 +# CONFIG_SA1100_H3800 is not set
3740 +# CONFIG_SA1100_H3XXX is not set
3741 +# CONFIG_H3600_SLEEVE is not set
3742 +# CONFIG_SA1100_EXTENEX1 is not set
3743 +# CONFIG_SA1100_FLEXANET is not set
3744 +# CONFIG_SA1100_FREEBIRD is not set
3745 +# CONFIG_SA1100_FRODO is not set
3746 +# CONFIG_SA1100_GRAPHICSCLIENT is not set
3747 +# CONFIG_SA1100_GRAPHICSMASTER is not set
3748 +# CONFIG_SA1100_HACKKIT is not set
3749 +# CONFIG_SA1100_BADGE4 is not set
3750 +# CONFIG_SA1100_JORNADA720 is not set
3751 +# CONFIG_SA1100_HUW_WEBPANEL is not set
3752 +# CONFIG_SA1100_ITSY is not set
3753 +# CONFIG_SA1100_LART is not set
3754 +# CONFIG_SA1100_NANOENGINE is not set
3755 +# CONFIG_SA1100_OMNIMETER is not set
3756 +# CONFIG_SA1100_PANGOLIN is not set
3757 +# CONFIG_SA1100_PLEB is not set
3758 +# CONFIG_SA1100_PT_SYSTEM3 is not set
3759 +# CONFIG_SA1100_SHANNON is not set
3760 +# CONFIG_SA1100_SHERMAN is not set
3761 +# CONFIG_SA1100_SIMPAD is not set
3762 +# CONFIG_SA1100_SIMPUTER is not set
3763 +# CONFIG_SA1100_PFS168 is not set
3764 +# CONFIG_SA1100_VICTOR is not set
3765 +# CONFIG_SA1100_XP860 is not set
3766 +# CONFIG_SA1100_YOPY is not set
3767 +# CONFIG_SA1100_USB is not set
3768 +# CONFIG_SA1100_USB_NETLINK is not set
3769 +# CONFIG_SA1100_USB_CHAR is not set
3770 +# CONFIG_SA1100_SSP is not set
3773 +# AT91RM9200 Implementations
3775 +# CONFIG_ARCH_AT91RM9200DK is not set
3778 +# Intel PXA250/210 Implementations
3780 +CONFIG_ARCH_LUBBOCK=y
3781 +# CONFIG_ARCH_PXA_IDP is not set
3782 +# CONFIG_ARCH_PXA_CERF is not set
3783 +# CONFIG_ARCH_TRIZEPS2 is not set
3785 +# CONFIG_PXA_USB is not set
3786 +# CONFIG_PXA_USB_NETLINK is not set
3787 +# CONFIG_PXA_USB_CHAR is not set
3790 +# CLPS711X/EP721X Implementations
3792 +# CONFIG_ARCH_AUTCPU12 is not set
3793 +# CONFIG_ARCH_CDB89712 is not set
3794 +# CONFIG_ARCH_CLEP7312 is not set
3795 +# CONFIG_ARCH_EDB7211 is not set
3796 +# CONFIG_ARCH_FORTUNET is not set
3797 +# CONFIG_ARCH_GUIDEA07 is not set
3798 +# CONFIG_ARCH_P720T is not set
3799 +# CONFIG_ARCH_EP7211 is not set
3800 +# CONFIG_ARCH_EP7212 is not set
3801 +# CONFIG_ARCH_ACORN is not set
3802 +# CONFIG_FOOTBRIDGE is not set
3803 +# CONFIG_FOOTBRIDGE_HOST is not set
3804 +# CONFIG_FOOTBRIDGE_ADDIN is not set
3810 +# CONFIG_CPU_26 is not set
3811 +# CONFIG_CPU_ARM610 is not set
3812 +# CONFIG_CPU_ARM710 is not set
3813 +# CONFIG_CPU_ARM720T is not set
3814 +# CONFIG_CPU_ARM920T is not set
3815 +# CONFIG_CPU_ARM922T is not set
3816 +# CONFIG_PLD is not set
3817 +# CONFIG_CPU_ARM926T is not set
3818 +# CONFIG_CPU_ARM1020 is not set
3819 +# CONFIG_CPU_ARM1026 is not set
3820 +# CONFIG_CPU_SA110 is not set
3821 +# CONFIG_CPU_SA1100 is not set
3823 +CONFIG_CPU_XSCALE=y
3824 +# CONFIG_XSCALE_CACHE_ERRATA is not set
3825 +# CONFIG_CPU_32v3 is not set
3826 +# CONFIG_CPU_32v4 is not set
3829 +# Processor Features
3831 +# CONFIG_DISCONTIGMEM is not set
3836 +# CONFIG_PCI is not set
3837 +# CONFIG_ISA is not set
3838 +# CONFIG_ISA_DMA is not set
3839 +# CONFIG_ZBOOT_ROM is not set
3840 +CONFIG_ZBOOT_ROM_TEXT=0
3841 +CONFIG_ZBOOT_ROM_BSS=0
3846 +# PCMCIA/CardBus support
3849 +# CONFIG_I82092 is not set
3850 +# CONFIG_I82365 is not set
3851 +# CONFIG_TCIC is not set
3852 +# CONFIG_PCMCIA_CLPS6700 is not set
3853 +# CONFIG_PCMCIA_SA1100 is not set
3854 +CONFIG_PCMCIA_PXA=y
3857 +# MMC device drivers
3862 +CONFIG_MMC_PARTITIONS=y
3865 +# CONFIG_BSD_PROCESS_ACCT is not set
3867 +# CONFIG_XIP_KERNEL is not set
3870 +# At least one math emulation must be selected
3873 +# CONFIG_FPE_NWFPE_XP is not set
3874 +# CONFIG_FPE_FASTFPE is not set
3876 +# CONFIG_KCORE_AOUT is not set
3877 +# CONFIG_BINFMT_AOUT is not set
3878 +CONFIG_BINFMT_ELF=y
3879 +# CONFIG_BINFMT_MISC is not set
3881 +# CONFIG_ARTHUR is not set
3882 +CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200 mem=32M"
3884 +CONFIG_LEDS_TIMER=y
3886 +CONFIG_ALIGNMENT_TRAP=y
3889 +# Parallel port support
3891 +# CONFIG_PARPORT is not set
3894 +# Memory Technology Devices (MTD)
3897 +# CONFIG_MTD_DEBUG is not set
3898 +CONFIG_MTD_PARTITIONS=y
3899 +# CONFIG_MTD_CONCAT is not set
3900 +CONFIG_MTD_REDBOOT_PARTS=y
3901 +# CONFIG_MTD_CMDLINE_PARTS is not set
3902 +# CONFIG_MTD_AFS_PARTS is not set
3905 +# User Modules And Translation Layers
3909 +# CONFIG_FTL is not set
3910 +# CONFIG_NFTL is not set
3913 +# RAM/ROM/Flash chip drivers
3916 +# CONFIG_MTD_JEDECPROBE is not set
3917 +CONFIG_MTD_GEN_PROBE=y
3918 +CONFIG_MTD_CFI_ADV_OPTIONS=y
3919 +CONFIG_MTD_CFI_NOSWAP=y
3920 +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
3921 +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
3922 +CONFIG_MTD_CFI_GEOMETRY=y
3923 +# CONFIG_MTD_CFI_B1 is not set
3924 +CONFIG_MTD_CFI_B2=y
3925 +CONFIG_MTD_CFI_B4=y
3926 +# CONFIG_MTD_CFI_B8 is not set
3927 +CONFIG_MTD_CFI_I1=y
3928 +CONFIG_MTD_CFI_I2=y
3929 +# CONFIG_MTD_CFI_I4 is not set
3930 +# CONFIG_MTD_CFI_I8 is not set
3931 +CONFIG_MTD_CFI_INTELEXT=y
3932 +# CONFIG_MTD_CFI_AMDSTD is not set
3933 +# CONFIG_MTD_CFI_STAA is not set
3934 +# CONFIG_MTD_RAM is not set
3935 +# CONFIG_MTD_ROM is not set
3936 +# CONFIG_MTD_ABSENT is not set
3937 +# CONFIG_MTD_OBSOLETE_CHIPS is not set
3938 +# CONFIG_MTD_AMDSTD is not set
3939 +# CONFIG_MTD_SHARP is not set
3940 +# CONFIG_MTD_JEDEC is not set
3943 +# Mapping drivers for chip access
3945 +# CONFIG_MTD_PHYSMAP is not set
3946 +CONFIG_MTD_LUBBOCK=y
3947 +# CONFIG_MTD_NORA is not set
3948 +# CONFIG_MTD_ARM_INTEGRATOR is not set
3949 +# CONFIG_MTD_CDB89712 is not set
3950 +# CONFIG_MTD_SA1100 is not set
3951 +# CONFIG_MTD_DC21285 is not set
3952 +# CONFIG_MTD_IQ80310 is not set
3953 +# CONFIG_MTD_FORTUNET is not set
3954 +# CONFIG_MTD_EPXA is not set
3955 +# CONFIG_MTD_AUTCPU12 is not set
3956 +# CONFIG_MTD_EDB7312 is not set
3957 +# CONFIG_MTD_IMPA7 is not set
3958 +# CONFIG_MTD_CEIVA is not set
3959 +# CONFIG_MTD_PCI is not set
3960 +# CONFIG_MTD_PCMCIA is not set
3963 +# Self-contained MTD device drivers
3965 +# CONFIG_MTD_PMC551 is not set
3966 +# CONFIG_MTD_SLRAM is not set
3967 +# CONFIG_MTD_MTDRAM is not set
3968 +# CONFIG_MTD_BLKMTD is not set
3971 +# Disk-On-Chip Device Drivers
3973 +# CONFIG_MTD_DOC1000 is not set
3974 +# CONFIG_MTD_DOC2000 is not set
3975 +# CONFIG_MTD_DOC2001 is not set
3976 +# CONFIG_MTD_DOCPROBE is not set
3979 +# NAND Flash Device Drivers
3981 +# CONFIG_MTD_NAND is not set
3984 +# Plug and Play configuration
3986 +# CONFIG_PNP is not set
3987 +# CONFIG_ISAPNP is not set
3992 +# CONFIG_BLK_DEV_FD is not set
3993 +# CONFIG_BLK_DEV_XD is not set
3994 +# CONFIG_PARIDE is not set
3995 +# CONFIG_BLK_CPQ_DA is not set
3996 +# CONFIG_BLK_CPQ_CISS_DA is not set
3997 +# CONFIG_CISS_SCSI_TAPE is not set
3998 +# CONFIG_BLK_DEV_DAC960 is not set
3999 +# CONFIG_BLK_DEV_UMEM is not set
4000 +# CONFIG_BLK_DEV_LOOP is not set
4001 +# CONFIG_BLK_DEV_NBD is not set
4002 +# CONFIG_BLK_DEV_RAM is not set
4003 +# CONFIG_BLK_DEV_INITRD is not set
4004 +# CONFIG_BLK_STATS is not set
4007 +# Multi-device support (RAID and LVM)
4009 +# CONFIG_MD is not set
4010 +# CONFIG_BLK_DEV_MD is not set
4011 +# CONFIG_MD_LINEAR is not set
4012 +# CONFIG_MD_RAID0 is not set
4013 +# CONFIG_MD_RAID1 is not set
4014 +# CONFIG_MD_RAID5 is not set
4015 +# CONFIG_MD_MULTIPATH is not set
4016 +# CONFIG_BLK_DEV_LVM is not set
4019 +# Networking options
4021 +# CONFIG_PACKET is not set
4022 +# CONFIG_NETLINK_DEV is not set
4023 +# CONFIG_NETFILTER is not set
4024 +# CONFIG_FILTER is not set
4027 +# CONFIG_IP_MULTICAST is not set
4028 +# CONFIG_IP_ADVANCED_ROUTER is not set
4030 +# CONFIG_IP_PNP_DHCP is not set
4031 +CONFIG_IP_PNP_BOOTP=y
4032 +# CONFIG_IP_PNP_RARP is not set
4033 +# CONFIG_NET_IPIP is not set
4034 +# CONFIG_NET_IPGRE is not set
4035 +# CONFIG_ARPD is not set
4036 +# CONFIG_INET_ECN is not set
4037 +# CONFIG_SYN_COOKIES is not set
4038 +# CONFIG_IPV6 is not set
4039 +# CONFIG_KHTTPD is not set
4040 +# CONFIG_ATM is not set
4041 +# CONFIG_VLAN_8021Q is not set
4046 +# CONFIG_IPX is not set
4047 +# CONFIG_ATALK is not set
4050 +# Appletalk devices
4052 +# CONFIG_DEV_APPLETALK is not set
4053 +# CONFIG_DECNET is not set
4054 +# CONFIG_BRIDGE is not set
4055 +# CONFIG_X25 is not set
4056 +# CONFIG_LAPB is not set
4057 +# CONFIG_LLC is not set
4058 +# CONFIG_NET_DIVERT is not set
4059 +# CONFIG_ECONET is not set
4060 +# CONFIG_WAN_ROUTER is not set
4061 +# CONFIG_NET_FASTROUTE is not set
4062 +# CONFIG_NET_HW_FLOWCONTROL is not set
4065 +# QoS and/or fair queueing
4067 +# CONFIG_NET_SCHED is not set
4072 +# CONFIG_NET_PKTGEN is not set
4075 +# Network device support
4077 +CONFIG_NETDEVICES=y
4082 +# CONFIG_ARCNET is not set
4083 +# CONFIG_DUMMY is not set
4084 +# CONFIG_BONDING is not set
4085 +# CONFIG_EQUALIZER is not set
4086 +# CONFIG_TUN is not set
4087 +# CONFIG_ETHERTAP is not set
4090 +# Ethernet (10 or 100Mbit)
4092 +CONFIG_NET_ETHERNET=y
4093 +# CONFIG_ARM_AM79C961A is not set
4094 +# CONFIG_ARM_CIRRUS is not set
4095 +# CONFIG_SUNLANCE is not set
4096 +# CONFIG_SUNBMAC is not set
4097 +# CONFIG_SUNQE is not set
4098 +# CONFIG_SUNGEM is not set
4099 +# CONFIG_NET_VENDOR_3COM is not set
4100 +# CONFIG_LANCE is not set
4101 +CONFIG_NET_VENDOR_SMC=y
4102 +# CONFIG_WD80x3 is not set
4103 +# CONFIG_ULTRAMCA is not set
4104 +# CONFIG_ULTRA is not set
4105 +# CONFIG_ULTRA32 is not set
4106 +# CONFIG_SMC9194 is not set
4108 +# CONFIG_NET_VENDOR_RACAL is not set
4109 +# CONFIG_NET_ISA is not set
4110 +# CONFIG_NET_PCI is not set
4111 +# CONFIG_NET_POCKET is not set
4114 +# Ethernet (1000 Mbit)
4116 +# CONFIG_ACENIC is not set
4117 +# CONFIG_DL2K is not set
4118 +# CONFIG_E1000 is not set
4119 +# CONFIG_MYRI_SBUS is not set
4120 +# CONFIG_NS83820 is not set
4121 +# CONFIG_HAMACHI is not set
4122 +# CONFIG_YELLOWFIN is not set
4123 +# CONFIG_R8169 is not set
4124 +# CONFIG_SK98LIN is not set
4125 +# CONFIG_TIGON3 is not set
4126 +# CONFIG_FDDI is not set
4127 +# CONFIG_HIPPI is not set
4128 +# CONFIG_PLIP is not set
4129 +# CONFIG_PPP is not set
4130 +# CONFIG_SLIP is not set
4133 +# Wireless LAN (non-hamradio)
4135 +# CONFIG_NET_RADIO is not set
4138 +# Token Ring devices
4140 +# CONFIG_TR is not set
4141 +# CONFIG_NET_FC is not set
4142 +# CONFIG_RCPCI is not set
4143 +# CONFIG_SHAPER is not set
4148 +# CONFIG_WAN is not set
4151 +# PCMCIA network device support
4153 +CONFIG_NET_PCMCIA=y
4154 +# CONFIG_PCMCIA_3C589 is not set
4155 +# CONFIG_PCMCIA_3C574 is not set
4156 +# CONFIG_PCMCIA_FMVJ18X is not set
4157 +CONFIG_PCMCIA_PCNET=y
4158 +# CONFIG_PCMCIA_AXNET is not set
4159 +# CONFIG_PCMCIA_NMCLAN is not set
4160 +# CONFIG_PCMCIA_SMC91C92 is not set
4161 +# CONFIG_PCMCIA_XIRC2PS is not set
4162 +# CONFIG_ARCNET_COM20020_CS is not set
4163 +# CONFIG_PCMCIA_IBMTR is not set
4164 +# CONFIG_NET_PCMCIA_RADIO is not set
4167 +# Amateur Radio support
4169 +# CONFIG_HAMRADIO is not set
4172 +# IrDA (infrared) support
4174 +# CONFIG_IRDA is not set
4177 +# ATA/ATAPI/MFM/RLL support
4182 +# IDE, ATA and ATAPI Block devices
4184 +CONFIG_BLK_DEV_IDE=y
4187 +# Please see Documentation/ide.txt for help/info on IDE drives
4189 +# CONFIG_BLK_DEV_HD_IDE is not set
4190 +# CONFIG_BLK_DEV_HD is not set
4191 +CONFIG_BLK_DEV_IDEDISK=y
4192 +# CONFIG_IDEDISK_MULTI_MODE is not set
4193 +# CONFIG_IDEDISK_STROKE is not set
4194 +CONFIG_BLK_DEV_IDECS=y
4195 +# CONFIG_BLK_DEV_IDECD is not set
4196 +# CONFIG_BLK_DEV_IDETAPE is not set
4197 +# CONFIG_BLK_DEV_IDEFLOPPY is not set
4198 +# CONFIG_BLK_DEV_IDESCSI is not set
4199 +# CONFIG_IDE_TASK_IOCTL is not set
4202 +# IDE chipset support/bugfixes
4204 +# CONFIG_BLK_DEV_CMD640 is not set
4205 +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
4206 +# CONFIG_BLK_DEV_ISAPNP is not set
4207 +# CONFIG_IDE_CHIPSETS is not set
4208 +# CONFIG_IDEDMA_AUTO is not set
4209 +# CONFIG_DMA_NONPCI is not set
4210 +CONFIG_BLK_DEV_IDE_MODES=y
4211 +# CONFIG_BLK_DEV_ATARAID is not set
4212 +# CONFIG_BLK_DEV_ATARAID_PDC is not set
4213 +# CONFIG_BLK_DEV_ATARAID_HPT is not set
4214 +# CONFIG_BLK_DEV_ATARAID_SII is not set
4219 +# CONFIG_SCSI is not set
4222 +# I2O device support
4224 +# CONFIG_I2O is not set
4225 +# CONFIG_I2O_BLOCK is not set
4226 +# CONFIG_I2O_LAN is not set
4227 +# CONFIG_I2O_SCSI is not set
4228 +# CONFIG_I2O_PROC is not set
4233 +# CONFIG_ISDN is not set
4236 +# Input core support
4239 +# CONFIG_INPUT_KEYBDEV is not set
4240 +# CONFIG_INPUT_MOUSEDEV is not set
4241 +# CONFIG_INPUT_JOYDEV is not set
4242 +CONFIG_INPUT_EVDEV=y
4243 +# CONFIG_INPUT_MX1TS is not set
4246 +# Character devices
4249 +# CONFIG_VT_CONSOLE is not set
4251 +CONFIG_SERIAL_CONSOLE=y
4252 +# CONFIG_SERIAL_EXTENDED is not set
4253 +# CONFIG_SERIAL_NONSTANDARD is not set
4258 +# CONFIG_SERIAL_ANAKIN is not set
4259 +# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
4260 +# CONFIG_SERIAL_AMBA is not set
4261 +# CONFIG_SERIAL_AMBA_CONSOLE is not set
4262 +# CONFIG_SERIAL_CLPS711X is not set
4263 +# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
4264 +# CONFIG_SERIAL_21285 is not set
4265 +# CONFIG_SERIAL_21285_OLD is not set
4266 +# CONFIG_SERIAL_21285_CONSOLE is not set
4267 +# CONFIG_SERIAL_UART00 is not set
4268 +# CONFIG_SERIAL_UART00_CONSOLE is not set
4269 +# CONFIG_SERIAL_SA1100 is not set
4270 +# CONFIG_SERIAL_SA1100_CONSOLE is not set
4271 +# CONFIG_SERIAL_OMAHA is not set
4272 +# CONFIG_SERIAL_OMAHA_CONSOLE is not set
4273 +# CONFIG_SERIAL_AT91 is not set
4274 +# CONFIG_SERIAL_AT91_CONSOLE is not set
4275 +# CONFIG_SERIAL_8250 is not set
4276 +# CONFIG_SERIAL_8250_CONSOLE is not set
4277 +# CONFIG_SERIAL_8250_EXTENDED is not set
4278 +# CONFIG_SERIAL_8250_MANY_PORTS is not set
4279 +# CONFIG_SERIAL_8250_SHARE_IRQ is not set
4280 +# CONFIG_SERIAL_8250_DETECT_IRQ is not set
4281 +# CONFIG_SERIAL_8250_MULTIPORT is not set
4282 +# CONFIG_SERIAL_8250_HUB6 is not set
4283 +CONFIG_UNIX98_PTYS=y
4284 +CONFIG_UNIX98_PTY_COUNT=256
4289 +# CONFIG_I2C is not set
4292 +# L3 serial bus support
4294 +# CONFIG_L3 is not set
4295 +# CONFIG_L3_ALGOBIT is not set
4296 +# CONFIG_L3_BIT_SA1100_GPIO is not set
4299 +# Other L3 adapters
4301 +# CONFIG_L3_SA1111 is not set
4302 +# CONFIG_BIT_SA1100_GPIO is not set
4308 +# CONFIG_ATIXL_BUSMOUSE is not set
4309 +# CONFIG_LOGIBUSMOUSE is not set
4310 +# CONFIG_MS_BUSMOUSE is not set
4313 +# CONFIG_82C710_MOUSE is not set
4314 +# CONFIG_PC110_PAD is not set
4315 +# CONFIG_MK712_MOUSE is not set
4320 +# CONFIG_INPUT_GAMEPORT is not set
4321 +# CONFIG_INPUT_NS558 is not set
4322 +# CONFIG_INPUT_LIGHTNING is not set
4323 +# CONFIG_INPUT_PCIGAME is not set
4324 +# CONFIG_INPUT_CS461X is not set
4325 +# CONFIG_INPUT_EMU10K1 is not set
4326 +# CONFIG_INPUT_SERIO is not set
4327 +# CONFIG_INPUT_SERPORT is not set
4332 +# CONFIG_INPUT_ANALOG is not set
4333 +# CONFIG_INPUT_A3D is not set
4334 +# CONFIG_INPUT_ADI is not set
4335 +# CONFIG_INPUT_COBRA is not set
4336 +# CONFIG_INPUT_GF2K is not set
4337 +# CONFIG_INPUT_GRIP is not set
4338 +# CONFIG_INPUT_INTERACT is not set
4339 +# CONFIG_INPUT_TMDC is not set
4340 +# CONFIG_INPUT_SIDEWINDER is not set
4341 +# CONFIG_INPUT_IFORCE_USB is not set
4342 +# CONFIG_INPUT_IFORCE_232 is not set
4343 +# CONFIG_INPUT_WARRIOR is not set
4344 +# CONFIG_INPUT_MAGELLAN is not set
4345 +# CONFIG_INPUT_SPACEORB is not set
4346 +# CONFIG_INPUT_SPACEBALL is not set
4347 +# CONFIG_INPUT_STINGER is not set
4348 +# CONFIG_INPUT_DB9 is not set
4349 +# CONFIG_INPUT_GAMECON is not set
4350 +# CONFIG_INPUT_TURBOGRAFX is not set
4351 +# CONFIG_QIC02_TAPE is not set
4352 +# CONFIG_IPMI_HANDLER is not set
4353 +# CONFIG_IPMI_PANIC_EVENT is not set
4354 +# CONFIG_IPMI_DEVICE_INTERFACE is not set
4355 +# CONFIG_IPMI_KCS is not set
4356 +# CONFIG_IPMI_WATCHDOG is not set
4361 +# CONFIG_WATCHDOG is not set
4362 +# CONFIG_SCx200_GPIO is not set
4363 +# CONFIG_AMD_PM768 is not set
4364 +# CONFIG_NVRAM is not set
4365 +# CONFIG_RTC is not set
4367 +# CONFIG_DTLK is not set
4368 +# CONFIG_R3964 is not set
4369 +# CONFIG_APPLICOM is not set
4372 +# Ftape, the floppy tape device driver
4374 +# CONFIG_FTAPE is not set
4375 +# CONFIG_AGP is not set
4376 +# CONFIG_DRM is not set
4379 +# PCMCIA character devices
4381 +# CONFIG_PCMCIA_SERIAL_CS is not set
4382 +# CONFIG_SYNCLINK_CS is not set
4385 +# Multimedia devices
4387 +# CONFIG_VIDEO_DEV is not set
4392 +# CONFIG_QUOTA is not set
4393 +# CONFIG_AUTOFS_FS is not set
4394 +# CONFIG_AUTOFS4_FS is not set
4395 +# CONFIG_REISERFS_FS is not set
4396 +# CONFIG_REISERFS_CHECK is not set
4397 +# CONFIG_REISERFS_PROC_INFO is not set
4398 +# CONFIG_ADFS_FS is not set
4399 +# CONFIG_ADFS_FS_RW is not set
4400 +# CONFIG_AFFS_FS is not set
4401 +# CONFIG_HFS_FS is not set
4402 +# CONFIG_BEFS_FS is not set
4403 +# CONFIG_BEFS_DEBUG is not set
4404 +# CONFIG_BFS_FS is not set
4405 +# CONFIG_EXT3_FS is not set
4406 +# CONFIG_JBD is not set
4407 +# CONFIG_JBD_DEBUG is not set
4410 +# CONFIG_UMSDOS_FS is not set
4411 +# CONFIG_VFAT_FS is not set
4412 +# CONFIG_EFS_FS is not set
4413 +# CONFIG_JFFS_FS is not set
4415 +CONFIG_JFFS2_FS_DEBUG=0
4416 +# CONFIG_CRAMFS is not set
4417 +# CONFIG_CRAMFS_LINEAR is not set
4418 +# CONFIG_CRAMFS_LINEAR_XIP is not set
4419 +# CONFIG_ROOT_CRAMFS_LINEAR is not set
4420 +# CONFIG_TMPFS is not set
4422 +# CONFIG_ISO9660_FS is not set
4423 +# CONFIG_JOLIET is not set
4424 +# CONFIG_ZISOFS is not set
4425 +# CONFIG_JFS_FS is not set
4426 +# CONFIG_JFS_DEBUG is not set
4427 +# CONFIG_JFS_STATISTICS is not set
4428 +# CONFIG_MINIX_FS is not set
4429 +# CONFIG_VXFS_FS is not set
4430 +# CONFIG_NTFS_FS is not set
4431 +# CONFIG_NTFS_RW is not set
4432 +# CONFIG_HPFS_FS is not set
4435 +CONFIG_DEVFS_MOUNT=y
4436 +# CONFIG_DEVFS_DEBUG is not set
4438 +# CONFIG_QNX4FS_FS is not set
4439 +# CONFIG_QNX4FS_RW is not set
4440 +# CONFIG_ROMFS_FS is not set
4442 +# CONFIG_SYSV_FS is not set
4443 +# CONFIG_UDF_FS is not set
4444 +# CONFIG_UDF_RW is not set
4445 +# CONFIG_UFS_FS is not set
4446 +# CONFIG_UFS_FS_WRITE is not set
4449 +# Network File Systems
4451 +# CONFIG_CODA_FS is not set
4452 +# CONFIG_INTERMEZZO_FS is not set
4454 +# CONFIG_NFS_V3 is not set
4456 +# CONFIG_NFSD is not set
4457 +# CONFIG_NFSD_V3 is not set
4458 +# CONFIG_NFSD_TCP is not set
4461 +# CONFIG_SMB_FS is not set
4462 +# CONFIG_NCP_FS is not set
4463 +# CONFIG_NCPFS_PACKET_SIGNING is not set
4464 +# CONFIG_NCPFS_IOCTL_LOCKING is not set
4465 +# CONFIG_NCPFS_STRONG is not set
4466 +# CONFIG_NCPFS_NFS_NS is not set
4467 +# CONFIG_NCPFS_OS2_NS is not set
4468 +# CONFIG_NCPFS_SMALLDOS is not set
4469 +# CONFIG_NCPFS_NLS is not set
4470 +# CONFIG_NCPFS_EXTRAS is not set
4471 +# CONFIG_ZISOFS_FS is not set
4476 +# CONFIG_PARTITION_ADVANCED is not set
4477 +CONFIG_MSDOS_PARTITION=y
4478 +# CONFIG_SMB_NLS is not set
4482 +# Native Language Support
4484 +CONFIG_NLS_DEFAULT="iso8859-1"
4485 +# CONFIG_NLS_CODEPAGE_437 is not set
4486 +# CONFIG_NLS_CODEPAGE_737 is not set
4487 +# CONFIG_NLS_CODEPAGE_775 is not set
4488 +# CONFIG_NLS_CODEPAGE_850 is not set
4489 +# CONFIG_NLS_CODEPAGE_852 is not set
4490 +# CONFIG_NLS_CODEPAGE_855 is not set
4491 +# CONFIG_NLS_CODEPAGE_857 is not set
4492 +# CONFIG_NLS_CODEPAGE_860 is not set
4493 +# CONFIG_NLS_CODEPAGE_861 is not set
4494 +# CONFIG_NLS_CODEPAGE_862 is not set
4495 +# CONFIG_NLS_CODEPAGE_863 is not set
4496 +# CONFIG_NLS_CODEPAGE_864 is not set
4497 +# CONFIG_NLS_CODEPAGE_865 is not set
4498 +# CONFIG_NLS_CODEPAGE_866 is not set
4499 +# CONFIG_NLS_CODEPAGE_869 is not set
4500 +# CONFIG_NLS_CODEPAGE_936 is not set
4501 +# CONFIG_NLS_CODEPAGE_950 is not set
4502 +# CONFIG_NLS_CODEPAGE_932 is not set
4503 +# CONFIG_NLS_CODEPAGE_949 is not set
4504 +# CONFIG_NLS_CODEPAGE_874 is not set
4505 +# CONFIG_NLS_ISO8859_8 is not set
4506 +# CONFIG_NLS_CODEPAGE_1250 is not set
4507 +# CONFIG_NLS_CODEPAGE_1251 is not set
4508 +CONFIG_NLS_ISO8859_1=y
4509 +# CONFIG_NLS_ISO8859_2 is not set
4510 +# CONFIG_NLS_ISO8859_3 is not set
4511 +# CONFIG_NLS_ISO8859_4 is not set
4512 +# CONFIG_NLS_ISO8859_5 is not set
4513 +# CONFIG_NLS_ISO8859_6 is not set
4514 +# CONFIG_NLS_ISO8859_7 is not set
4515 +# CONFIG_NLS_ISO8859_9 is not set
4516 +# CONFIG_NLS_ISO8859_13 is not set
4517 +# CONFIG_NLS_ISO8859_14 is not set
4518 +# CONFIG_NLS_ISO8859_15 is not set
4519 +# CONFIG_NLS_KOI8_R is not set
4520 +# CONFIG_NLS_KOI8_U is not set
4521 +# CONFIG_NLS_UTF8 is not set
4527 +# CONFIG_VGA_CONSOLE is not set
4530 +# Frame-buffer support
4533 +CONFIG_DUMMY_CONSOLE=y
4534 +# CONFIG_FB_ACORN is not set
4535 +# CONFIG_FB_ANAKIN is not set
4536 +# CONFIG_FB_CLPS711X is not set
4537 +# CONFIG_FB_SA1100 is not set
4538 +# CONFIG_FB_DBMX1 is not set
4540 +# CONFIG_FB_PXA_8BPP is not set
4541 +CONFIG_FB_PXA_16BPP=y
4542 +# CONFIG_FB_PXA_QVGA is not set
4543 +# CONFIG_FB_CYBER2000 is not set
4544 +# CONFIG_FB_VIRTUAL is not set
4545 +# CONFIG_FBCON_ADVANCED is not set
4546 +CONFIG_FBCON_CFB2=y
4547 +CONFIG_FBCON_CFB4=y
4548 +CONFIG_FBCON_CFB8=y
4549 +CONFIG_FBCON_CFB16=y
4550 +CONFIG_FBCON_FONTWIDTH8_ONLY=y
4551 +# CONFIG_FBCON_FONTS is not set
4559 +# CONFIG_SOUND_ALI5455 is not set
4560 +# CONFIG_SOUND_BT878 is not set
4561 +# CONFIG_SOUND_CMPCI is not set
4562 +# CONFIG_SOUND_EMU10K1 is not set
4563 +# CONFIG_MIDI_EMU10K1 is not set
4564 +# CONFIG_SOUND_FUSION is not set
4565 +# CONFIG_SOUND_CS4281 is not set
4566 +# CONFIG_SOUND_ES1370 is not set
4567 +# CONFIG_SOUND_ES1371 is not set
4568 +# CONFIG_SOUND_ESSSOLO1 is not set
4569 +# CONFIG_SOUND_MAESTRO is not set
4570 +# CONFIG_SOUND_MAESTRO3 is not set
4571 +# CONFIG_SOUND_FORTE is not set
4572 +# CONFIG_SOUND_ICH is not set
4573 +# CONFIG_SOUND_RME96XX is not set
4574 +# CONFIG_SOUND_SONICVIBES is not set
4575 +# CONFIG_SOUND_TRIDENT is not set
4576 +# CONFIG_SOUND_MSNDCLAS is not set
4577 +# CONFIG_SOUND_MSNDPIN is not set
4578 +# CONFIG_SOUND_VIA82CXXX is not set
4579 +# CONFIG_MIDI_VIA82CXXX is not set
4580 +# CONFIG_SOUND_OSS is not set
4581 +# CONFIG_SOUND_VIDC is not set
4582 +# CONFIG_SOUND_WAVEARTIST is not set
4583 +CONFIG_SOUND_PXA_AC97=y
4584 +# CONFIG_SOUND_TVMIXER is not set
4587 +# Multimedia Capabilities Port drivers
4589 +# CONFIG_MCP is not set
4590 +# CONFIG_MCP_SA1100 is not set
4591 +# CONFIG_MCP_UCB1200 is not set
4592 +# CONFIG_MCP_UCB1200_AUDIO is not set
4593 +# CONFIG_MCP_UCB1200_TS is not set
4594 +CONFIG_MCP_UCB1400_TS=y
4599 +# CONFIG_USB is not set
4602 +# Bluetooth support
4604 +# CONFIG_BLUEZ is not set
4609 +CONFIG_FRAME_POINTER=y
4610 +CONFIG_DEBUG_USER=y
4611 +CONFIG_DEBUG_INFO=y
4612 +# CONFIG_NO_PGT_CACHE is not set
4613 +CONFIG_DEBUG_KERNEL=y
4614 +# CONFIG_DEBUG_SLAB is not set
4615 +CONFIG_MAGIC_SYSRQ=y
4616 +# CONFIG_DEBUG_SPINLOCK is not set
4617 +# CONFIG_DEBUG_WAITQ is not set
4618 +CONFIG_DEBUG_BUGVERBOSE=y
4619 +CONFIG_DEBUG_ERRORS=y
4621 +# CONFIG_DEBUG_DC21285_PORT is not set
4622 +# CONFIG_DEBUG_CLPS711X_UART2 is not set
4627 +CONFIG_ZLIB_INFLATE=y
4628 +CONFIG_ZLIB_DEFLATE=y
4630 +++ linux-2.4.27/arch/arm/def-configs/pxa_idp
4633 +# Automatically generated by make menuconfig: don't edit
4636 +# CONFIG_EISA is not set
4637 +# CONFIG_SBUS is not set
4638 +# CONFIG_MCA is not set
4640 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
4641 +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
4642 +# CONFIG_GENERIC_BUST_SPINLOCK is not set
4643 +# CONFIG_GENERIC_ISA_DMA is not set
4646 +# Code maturity level options
4648 +CONFIG_EXPERIMENTAL=y
4649 +# CONFIG_OBSOLETE is not set
4652 +# Loadable module support
4655 +# CONFIG_MODVERSIONS is not set
4661 +# CONFIG_ARCH_ANAKIN is not set
4662 +# CONFIG_ARCH_ARCA5K is not set
4663 +# CONFIG_ARCH_CLPS7500 is not set
4664 +# CONFIG_ARCH_CLPS711X is not set
4665 +# CONFIG_ARCH_CO285 is not set
4667 +# CONFIG_ARCH_EBSA110 is not set
4668 +# CONFIG_ARCH_CAMELOT is not set
4669 +# CONFIG_ARCH_FOOTBRIDGE is not set
4670 +# CONFIG_ARCH_INTEGRATOR is not set
4671 +# CONFIG_ARCH_OMAHA is not set
4672 +# CONFIG_ARCH_L7200 is not set
4673 +# CONFIG_ARCH_MX1ADS is not set
4674 +# CONFIG_ARCH_RPC is not set
4675 +# CONFIG_ARCH_RISCSTATION is not set
4676 +# CONFIG_ARCH_SA1100 is not set
4677 +# CONFIG_ARCH_SHARK is not set
4680 +# Archimedes/A5000 Implementations
4682 +# CONFIG_ARCH_ARC is not set
4683 +# CONFIG_ARCH_A5K is not set
4686 +# Footbridge Implementations
4688 +# CONFIG_ARCH_CATS is not set
4689 +# CONFIG_ARCH_PERSONAL_SERVER is not set
4690 +# CONFIG_ARCH_EBSA285_ADDIN is not set
4691 +# CONFIG_ARCH_EBSA285_HOST is not set
4692 +# CONFIG_ARCH_NETWINDER is not set
4695 +# SA11x0 Implementations
4697 +# CONFIG_SA1100_ACCELENT is not set
4698 +# CONFIG_SA1100_ASSABET is not set
4699 +# CONFIG_ASSABET_NEPONSET is not set
4700 +# CONFIG_SA1100_ADSBITSY is not set
4701 +# CONFIG_SA1100_BRUTUS is not set
4702 +# CONFIG_SA1100_CEP is not set
4703 +# CONFIG_SA1100_CERF is not set
4704 +# CONFIG_SA1100_H3100 is not set
4705 +# CONFIG_SA1100_H3600 is not set
4706 +# CONFIG_SA1100_H3800 is not set
4707 +# CONFIG_SA1100_H3XXX is not set
4708 +# CONFIG_SA1100_EXTENEX1 is not set
4709 +# CONFIG_SA1100_FLEXANET is not set
4710 +# CONFIG_SA1100_FREEBIRD is not set
4711 +# CONFIG_SA1100_FRODO is not set
4712 +# CONFIG_SA1100_GRAPHICSCLIENT is not set
4713 +# CONFIG_SA1100_GRAPHICSMASTER is not set
4714 +# CONFIG_SA1100_BADGE4 is not set
4715 +# CONFIG_SA1100_JORNADA720 is not set
4716 +# CONFIG_SA1100_HUW_WEBPANEL is not set
4717 +# CONFIG_SA1100_ITSY is not set
4718 +# CONFIG_SA1100_LART is not set
4719 +# CONFIG_SA1100_NANOENGINE is not set
4720 +# CONFIG_SA1100_OMNIMETER is not set
4721 +# CONFIG_SA1100_PANGOLIN is not set
4722 +# CONFIG_SA1100_PLEB is not set
4723 +# CONFIG_SA1100_PT_SYSTEM3 is not set
4724 +# CONFIG_SA1100_SHANNON is not set
4725 +# CONFIG_SA1100_SHERMAN is not set
4726 +# CONFIG_SA1100_SIMPAD is not set
4727 +# CONFIG_SA1100_SIMPUTER is not set
4728 +# CONFIG_SA1100_PFS168 is not set
4729 +# CONFIG_SA1100_VICTOR is not set
4730 +# CONFIG_SA1100_XP860 is not set
4731 +# CONFIG_SA1100_YOPY is not set
4732 +# CONFIG_SA1100_USB is not set
4733 +# CONFIG_SA1100_USB_NETLINK is not set
4734 +# CONFIG_SA1100_USB_CHAR is not set
4735 +# CONFIG_H3600_SLEEVE is not set
4738 +# Intel PXA250/210 Implementations
4740 +# CONFIG_ARCH_LUBBOCK is not set
4741 +CONFIG_ARCH_PXA_IDP=y
4742 +# CONFIG_ARCH_PXA_CERF is not set
4744 +CONFIG_PXA_USB_NETLINK=m
4745 +CONFIG_PXA_USB_CHAR=m
4748 +# CLPS711X/EP721X Implementations
4750 +# CONFIG_ARCH_AUTCPU12 is not set
4751 +# CONFIG_ARCH_CDB89712 is not set
4752 +# CONFIG_ARCH_CLEP7312 is not set
4753 +# CONFIG_ARCH_EDB7211 is not set
4754 +# CONFIG_ARCH_P720T is not set
4755 +# CONFIG_ARCH_FORTUNET is not set
4756 +# CONFIG_ARCH_EP7211 is not set
4757 +# CONFIG_ARCH_EP7212 is not set
4758 +# CONFIG_ARCH_ACORN is not set
4759 +# CONFIG_FOOTBRIDGE is not set
4760 +# CONFIG_FOOTBRIDGE_HOST is not set
4761 +# CONFIG_FOOTBRIDGE_ADDIN is not set
4763 +# CONFIG_CPU_26 is not set
4764 +# CONFIG_CPU_ARM610 is not set
4765 +# CONFIG_CPU_ARM710 is not set
4766 +# CONFIG_CPU_ARM720T is not set
4767 +# CONFIG_CPU_ARM920T is not set
4768 +# CONFIG_CPU_ARM922T is not set
4769 +# CONFIG_PLD is not set
4770 +# CONFIG_CPU_ARM926T is not set
4771 +# CONFIG_CPU_ARM1020 is not set
4772 +# CONFIG_CPU_ARM1026 is not set
4773 +# CONFIG_CPU_SA110 is not set
4774 +# CONFIG_CPU_SA1100 is not set
4776 +CONFIG_CPU_XSCALE=y
4777 +# CONFIG_XSCALE_CACHE_ERRATA is not set
4778 +# CONFIG_CPU_32v3 is not set
4779 +# CONFIG_CPU_32v4 is not set
4780 +# CONFIG_DISCONTIGMEM is not set
4785 +# CONFIG_PCI is not set
4786 +# CONFIG_ISA is not set
4787 +# CONFIG_ISA_DMA is not set
4788 +# CONFIG_ZBOOT_ROM is not set
4789 +CONFIG_ZBOOT_ROM_TEXT=0
4790 +CONFIG_ZBOOT_ROM_BSS=0
4794 +# PCMCIA/CardBus support
4797 +# CONFIG_I82092 is not set
4798 +# CONFIG_I82365 is not set
4799 +# CONFIG_TCIC is not set
4800 +# CONFIG_PCMCIA_CLPS6700 is not set
4801 +# CONFIG_PCMCIA_SA1100 is not set
4802 +CONFIG_PCMCIA_PXA=y
4805 +# CONFIG_BSD_PROCESS_ACCT is not set
4808 +# CONFIG_FPE_FASTFPE is not set
4810 +# CONFIG_KCORE_AOUT is not set
4811 +# CONFIG_BINFMT_AOUT is not set
4812 +CONFIG_BINFMT_ELF=y
4813 +# CONFIG_BINFMT_MISC is not set
4815 +# CONFIG_ARTHUR is not set
4816 +CONFIG_CMDLINE="root=/dev/mtdblock2 init=/linuxrc console=ttyS0,115200"
4818 +CONFIG_LEDS_TIMER=y
4820 +CONFIG_ALIGNMENT_TRAP=y
4823 +# Parallel port support
4825 +# CONFIG_PARPORT is not set
4828 +# Memory Technology Devices (MTD)
4831 +# CONFIG_MTD_DEBUG is not set
4832 +CONFIG_MTD_PARTITIONS=y
4833 +# CONFIG_MTD_CONCAT is not set
4834 +# CONFIG_MTD_REDBOOT_PARTS is not set
4835 +# CONFIG_MTD_CMDLINE_PARTS is not set
4836 +# CONFIG_MTD_AFS_PARTS is not set
4839 +# CONFIG_FTL is not set
4840 +# CONFIG_NFTL is not set
4843 +# RAM/ROM/Flash chip drivers
4846 +# CONFIG_MTD_JEDECPROBE is not set
4847 +CONFIG_MTD_GEN_PROBE=y
4848 +CONFIG_MTD_CFI_ADV_OPTIONS=y
4849 +CONFIG_MTD_CFI_NOSWAP=y
4850 +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
4851 +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
4852 +CONFIG_MTD_CFI_GEOMETRY=y
4853 +# CONFIG_MTD_CFI_B1 is not set
4854 +# CONFIG_MTD_CFI_B2 is not set
4855 +CONFIG_MTD_CFI_B4=y
4856 +# CONFIG_MTD_CFI_B8 is not set
4857 +# CONFIG_MTD_CFI_I1 is not set
4858 +CONFIG_MTD_CFI_I2=y
4859 +# CONFIG_MTD_CFI_I4 is not set
4860 +# CONFIG_MTD_CFI_I8 is not set
4861 +CONFIG_MTD_CFI_INTELEXT=y
4862 +# CONFIG_MTD_CFI_AMDSTD is not set
4863 +# CONFIG_MTD_RAM is not set
4864 +# CONFIG_MTD_ROM is not set
4865 +# CONFIG_MTD_ABSENT is not set
4866 +# CONFIG_MTD_OBSOLETE_CHIPS is not set
4867 +# CONFIG_MTD_AMDSTD is not set
4868 +# CONFIG_MTD_SHARP is not set
4869 +# CONFIG_MTD_JEDEC is not set
4872 +# Mapping drivers for chip access
4874 +# CONFIG_MTD_PHYSMAP is not set
4875 +CONFIG_MTD_LUBBOCK=y
4876 +# CONFIG_MTD_NORA is not set
4877 +# CONFIG_MTD_ARM_INTEGRATOR is not set
4878 +# CONFIG_MTD_CDB89712 is not set
4879 +# CONFIG_MTD_SA1100 is not set
4880 +# CONFIG_MTD_DC21285 is not set
4881 +# CONFIG_MTD_IQ80310 is not set
4882 +# CONFIG_MTD_FORTUNET is not set
4883 +# CONFIG_MTD_PXA_CERF is not set
4884 +# CONFIG_MTD_EPXA10DB is not set
4885 +# CONFIG_MTD_AUTCPU12 is not set
4886 +# CONFIG_MTD_EDB7312 is not set
4887 +# CONFIG_MTD_IMPA7 is not set
4888 +CONFIG_ASI_MTD0_SIZE=40000
4889 +CONFIG_ASI_MTD1_SIZE=100000
4890 +CONFIG_ASI_MTD2_SIZE=1e00000
4891 +# CONFIG_MTD_PCI is not set
4894 +# Self-contained MTD device drivers
4896 +# CONFIG_MTD_PMC551 is not set
4897 +# CONFIG_MTD_SLRAM is not set
4898 +# CONFIG_MTD_MTDRAM is not set
4899 +# CONFIG_MTD_BLKMTD is not set
4900 +# CONFIG_MTD_DOC1000 is not set
4901 +# CONFIG_MTD_DOC2000 is not set
4902 +# CONFIG_MTD_DOC2001 is not set
4903 +# CONFIG_MTD_DOCPROBE is not set
4906 +# NAND Flash Device Drivers
4908 +# CONFIG_MTD_NAND is not set
4911 +# Plug and Play configuration
4913 +# CONFIG_PNP is not set
4914 +# CONFIG_ISAPNP is not set
4919 +# CONFIG_BLK_DEV_FD is not set
4920 +# CONFIG_BLK_DEV_XD is not set
4921 +# CONFIG_PARIDE is not set
4922 +# CONFIG_BLK_CPQ_DA is not set
4923 +# CONFIG_BLK_CPQ_CISS_DA is not set
4924 +# CONFIG_CISS_SCSI_TAPE is not set
4925 +# CONFIG_BLK_DEV_DAC960 is not set
4926 +# CONFIG_BLK_DEV_UMEM is not set
4927 +CONFIG_BLK_DEV_LOOP=y
4928 +# CONFIG_BLK_DEV_NBD is not set
4929 +CONFIG_BLK_DEV_RAM=y
4930 +CONFIG_BLK_DEV_RAM_SIZE=4096
4931 +CONFIG_BLK_DEV_INITRD=y
4934 +# Multi-device support (RAID and LVM)
4936 +# CONFIG_MD is not set
4937 +# CONFIG_BLK_DEV_MD is not set
4938 +# CONFIG_MD_LINEAR is not set
4939 +# CONFIG_MD_RAID0 is not set
4940 +# CONFIG_MD_RAID1 is not set
4941 +# CONFIG_MD_RAID5 is not set
4942 +# CONFIG_MD_MULTIPATH is not set
4943 +# CONFIG_BLK_DEV_LVM is not set
4946 +# Networking options
4949 +# CONFIG_PACKET_MMAP is not set
4950 +# CONFIG_NETLINK_DEV is not set
4951 +# CONFIG_NETFILTER is not set
4952 +# CONFIG_FILTER is not set
4955 +# CONFIG_IP_MULTICAST is not set
4956 +# CONFIG_IP_ADVANCED_ROUTER is not set
4957 +# CONFIG_IP_PNP is not set
4958 +# CONFIG_NET_IPIP is not set
4959 +# CONFIG_NET_IPGRE is not set
4960 +# CONFIG_ARPD is not set
4961 +# CONFIG_INET_ECN is not set
4962 +# CONFIG_SYN_COOKIES is not set
4963 +# CONFIG_IPV6 is not set
4964 +# CONFIG_KHTTPD is not set
4965 +# CONFIG_ATM is not set
4966 +# CONFIG_VLAN_8021Q is not set
4967 +# CONFIG_IPX is not set
4968 +# CONFIG_ATALK is not set
4971 +# Appletalk devices
4973 +# CONFIG_DEV_APPLETALK is not set
4974 +# CONFIG_DECNET is not set
4975 +# CONFIG_BRIDGE is not set
4976 +# CONFIG_X25 is not set
4977 +# CONFIG_LAPB is not set
4978 +# CONFIG_LLC is not set
4979 +# CONFIG_NET_DIVERT is not set
4980 +# CONFIG_ECONET is not set
4981 +# CONFIG_WAN_ROUTER is not set
4982 +# CONFIG_NET_FASTROUTE is not set
4983 +# CONFIG_NET_HW_FLOWCONTROL is not set
4986 +# QoS and/or fair queueing
4988 +# CONFIG_NET_SCHED is not set
4993 +# CONFIG_NET_PKTGEN is not set
4996 +# Network device support
4998 +CONFIG_NETDEVICES=y
5003 +# CONFIG_ARCNET is not set
5004 +# CONFIG_DUMMY is not set
5005 +# CONFIG_BONDING is not set
5006 +# CONFIG_EQUALIZER is not set
5007 +# CONFIG_TUN is not set
5008 +# CONFIG_ETHERTAP is not set
5011 +# Ethernet (10 or 100Mbit)
5013 +CONFIG_NET_ETHERNET=y
5014 +# CONFIG_ARM_AM79C961A is not set
5015 +# CONFIG_ARM_CIRRUS is not set
5016 +# CONFIG_SUNLANCE is not set
5017 +# CONFIG_SUNBMAC is not set
5018 +# CONFIG_SUNQE is not set
5019 +# CONFIG_SUNGEM is not set
5020 +# CONFIG_NET_VENDOR_3COM is not set
5021 +# CONFIG_LANCE is not set
5022 +CONFIG_NET_VENDOR_SMC=y
5023 +# CONFIG_WD80x3 is not set
5024 +# CONFIG_ULTRAMCA is not set
5025 +# CONFIG_ULTRA is not set
5026 +# CONFIG_ULTRA32 is not set
5027 +# CONFIG_SMC9194 is not set
5029 +# CONFIG_NET_VENDOR_RACAL is not set
5030 +# CONFIG_NET_ISA is not set
5031 +# CONFIG_NET_PCI is not set
5032 +CONFIG_NET_POCKET=y
5033 +# CONFIG_DE600 is not set
5034 +# CONFIG_DE620 is not set
5037 +# Ethernet (1000 Mbit)
5039 +# CONFIG_ACENIC is not set
5040 +# CONFIG_DL2K is not set
5041 +# CONFIG_MYRI_SBUS is not set
5042 +# CONFIG_NS83820 is not set
5043 +# CONFIG_HAMACHI is not set
5044 +# CONFIG_YELLOWFIN is not set
5045 +# CONFIG_SK98LIN is not set
5046 +# CONFIG_TIGON3 is not set
5047 +# CONFIG_FDDI is not set
5048 +# CONFIG_HIPPI is not set
5049 +# CONFIG_PLIP is not set
5050 +# CONFIG_PPP is not set
5051 +# CONFIG_SLIP is not set
5054 +# Wireless LAN (non-hamradio)
5057 +# CONFIG_STRIP is not set
5059 +# CONFIG_ARLAN is not set
5060 +CONFIG_AIRONET4500=y
5061 +# CONFIG_AIRONET4500_NONCS is not set
5062 +# CONFIG_AIRONET4500_PROC is not set
5064 +CONFIG_PCMCIA_HERMES=m
5066 +CONFIG_NET_WIRELESS=y
5069 +# Token Ring devices
5071 +# CONFIG_TR is not set
5072 +# CONFIG_NET_FC is not set
5073 +# CONFIG_RCPCI is not set
5074 +# CONFIG_SHAPER is not set
5079 +# CONFIG_WAN is not set
5082 +# PCMCIA network device support
5084 +CONFIG_NET_PCMCIA=y
5085 +# CONFIG_PCMCIA_3C589 is not set
5086 +# CONFIG_PCMCIA_3C574 is not set
5087 +# CONFIG_PCMCIA_FMVJ18X is not set
5088 +CONFIG_PCMCIA_PCNET=m
5089 +# CONFIG_PCMCIA_AXNET is not set
5090 +CONFIG_PCMCIA_NMCLAN=m
5091 +CONFIG_PCMCIA_SMC91C92=m
5092 +CONFIG_PCMCIA_XIRC2PS=m
5093 +# CONFIG_ARCNET_COM20020_CS is not set
5094 +# CONFIG_PCMCIA_IBMTR is not set
5095 +CONFIG_NET_PCMCIA_RADIO=y
5096 +CONFIG_PCMCIA_RAYCS=m
5097 +CONFIG_PCMCIA_NETWAVE=m
5098 +CONFIG_PCMCIA_WAVELAN=m
5099 +CONFIG_AIRONET4500_CS=m
5102 +# Amateur Radio support
5104 +# CONFIG_HAMRADIO is not set
5107 +# IrDA (infrared) support
5111 +# CONFIG_IRNET is not set
5113 +CONFIG_IRDA_ULTRA=y
5114 +# CONFIG_IRDA_CACHE_LAST_LSAP is not set
5115 +# CONFIG_IRDA_FAST_RR is not set
5116 +CONFIG_IRDA_DEBUG=y
5119 +# Infrared-port device drivers
5122 +# CONFIG_IRPORT_SIR is not set
5123 +# CONFIG_DONGLE is not set
5124 +# CONFIG_USB_IRDA is not set
5125 +# CONFIG_NSC_FIR is not set
5126 +# CONFIG_WINBOND_FIR is not set
5127 +# CONFIG_TOSHIBA_FIR is not set
5128 +# CONFIG_SMC_IRCC_FIR is not set
5129 +# CONFIG_ALI_FIR is not set
5130 +# CONFIG_VLSI_FIR is not set
5134 +# ATA/ATAPI/MFM/RLL support
5139 +# IDE, ATA and ATAPI Block devices
5141 +CONFIG_BLK_DEV_IDE=y
5142 +# CONFIG_BLK_DEV_HD_IDE is not set
5143 +# CONFIG_BLK_DEV_HD is not set
5144 +CONFIG_BLK_DEV_IDEDISK=y
5145 +# CONFIG_IDEDISK_MULTI_MODE is not set
5146 +# CONFIG_IDEDISK_STROKE is not set
5147 +# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
5148 +# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
5149 +# CONFIG_BLK_DEV_IDEDISK_IBM is not set
5150 +# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
5151 +# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
5152 +# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
5153 +# CONFIG_BLK_DEV_IDEDISK_WD is not set
5154 +# CONFIG_BLK_DEV_COMMERIAL is not set
5155 +# CONFIG_BLK_DEV_TIVO is not set
5156 +CONFIG_BLK_DEV_IDECS=m
5157 +# CONFIG_BLK_DEV_IDECD is not set
5158 +# CONFIG_BLK_DEV_IDETAPE is not set
5159 +# CONFIG_BLK_DEV_IDEFLOPPY is not set
5160 +# CONFIG_BLK_DEV_IDESCSI is not set
5161 +# CONFIG_IDE_TASK_IOCTL is not set
5162 +# CONFIG_BLK_DEV_CMD640 is not set
5163 +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
5164 +# CONFIG_BLK_DEV_ISAPNP is not set
5165 +# CONFIG_IDE_CHIPSETS is not set
5166 +# CONFIG_IDEDMA_AUTO is not set
5167 +# CONFIG_DMA_NONPCI is not set
5168 +# CONFIG_BLK_DEV_IDE_MODES is not set
5169 +# CONFIG_BLK_DEV_ATARAID is not set
5170 +# CONFIG_BLK_DEV_ATARAID_PDC is not set
5171 +# CONFIG_BLK_DEV_ATARAID_HPT is not set
5176 +# CONFIG_SCSI is not set
5179 +# I2O device support
5181 +# CONFIG_I2O is not set
5182 +# CONFIG_I2O_BLOCK is not set
5183 +# CONFIG_I2O_LAN is not set
5184 +# CONFIG_I2O_SCSI is not set
5185 +# CONFIG_I2O_PROC is not set
5190 +# CONFIG_ISDN is not set
5193 +# Input core support
5196 +CONFIG_INPUT_KEYBDEV=m
5197 +CONFIG_INPUT_MOUSEDEV=m
5198 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
5199 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
5200 +# CONFIG_INPUT_JOYDEV is not set
5201 +CONFIG_INPUT_EVDEV=y
5204 +# Character devices
5207 +# CONFIG_VT_CONSOLE is not set
5209 +CONFIG_SERIAL_CONSOLE=y
5210 +# CONFIG_SERIAL_EXTENDED is not set
5211 +# CONFIG_SERIAL_NONSTANDARD is not set
5216 +# CONFIG_SERIAL_ANAKIN is not set
5217 +# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
5218 +# CONFIG_SERIAL_AMBA is not set
5219 +# CONFIG_SERIAL_AMBA_CONSOLE is not set
5220 +# CONFIG_SERIAL_CLPS711X is not set
5221 +# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
5222 +# CONFIG_SERIAL_21285 is not set
5223 +# CONFIG_SERIAL_21285_OLD is not set
5224 +# CONFIG_SERIAL_21285_CONSOLE is not set
5225 +# CONFIG_SERIAL_UART00 is not set
5226 +# CONFIG_SERIAL_UART00_CONSOLE is not set
5227 +# CONFIG_SERIAL_SA1100 is not set
5228 +# CONFIG_SERIAL_SA1100_CONSOLE is not set
5229 +# CONFIG_SERIAL_OMAHA is not set
5230 +# CONFIG_SERIAL_OMAHA_CONSOLE is not set
5231 +# CONFIG_SERIAL_8250 is not set
5232 +# CONFIG_SERIAL_8250_CONSOLE is not set
5233 +# CONFIG_SERIAL_8250_EXTENDED is not set
5234 +# CONFIG_SERIAL_8250_MANY_PORTS is not set
5235 +# CONFIG_SERIAL_8250_SHARE_IRQ is not set
5236 +# CONFIG_SERIAL_8250_DETECT_IRQ is not set
5237 +# CONFIG_SERIAL_8250_MULTIPORT is not set
5238 +# CONFIG_SERIAL_8250_HUB6 is not set
5239 +# CONFIG_IDP_KEYB is not set
5240 +CONFIG_MATRIX_KEYBOARD=y
5241 +# CONFIG_SA1111_PS2_KEYB is not set
5242 +CONFIG_UNIX98_PTYS=y
5243 +CONFIG_UNIX98_PTY_COUNT=256
5248 +# CONFIG_I2C is not set
5251 +# L3 serial bus support
5253 +# CONFIG_L3 is not set
5254 +# CONFIG_L3_ALGOBIT is not set
5255 +# CONFIG_L3_BIT_SA1100_GPIO is not set
5256 +# CONFIG_L3_SA1111 is not set
5257 +# CONFIG_BIT_SA1100_GPIO is not set
5263 +# CONFIG_ATIXL_BUSMOUSE is not set
5264 +# CONFIG_LOGIBUSMOUSE is not set
5265 +# CONFIG_MS_BUSMOUSE is not set
5268 +# CONFIG_82C710_MOUSE is not set
5269 +# CONFIG_PC110_PAD is not set
5270 +# CONFIG_MK712_MOUSE is not set
5275 +# CONFIG_INPUT_GAMEPORT is not set
5276 +# CONFIG_INPUT_NS558 is not set
5277 +# CONFIG_INPUT_LIGHTNING is not set
5278 +# CONFIG_INPUT_PCIGAME is not set
5279 +# CONFIG_INPUT_CS461X is not set
5280 +# CONFIG_INPUT_EMU10K1 is not set
5281 +# CONFIG_INPUT_SERIO is not set
5282 +# CONFIG_INPUT_SERPORT is not set
5283 +# CONFIG_INPUT_ANALOG is not set
5284 +# CONFIG_INPUT_A3D is not set
5285 +# CONFIG_INPUT_ADI is not set
5286 +# CONFIG_INPUT_COBRA is not set
5287 +# CONFIG_INPUT_GF2K is not set
5288 +# CONFIG_INPUT_GRIP is not set
5289 +# CONFIG_INPUT_INTERACT is not set
5290 +# CONFIG_INPUT_TMDC is not set
5291 +# CONFIG_INPUT_SIDEWINDER is not set
5292 +# CONFIG_INPUT_IFORCE_USB is not set
5293 +# CONFIG_INPUT_IFORCE_232 is not set
5294 +# CONFIG_INPUT_WARRIOR is not set
5295 +# CONFIG_INPUT_MAGELLAN is not set
5296 +# CONFIG_INPUT_SPACEORB is not set
5297 +# CONFIG_INPUT_SPACEBALL is not set
5298 +# CONFIG_INPUT_STINGER is not set
5299 +# CONFIG_INPUT_DB9 is not set
5300 +# CONFIG_INPUT_GAMECON is not set
5301 +# CONFIG_INPUT_TURBOGRAFX is not set
5302 +# CONFIG_QIC02_TAPE is not set
5307 +# CONFIG_WATCHDOG is not set
5308 +# CONFIG_NVRAM is not set
5309 +# CONFIG_RTC is not set
5310 +# CONFIG_PXA_RTC is not set
5311 +# CONFIG_DTLK is not set
5312 +# CONFIG_R3964 is not set
5313 +# CONFIG_APPLICOM is not set
5316 +# Ftape, the floppy tape device driver
5318 +# CONFIG_FTAPE is not set
5319 +# CONFIG_AGP is not set
5320 +# CONFIG_DRM is not set
5323 +# PCMCIA character devices
5325 +CONFIG_PCMCIA_SERIAL_CS=m
5328 +# Multimedia devices
5330 +# CONFIG_VIDEO_DEV is not set
5335 +# CONFIG_QUOTA is not set
5336 +# CONFIG_AUTOFS_FS is not set
5337 +# CONFIG_AUTOFS4_FS is not set
5338 +# CONFIG_REISERFS_FS is not set
5339 +# CONFIG_REISERFS_CHECK is not set
5340 +# CONFIG_REISERFS_PROC_INFO is not set
5341 +# CONFIG_ADFS_FS is not set
5342 +# CONFIG_ADFS_FS_RW is not set
5343 +# CONFIG_AFFS_FS is not set
5344 +# CONFIG_HFS_FS is not set
5345 +# CONFIG_BFS_FS is not set
5348 +# CONFIG_JBD_DEBUG is not set
5351 +# CONFIG_UMSDOS_FS is not set
5353 +# CONFIG_EFS_FS is not set
5354 +# CONFIG_JFFS_FS is not set
5356 +CONFIG_JFFS2_FS_DEBUG=0
5358 +# CONFIG_TMPFS is not set
5360 +# CONFIG_ISO9660_FS is not set
5361 +# CONFIG_JOLIET is not set
5362 +# CONFIG_ZISOFS is not set
5363 +# CONFIG_MINIX_FS is not set
5364 +# CONFIG_VXFS_FS is not set
5365 +# CONFIG_NTFS_FS is not set
5366 +# CONFIG_NTFS_RW is not set
5367 +# CONFIG_HPFS_FS is not set
5370 +CONFIG_DEVFS_MOUNT=y
5371 +# CONFIG_DEVFS_DEBUG is not set
5373 +# CONFIG_QNX4FS_FS is not set
5374 +# CONFIG_QNX4FS_RW is not set
5375 +# CONFIG_ROMFS_FS is not set
5377 +# CONFIG_SYSV_FS is not set
5378 +# CONFIG_UDF_FS is not set
5379 +# CONFIG_UDF_RW is not set
5380 +# CONFIG_UFS_FS is not set
5381 +# CONFIG_UFS_FS_WRITE is not set
5384 +# Network File Systems
5386 +# CONFIG_CODA_FS is not set
5387 +# CONFIG_INTERMEZZO_FS is not set
5390 +# CONFIG_ROOT_NFS is not set
5391 +# CONFIG_NFSD is not set
5392 +# CONFIG_NFSD_V3 is not set
5396 +# CONFIG_SMB_FS is not set
5397 +# CONFIG_NCP_FS is not set
5398 +# CONFIG_NCPFS_PACKET_SIGNING is not set
5399 +# CONFIG_NCPFS_IOCTL_LOCKING is not set
5400 +# CONFIG_NCPFS_STRONG is not set
5401 +# CONFIG_NCPFS_NFS_NS is not set
5402 +# CONFIG_NCPFS_OS2_NS is not set
5403 +# CONFIG_NCPFS_SMALLDOS is not set
5404 +# CONFIG_NCPFS_NLS is not set
5405 +# CONFIG_NCPFS_EXTRAS is not set
5406 +# CONFIG_ZISOFS_FS is not set
5407 +CONFIG_ZLIB_FS_INFLATE=y
5412 +CONFIG_PARTITION_ADVANCED=y
5413 +# CONFIG_ACORN_PARTITION is not set
5414 +# CONFIG_OSF_PARTITION is not set
5415 +# CONFIG_AMIGA_PARTITION is not set
5416 +# CONFIG_ATARI_PARTITION is not set
5417 +# CONFIG_MAC_PARTITION is not set
5418 +CONFIG_MSDOS_PARTITION=y
5419 +# CONFIG_BSD_DISKLABEL is not set
5420 +# CONFIG_MINIX_SUBPARTITION is not set
5421 +# CONFIG_SOLARIS_X86_PARTITION is not set
5422 +# CONFIG_UNIXWARE_DISKLABEL is not set
5423 +# CONFIG_LDM_PARTITION is not set
5424 +# CONFIG_SGI_PARTITION is not set
5425 +# CONFIG_ULTRIX_PARTITION is not set
5426 +# CONFIG_SUN_PARTITION is not set
5427 +# CONFIG_SMB_NLS is not set
5431 +# Native Language Support
5433 +CONFIG_NLS_DEFAULT="iso8859-1"
5434 +CONFIG_NLS_CODEPAGE_437=m
5435 +# CONFIG_NLS_CODEPAGE_737 is not set
5436 +# CONFIG_NLS_CODEPAGE_775 is not set
5437 +# CONFIG_NLS_CODEPAGE_850 is not set
5438 +# CONFIG_NLS_CODEPAGE_852 is not set
5439 +# CONFIG_NLS_CODEPAGE_855 is not set
5440 +# CONFIG_NLS_CODEPAGE_857 is not set
5441 +# CONFIG_NLS_CODEPAGE_860 is not set
5442 +# CONFIG_NLS_CODEPAGE_861 is not set
5443 +# CONFIG_NLS_CODEPAGE_862 is not set
5444 +# CONFIG_NLS_CODEPAGE_863 is not set
5445 +# CONFIG_NLS_CODEPAGE_864 is not set
5446 +# CONFIG_NLS_CODEPAGE_865 is not set
5447 +# CONFIG_NLS_CODEPAGE_866 is not set
5448 +# CONFIG_NLS_CODEPAGE_869 is not set
5449 +# CONFIG_NLS_CODEPAGE_936 is not set
5450 +# CONFIG_NLS_CODEPAGE_950 is not set
5451 +# CONFIG_NLS_CODEPAGE_932 is not set
5452 +# CONFIG_NLS_CODEPAGE_949 is not set
5453 +# CONFIG_NLS_CODEPAGE_874 is not set
5454 +# CONFIG_NLS_ISO8859_8 is not set
5455 +# CONFIG_NLS_CODEPAGE_1250 is not set
5456 +# CONFIG_NLS_CODEPAGE_1251 is not set
5457 +CONFIG_NLS_ISO8859_1=y
5458 +# CONFIG_NLS_ISO8859_2 is not set
5459 +# CONFIG_NLS_ISO8859_3 is not set
5460 +# CONFIG_NLS_ISO8859_4 is not set
5461 +# CONFIG_NLS_ISO8859_5 is not set
5462 +# CONFIG_NLS_ISO8859_6 is not set
5463 +# CONFIG_NLS_ISO8859_7 is not set
5464 +# CONFIG_NLS_ISO8859_9 is not set
5465 +# CONFIG_NLS_ISO8859_13 is not set
5466 +# CONFIG_NLS_ISO8859_14 is not set
5467 +# CONFIG_NLS_ISO8859_15 is not set
5468 +# CONFIG_NLS_KOI8_R is not set
5469 +# CONFIG_NLS_KOI8_U is not set
5470 +# CONFIG_NLS_UTF8 is not set
5476 +# CONFIG_VGA_CONSOLE is not set
5479 +# Frame-buffer support
5482 +CONFIG_DUMMY_CONSOLE=y
5483 +# CONFIG_FB_ACORN is not set
5484 +# CONFIG_FB_ANAKIN is not set
5485 +# CONFIG_FB_CLPS711X is not set
5486 +# CONFIG_FB_SA1100 is not set
5488 +# CONFIG_FB_CYBER2000 is not set
5489 +# CONFIG_FB_VIRTUAL is not set
5490 +# CONFIG_FBCON_ADVANCED is not set
5491 +CONFIG_FBCON_CFB2=y
5492 +CONFIG_FBCON_CFB4=y
5493 +CONFIG_FBCON_CFB8=y
5494 +CONFIG_FBCON_CFB16=y
5495 +# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
5496 +# CONFIG_FBCON_FONTS is not set
5504 +# CONFIG_SOUND_BT878 is not set
5505 +# CONFIG_SOUND_CMPCI is not set
5506 +# CONFIG_SOUND_EMU10K1 is not set
5507 +# CONFIG_MIDI_EMU10K1 is not set
5508 +# CONFIG_SOUND_FUSION is not set
5509 +# CONFIG_SOUND_CS4281 is not set
5510 +# CONFIG_SOUND_ES1370 is not set
5511 +# CONFIG_SOUND_ES1371 is not set
5512 +# CONFIG_SOUND_ESSSOLO1 is not set
5513 +# CONFIG_SOUND_MAESTRO is not set
5514 +# CONFIG_SOUND_MAESTRO3 is not set
5515 +# CONFIG_SOUND_ICH is not set
5516 +# CONFIG_SOUND_RME96XX is not set
5517 +# CONFIG_SOUND_SONICVIBES is not set
5518 +# CONFIG_SOUND_TRIDENT is not set
5519 +# CONFIG_SOUND_MSNDCLAS is not set
5520 +# CONFIG_SOUND_MSNDPIN is not set
5521 +# CONFIG_SOUND_VIA82CXXX is not set
5522 +# CONFIG_MIDI_VIA82CXXX is not set
5523 +# CONFIG_SOUND_OSS is not set
5524 +# CONFIG_SOUND_WAVEARTIST is not set
5525 +CONFIG_SOUND_PXA_AC97=y
5526 +# CONFIG_SOUND_TVMIXER is not set
5529 +# Multimedia Capabilities Port drivers
5531 +# CONFIG_MCP is not set
5532 +# CONFIG_MCP_SA1100 is not set
5533 +# CONFIG_MCP_UCB1200 is not set
5534 +# CONFIG_MCP_UCB1200_AUDIO is not set
5535 +# CONFIG_MCP_UCB1200_TS is not set
5536 +CONFIG_MCP_UCB1400_TS=m
5541 +# CONFIG_USB is not set
5544 +# Bluetooth support
5546 +# CONFIG_BLUEZ is not set
5551 +CONFIG_FRAME_POINTER=y
5552 +CONFIG_DEBUG_USER=y
5553 +# CONFIG_DEBUG_INFO is not set
5554 +# CONFIG_NO_PGT_CACHE is not set
5555 +CONFIG_DEBUG_KERNEL=y
5556 +CONFIG_DEBUG_SLAB=y
5557 +# CONFIG_MAGIC_SYSRQ is not set
5558 +# CONFIG_DEBUG_SPINLOCK is not set
5559 +# CONFIG_DEBUG_WAITQ is not set
5560 +CONFIG_DEBUG_BUGVERBOSE=y
5561 +CONFIG_DEBUG_ERRORS=y
5562 +# CONFIG_DEBUG_LL is not set
5563 +# CONFIG_DEBUG_DC21285_PORT is not set
5564 +# CONFIG_DEBUG_CLPS711X_UART2 is not set
5566 +++ linux-2.4.27/arch/arm/def-configs/trizeps2
5569 +# Automatically generated by make menuconfig: don't edit
5572 +# CONFIG_EISA is not set
5573 +# CONFIG_SBUS is not set
5574 +# CONFIG_MCA is not set
5576 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
5577 +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
5578 +# CONFIG_GENERIC_BUST_SPINLOCK is not set
5579 +# CONFIG_GENERIC_ISA_DMA is not set
5582 +# Code maturity level options
5584 +CONFIG_EXPERIMENTAL=y
5585 +# CONFIG_OBSOLETE is not set
5588 +# Loadable module support
5591 +# CONFIG_MODVERSIONS is not set
5597 +# CONFIG_ARCH_ANAKIN is not set
5598 +# CONFIG_ARCH_ARCA5K is not set
5599 +# CONFIG_ARCH_CLPS7500 is not set
5600 +# CONFIG_ARCH_CLPS711X is not set
5601 +# CONFIG_ARCH_CO285 is not set
5603 +# CONFIG_ARCH_EBSA110 is not set
5604 +# CONFIG_ARCH_CAMELOT is not set
5605 +# CONFIG_ARCH_FOOTBRIDGE is not set
5606 +# CONFIG_ARCH_INTEGRATOR is not set
5607 +# CONFIG_ARCH_OMAHA is not set
5608 +# CONFIG_ARCH_L7200 is not set
5609 +# CONFIG_ARCH_MX1ADS is not set
5610 +# CONFIG_ARCH_RPC is not set
5611 +# CONFIG_ARCH_RISCSTATION is not set
5612 +# CONFIG_ARCH_SA1100 is not set
5613 +# CONFIG_ARCH_SHARK is not set
5616 +# Archimedes/A5000 Implementations
5618 +# CONFIG_ARCH_ARC is not set
5619 +# CONFIG_ARCH_A5K is not set
5622 +# Footbridge Implementations
5624 +# CONFIG_ARCH_CATS is not set
5625 +# CONFIG_ARCH_PERSONAL_SERVER is not set
5626 +# CONFIG_ARCH_EBSA285_ADDIN is not set
5627 +# CONFIG_ARCH_EBSA285_HOST is not set
5628 +# CONFIG_ARCH_NETWINDER is not set
5631 +# SA11x0 Implementations
5633 +# CONFIG_SA1100_ACCELENT is not set
5634 +# CONFIG_SA1100_ASSABET is not set
5635 +# CONFIG_ASSABET_NEPONSET is not set
5636 +# CONFIG_SA1100_ADSBITSY is not set
5637 +# CONFIG_SA1100_BRUTUS is not set
5638 +# CONFIG_SA1100_CEP is not set
5639 +# CONFIG_SA1100_CERF is not set
5640 +# CONFIG_SA1100_H3100 is not set
5641 +# CONFIG_SA1100_H3600 is not set
5642 +# CONFIG_SA1100_H3800 is not set
5643 +# CONFIG_SA1100_H3XXX is not set
5644 +# CONFIG_SA1100_EXTENEX1 is not set
5645 +# CONFIG_SA1100_FLEXANET is not set
5646 +# CONFIG_SA1100_FREEBIRD is not set
5647 +# CONFIG_SA1100_FRODO is not set
5648 +# CONFIG_SA1100_GRAPHICSCLIENT is not set
5649 +# CONFIG_SA1100_GRAPHICSMASTER is not set
5650 +# CONFIG_SA1100_BADGE4 is not set
5651 +# CONFIG_SA1100_JORNADA720 is not set
5652 +# CONFIG_SA1100_HUW_WEBPANEL is not set
5653 +# CONFIG_SA1100_ITSY is not set
5654 +# CONFIG_SA1100_LART is not set
5655 +# CONFIG_SA1100_NANOENGINE is not set
5656 +# CONFIG_SA1100_OMNIMETER is not set
5657 +# CONFIG_SA1100_PANGOLIN is not set
5658 +# CONFIG_SA1100_PLEB is not set
5659 +# CONFIG_SA1100_PT_SYSTEM3 is not set
5660 +# CONFIG_SA1100_SHANNON is not set
5661 +# CONFIG_SA1100_SHERMAN is not set
5662 +# CONFIG_SA1100_SIMPAD is not set
5663 +# CONFIG_SA1100_SIMPUTER is not set
5664 +# CONFIG_SA1100_PFS168 is not set
5665 +# CONFIG_SA1100_VICTOR is not set
5666 +# CONFIG_SA1100_XP860 is not set
5667 +# CONFIG_SA1100_YOPY is not set
5668 +# CONFIG_SA1100_USB is not set
5669 +# CONFIG_SA1100_USB_NETLINK is not set
5670 +# CONFIG_SA1100_USB_CHAR is not set
5671 +# CONFIG_H3600_SLEEVE is not set
5674 +# Intel PXA250/210 Implementations
5676 +# CONFIG_ARCH_LUBBOCK is not set
5677 +# CONFIG_ARCH_PXA_IDP is not set
5678 +# CONFIG_ARCH_PXA_CERF is not set
5679 +CONFIG_ARCH_TRIZEPS2=y
5682 +# CONFIG_PXA_USB_NETLINK is not set
5683 +# CONFIG_PXA_USB_CHAR is not set
5686 +# CLPS711X/EP721X Implementations
5688 +# CONFIG_ARCH_AUTCPU12 is not set
5689 +# CONFIG_ARCH_CDB89712 is not set
5690 +# CONFIG_ARCH_CLEP7312 is not set
5691 +# CONFIG_ARCH_EDB7211 is not set
5692 +# CONFIG_ARCH_P720T is not set
5693 +# CONFIG_ARCH_FORTUNET is not set
5694 +# CONFIG_ARCH_EP7211 is not set
5695 +# CONFIG_ARCH_EP7212 is not set
5696 +# CONFIG_ARCH_ACORN is not set
5697 +# CONFIG_FOOTBRIDGE is not set
5698 +# CONFIG_FOOTBRIDGE_HOST is not set
5699 +# CONFIG_FOOTBRIDGE_ADDIN is not set
5701 +# CONFIG_CPU_26 is not set
5702 +# CONFIG_CPU_ARM610 is not set
5703 +# CONFIG_CPU_ARM710 is not set
5704 +# CONFIG_CPU_ARM720T is not set
5705 +# CONFIG_CPU_ARM920T is not set
5706 +# CONFIG_CPU_ARM922T is not set
5707 +# CONFIG_PLD is not set
5708 +# CONFIG_CPU_ARM926T is not set
5709 +# CONFIG_CPU_ARM1020 is not set
5710 +# CONFIG_CPU_ARM1026 is not set
5711 +# CONFIG_CPU_SA110 is not set
5712 +# CONFIG_CPU_SA1100 is not set
5714 +CONFIG_CPU_XSCALE=y
5715 +# CONFIG_XSCALE_CACHE_ERRATA is not set
5716 +# CONFIG_CPU_32v3 is not set
5717 +# CONFIG_CPU_32v4 is not set
5718 +# CONFIG_DISCONTIGMEM is not set
5723 +# CONFIG_PCI is not set
5724 +# CONFIG_ISA is not set
5725 +# CONFIG_ISA_DMA is not set
5726 +# CONFIG_ZBOOT_ROM is not set
5727 +CONFIG_ZBOOT_ROM_TEXT=0
5728 +CONFIG_ZBOOT_ROM_BSS=0
5732 +# PCMCIA/CardBus support
5735 +# CONFIG_I82092 is not set
5736 +# CONFIG_I82365 is not set
5737 +# CONFIG_TCIC is not set
5738 +# CONFIG_PCMCIA_CLPS6700 is not set
5739 +# CONFIG_PCMCIA_SA1100 is not set
5740 +CONFIG_PCMCIA_PXA=y
5743 +# CONFIG_BSD_PROCESS_ACCT is not set
5746 +# CONFIG_FPE_FASTFPE is not set
5748 +# CONFIG_KCORE_AOUT is not set
5749 +# CONFIG_BINFMT_AOUT is not set
5750 +CONFIG_BINFMT_ELF=y
5751 +# CONFIG_BINFMT_MISC is not set
5752 +# CONFIG_PM is not set
5753 +# CONFIG_ARTHUR is not set
5754 +CONFIG_CMDLINE="root=/dev/mtdblock3 rw console=ttyS0,38400 mem=32M noinitrd init=/linuxrc"
5755 +CONFIG_ALIGNMENT_TRAP=y
5758 +# Parallel port support
5760 +# CONFIG_PARPORT is not set
5763 +# Memory Technology Devices (MTD)
5766 +# CONFIG_MTD_DEBUG is not set
5767 +CONFIG_MTD_PARTITIONS=y
5768 +# CONFIG_MTD_CONCAT is not set
5769 +CONFIG_MTD_REDBOOT_PARTS=y
5770 +CONFIG_MTD_CMDLINE_PARTS=y
5771 +# CONFIG_MTD_AFS_PARTS is not set
5774 +# CONFIG_FTL is not set
5775 +# CONFIG_NFTL is not set
5778 +# RAM/ROM/Flash chip drivers
5781 +# CONFIG_MTD_JEDECPROBE is not set
5782 +CONFIG_MTD_GEN_PROBE=y
5783 +# CONFIG_MTD_CFI_ADV_OPTIONS is not set
5784 +CONFIG_MTD_CFI_INTELEXT=y
5785 +# CONFIG_MTD_CFI_AMDSTD is not set
5786 +# CONFIG_MTD_RAM is not set
5787 +# CONFIG_MTD_ROM is not set
5788 +# CONFIG_MTD_ABSENT is not set
5789 +# CONFIG_MTD_OBSOLETE_CHIPS is not set
5790 +# CONFIG_MTD_AMDSTD is not set
5791 +# CONFIG_MTD_SHARP is not set
5792 +# CONFIG_MTD_JEDEC is not set
5795 +# Mapping drivers for chip access
5797 +# CONFIG_MTD_PHYSMAP is not set
5798 +# CONFIG_MTD_LUBBOCK is not set
5799 +# CONFIG_MTD_NORA is not set
5800 +# CONFIG_MTD_ARM_INTEGRATOR is not set
5801 +# CONFIG_MTD_CDB89712 is not set
5802 +# CONFIG_MTD_SA1100 is not set
5803 +# CONFIG_MTD_DC21285 is not set
5804 +# CONFIG_MTD_IQ80310 is not set
5805 +# CONFIG_MTD_FORTUNET is not set
5806 +# CONFIG_MTD_PXA_CERF is not set
5807 +# CONFIG_MTD_EPXA10DB is not set
5808 +# CONFIG_MTD_AUTCPU12 is not set
5809 +# CONFIG_MTD_EDB7312 is not set
5810 +# CONFIG_MTD_IMPA7 is not set
5811 +CONFIG_MTD_TRIZEPS2=y
5812 +# CONFIG_MTD_PCI is not set
5815 +# Self-contained MTD device drivers
5817 +# CONFIG_MTD_PMC551 is not set
5818 +# CONFIG_MTD_SLRAM is not set
5819 +# CONFIG_MTD_MTDRAM is not set
5820 +# CONFIG_MTD_BLKMTD is not set
5821 +# CONFIG_MTD_DOC1000 is not set
5822 +# CONFIG_MTD_DOC2000 is not set
5823 +# CONFIG_MTD_DOC2001 is not set
5824 +# CONFIG_MTD_DOCPROBE is not set
5827 +# NAND Flash Device Drivers
5829 +# CONFIG_MTD_NAND is not set
5832 +# Plug and Play configuration
5834 +# CONFIG_PNP is not set
5835 +# CONFIG_ISAPNP is not set
5840 +# CONFIG_BLK_DEV_FD is not set
5841 +# CONFIG_BLK_DEV_XD is not set
5842 +# CONFIG_PARIDE is not set
5843 +# CONFIG_BLK_CPQ_DA is not set
5844 +# CONFIG_BLK_CPQ_CISS_DA is not set
5845 +# CONFIG_CISS_SCSI_TAPE is not set
5846 +# CONFIG_BLK_DEV_DAC960 is not set
5847 +# CONFIG_BLK_DEV_UMEM is not set
5848 +CONFIG_BLK_DEV_LOOP=y
5849 +# CONFIG_BLK_DEV_NBD is not set
5850 +# CONFIG_BLK_DEV_RAM is not set
5851 +# CONFIG_BLK_DEV_INITRD is not set
5854 +# Multi-device support (RAID and LVM)
5856 +# CONFIG_MD is not set
5857 +# CONFIG_BLK_DEV_MD is not set
5858 +# CONFIG_MD_LINEAR is not set
5859 +# CONFIG_MD_RAID0 is not set
5860 +# CONFIG_MD_RAID1 is not set
5861 +# CONFIG_MD_RAID5 is not set
5862 +# CONFIG_MD_MULTIPATH is not set
5863 +# CONFIG_BLK_DEV_LVM is not set
5866 +# Networking options
5868 +# CONFIG_PACKET is not set
5869 +# CONFIG_NETLINK_DEV is not set
5870 +# CONFIG_NETFILTER is not set
5871 +# CONFIG_FILTER is not set
5874 +# CONFIG_IP_MULTICAST is not set
5875 +# CONFIG_IP_ADVANCED_ROUTER is not set
5877 +# CONFIG_IP_PNP_DHCP is not set
5878 +CONFIG_IP_PNP_BOOTP=y
5879 +# CONFIG_IP_PNP_RARP is not set
5880 +# CONFIG_NET_IPIP is not set
5881 +# CONFIG_NET_IPGRE is not set
5882 +# CONFIG_ARPD is not set
5883 +# CONFIG_INET_ECN is not set
5884 +# CONFIG_SYN_COOKIES is not set
5885 +# CONFIG_IPV6 is not set
5886 +# CONFIG_KHTTPD is not set
5887 +# CONFIG_ATM is not set
5888 +# CONFIG_VLAN_8021Q is not set
5889 +# CONFIG_IPX is not set
5890 +# CONFIG_ATALK is not set
5893 +# Appletalk devices
5895 +# CONFIG_DEV_APPLETALK is not set
5896 +# CONFIG_DECNET is not set
5897 +# CONFIG_BRIDGE is not set
5898 +# CONFIG_X25 is not set
5899 +# CONFIG_LAPB is not set
5900 +# CONFIG_LLC is not set
5901 +# CONFIG_NET_DIVERT is not set
5902 +# CONFIG_ECONET is not set
5903 +# CONFIG_WAN_ROUTER is not set
5904 +# CONFIG_NET_FASTROUTE is not set
5905 +# CONFIG_NET_HW_FLOWCONTROL is not set
5908 +# QoS and/or fair queueing
5910 +# CONFIG_NET_SCHED is not set
5915 +# CONFIG_NET_PKTGEN is not set
5918 +# Network device support
5920 +CONFIG_NETDEVICES=y
5925 +# CONFIG_ARCNET is not set
5926 +# CONFIG_DUMMY is not set
5927 +# CONFIG_BONDING is not set
5928 +# CONFIG_EQUALIZER is not set
5929 +# CONFIG_TUN is not set
5930 +# CONFIG_ETHERTAP is not set
5933 +# Ethernet (10 or 100Mbit)
5935 +CONFIG_NET_ETHERNET=y
5936 +# CONFIG_ARM_AM79C961A is not set
5937 +# CONFIG_ARM_CIRRUS is not set
5938 +# CONFIG_SUNLANCE is not set
5939 +# CONFIG_SUNBMAC is not set
5940 +# CONFIG_SUNQE is not set
5941 +# CONFIG_SUNGEM is not set
5942 +# CONFIG_NET_VENDOR_3COM is not set
5943 +# CONFIG_LANCE is not set
5944 +CONFIG_NET_VENDOR_SMC=y
5945 +# CONFIG_WD80x3 is not set
5946 +# CONFIG_ULTRAMCA is not set
5947 +# CONFIG_ULTRA is not set
5948 +# CONFIG_ULTRA32 is not set
5950 +# CONFIG_NET_VENDOR_RACAL is not set
5951 +# CONFIG_NET_ISA is not set
5952 +# CONFIG_NET_PCI is not set
5953 +# CONFIG_NET_POCKET is not set
5956 +# Ethernet (1000 Mbit)
5958 +# CONFIG_ACENIC is not set
5959 +# CONFIG_DL2K is not set
5960 +# CONFIG_MYRI_SBUS is not set
5961 +# CONFIG_NS83820 is not set
5962 +# CONFIG_HAMACHI is not set
5963 +# CONFIG_YELLOWFIN is not set
5964 +# CONFIG_SK98LIN is not set
5965 +# CONFIG_TIGON3 is not set
5966 +# CONFIG_FDDI is not set
5967 +# CONFIG_HIPPI is not set
5968 +# CONFIG_PLIP is not set
5970 +# CONFIG_PPP_MULTILINK is not set
5971 +# CONFIG_PPP_FILTER is not set
5973 +CONFIG_PPP_SYNC_TTY=m
5974 +CONFIG_PPP_DEFLATE=m
5975 +CONFIG_PPP_BSDCOMP=m
5976 +# CONFIG_PPPOE is not set
5977 +# CONFIG_SLIP is not set
5980 +# Wireless LAN (non-hamradio)
5983 +# CONFIG_STRIP is not set
5984 +# CONFIG_WAVELAN is not set
5985 +# CONFIG_ARLAN is not set
5986 +# CONFIG_AIRONET4500 is not set
5987 +# CONFIG_AIRONET4500_NONCS is not set
5988 +# CONFIG_AIRONET4500_PROC is not set
5989 +# CONFIG_HERMES is not set
5990 +# CONFIG_PCMCIA_HERMES is not set
5992 +CONFIG_NET_WIRELESS=y
5995 +# Token Ring devices
5997 +# CONFIG_TR is not set
5998 +# CONFIG_NET_FC is not set
5999 +# CONFIG_RCPCI is not set
6000 +# CONFIG_SHAPER is not set
6005 +# CONFIG_WAN is not set
6008 +# PCMCIA network device support
6010 +CONFIG_NET_PCMCIA=y
6011 +# CONFIG_PCMCIA_3C589 is not set
6012 +CONFIG_PCMCIA_3C574=m
6013 +# CONFIG_PCMCIA_FMVJ18X is not set
6014 +# CONFIG_PCMCIA_PCNET is not set
6015 +# CONFIG_PCMCIA_AXNET is not set
6016 +# CONFIG_PCMCIA_NMCLAN is not set
6017 +# CONFIG_PCMCIA_SMC91C92 is not set
6018 +# CONFIG_PCMCIA_XIRC2PS is not set
6019 +# CONFIG_ARCNET_COM20020_CS is not set
6020 +# CONFIG_PCMCIA_IBMTR is not set
6021 +CONFIG_NET_PCMCIA_RADIO=y
6022 +# CONFIG_PCMCIA_RAYCS is not set
6023 +# CONFIG_PCMCIA_NETWAVE is not set
6024 +# CONFIG_PCMCIA_WAVELAN is not set
6025 +# CONFIG_AIRONET4500_CS is not set
6028 +# Amateur Radio support
6030 +# CONFIG_HAMRADIO is not set
6033 +# IrDA (infrared) support
6035 +# CONFIG_IRDA is not set
6038 +# ATA/ATAPI/MFM/RLL support
6043 +# IDE, ATA and ATAPI Block devices
6045 +CONFIG_BLK_DEV_IDE=m
6046 +# CONFIG_BLK_DEV_HD_IDE is not set
6047 +# CONFIG_BLK_DEV_HD is not set
6048 +CONFIG_BLK_DEV_IDEDISK=m
6049 +# CONFIG_IDEDISK_MULTI_MODE is not set
6050 +# CONFIG_IDEDISK_STROKE is not set
6051 +# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
6052 +# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
6053 +# CONFIG_BLK_DEV_IDEDISK_IBM is not set
6054 +# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
6055 +# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
6056 +# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
6057 +# CONFIG_BLK_DEV_IDEDISK_WD is not set
6058 +# CONFIG_BLK_DEV_COMMERIAL is not set
6059 +# CONFIG_BLK_DEV_TIVO is not set
6060 +CONFIG_BLK_DEV_IDECS=m
6061 +# CONFIG_BLK_DEV_IDECD is not set
6062 +# CONFIG_BLK_DEV_IDETAPE is not set
6063 +# CONFIG_BLK_DEV_IDEFLOPPY is not set
6064 +# CONFIG_BLK_DEV_IDESCSI is not set
6065 +# CONFIG_IDE_TASK_IOCTL is not set
6066 +# CONFIG_BLK_DEV_CMD640 is not set
6067 +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
6068 +# CONFIG_BLK_DEV_ISAPNP is not set
6069 +# CONFIG_IDE_CHIPSETS is not set
6070 +# CONFIG_IDEDMA_AUTO is not set
6071 +# CONFIG_DMA_NONPCI is not set
6072 +# CONFIG_BLK_DEV_IDE_MODES is not set
6073 +# CONFIG_BLK_DEV_ATARAID is not set
6074 +# CONFIG_BLK_DEV_ATARAID_PDC is not set
6075 +# CONFIG_BLK_DEV_ATARAID_HPT is not set
6080 +# CONFIG_SCSI is not set
6083 +# I2O device support
6085 +# CONFIG_I2O is not set
6086 +# CONFIG_I2O_BLOCK is not set
6087 +# CONFIG_I2O_LAN is not set
6088 +# CONFIG_I2O_SCSI is not set
6089 +# CONFIG_I2O_PROC is not set
6094 +# CONFIG_ISDN is not set
6097 +# Input core support
6099 +# CONFIG_INPUT is not set
6100 +# CONFIG_INPUT_KEYBDEV is not set
6101 +# CONFIG_INPUT_MOUSEDEV is not set
6102 +# CONFIG_INPUT_JOYDEV is not set
6103 +# CONFIG_INPUT_EVDEV is not set
6106 +# Character devices
6109 +# CONFIG_VT_CONSOLE is not set
6111 +CONFIG_SERIAL_CONSOLE=y
6112 +# CONFIG_SERIAL_EXTENDED is not set
6113 +# CONFIG_SERIAL_NONSTANDARD is not set
6118 +# CONFIG_SERIAL_ANAKIN is not set
6119 +# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
6120 +# CONFIG_SERIAL_AMBA is not set
6121 +# CONFIG_SERIAL_AMBA_CONSOLE is not set
6122 +# CONFIG_SERIAL_CLPS711X is not set
6123 +# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
6124 +# CONFIG_SERIAL_21285 is not set
6125 +# CONFIG_SERIAL_21285_OLD is not set
6126 +# CONFIG_SERIAL_21285_CONSOLE is not set
6127 +# CONFIG_SERIAL_UART00 is not set
6128 +# CONFIG_SERIAL_UART00_CONSOLE is not set
6129 +# CONFIG_SERIAL_SA1100 is not set
6130 +# CONFIG_SERIAL_SA1100_CONSOLE is not set
6131 +# CONFIG_SERIAL_OMAHA is not set
6132 +# CONFIG_SERIAL_OMAHA_CONSOLE is not set
6133 +# CONFIG_SERIAL_8250 is not set
6134 +# CONFIG_SERIAL_8250_CONSOLE is not set
6135 +# CONFIG_SERIAL_8250_EXTENDED is not set
6136 +# CONFIG_SERIAL_8250_MANY_PORTS is not set
6137 +# CONFIG_SERIAL_8250_SHARE_IRQ is not set
6138 +# CONFIG_SERIAL_8250_DETECT_IRQ is not set
6139 +# CONFIG_SERIAL_8250_MULTIPORT is not set
6140 +# CONFIG_SERIAL_8250_HUB6 is not set
6141 +CONFIG_UNIX98_PTYS=y
6142 +CONFIG_UNIX98_PTY_COUNT=256
6148 +# CONFIG_I2C_ALGOBIT is not set
6149 +# CONFIG_I2C_ALGOPCF is not set
6150 +CONFIG_I2C_PXA_ALGO=y
6151 +CONFIG_I2C_PXA_ADAP=y
6152 +CONFIG_I2C_CHARDEV=y
6154 +# CONFIG_I2C_DS1307 is not set
6157 +# L3 serial bus support
6159 +# CONFIG_L3 is not set
6160 +# CONFIG_L3_ALGOBIT is not set
6161 +# CONFIG_L3_BIT_SA1100_GPIO is not set
6162 +# CONFIG_L3_SA1111 is not set
6163 +# CONFIG_BIT_SA1100_GPIO is not set
6168 +# CONFIG_BUSMOUSE is not set
6169 +# CONFIG_MOUSE is not set
6174 +# CONFIG_INPUT_GAMEPORT is not set
6175 +# CONFIG_QIC02_TAPE is not set
6180 +# CONFIG_WATCHDOG is not set
6181 +# CONFIG_NVRAM is not set
6182 +# CONFIG_RTC is not set
6184 +# CONFIG_DTLK is not set
6185 +# CONFIG_R3964 is not set
6186 +# CONFIG_APPLICOM is not set
6189 +# Ftape, the floppy tape device driver
6191 +# CONFIG_FTAPE is not set
6192 +# CONFIG_AGP is not set
6193 +# CONFIG_DRM is not set
6196 +# PCMCIA character devices
6198 +# CONFIG_PCMCIA_SERIAL_CS is not set
6199 +CONFIG_TRIZEPS2_TTLIO=m
6202 +# Multimedia devices
6204 +# CONFIG_VIDEO_DEV is not set
6209 +# CONFIG_QUOTA is not set
6210 +# CONFIG_AUTOFS_FS is not set
6211 +# CONFIG_AUTOFS4_FS is not set
6212 +# CONFIG_REISERFS_FS is not set
6213 +# CONFIG_REISERFS_CHECK is not set
6214 +# CONFIG_REISERFS_PROC_INFO is not set
6215 +# CONFIG_ADFS_FS is not set
6216 +# CONFIG_ADFS_FS_RW is not set
6217 +# CONFIG_AFFS_FS is not set
6218 +# CONFIG_HFS_FS is not set
6219 +# CONFIG_BFS_FS is not set
6222 +# CONFIG_JBD_DEBUG is not set
6225 +# CONFIG_UMSDOS_FS is not set
6227 +# CONFIG_EFS_FS is not set
6228 +# CONFIG_JFFS_FS is not set
6230 +CONFIG_JFFS2_FS_DEBUG=0
6231 +# CONFIG_CRAMFS is not set
6234 +# CONFIG_ISO9660_FS is not set
6235 +# CONFIG_JOLIET is not set
6236 +# CONFIG_ZISOFS is not set
6237 +# CONFIG_MINIX_FS is not set
6238 +# CONFIG_VXFS_FS is not set
6239 +# CONFIG_NTFS_FS is not set
6240 +# CONFIG_NTFS_RW is not set
6241 +# CONFIG_HPFS_FS is not set
6243 +# CONFIG_DEVFS_FS is not set
6244 +# CONFIG_DEVFS_MOUNT is not set
6245 +# CONFIG_DEVFS_DEBUG is not set
6247 +# CONFIG_QNX4FS_FS is not set
6248 +# CONFIG_QNX4FS_RW is not set
6249 +# CONFIG_ROMFS_FS is not set
6251 +# CONFIG_SYSV_FS is not set
6252 +# CONFIG_UDF_FS is not set
6253 +# CONFIG_UDF_RW is not set
6254 +# CONFIG_UFS_FS is not set
6255 +# CONFIG_UFS_FS_WRITE is not set
6258 +# Network File Systems
6260 +# CONFIG_CODA_FS is not set
6261 +# CONFIG_INTERMEZZO_FS is not set
6263 +# CONFIG_NFS_V3 is not set
6264 +# CONFIG_ROOT_NFS is not set
6265 +# CONFIG_NFSD is not set
6266 +# CONFIG_NFSD_V3 is not set
6269 +# CONFIG_SMB_FS is not set
6270 +# CONFIG_NCP_FS is not set
6271 +# CONFIG_NCPFS_PACKET_SIGNING is not set
6272 +# CONFIG_NCPFS_IOCTL_LOCKING is not set
6273 +# CONFIG_NCPFS_STRONG is not set
6274 +# CONFIG_NCPFS_NFS_NS is not set
6275 +# CONFIG_NCPFS_OS2_NS is not set
6276 +# CONFIG_NCPFS_SMALLDOS is not set
6277 +# CONFIG_NCPFS_NLS is not set
6278 +# CONFIG_NCPFS_EXTRAS is not set
6279 +# CONFIG_ZISOFS_FS is not set
6280 +# CONFIG_ZLIB_FS_INFLATE is not set
6285 +# CONFIG_PARTITION_ADVANCED is not set
6286 +CONFIG_MSDOS_PARTITION=y
6287 +# CONFIG_SMB_NLS is not set
6291 +# Native Language Support
6293 +CONFIG_NLS_DEFAULT="iso8859-1"
6294 +# CONFIG_NLS_CODEPAGE_437 is not set
6295 +# CONFIG_NLS_CODEPAGE_737 is not set
6296 +# CONFIG_NLS_CODEPAGE_775 is not set
6297 +# CONFIG_NLS_CODEPAGE_850 is not set
6298 +# CONFIG_NLS_CODEPAGE_852 is not set
6299 +# CONFIG_NLS_CODEPAGE_855 is not set
6300 +# CONFIG_NLS_CODEPAGE_857 is not set
6301 +# CONFIG_NLS_CODEPAGE_860 is not set
6302 +# CONFIG_NLS_CODEPAGE_861 is not set
6303 +# CONFIG_NLS_CODEPAGE_862 is not set
6304 +# CONFIG_NLS_CODEPAGE_863 is not set
6305 +# CONFIG_NLS_CODEPAGE_864 is not set
6306 +# CONFIG_NLS_CODEPAGE_865 is not set
6307 +# CONFIG_NLS_CODEPAGE_866 is not set
6308 +# CONFIG_NLS_CODEPAGE_869 is not set
6309 +# CONFIG_NLS_CODEPAGE_936 is not set
6310 +# CONFIG_NLS_CODEPAGE_950 is not set
6311 +# CONFIG_NLS_CODEPAGE_932 is not set
6312 +# CONFIG_NLS_CODEPAGE_949 is not set
6313 +# CONFIG_NLS_CODEPAGE_874 is not set
6314 +# CONFIG_NLS_ISO8859_8 is not set
6315 +# CONFIG_NLS_CODEPAGE_1250 is not set
6316 +# CONFIG_NLS_CODEPAGE_1251 is not set
6317 +CONFIG_NLS_ISO8859_1=y
6318 +# CONFIG_NLS_ISO8859_2 is not set
6319 +# CONFIG_NLS_ISO8859_3 is not set
6320 +# CONFIG_NLS_ISO8859_4 is not set
6321 +# CONFIG_NLS_ISO8859_5 is not set
6322 +# CONFIG_NLS_ISO8859_6 is not set
6323 +# CONFIG_NLS_ISO8859_7 is not set
6324 +# CONFIG_NLS_ISO8859_9 is not set
6325 +# CONFIG_NLS_ISO8859_13 is not set
6326 +# CONFIG_NLS_ISO8859_14 is not set
6327 +# CONFIG_NLS_ISO8859_15 is not set
6328 +# CONFIG_NLS_KOI8_R is not set
6329 +# CONFIG_NLS_KOI8_U is not set
6330 +# CONFIG_NLS_UTF8 is not set
6336 +# CONFIG_VGA_CONSOLE is not set
6339 +# Frame-buffer support
6342 +CONFIG_DUMMY_CONSOLE=y
6343 +# CONFIG_FB_ACORN is not set
6344 +# CONFIG_FB_ANAKIN is not set
6345 +# CONFIG_FB_CLPS711X is not set
6346 +# CONFIG_FB_SA1100 is not set
6348 +# CONFIG_FB_CYBER2000 is not set
6349 +# CONFIG_FB_VIRTUAL is not set
6350 +CONFIG_FBCON_ADVANCED=y
6351 +# CONFIG_FBCON_MFB is not set
6352 +# CONFIG_FBCON_CFB2 is not set
6353 +# CONFIG_FBCON_CFB4 is not set
6354 +# CONFIG_FBCON_CFB8 is not set
6355 +CONFIG_FBCON_CFB16=y
6356 +# CONFIG_FBCON_CFB24 is not set
6357 +# CONFIG_FBCON_CFB32 is not set
6358 +# CONFIG_FBCON_AFB is not set
6359 +# CONFIG_FBCON_ILBM is not set
6360 +# CONFIG_FBCON_IPLAN2P2 is not set
6361 +# CONFIG_FBCON_IPLAN2P4 is not set
6362 +# CONFIG_FBCON_IPLAN2P8 is not set
6363 +# CONFIG_FBCON_MAC is not set
6364 +# CONFIG_FBCON_VGA_PLANES is not set
6365 +# CONFIG_FBCON_VGA is not set
6366 +# CONFIG_FBCON_HGA is not set
6367 +CONFIG_FBCON_FONTWIDTH8_ONLY=y
6368 +CONFIG_FBCON_FONTS=y
6369 +# CONFIG_FONT_8x8 is not set
6370 +# CONFIG_FONT_8x16 is not set
6371 +# CONFIG_FONT_SUN8x16 is not set
6372 +# CONFIG_FONT_PEARL_8x8 is not set
6373 +CONFIG_FONT_ACORN_8x8=y
6379 +# CONFIG_SOUND_BT878 is not set
6380 +# CONFIG_SOUND_CMPCI is not set
6381 +# CONFIG_SOUND_EMU10K1 is not set
6382 +# CONFIG_MIDI_EMU10K1 is not set
6383 +# CONFIG_SOUND_FUSION is not set
6384 +# CONFIG_SOUND_CS4281 is not set
6385 +# CONFIG_SOUND_ES1370 is not set
6386 +# CONFIG_SOUND_ES1371 is not set
6387 +# CONFIG_SOUND_ESSSOLO1 is not set
6388 +# CONFIG_SOUND_MAESTRO is not set
6389 +# CONFIG_SOUND_MAESTRO3 is not set
6390 +# CONFIG_SOUND_ICH is not set
6391 +# CONFIG_SOUND_RME96XX is not set
6392 +# CONFIG_SOUND_SONICVIBES is not set
6393 +# CONFIG_SOUND_TRIDENT is not set
6394 +# CONFIG_SOUND_MSNDCLAS is not set
6395 +# CONFIG_SOUND_MSNDPIN is not set
6396 +# CONFIG_SOUND_VIA82CXXX is not set
6397 +# CONFIG_MIDI_VIA82CXXX is not set
6398 +# CONFIG_SOUND_OSS is not set
6399 +# CONFIG_SOUND_WAVEARTIST is not set
6400 +CONFIG_SOUND_PXA_AC97=y
6401 +# CONFIG_SOUND_TVMIXER is not set
6404 +# Multimedia Capabilities Port drivers
6407 +# CONFIG_MCP_SA1100 is not set
6408 +# CONFIG_MCP_UCB1200 is not set
6409 +# CONFIG_MCP_UCB1200_AUDIO is not set
6410 +# CONFIG_MCP_UCB1200_TS is not set
6411 +CONFIG_MCP_UCB1400_TS=y
6412 +CONFIG_MCP_UCB1X00_TS_COMPAT=y
6417 +# CONFIG_USB is not set
6420 +# Bluetooth support
6422 +# CONFIG_BLUEZ is not set
6427 +CONFIG_FRAME_POINTER=y
6428 +CONFIG_DEBUG_USER=y
6429 +CONFIG_DEBUG_INFO=y
6430 +# CONFIG_NO_PGT_CACHE is not set
6431 +CONFIG_DEBUG_KERNEL=y
6432 +# CONFIG_DEBUG_SLAB is not set
6433 +CONFIG_MAGIC_SYSRQ=y
6434 +# CONFIG_DEBUG_SPINLOCK is not set
6435 +# CONFIG_DEBUG_WAITQ is not set
6436 +CONFIG_DEBUG_BUGVERBOSE=y
6437 +CONFIG_DEBUG_ERRORS=y
6439 +# CONFIG_DEBUG_DC21285_PORT is not set
6440 +# CONFIG_DEBUG_CLPS711X_UART2 is not set
6441 --- linux-2.4.27/arch/arm/kernel/Makefile~2.4.27-vrs1-pxa1
6442 +++ linux-2.4.27/arch/arm/kernel/Makefile
6444 HEAD_OBJ = head-$(PROCESSOR).o
6445 ENTRY_OBJ = entry-$(PROCESSOR).o
6447 -AFLAGS_head-armv.o := -DTEXTADDR=$(TEXTADDR)
6448 +AFLAGS_head-armv.o := -DTEXTADDR=$(TEXTADDR) -DDATAADDR=$(DATAADDR)
6449 AFLAGS_head-armo.o := -DTEXTADDR=$(TEXTADDR)
6451 # This is depreciated.
6453 $(CONFIG_FOOTBRIDGE) $(CONFIG_ARCH_EBSA110) \
6454 $(CONFIG_ARCH_SA1100) $(CONFIG_ARCH_CAMELOT) \
6455 $(CONFIG_ARCH_MX1ADS) $(CONFIG_ARCH_OMAHA) \
6456 - $(CONFIG_ARCH_AT91RM9200)
6457 + $(CONFIG_ARCH_AT91RM9200) $(CONFIG_ARCH_PXA)
6459 ifneq ($(findstring y,$(no-irq-arch)),y)
6461 --- linux-2.4.27/arch/arm/kernel/debug-armv.S~2.4.27-vrs1-pxa1
6462 +++ linux-2.4.27/arch/arm/kernel/debug-armv.S
6463 @@ -221,6 +221,31 @@
6467 +#elif defined(CONFIG_ARCH_PXA)
6469 + .macro addruart,rx
6470 + mrc p15, 0, \rx, c1, c0
6471 + tst \rx, #1 @ MMU enabled?
6472 + moveq \rx, #0x40000000 @ physical
6473 + movne \rx, #io_p2v(0x40000000) @ virtual
6474 + orr \rx, \rx, #0x00100000 @ FFUART
6477 + .macro senduart,rd,rx
6478 + str \rd, [\rx, #0]
6481 + .macro busyuart,rd,rx
6482 +1002: ldr \rd, [\rx, #0x14]
6483 + tst \rd, #(1 << 6)
6487 + .macro waituart,rd,rx
6488 +1001: ldr \rd, [\rx, #0x14]
6489 + tst \rd, #(1 << 5)
6492 #elif defined(CONFIG_ARCH_CLPS7500)
6494 mov \rx, #0xe0000000
6495 --- linux-2.4.27/arch/arm/kernel/entry-armv.S~2.4.27-vrs1-pxa1
6496 +++ linux-2.4.27/arch/arm/kernel/entry-armv.S
6497 @@ -615,6 +615,27 @@
6501 +#elif CONFIG_ARCH_PXA
6503 + .macro disable_fiq
6506 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
6507 + mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
6508 + add \base, \base, #0x00d00000
6509 + ldr \irqstat, [\base, #0] @ ICIP
6510 + ldr \irqnr, [\base, #4] @ ICMR
6511 + ands \irqstat, \irqstat, \irqnr
6513 + rsb \irqnr, \irqstat, #0
6514 + and \irqstat, \irqstat, \irqnr
6515 + clz \irqnr, \irqstat
6516 + rsb \irqnr, \irqnr, #(31 - PXA_IRQ_SKIP)
6520 + .macro irq_prio_table
6523 #error Unknown architecture
6525 @@ -891,9 +912,17 @@
6526 stmfd sp!, {r4 - sl, fp, lr} @ Store most regs on stack
6528 str ip, [sp, #-4]! @ Save cpsr_SVC
6529 +#ifdef CONFIG_CPU_XSCALE
6531 + stmfd sp!, {r4, r5}
6533 str sp, [r0, #TSS_SAVE] @ Save sp_SVC
6534 ldr sp, [r1, #TSS_SAVE] @ Get saved sp_SVC
6535 ldr r2, [r1, #TSS_DOMAIN]
6536 +#ifdef CONFIG_CPU_XSCALE
6537 + ldmfd sp!, {r4, r5}
6541 mcr p15, 0, r2, c3, c0 @ Set domain register
6542 msr spsr, ip @ Save tasks CPSR into SPSR for this return
6543 --- linux-2.4.27/arch/arm/kernel/head-armv.S~2.4.27-vrs1-pxa1
6544 +++ linux-2.4.27/arch/arm/kernel/head-armv.S
6547 * swapper_pg_dir, pgtbl and krnladr are all closely related.
6549 +#ifndef CONFIG_XIP_KERNEL
6550 #if (TEXTADDR & 0xffff) != 0x8000
6551 #error TEXTADDR must start at 0xXXXX8000
6555 sub \reg, \reg, #0x4000
6558 +#if (DATAADDR & 0xffff) != 0x8000
6559 +#error DATAADDR must start at 0xXXXX8000
6562 +#define PAGE_OFFSET 0xc0000000
6563 +#ifdef CONFIG_ARCH_LUBBOCK
6564 +#define PHYS_OFFSET 0xa0000000
6565 +#elif CONFIG_ARCH_OMAP
6566 +#define PHYS_OFFSET 0x10000000
6569 + .globl SYMBOL_NAME(swapper_pg_dir)
6570 + .equ SYMBOL_NAME(swapper_pg_dir), DATAADDR - 0x4000
6572 + .macro pgtbl, reg, rambase
6574 + add \reg, \reg, #PHYS_OFFSET - PAGE_OFFSET
6579 * Since the page table is closely related to the kernel start address, we
6580 @@ -131,6 +152,32 @@
6581 mov r1, #MACH_TYPE_L7200
6584 +#ifdef CONFIG_XIP_KERNEL
6586 +#if defined(CONFIG_ARCH_LUBBOCK)
6587 + mov r1, #MACH_TYPE_LUBBOCK
6590 + @ Data cache might be active.
6591 + @ Be sure to flush kernel binary out of the cache,
6592 + @ whatever state it is, before it is turned off.
6593 + @ This is done by fetching through currently executed
6594 + @ memory to be sure we hit the same cache.
6596 + add r3, r2, #0x10000 @ 64 kb is quite enough...
6597 +1: ldr r0, [r2], #32
6600 + mcr p15, 0, r0, c7, c10, 4 @ drain WB
6601 + mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
6603 + @ disabling MMU and caches
6604 + mrc p15, 0, r0, c1, c0, 0 @ read control reg
6605 + bic r0, r0, #0x05 @ clear DC, MMU
6606 + bic r0, r0, #0x1000 @ clear Icache
6607 + mcr p15, 0, r0, c1, c0, 0
6610 mov r0, #F_BIT | I_BIT | MODE_SVC @ make sure svc mode
6611 msr cpsr_c, r0 @ and all irqs disabled
6612 bl __lookup_processor_type
6613 @@ -179,6 +226,17 @@
6617 +#ifdef CONFIG_XIP_KERNEL
6618 + ldr r3, ETEXT @ data section copy
6628 adr r3, __switch_data + 4
6629 ldmia r3, {r4, r5, r6, r7, r8, sp}@ r2 = compat
6630 @ sp = stack pointer
6635 +#ifndef CONFIG_XIP_KERNEL
6638 * Create identity mapping for first MB of kernel to
6639 * cater for the MMU enable. This identity mapping
6640 @@ -271,6 +331,43 @@
6641 add r3, r8, r2 @ flags + rambase
6644 +#else /* CONFIG_XIP_KERNEL */
6646 + mov r3, pc, lsr #20
6647 + mov r3, r3, lsl #20 @ phys kernel start
6649 + add r0, r4, r3, lsr #18
6653 + mov r0, #TEXTADDR & 0xff000000
6654 + add r0, r0, #TEXTADDR & 0x00f00000 @ virt kernel start
6655 + add r0, r4, r0, lsr #18
6656 + add r2, r3, #4 << 20 @ kernel + 4MB
6660 + add r3, r3, #1 << 20
6664 + bic r3, r4, #0x000ff000 @ ram start
6665 + add r0, r4, r3, lsr #18
6669 + add r0, r3, #PAGE_OFFSET - PHYS_OFFSET
6670 + add r0, r4, r0, lsr #18
6671 + add r2, r3, #4 << 20 @ ram + 4MB
6675 + add r3, r3, #1 << 20
6679 +#endif /* CONFIG_XIP_KERNEL */
6681 bic r8, r8, #0x0c @ turn off cacheable
6682 @ and bufferable bits
6683 #ifdef CONFIG_DEBUG_LL
6684 @@ -433,3 +530,13 @@
6686 2: ldmib r4, {r5, r6, r7} @ found, get results
6689 +#ifdef CONFIG_XIP_KERNEL
6691 +PGTBL: .long SYMBOL_NAME(swapper_pg_dir)
6693 +ETEXT: .long SYMBOL_NAME(_endtext)
6694 +SDATA: .long SYMBOL_NAME(_sdata)
6695 +EDATA: .long SYMBOL_NAME(__bss_start)
6698 --- linux-2.4.27/arch/arm/kernel/setup.c~2.4.27-vrs1-pxa1
6699 +++ linux-2.4.27/arch/arm/kernel/setup.c
6701 extern void reboot_setup(char *str);
6702 extern int root_mountflags;
6703 extern int _stext, _text, _etext, _edata, _end;
6704 +#ifdef CONFIG_XIP_KERNEL
6705 +extern int _endtext, _sdata;
6709 unsigned int processor_id;
6710 unsigned int __machine_arch_type;
6711 @@ -105,6 +109,109 @@
6712 #define lp1 io_res[1]
6713 #define lp2 io_res[2]
6715 +#ifdef CONFIG_CPU_32
6716 +static const char *cache_types[16] = {
6735 +static const char *cache_clean[16] = {
6754 +static const char *cache_lockdown[16] = {
6773 +#define CACHE_TYPE(x) (((x) >> 25) & 15)
6774 +#define CACHE_S(x) ((x) & (1 << 24))
6775 +#define CACHE_DSIZE(x) (((x) >> 12) & 4095) /* only if S=1 */
6776 +#define CACHE_ISIZE(x) ((x) & 4095)
6778 +#define CACHE_SIZE(y) (((y) >> 6) & 7)
6779 +#define CACHE_ASSOC(y) (((y) >> 3) & 7)
6780 +#define CACHE_M(y) ((y) & (1 << 2))
6781 +#define CACHE_LINE(y) ((y) & 3)
6783 +static inline void dump_cache(const char *prefix, unsigned int cache)
6785 + unsigned int mult = 2 + (CACHE_M(cache) ? 1 : 0);
6787 + printk("%s size %dK associativity %d line length %d sets %d\n",
6789 + mult << (8 + CACHE_SIZE(cache)),
6790 + (mult << CACHE_ASSOC(cache)) >> 1,
6791 + 8 << CACHE_LINE(cache),
6792 + 1 << (6 + CACHE_SIZE(cache) - CACHE_ASSOC(cache) -
6793 + CACHE_LINE(cache)));
6796 +static inline void dump_cpu_cache_id(void)
6798 + unsigned int cache_info;
6800 + asm("mrc p15, 0, %0, c0, c0, 1" : "=r" (cache_info));
6802 + if (cache_info == processor_id)
6805 + printk("CPU: D %s cache\n", cache_types[CACHE_TYPE(cache_info)]);
6806 + if (CACHE_S(cache_info)) {
6807 + dump_cache("CPU: I cache", CACHE_ISIZE(cache_info));
6808 + dump_cache("CPU: D cache", CACHE_DSIZE(cache_info));
6810 + dump_cache("CPU: cache", CACHE_ISIZE(cache_info));
6815 +#define dump_cpu_cache_id() do { } while (0)
6818 static void __init setup_processor(void)
6820 extern struct proc_info_list __proc_info_begin, __proc_info_end;
6821 @@ -272,7 +379,11 @@
6823 kernel_code.start = __virt_to_phys(init_mm.start_code);
6824 kernel_code.end = __virt_to_phys(init_mm.end_code - 1);
6825 +#ifndef CONFIG_XIP_KERNEL
6826 kernel_data.start = __virt_to_phys(init_mm.end_code);
6828 + kernel_data.start = __virt_to_phys(init_mm.start_data);
6830 kernel_data.end = __virt_to_phys(init_mm.brk - 1);
6832 for (i = 0; i < mi->nr_banks; i++) {
6833 @@ -531,7 +642,12 @@
6836 init_mm.start_code = (unsigned long) &_text;
6837 +#ifndef CONFIG_XIP_KERNEL
6838 init_mm.end_code = (unsigned long) &_etext;
6840 + init_mm.end_code = (unsigned long) &_endtext;
6841 + init_mm.start_data = (unsigned long) &_sdata;
6843 init_mm.end_data = (unsigned long) &_edata;
6844 init_mm.brk = (unsigned long) &_end;
6846 @@ -568,6 +684,41 @@
6850 +static const char *proc_arch[16] = {
6870 +c_show_cache(struct seq_file *m, const char *type, unsigned int cache)
6872 + unsigned int mult = 2 + (CACHE_M(cache) ? 1 : 0);
6874 + seq_printf(m, "%s size\t\t: %d\n"
6875 + "%s assoc\t\t: %d\n"
6876 + "%s line length\t: %d\n"
6877 + "%s sets\t\t: %d\n",
6878 + type, mult << (8 + CACHE_SIZE(cache)),
6879 + type, (mult << CACHE_ASSOC(cache)) >> 1,
6880 + type, 8 << CACHE_LINE(cache),
6881 + type, 1 << (6 + CACHE_SIZE(cache) - CACHE_ASSOC(cache) -
6882 + CACHE_LINE(cache)));
6885 static int c_show(struct seq_file *m, void *v)
6888 @@ -586,7 +737,60 @@
6889 if (elf_hwcap & (1 << i))
6890 seq_printf(m, "%s ", hwcap_str[i]);
6892 - seq_puts(m, "\n\n");
6893 + seq_puts(m, "\n");
6895 + if ((processor_id & 0x0000f000) == 0x00000000) {
6897 + seq_printf(m, "CPU part\t\t: %07x\n", processor_id >> 4);
6898 + } else if ((processor_id & 0x0000f000) == 0x00007000) {
6900 + seq_printf(m, "CPU implementor\t: 0x%02x\n"
6901 + "CPU architecture: %s\n"
6902 + "CPU variant\t: 0x%02x\n"
6903 + "CPU part\t: 0x%03x\n",
6904 + processor_id >> 24,
6905 + processor_id & (1 << 23) ? "4T" : "3",
6906 + (processor_id >> 16) & 127,
6907 + (processor_id >> 4) & 0xfff);
6910 + seq_printf(m, "CPU implementor\t: 0x%02x\n"
6911 + "CPU architecture: %s\n"
6912 + "CPU variant\t: 0x%x\n"
6913 + "CPU part\t: 0x%03x\n",
6914 + processor_id >> 24,
6915 + proc_arch[(processor_id >> 16) & 15],
6916 + (processor_id >> 20) & 15,
6917 + (processor_id >> 4) & 0xfff);
6919 + seq_printf(m, "CPU revision\t: %d\n", processor_id & 15);
6921 +#ifdef CONFIG_CPU_32
6923 + unsigned int cache_info;
6925 + asm("mrc p15, 0, %0, c0, c0, 1" : "=r" (cache_info));
6926 + if (cache_info != processor_id) {
6927 + seq_printf(m, "Cache type\t: %s\n"
6928 + "Cache clean\t: %s\n"
6929 + "Cache lockdown\t: %s\n"
6930 + "Cache unified\t: %s\n",
6931 + cache_types[CACHE_TYPE(cache_info)],
6932 + cache_clean[CACHE_TYPE(cache_info)],
6933 + cache_lockdown[CACHE_TYPE(cache_info)],
6934 + CACHE_S(cache_info) ? "harvard" : "unified");
6936 + if (CACHE_S(cache_info)) {
6937 + c_show_cache(m, "I", CACHE_ISIZE(cache_info));
6938 + c_show_cache(m, "D", CACHE_DSIZE(cache_info));
6940 + c_show_cache(m, "Cache", CACHE_ISIZE(cache_info));
6946 + seq_puts(m, "\n");
6948 seq_printf(m, "Hardware\t: %s\n", machine_name);
6949 seq_printf(m, "Revision\t: %04x\n", system_rev);
6950 --- linux-2.4.27/arch/arm/lib/copy_page.S~2.4.27-vrs1-pxa1
6951 +++ linux-2.4.27/arch/arm/lib/copy_page.S
6953 #include <asm/assembler.h>
6954 #include <asm/constants.h>
6956 +#define COPY_COUNT (PAGE_SZ/64 PLD( -1 ))
6964 stmfd sp!, {r4, lr} @ 2
6965 - mov r2, #PAGE_SZ/64 @ 1
6966 + PLD( pld [r1, #0] )
6967 + PLD( pld [r1, #32] )
6968 + mov r2, #COPY_COUNT @ 1
6969 ldmia r1!, {r3, r4, ip, lr} @ 4+1
6970 -1: stmia r0!, {r3, r4, ip, lr} @ 4
6971 +1: PLD( pld [r1, #64] )
6972 + PLD( pld [r1, #96] )
6973 +2: stmia r0!, {r3, r4, ip, lr} @ 4
6974 ldmia r1!, {r3, r4, ip, lr} @ 4+1
6975 stmia r0!, {r3, r4, ip, lr} @ 4
6976 ldmia r1!, {r3, r4, ip, lr} @ 4+1
6978 ldmia r1!, {r3, r4, ip, lr} @ 4
6980 stmia r0!, {r3, r4, ip, lr} @ 4
6981 - ldmneia r1!, {r3, r4, ip, lr} @ 4
6983 + ldmgtia r1!, {r3, r4, ip, lr} @ 4
6985 + PLD( ldmeqia r1!, {r3, r4, ip, lr} )
6987 LOADREGS(fd, sp!, {r4, pc}) @ 3
6988 --- linux-2.4.27/arch/arm/lib/findbit.S~2.4.27-vrs1-pxa1
6989 +++ linux-2.4.27/arch/arm/lib/findbit.S
6992 * One or more bits in the LSB of r3 are assumed to be set.
6994 -.found: tst r3, #0x0f
6996 +#if __LINUX_ARM_ARCH__ >= 5
7005 movne r3, r3, lsl #4
7014 --- linux-2.4.27/arch/arm/lib/getuser.S~2.4.27-vrs1-pxa1
7015 +++ linux-2.4.27/arch/arm/lib/getuser.S
7017 * Inputs: r0 contains the address
7018 * Outputs: r0 is the error code
7019 * r1, r2 contains the zero-extended value
7021 + * ip, lr corrupted
7023 * No other registers must be altered. (see include/asm-arm/uaccess.h
7024 * for specific ASM register usage).
7027 .global __get_user_2
7029 - bic r2, sp, #0x1f00
7030 - bic r2, r2, #0x00ff
7031 - ldr r2, [r2, #TSK_ADDR_LIMIT]
7034 + bic ip, sp, #0x1f00
7035 + bic ip, ip, #0x00ff
7036 + ldr ip, [ip, #TSK_ADDR_LIMIT]
7039 2: ldrlsbt r1, [r0], #1
7040 -3: ldrlsbt r2, [r0]
7041 - orrls r1, r1, r2, lsl #8
7042 +3: ldrlsbt ip, [r0]
7043 + orrls r1, r1, ip, lsl #8
7047 --- linux-2.4.27/arch/arm/lib/memcpy.S~2.4.27-vrs1-pxa1
7048 +++ linux-2.4.27/arch/arm/lib/memcpy.S
7050 * published by the Free Software Foundation.
7052 * ASM optimised string functions
7054 + * Big Endian, prefetching and code factorization provided by Nicolas Pitre:
7055 + * Copyright (C) 2002-2003 MontaVista Software, Inc.
7057 #include <linux/linkage.h>
7058 #include <asm/assembler.h>
7062 * Prototype: void memcpy(void *to,const void *from,unsigned long n);
7063 - * ARM3: cant use memcopy here!!!
7075 + PLD( pld [r1, #0] )
7083 - subs r2, r2, #0x14
7085 -2: ldmia r1!,{r3 - r9, ip}
7086 - stmia r0!,{r3 - r9, ip}
7090 + PLD( subs r2, r2, #65 )
7092 + PLD( pld [r1, #32] )
7094 + PLD( @ cache alignment )
7095 + PLD( ands ip, r1, #31 )
7096 + PLD( pld [r1, #64] )
7098 + PLD( rsb ip, ip, #32 )
7100 + PLD( pld [r1, #96] )
7102 + PLD( cmp ip, #16 )
7103 + PLD( sub r2, r2, ip )
7104 + PLD( ldmgeia r1!, {r3 - r6} )
7105 + PLD( stmgeia r0!, {r3 - r6} )
7107 + PLD( and ip, ip, #15 )
7109 + PLD( ldr r3, [r1], #4 )
7110 + PLD( ldrge r4, [r1], #4 )
7111 + PLD( ldrgt r5, [r1], #4 )
7112 + PLD( str r3, [r0], #4 )
7113 + PLD( strge r4, [r0], #4 )
7114 + PLD( strgt r5, [r0], #4 )
7116 +2: PLD( pld [r1, #96] )
7117 +3: ldmia r1!, {r3 - r9, ip}
7119 + stmia r0!, {r3 - r9, ip}
7122 + PLD( cmn r2, #65 )
7124 + PLD( add r2, r2, #65 )
7126 ldmgeia r1!, {r3 - r6}
7128 stmgeia r0!, {r3 - r6}
7129 - subge r2, r2, #0x10
7130 -3: adds r2, r2, #0x14
7131 -4: ldmgeia r1!, {r3 - r5}
7133 + ldmgeia r1!, {r3 - r5}
7135 stmgeia r0!, {r3 - r5}
7136 - subges r2, r2, #12
7142 ldmgeia r1!, {r4, r5}
7145 stmgeia r0!, {r4, r5}
7150 @@ -92,122 +126,175 @@
7163 + .macro forward_copy_shift pull push
7168 -9: mov r3, r7, lsr #8
7169 - ldmia r1!, {r4 - r7}
7170 - orr r3, r3, r4, lsl #24
7171 - mov r4, r4, lsr #8
7172 - orr r4, r4, r5, lsl #24
7173 - mov r5, r5, lsr #8
7174 - orr r5, r5, r6, lsl #24
7175 - mov r6, r6, lsr #8
7176 - orr r6, r6, r7, lsl #24
7177 + PLD( pld [r1, #0] )
7182 + PLD( subs r2, r2, #97 )
7184 + PLD( pld [r1, #32] )
7186 + PLD( @ cache alignment )
7187 + PLD( rsb ip, r1, #36 )
7188 + PLD( pld [r1, #64] )
7189 + PLD( ands ip, ip, #31 )
7190 + PLD( pld [r1, #96] )
7193 + PLD( pld [r1, #128] )
7195 + PLD( sub r2, r2, ip )
7196 +9: PLD( mov r3, lr, pull #\pull )
7197 + PLD( ldr lr, [r1], #4 )
7198 + PLD( subs ip, ip, #4 )
7199 + PLD( orr r3, r3, lr, push #\push )
7200 + PLD( str r3, [r0], #4 )
7203 +10: PLD( pld [r1, #128] )
7204 +11: mov r3, lr, pull #\pull
7205 + ldmia r1!, {r4 - r9, ip, lr}
7207 + orr r3, r3, r4, push #\push
7208 + mov r4, r4, pull #\pull
7209 + orr r4, r4, r5, push #\push
7210 + mov r5, r5, pull #\pull
7211 + orr r5, r5, r6, push #\push
7212 + mov r6, r6, pull #\pull
7213 + orr r6, r6, r7, push #\push
7214 + mov r7, r7, pull #\pull
7215 + orr r7, r7, r8, push #\push
7216 + mov r8, r8, pull #\pull
7217 + orr r8, r8, r9, push #\push
7218 + mov r9, r9, pull #\pull
7219 + orr r9, r9, ip, push #\push
7220 + mov ip, ip, pull #\pull
7221 + orr ip, ip, lr, push #\push
7222 + stmia r0!, {r3 - r9, ip}
7224 + PLD( cmn r2, #97 )
7226 + PLD( add r2, r2, #97 )
7229 +12: mov r3, lr, pull #\pull
7230 + ldmia r1!, {r4 - r6, lr}
7232 + orr r3, r3, r4, push #\push
7233 + mov r4, r4, pull #\pull
7234 + orr r4, r4, r5, push #\push
7235 + mov r5, r5, pull #\pull
7236 + orr r5, r5, r6, push #\push
7237 + mov r6, r6, pull #\pull
7238 + orr r6, r6, lr, push #\push
7239 stmia r0!, {r3 - r6}
7244 -10: mov r3, r7, lsr #8
7246 +13: adds r2, r2, #28
7248 +14: mov r3, lr, pull #\pull
7251 - orr r3, r3, r7, lsl #24
7252 + orr r3, r3, lr, push #\push
7255 -100: sub r1, r1, #3
7261 + forward_copy_shift pull=8 push=24
7268 -12: mov r3, r7, lsr #16
7269 - ldmia r1!, {r4 - r7}
7270 - orr r3, r3, r4, lsl #16
7271 - mov r4, r4, lsr #16
7272 - orr r4, r4, r5, lsl #16
7273 - mov r5, r5, lsr #16
7274 - orr r5, r5, r6, lsl #16
7275 - mov r6, r6, lsr #16
7276 - orr r6, r6, r7,LSL#16
7277 - stmia r0!, {r3 - r6}
7282 -13: mov r3, r7, lsr #16
7285 - orr r3, r3, r7, lsl #16
7289 +16: forward_copy_shift pull=16 push=16
7296 -16: mov r3, r7, lsr #24
7297 - ldmia r1!,{r4 - r7}
7298 - orr r3, r3, r4, lsl #8
7299 - mov r4, r4, lsr #24
7300 - orr r4, r4, r5, lsl #8
7301 - mov r5, r5, lsr #24
7302 - orr r5, r5, r6, lsl #8
7303 - mov r6, r6, lsr #24
7304 - orr r6, r6, r7, lsl #8
7305 - stmia r0!, {r3 - r6}
7310 -17: mov r3, r7, lsr #24
7313 - orr r3, r3, r7, lsl#8
7317 +17: forward_copy_shift pull=24 push=8
7327 + PLD( pld [r1, #-4] )
7333 -20: subs r2, r2, #8
7334 +19: subs r2, r2, #8
7336 - subs r2, r2, #0x14
7339 -21: ldmdb r1!, {r3 - r9, ip}
7340 - stmdb r0!, {r3 - r9, ip}
7342 + PLD( subs r2, r2, #96 )
7343 + PLD( pld [r1, #-32] )
7346 + PLD( @ cache alignment )
7347 + PLD( ands ip, r1, #31 )
7348 + PLD( pld [r1, #-64] )
7351 + PLD( pld [r1, #-96] )
7353 + PLD( cmp ip, #16 )
7354 + PLD( sub r2, r2, ip )
7355 + PLD( ldmgedb r1!, {r3 - r6} )
7356 + PLD( stmgedb r0!, {r3 - r6} )
7358 + PLD( and ip, ip, #15 )
7360 + PLD( ldr r3, [r1, #-4]! )
7361 + PLD( ldrge r4, [r1, #-4]! )
7362 + PLD( ldrgt r5, [r1, #-4]! )
7363 + PLD( str r3, [r0, #-4]! )
7364 + PLD( strge r4, [r0, #-4]! )
7365 + PLD( strgt r5, [r0, #-4]! )
7367 +20: PLD( pld [r1, #-96] )
7368 + PLD( pld [r1, #-128] )
7369 +21: ldmdb r1!, {r3 - r6}
7373 + stmdb r0!, {r3 - r6}
7374 + ldmdb r1!, {r3 - r6}
7375 + stmgedb r0!, {r3 - r6}
7376 ldmgedb r1!, {r3 - r6}
7377 stmgedb r0!, {r3 - r6}
7378 + ldmgedb r1!, {r3 - r6}
7379 + subges r2, r2, #32
7380 + stmdb r0!, {r3 - r6}
7382 + PLD( cmn r2, #96 )
7384 + PLD( add r2, r2, #96 )
7386 + ldmgedb r1!, {r3 - r6}
7388 + stmgedb r0!, {r3 - r6}
7390 ldmgedb r1!, {r3 - r5}
7391 - stmgedb r0!, {r3 - r5}
7393 + stmgedb r0!, {r3 - r5}
7397 ldrlt r3, [r1, #-4]!
7398 ldmgedb r1!, {r4, r5}
7400 strlt r3, [r0, #-4]!
7401 stmgedb r0!, {r4, r5}
7406 @@ -230,89 +317,101 @@
7421 -27: mov r7, r3, lsl #8
7422 - ldmdb r1!, {r3, r4, r5, r6}
7423 - orr r7, r7, r6, lsr #24
7424 - mov r6, r6, lsl #8
7425 - orr r6, r6, r5, lsr #24
7426 - mov r5, r5, lsl #8
7427 - orr r5, r5, r4, lsr #24
7428 - mov r4, r4, lsl #8
7429 - orr r4, r4, r3, lsr #24
7430 - stmdb r0!, {r4, r5, r6, r7}
7435 -28: mov ip, r3, lsl #8
7436 - ldr r3, [r1, #-4]!
7438 - orr ip, ip, r3, lsr #24
7439 - str ip, [r0, #-4]!
7449 + .macro backward_copy_shift push pull
7452 + PLD( pld [r1, #-4] )
7455 -31: mov r7, r3, lsl #16
7456 - ldmdb r1!, {r3, r4, r5, r6}
7457 - orr r7, r7, r6, lsr #16
7458 - mov r6, r6, lsl #16
7459 - orr r6, r6, r5, lsr #16
7460 - mov r5, r5, lsl #16
7461 - orr r5, r5, r4, lsr #16
7462 - mov r4, r4, lsl #16
7463 - orr r4, r4, r3, lsr #16
7464 - stmdb r0!, {r4, r5, r6, r7}
7471 + PLD( subs r2, r2, #96 )
7472 + PLD( pld [r1, #-32] )
7474 + PLD( pld [r1, #-64] )
7476 + PLD( @ cache alignment )
7477 + PLD( ands ip, r1, #31 )
7478 + PLD( pld [r1, #-96] )
7481 + PLD( pld [r1, #-128] )
7483 + PLD( sub r2, r2, ip )
7484 +27: PLD( mov r4, r3, push #\push )
7485 + PLD( ldr r3, [r1, #-4]! )
7486 + PLD( subs ip, ip, #4 )
7487 + PLD( orr r4, r4, r3, pull #\pull )
7488 + PLD( str r4, [r0, #-4]! )
7491 +28: PLD( pld [r1, #-128] )
7492 +29: mov lr, r3, push #\push
7493 + ldmdb r1!, {r3 - r9, ip}
7495 + orr lr, lr, ip, pull #\pull
7496 + mov ip, ip, push #\push
7497 + orr ip, ip, r9, pull #\pull
7498 + mov r9, r9, push #\push
7499 + orr r9, r9, r8, pull #\pull
7500 + mov r8, r8, push #\push
7501 + orr r8, r8, r7, pull #\pull
7502 + mov r7, r7, push #\push
7503 + orr r7, r7, r6, pull #\pull
7504 + mov r6, r6, push #\push
7505 + orr r6, r6, r5, pull #\pull
7506 + mov r5, r5, push #\push
7507 + orr r5, r5, r4, pull #\pull
7508 + mov r4, r4, push #\push
7509 + orr r4, r4, r3, pull #\pull
7510 + stmdb r0!, {r4 - r9, ip, lr}
7512 + PLD( cmn r2, #96 )
7514 + PLD( add r2, r2, #96 )
7517 +30: mov r7, r3, push #\push
7518 + ldmdb r1!, {r3 - r6}
7520 + orr r7, r7, r6, pull #\pull
7521 + mov r6, r6, push #\push
7522 + orr r6, r6, r5, pull #\pull
7523 + mov r5, r5, push #\push
7524 + orr r5, r5, r4, pull #\pull
7525 + mov r4, r4, push #\push
7526 + orr r4, r4, r3, pull #\pull
7527 + stmdb r0!, {r4 - r7}
7528 +31: adds r2, r2, #28
7530 -32: mov ip, r3, lsl #16
7531 +32: mov r4, r3, push #\push
7534 - orr ip, ip, r3, lsr #16
7535 - str ip, [r0, #-4]!
7536 + orr r4, r4, r3, pull #\pull
7537 + str r4, [r0, #-4]!
7544 + backward_copy_shift push=8 pull=24
7551 -35: mov r7, r3, lsl #24
7552 - ldmdb r1!, {r3, r4, r5, r6}
7553 - orr r7, r7, r6, lsr #8
7554 - mov r6, r6, lsl #24
7555 - orr r6, r6, r5, lsr #8
7556 - mov r5, r5, lsl #24
7557 - orr r5, r5, r4, lsr #8
7558 - mov r4, r4, lsl #24
7559 - orr r4, r4, r3, lsr #8
7560 - stmdb r0!, {r4, r5, r6, r7}
7565 -36: mov ip, r3, lsl #24
7566 - ldr r3, [r1, #-4]!
7568 - orr ip, ip, r3, lsr #8
7569 - str ip, [r0, #-4]!
7572 +34: backward_copy_shift push=16 pull=16
7576 +35: backward_copy_shift push=24 pull=8
7581 --- linux-2.4.27/arch/arm/lib/uaccess.S~2.4.27-vrs1-pxa1
7582 +++ linux-2.4.27/arch/arm/lib/uaccess.S
7584 stmfd sp!, {r2, r4 - r7, lr}
7587 + PLD( pld [r1, #0] )
7588 + PLD( pld [r0, #0] )
7590 bne .c2u_dest_not_aligned
7596 + PLD( pld [r1, #28] )
7597 + PLD( pld [r0, #28] )
7598 + PLD( subs ip, ip, #64 )
7599 + PLD( blt .c2u_0cpynopld )
7600 + PLD( pld [r1, #60] )
7601 + PLD( pld [r0, #60] )
7603 -.c2u_0cpy8lp: ldmia r1!, {r3 - r6}
7605 + PLD( pld [r1, #92] )
7606 + PLD( pld [r0, #92] )
7607 +.c2u_0cpynopld: ldmia r1!, {r3 - r6}
7608 stmia r0!, {r3 - r6} @ Shouldnt fault
7609 ldmia r1!, {r3 - r6}
7610 - stmia r0!, {r3 - r6} @ Shouldnt fault
7612 + stmia r0!, {r3 - r6} @ Shouldnt fault
7614 + PLD( cmn ip, #64 )
7615 + PLD( bge .c2u_0cpynopld )
7616 + PLD( add ip, ip, #64 )
7618 .c2u_0rem8lp: cmn ip, #16
7619 ldmgeia r1!, {r3 - r6}
7620 stmgeia r0!, {r3 - r6} @ Shouldnt fault
7622 .c2u_1fupi: subs r2, r2, #4
7625 - mov r3, r7, lsr #8
7626 + mov r3, r7, pull #8
7628 - orr r3, r3, r7, lsl #24
7629 + orr r3, r3, r7, push #24
7630 USER( strt r3, [r0], #4) @ May fault
7631 mov ip, r0, lsl #32 - PAGE_SHIFT
7633 @@ -128,50 +143,63 @@
7637 + PLD( pld [r1, #12] )
7638 + PLD( pld [r0, #12] )
7639 + PLD( subs ip, ip, #32 )
7640 + PLD( blt .c2u_1cpynopld )
7641 + PLD( pld [r1, #28] )
7642 + PLD( pld [r0, #28] )
7644 -.c2u_1cpy8lp: mov r3, r7, lsr #8
7646 + PLD( pld [r1, #44] )
7647 + PLD( pld [r0, #44] )
7648 +.c2u_1cpynopld: mov r3, r7, pull #8
7649 ldmia r1!, {r4 - r7}
7650 - orr r3, r3, r4, lsl #24
7651 - mov r4, r4, lsr #8
7652 - orr r4, r4, r5, lsl #24
7653 - mov r5, r5, lsr #8
7654 - orr r5, r5, r6, lsl #24
7655 - mov r6, r6, lsr #8
7656 - orr r6, r6, r7, lsl #24
7657 - stmia r0!, {r3 - r6} @ Shouldnt fault
7659 + orr r3, r3, r4, push #24
7660 + mov r4, r4, pull #8
7661 + orr r4, r4, r5, push #24
7662 + mov r5, r5, pull #8
7663 + orr r5, r5, r6, push #24
7664 + mov r6, r6, pull #8
7665 + orr r6, r6, r7, push #24
7666 + stmia r0!, {r3 - r6} @ Shouldnt fault
7668 + PLD( cmn ip, #32 )
7669 + PLD( bge .c2u_1cpynopld )
7670 + PLD( add ip, ip, #32 )
7672 .c2u_1rem8lp: tst ip, #8
7673 - movne r3, r7, lsr #8
7674 + movne r3, r7, pull #8
7675 ldmneia r1!, {r4, r7}
7676 - orrne r3, r3, r4, lsl #24
7677 - movne r4, r4, lsr #8
7678 - orrne r4, r4, r7, lsl #24
7679 + orrne r3, r3, r4, push #24
7680 + movne r4, r4, pull #8
7681 + orrne r4, r4, r7, push #24
7682 stmneia r0!, {r3 - r4} @ Shouldnt fault
7684 - movne r3, r7, lsr #8
7685 + movne r3, r7, pull #8
7687 - orrne r3, r3, r7, lsl #24
7688 + orrne r3, r3, r7, push #24
7689 strnet r3, [r0], #4 @ Shouldnt fault
7692 -.c2u_1nowords: mov r3, r7, lsr #8
7693 +.c2u_1nowords: mov r3, r7, lsr #byte(1)
7697 USER( strbt r3, [r0], #1) @ May fault
7698 - movge r3, r3, lsr #8
7699 + movge r3, r7, lsr #byte(2)
7700 USER( strgebt r3, [r0], #1) @ May fault
7701 - movgt r3, r3, lsr #8
7702 + movgt r3, r7, lsr #byte(3)
7703 USER( strgtbt r3, [r0], #1) @ May fault
7706 .c2u_2fupi: subs r2, r2, #4
7709 - mov r3, r7, lsr #16
7710 + mov r3, r7, pull #16
7712 - orr r3, r3, r7, lsl #16
7713 + orr r3, r3, r7, push #16
7714 USER( strt r3, [r0], #4) @ May fault
7715 mov ip, r0, lsl #32 - PAGE_SHIFT
7717 @@ -182,39 +210,52 @@
7721 + PLD( pld [r1, #12] )
7722 + PLD( pld [r0, #12] )
7723 + PLD( subs ip, ip, #32 )
7724 + PLD( blt .c2u_2cpynopld )
7725 + PLD( pld [r1, #28] )
7726 + PLD( pld [r0, #28] )
7728 -.c2u_2cpy8lp: mov r3, r7, lsr #16
7730 + PLD( pld [r1, #44] )
7731 + PLD( pld [r0, #44] )
7732 +.c2u_2cpynopld: mov r3, r7, pull #16
7733 ldmia r1!, {r4 - r7}
7734 - orr r3, r3, r4, lsl #16
7735 - mov r4, r4, lsr #16
7736 - orr r4, r4, r5, lsl #16
7737 - mov r5, r5, lsr #16
7738 - orr r5, r5, r6, lsl #16
7739 - mov r6, r6, lsr #16
7740 - orr r6, r6, r7, lsl #16
7741 - stmia r0!, {r3 - r6} @ Shouldnt fault
7743 + orr r3, r3, r4, push #16
7744 + mov r4, r4, pull #16
7745 + orr r4, r4, r5, push #16
7746 + mov r5, r5, pull #16
7747 + orr r5, r5, r6, push #16
7748 + mov r6, r6, pull #16
7749 + orr r6, r6, r7, push #16
7750 + stmia r0!, {r3 - r6} @ Shouldnt fault
7752 + PLD( cmn ip, #32 )
7753 + PLD( bge .c2u_2cpynopld )
7754 + PLD( add ip, ip, #32 )
7756 .c2u_2rem8lp: tst ip, #8
7757 - movne r3, r7, lsr #16
7758 + movne r3, r7, pull #16
7759 ldmneia r1!, {r4, r7}
7760 - orrne r3, r3, r4, lsl #16
7761 - movne r4, r4, lsr #16
7762 - orrne r4, r4, r7, lsl #16
7763 + orrne r3, r3, r4, push #16
7764 + movne r4, r4, pull #16
7765 + orrne r4, r4, r7, push #16
7766 stmneia r0!, {r3 - r4} @ Shouldnt fault
7768 - movne r3, r7, lsr #16
7769 + movne r3, r7, pull #16
7771 - orrne r3, r3, r7, lsl #16
7772 + orrne r3, r3, r7, push #16
7773 strnet r3, [r0], #4 @ Shouldnt fault
7776 -.c2u_2nowords: mov r3, r7, lsr #16
7777 +.c2u_2nowords: mov r3, r7, lsr #byte(2)
7781 USER( strbt r3, [r0], #1) @ May fault
7782 - movge r3, r3, lsr #8
7783 + movge r3, r7, lsr #byte(3)
7784 USER( strgebt r3, [r0], #1) @ May fault
7786 USER( strgtbt r3, [r0], #1) @ May fault
7788 .c2u_3fupi: subs r2, r2, #4
7791 - mov r3, r7, lsr #24
7792 + mov r3, r7, pull #24
7794 - orr r3, r3, r7, lsl #8
7795 + orr r3, r3, r7, push #8
7796 USER( strt r3, [r0], #4) @ May fault
7797 mov ip, r0, lsl #32 - PAGE_SHIFT
7799 @@ -236,41 +277,54 @@
7803 + PLD( pld [r1, #12] )
7804 + PLD( pld [r0, #12] )
7805 + PLD( subs ip, ip, #32 )
7806 + PLD( blt .c2u_3cpynopld )
7807 + PLD( pld [r1, #28] )
7808 + PLD( pld [r0, #28] )
7810 -.c2u_3cpy8lp: mov r3, r7, lsr #24
7812 + PLD( pld [r1, #44] )
7813 + PLD( pld [r0, #44] )
7814 +.c2u_3cpynopld: mov r3, r7, pull #24
7815 ldmia r1!, {r4 - r7}
7816 - orr r3, r3, r4, lsl #8
7817 - mov r4, r4, lsr #24
7818 - orr r4, r4, r5, lsl #8
7819 - mov r5, r5, lsr #24
7820 - orr r5, r5, r6, lsl #8
7821 - mov r6, r6, lsr #24
7822 - orr r6, r6, r7, lsl #8
7823 - stmia r0!, {r3 - r6} @ Shouldnt fault
7825 + orr r3, r3, r4, push #8
7826 + mov r4, r4, pull #24
7827 + orr r4, r4, r5, push #8
7828 + mov r5, r5, pull #24
7829 + orr r5, r5, r6, push #8
7830 + mov r6, r6, pull #24
7831 + orr r6, r6, r7, push #8
7832 + stmia r0!, {r3 - r6} @ Shouldnt fault
7834 + PLD( cmn ip, #32 )
7835 + PLD( bge .c2u_3cpynopld )
7836 + PLD( add ip, ip, #32 )
7838 .c2u_3rem8lp: tst ip, #8
7839 - movne r3, r7, lsr #24
7840 + movne r3, r7, pull #24
7841 ldmneia r1!, {r4, r7}
7842 - orrne r3, r3, r4, lsl #8
7843 - movne r4, r4, lsr #24
7844 - orrne r4, r4, r7, lsl #8
7845 + orrne r3, r3, r4, push #8
7846 + movne r4, r4, pull #24
7847 + orrne r4, r4, r7, push #8
7848 stmneia r0!, {r3 - r4} @ Shouldnt fault
7850 - movne r3, r7, lsr #24
7851 + movne r3, r7, pull #24
7853 - orrne r3, r3, r7, lsl #8
7854 + orrne r3, r3, r7, push #8
7855 strnet r3, [r0], #4 @ Shouldnt fault
7858 -.c2u_3nowords: mov r3, r7, lsr #24
7859 +.c2u_3nowords: mov r3, r7, lsr #byte(3)
7863 USER( strbt r3, [r0], #1) @ May fault
7864 - ldrge r3, [r1], #0
7865 + ldrgeb r3, [r1], #1
7866 USER( strgebt r3, [r0], #1) @ May fault
7867 - movgt r3, r3, lsr #8
7868 + ldrgtb r3, [r1], #0
7869 USER( strgtbt r3, [r0], #1) @ May fault
7873 stmfd sp!, {r0, r2, r4 - r7, lr}
7876 + PLD( pld [r1, #0] )
7877 + PLD( pld [r0, #0] )
7879 bne .cfu_dest_not_aligned
7881 @@ -329,13 +385,26 @@
7885 + PLD( pld [r1, #28] )
7886 + PLD( pld [r0, #28] )
7887 + PLD( subs ip, ip, #64 )
7888 + PLD( blt .cfu_0cpynopld )
7889 + PLD( pld [r1, #60] )
7890 + PLD( pld [r0, #60] )
7892 -.cfu_0cpy8lp: ldmia r1!, {r3 - r6} @ Shouldnt fault
7894 + PLD( pld [r1, #92] )
7895 + PLD( pld [r0, #92] )
7896 +.cfu_0cpynopld: ldmia r1!, {r3 - r6} @ Shouldnt fault
7897 stmia r0!, {r3 - r6}
7898 ldmia r1!, {r3 - r6} @ Shouldnt fault
7899 - stmia r0!, {r3 - r6}
7901 + stmia r0!, {r3 - r6}
7903 + PLD( cmn ip, #64 )
7904 + PLD( bge .cfu_0cpynopld )
7905 + PLD( add ip, ip, #64 )
7907 .cfu_0rem8lp: cmn ip, #16
7908 ldmgeia r1!, {r3 - r6} @ Shouldnt fault
7909 stmgeia r0!, {r3 - r6}
7911 .cfu_1fupi: subs r2, r2, #4
7914 - mov r3, r7, lsr #8
7915 + mov r3, r7, pull #8
7916 USER( ldrt r7, [r1], #4) @ May fault
7917 - orr r3, r3, r7, lsl #24
7918 + orr r3, r3, r7, push #24
7920 mov ip, r1, lsl #32 - PAGE_SHIFT
7922 @@ -387,50 +456,63 @@
7926 + PLD( pld [r1, #12] )
7927 + PLD( pld [r0, #12] )
7928 + PLD( subs ip, ip, #32 )
7929 + PLD( blt .cfu_1cpynopld )
7930 + PLD( pld [r1, #28] )
7931 + PLD( pld [r0, #28] )
7933 -.cfu_1cpy8lp: mov r3, r7, lsr #8
7935 + PLD( pld [r1, #44] )
7936 + PLD( pld [r0, #44] )
7937 +.cfu_1cpynopld: mov r3, r7, pull #8
7938 ldmia r1!, {r4 - r7} @ Shouldnt fault
7939 - orr r3, r3, r4, lsl #24
7940 - mov r4, r4, lsr #8
7941 - orr r4, r4, r5, lsl #24
7942 - mov r5, r5, lsr #8
7943 - orr r5, r5, r6, lsl #24
7944 - mov r6, r6, lsr #8
7945 - orr r6, r6, r7, lsl #24
7946 - stmia r0!, {r3 - r6}
7948 + orr r3, r3, r4, push #24
7949 + mov r4, r4, pull #8
7950 + orr r4, r4, r5, push #24
7951 + mov r5, r5, pull #8
7952 + orr r5, r5, r6, push #24
7953 + mov r6, r6, pull #8
7954 + orr r6, r6, r7, push #24
7955 + stmia r0!, {r3 - r6}
7957 + PLD( cmn ip, #32 )
7958 + PLD( bge .cfu_1cpynopld )
7959 + PLD( add ip, ip, #32 )
7961 .cfu_1rem8lp: tst ip, #8
7962 - movne r3, r7, lsr #8
7963 + movne r3, r7, pull #8
7964 ldmneia r1!, {r4, r7} @ Shouldnt fault
7965 - orrne r3, r3, r4, lsl #24
7966 - movne r4, r4, lsr #8
7967 - orrne r4, r4, r7, lsl #24
7968 + orrne r3, r3, r4, push #24
7969 + movne r4, r4, pull #8
7970 + orrne r4, r4, r7, push #24
7971 stmneia r0!, {r3 - r4}
7973 - movne r3, r7, lsr #8
7974 + movne r3, r7, pull #8
7975 USER( ldrnet r7, [r1], #4) @ May fault
7976 - orrne r3, r3, r7, lsl #24
7977 + orrne r3, r3, r7, push #24
7981 -.cfu_1nowords: mov r3, r7, lsr #8
7982 +.cfu_1nowords: mov r3, r7, lsr #byte(1)
7987 - movge r3, r3, lsr #8
7988 + movge r3, r7, lsr #byte(2)
7990 - movgt r3, r3, lsr #8
7991 + movgt r3, r7, lsr #byte(3)
7995 .cfu_2fupi: subs r2, r2, #4
7998 - mov r3, r7, lsr #16
7999 + mov r3, r7, pull #16
8000 USER( ldrt r7, [r1], #4) @ May fault
8001 - orr r3, r3, r7, lsl #16
8002 + orr r3, r3, r7, push #16
8004 mov ip, r1, lsl #32 - PAGE_SHIFT
8006 @@ -441,39 +523,52 @@
8010 + PLD( pld [r1, #12] )
8011 + PLD( pld [r0, #12] )
8012 + PLD( subs ip, ip, #32 )
8013 + PLD( blt .cfu_2cpynopld )
8014 + PLD( pld [r1, #28] )
8015 + PLD( pld [r0, #28] )
8017 -.cfu_2cpy8lp: mov r3, r7, lsr #16
8019 + PLD( pld [r1, #44] )
8020 + PLD( pld [r0, #44] )
8021 +.cfu_2cpynopld: mov r3, r7, pull #16
8022 ldmia r1!, {r4 - r7} @ Shouldnt fault
8023 - orr r3, r3, r4, lsl #16
8024 - mov r4, r4, lsr #16
8025 - orr r4, r4, r5, lsl #16
8026 - mov r5, r5, lsr #16
8027 - orr r5, r5, r6, lsl #16
8028 - mov r6, r6, lsr #16
8029 - orr r6, r6, r7, lsl #16
8030 - stmia r0!, {r3 - r6}
8032 + orr r3, r3, r4, push #16
8033 + mov r4, r4, pull #16
8034 + orr r4, r4, r5, push #16
8035 + mov r5, r5, pull #16
8036 + orr r5, r5, r6, push #16
8037 + mov r6, r6, pull #16
8038 + orr r6, r6, r7, push #16
8039 + stmia r0!, {r3 - r6}
8041 + PLD( cmn ip, #32 )
8042 + PLD( bge .cfu_2cpynopld )
8043 + PLD( add ip, ip, #32 )
8045 .cfu_2rem8lp: tst ip, #8
8046 - movne r3, r7, lsr #16
8047 + movne r3, r7, pull #16
8048 ldmneia r1!, {r4, r7} @ Shouldnt fault
8049 - orrne r3, r3, r4, lsl #16
8050 - movne r4, r4, lsr #16
8051 - orrne r4, r4, r7, lsl #16
8052 + orrne r3, r3, r4, push #16
8053 + movne r4, r4, pull #16
8054 + orrne r4, r4, r7, push #16
8055 stmneia r0!, {r3 - r4}
8057 - movne r3, r7, lsr #16
8058 + movne r3, r7, pull #16
8059 USER( ldrnet r7, [r1], #4) @ May fault
8060 - orrne r3, r3, r7, lsl #16
8061 + orrne r3, r3, r7, push #16
8065 -.cfu_2nowords: mov r3, r7, lsr #16
8066 +.cfu_2nowords: mov r3, r7, lsr #byte(2)
8071 - movge r3, r3, lsr #8
8072 + movge r3, r7, lsr #byte(3)
8074 USER( ldrgtbt r3, [r1], #0) @ May fault
8077 .cfu_3fupi: subs r2, r2, #4
8080 - mov r3, r7, lsr #24
8081 + mov r3, r7, pull #24
8082 USER( ldrt r7, [r1], #4) @ May fault
8083 - orr r3, r3, r7, lsl #8
8084 + orr r3, r3, r7, push #8
8086 mov ip, r1, lsl #32 - PAGE_SHIFT
8088 @@ -495,41 +590,54 @@
8092 + PLD( pld [r1, #12] )
8093 + PLD( pld [r0, #12] )
8094 + PLD( subs ip, ip, #32 )
8095 + PLD( blt .cfu_3cpynopld )
8096 + PLD( pld [r1, #28] )
8097 + PLD( pld [r0, #28] )
8099 -.cfu_3cpy8lp: mov r3, r7, lsr #24
8101 + PLD( pld [r1, #44] )
8102 + PLD( pld [r0, #44] )
8103 +.cfu_3cpynopld: mov r3, r7, pull #24
8104 ldmia r1!, {r4 - r7} @ Shouldnt fault
8105 - orr r3, r3, r4, lsl #8
8106 - mov r4, r4, lsr #24
8107 - orr r4, r4, r5, lsl #8
8108 - mov r5, r5, lsr #24
8109 - orr r5, r5, r6, lsl #8
8110 - mov r6, r6, lsr #24
8111 - orr r6, r6, r7, lsl #8
8112 + orr r3, r3, r4, push #8
8113 + mov r4, r4, pull #24
8114 + orr r4, r4, r5, push #8
8115 + mov r5, r5, pull #24
8116 + orr r5, r5, r6, push #8
8117 + mov r6, r6, pull #24
8118 + orr r6, r6, r7, push #8
8119 stmia r0!, {r3 - r6}
8122 + PLD( cmn ip, #32 )
8123 + PLD( bge .cfu_3cpynopld )
8124 + PLD( add ip, ip, #32 )
8126 .cfu_3rem8lp: tst ip, #8
8127 - movne r3, r7, lsr #24
8128 + movne r3, r7, pull #24
8129 ldmneia r1!, {r4, r7} @ Shouldnt fault
8130 - orrne r3, r3, r4, lsl #8
8131 - movne r4, r4, lsr #24
8132 - orrne r4, r4, r7, lsl #8
8133 + orrne r3, r3, r4, push #8
8134 + movne r4, r4, pull #24
8135 + orrne r4, r4, r7, push #8
8136 stmneia r0!, {r3 - r4}
8138 - movne r3, r7, lsr #24
8139 + movne r3, r7, pull #24
8140 USER( ldrnet r7, [r1], #4) @ May fault
8141 - orrne r3, r3, r7, lsl #8
8142 + orrne r3, r3, r7, push #8
8146 -.cfu_3nowords: mov r3, r7, lsr #24
8147 +.cfu_3nowords: mov r3, r7, lsr #byte(3)
8152 -USER( ldrget r3, [r1], #0) @ May fault
8153 +USER( ldrgebt r3, [r1], #1) @ May fault
8155 - movgt r3, r3, lsr #8
8156 +USER( ldrgtbt r3, [r1], #1) @ May fault
8161 ldr r1, [sp], #4 @ unsigned long count
8162 subs r4, r1, r2 @ bytes left to copy
8164 - blne SYMBOL_NAME(__memzero)
8167 LOADREGS(fd,sp!, {r4 - r7, pc})
8170 +++ linux-2.4.27/arch/arm/mach-pxa/Makefile
8173 +# Makefile for the linux kernel.
8175 +# Note! Dependencies are done automagically by 'make dep', which also
8176 +# removes any old dependencies. DON'T put your own dependencies here
8177 +# unless it's something special (ie not a .c file).
8179 +USE_STANDARD_AS_RULE := true
8188 +export-objs := generic.o irq.o dma.o sa1111.o \
8189 + usb_ctl.o usb_recv.o usb_send.o
8191 +# Common support (must be linked before board specific support)
8192 +obj-y += generic.o irq.o dma.o
8193 +obj-$(CONFIG_SA1111) += sa1111.o
8195 +# Specific board support
8196 +obj-$(CONFIG_ARCH_CSB226) += csb226.o
8197 +obj-$(CONFIG_ARCH_INNOKOM) += innokom.o
8198 +obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
8199 +obj-$(CONFIG_ARCH_PXA_CERF) += cerf.o
8200 +obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
8201 +obj-$(CONFIG_ARCH_TRIZEPS2) += trizeps2.o
8203 +# Support for blinky lights
8205 +leds-$(CONFIG_ARCH_CSB226) += leds-csb226.o
8206 +leds-$(CONFIG_ARCH_INNOKOM) += leds-innokom.o
8207 +leds-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o
8208 +leds-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
8209 +leds-$(CONFIG_ARCH_PXA_CERF) += leds-cerf.o
8211 +obj-$(CONFIG_LEDS) += $(leds-y)
8213 +# PXA USB client support
8214 +list-multi += pxausb_core.o
8215 +pxausb_core-objs := usb_ctl.o usb_ep0.o usb_recv.o usb_send.o
8216 +obj-$(CONFIG_PXA_USB) += pxausb_core.o
8217 +obj-$(CONFIG_PXA_USB_NETLINK) += usb-eth.o
8218 +obj-$(CONFIG_PXA_USB_CHAR) += usb-char.o
8221 +obj-$(CONFIG_PM) += pm.o sleep.o
8222 +obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
8224 +include $(TOPDIR)/Rules.make
8226 +pxausb_core.o: $(pxausb_core-objs)
8227 + $(LD) -r -o $@ $(pxausb_core-objs)
8229 +++ linux-2.4.27/arch/arm/mach-pxa/cerf.c
8232 + * linux/arch/arm/mach-pxa/cerf.c
8234 + * This program is free software; you can redistribute it and/or modify
8235 + * it under the terms of the GNU General Public License version 2 as
8236 + * published by the Free Software Foundation.
8238 +#include <linux/init.h>
8239 +#include <linux/major.h>
8240 +#include <linux/fs.h>
8241 +#include <linux/interrupt.h>
8242 +#include <linux/sched.h>
8244 +#include <asm/types.h>
8245 +#include <asm/setup.h>
8246 +#include <asm/memory.h>
8247 +#include <asm/mach-types.h>
8248 +#include <asm/hardware.h>
8249 +#include <asm/irq.h>
8251 +#include <asm/mach/arch.h>
8252 +#include <asm/mach/map.h>
8253 +#include <asm/mach/irq.h>
8255 +#include <asm/io.h>
8256 +#include <asm/arch/irq.h>
8258 +#include "generic.h"
8261 + * Set this to zero to remove all the debug statements via
8262 + * dead code elimination.
8264 +#define DEBUGGING 1
8267 +static unsigned int cerf_debug = DEBUGGING;
8269 +#define cerf_debug 0
8272 +static void __init cerf_init_irq(void)
8276 + if( cerf_debug > 1)
8279 + GPDR0 = 0xc05b9130;
8280 + GPDR1 = 0xfcffab82;
8281 + GPDR2 = 0x0001ffff;
8284 + printk(KERN_INFO "Pin directions:\n");
8285 + printk(KERN_INFO "GPDR0 0x%08x\n", GPDR0);
8286 + printk(KERN_INFO "GPDR1 0x%08x\n", GPDR1);
8287 + printk(KERN_INFO "GPDR2 0x%08x\n", GPDR2);
8289 + printk(KERN_INFO "Pin State:\n");
8290 + printk(KERN_INFO "GPLR0 0x%08x\n", GPLR0);
8291 + printk(KERN_INFO "GPLR1 0x%08x\n", GPLR1);
8292 + printk(KERN_INFO "GPLR2 0x%08x\n", GPLR2);
8294 + printk(KERN_INFO "Rising Edge:\n");
8295 + printk(KERN_INFO "GRER0 0x%08x\n", GRER0);
8296 + printk(KERN_INFO "GRER1 0x%08x\n", GRER1);
8297 + printk(KERN_INFO "GRER2 0x%08x\n", GRER2);
8299 + printk(KERN_INFO "Falling Edge:\n");
8300 + printk(KERN_INFO "GFER0 0x%08x\n", GFER0);
8301 + printk(KERN_INFO "GFER1 0x%08x\n", GFER1);
8302 + printk(KERN_INFO "GFER2 0x%08x\n", GFER2);
8305 + /* set_GPIO_IRQ_edge has to be called before an irq can be requested */
8306 + set_GPIO_IRQ_edge( 0, GPIO_FALLING_EDGE); /* CPLD */
8307 +#ifdef CONFIG_PXA_CERF_PDA
8308 + set_GPIO_IRQ_edge( 2, GPIO_RISING_EDGE); /* UART B Interrupt */
8309 + set_GPIO_IRQ_edge( 3, GPIO_RISING_EDGE); /* UART A Interrupt */
8310 + set_GPIO_IRQ_edge( 32, GPIO_RISING_EDGE); /* UCB1400 Interrupt */
8312 + set_GPIO_IRQ_edge( 14, GPIO_FALLING_EDGE); /* PCMCIA Card Detect */
8313 + set_GPIO_IRQ_edge( 21, GPIO_RISING_EDGE); /* Ethernet Interrupt */
8316 +static int __init cerf_init(void)
8319 + * All of the code that was here was SA1111 init code
8320 + * which we do not have.
8325 +__initcall(cerf_init);
8328 +fixup_cerf(struct machine_desc *desc, struct param_struct *params,
8329 + char **cmdline, struct meminfo *mi)
8331 + SET_BANK (0, CERF_RAM_BASE, CERF_RAM_SIZE);
8334 +#if 0 // Enable this stuff if you plan on not using jffs2
8335 + setup_ramdisk (1, 0, 0, 8192);
8336 + setup_initrd (__phys_to_virt(0xa1000000), 4*1024*1024);
8337 + ROOT_DEV = MKDEV(RAMDISK_MAJOR,0);
8342 + * IO map for the devices.
8344 +static struct map_desc cerf_io_desc[] __initdata = {
8345 + /* virtual physical length domain r w c b */
8346 + { CERF_FLASH_BASE , CERF_FLASH_PHYS , CERF_FLASH_SIZE , DOMAIN_IO, 0, 1, 0, 0 },
8347 + { CERF_ETH_BASE , CERF_ETH_PHYS , CERF_ETH_SIZE , DOMAIN_IO, 0, 1, 0, 0 },
8348 +#ifdef CONFIG_PXA_CERF_PDA
8349 + { CERF_BT_BASE , CERF_BT_PHYS , CERF_BT_SIZE , DOMAIN_IO, 0, 1, 0, 0 },
8350 + { CERF_SERIAL_BASE, CERF_SERIAL_PHYS, CERF_SERIAL_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
8351 + { CERF_CPLD_BASE , CERF_CPLD_PHYS , CERF_CPLD_SIZE , DOMAIN_IO, 0, 1, 0, 0 },
8357 +static void __init cerf_map_io(void)
8360 + iotable_init(cerf_io_desc);
8362 + if( cerf_debug > 1)
8364 + printk(KERN_INFO "origMCS0 = 0x%08x\n", MSC0);
8365 + printk(KERN_INFO "origMCS1 = 0x%08x\n", MSC1);
8366 + printk(KERN_INFO "origMCS2 = 0x%08x\n", MSC2);
8369 + /* setup memory timing for CS0/1 */
8370 + MSC0 = MSC_CS(0, MSC_RBUFF(MSC_RBUFF_SLOW) |
8376 +#ifdef CONFIG_PXA_CERF_PDA
8377 + MSC_CS(1, MSC_RBUFF(MSC_RBUFF_SLOW) |
8383 +#elif defined(CONFIG_PXA_CERF_BOARD)
8384 + MSC_CS(1, MSC_RBUFF(MSC_RBUFF_SLOW) |
8391 + printk(KERN_INFO "MCS0 = 0x%08x\n", MSC0);
8393 + /* setup memory timing for CS2/3 */
8394 + MSC1 = MSC_CS(2, MSC_RBUFF(MSC_RBUFF_SLOW) |
8400 + MSC_CS(3, MSC_RBUFF(MSC_RBUFF_SLOW) |
8406 + printk(KERN_INFO "MCS1 = 0x%08x\n", MSC1);
8408 + /* setup memory timing for CS4/5 */
8409 + MSC2 = MSC_CS(4, MSC_RBUFF(MSC_RBUFF_SLOW) |
8415 + MSC_CS(5, MSC_RBUFF(MSC_RBUFF_SLOW) |
8421 + printk(KERN_INFO "MCS2 = 0x%08x\n", MSC2);
8423 +#ifdef CONFIG_SOUND_PXA_AC97
8424 + printk(KERN_INFO "Enabling sound amp for pxa cerf pda.\n");
8425 + outw( CERF_PDA_SOUND_ENABLE, CERF_CPLD_BASE+CERF_PDA_CPLD_SOUND_ENA);
8428 +#ifdef CONFIG_FB_PXA
8429 + printk(KERN_INFO "Setting LCD to brightness to %d/15\n", CERF_PDA_DEFAULT_BRIGHTNESS);
8430 + outw( CERF_PDA_DEFAULT_BRIGHTNESS, CERF_CPLD_BASE+CERF_PDA_CPLD_BRIGHTNESS);
8434 + /* Enable IrDA UART (SIR)*/
8435 + CKEN |= CKEN5_STUART;
8437 + /* We want to get our goods from the STUART */
8438 + set_GPIO_mode(GPIO46_STRXD_MD);
8439 + set_GPIO_mode(GPIO47_STTXD_MD);
8441 + /* make sure FIR ICP is off */
8444 + /* configure STUART to for SIR
8445 + * NOTE: RCVEIR and XMITIR must not be set at the same time!
8446 + * Start with receive in IR mode, and switch transmit to IR only
8447 + * when we need to send something in serial driver.
8449 + STISR = IrSR_IR_RECEIVE_ON;
8453 + /* Connect FIR ICP to GPIO pins */
8454 + CKEN |= CKEN13_FICP;
8455 + set_GPIO_mode(GPIO46_ICPRXD_MD);
8456 + set_GPIO_mode(GPIO47_ICPTXD_MD);
8457 + ICCR0 = 0x1 | 0x18; //ICP unit enable
8461 + /* Enable BT UART */
8462 + CKEN |= CKEN7_BTUART;
8463 + set_GPIO_mode(GPIO42_BTRXD_MD);
8464 + set_GPIO_mode(GPIO43_BTTXD_MD);
8465 + set_GPIO_mode(GPIO44_BTCTS_MD);
8466 + set_GPIO_mode(GPIO45_BTRTS_MD);
8469 + if( cerf_debug > 1)
8471 + printk(KERN_INFO "GPDR0 0x%08x\n", GPDR0);
8472 + printk(KERN_INFO "GPDR1 0x%08x\n", GPDR1);
8473 + printk(KERN_INFO "GPDR2 0x%08x\n", GPDR2);
8474 + printk(KERN_INFO "GPLR0 0x%08x\n", GPLR0);
8475 + printk(KERN_INFO "GPLR1 0x%08x\n", GPLR1);
8476 + printk(KERN_INFO "GPLR2 0x%08x\n", GPLR2);
8477 + printk(KERN_INFO "GAFR0_L 0x%08x\n", GAFR0_L);
8478 + printk(KERN_INFO "GAFR0_U 0x%08x\n", GAFR0_U);
8479 + printk(KERN_INFO "GAFR1_L 0x%08x\n", GAFR1_L);
8480 + printk(KERN_INFO "GAFR1_U 0x%08x\n", GAFR1_U);
8481 + printk(KERN_INFO "GAFR2_L 0x%08x\n", GAFR2_L);
8482 + printk(KERN_INFO "GAFR2_U 0x%08x\n", GAFR2_U);
8483 + printk(KERN_INFO "CKEN = 0x%08x\n", CKEN);
8484 + printk(KERN_INFO "ICCR0 = 0x%08x\n", ICCR0);
8485 + printk(KERN_INFO "STISR = 0x%08x\n", STISR);
8489 +MACHINE_START(PXA_CERF, "CerfBoard PXA Reference Board")
8490 + MAINTAINER("Intrinsyc Software Inc.")
8491 + BOOT_MEM(0xa0000000, 0x40000000, 0xfc000000)
8492 + BOOT_PARAMS(0xa0000100)
8494 + MAPIO(cerf_map_io)
8495 + INITIRQ(cerf_init_irq)
8498 +++ linux-2.4.27/arch/arm/mach-pxa/cpu-pxa.c
8501 + * linux/arch/arm/mach-pxa/cpu-pxa.c
8503 + * Copyright (C) 2002,2003 Intrinsyc Software
8505 + * This program is free software; you can redistribute it and/or modify
8506 + * it under the terms of the GNU General Public License version 2 as
8507 + * published by the Free Software Foundation.
8510 + * 31-Jul-2002 : Initial version [FB]
8511 + * 29-Jan-2003 : added PXA255 support [FB]
8515 + * Quote from erratum 134:
8516 + * ""If the operation of these peripherals would be adversely affected,
8517 + * then these peripherals would have to be disabled during a frequency
8518 + * change. (MMC,FFUART,STUART,BTUART,IRDA,SSP,UDC,AC97)""
8520 + * This sounds like they are not sure what the bug is...
8521 + * If you run into problems with any of these peripherals, the effected
8522 + * driver should register with cpu freq notification and disable/enable
8523 + * the peripheral on CPUFREQ_PRECHANGE and CPUFREQ_POSTCHANGE.
8525 + * So far I've tested this code only under light load. It works for me.
8528 + * - determine min/max freq at runtime
8529 + * - determine pxbus value at runtime
8533 +#include <linux/kernel.h>
8534 +#include <linux/module.h>
8535 +#include <linux/sched.h>
8536 +#include <linux/init.h>
8537 +#include <linux/cpufreq.h>
8539 +#include <asm/hardware.h>
8541 +#define DEBUGGING 1
8544 +static unsigned int freq_debug = DEBUGGING;
8546 +#define freq_debug 0
8552 + unsigned int cccr;
8553 + unsigned int pxbus;
8556 +#define CCLKCFG_TURBO 0x1
8557 +#define CCLKCFG_FCS 0x2
8559 +#define PXA250_REV_A1 0x1
8560 +#define PXA250_REV_B2 0x4
8561 +#define PXA25x_MIN_FREQ 99000
8563 +//#define PXA25x_ALLOW_OVERCLOCK
8565 +#ifdef PXA25x_ALLOW_OVERCLOCK
8566 +#warning *** Overclocking enabled - this may fry your hardware - you have been warned ***
8568 +#define PXA25x_MAX_FREQ 471000
8571 +#define PXA25x_MAX_FREQ 400000
8574 +/* If CONFIG_CPU_FREQ is turned on but we find (at runtime)
8575 + * we can't support scaling, try to handle requests gracefully.
8577 +static int supported;
8579 +static pxa_freqs_t pxa250_valid_freqs[] =
8581 + {199100, 0x141, 99}, /* mem= 99, run=199, turbo=199, PXbus= 99 */
8582 + {298600, 0x1c1, 99}, /* mem= 99, run=199, turbo=298, PXbus= 99 */
8583 + {398100, 0x241, 99}, /* mem= 99, run=199, turbo=398, PXbus= 99 */
8587 +static pxa_freqs_t pxa255_valid_freqs[] =
8589 + { 99000, 0x121, 50}, /* mem= 99, run= 99, turbo= 99, PXbus= 50 */
8590 +OC( {118000, 0x122, 59},)/* mem=118, run=118, turbo=118, PXbus= 59 OC'd mem */
8591 + {199100, 0x141, 99}, /* mem= 99, run=199, turbo=199, PXbus= 99 */
8592 +OC( {236000, 0x142,118},)/* mem=118, run=236, turbo=236, PXbus=118 OC'd mem */
8593 + {298600, 0x1c1, 99}, /* mem= 99, run=199, turbo=298, PXbus= 99 */
8594 +OC( {354000, 0x1c2,118},)/* mem=118, run=236, turbo=354, PXbus=118 OC'd mem */
8595 + {398099, 0x241, 99}, /* mem= 99, run=199, turbo=398, PXbus= 99 */
8596 + {398100, 0x161,196}, /* mem= 99, run=398, turbo=398, PXbus=196 */
8597 +OC( {471000, 0x162,236},)/* mem=118, run=471, turbo=471, PXbus=236 OC'd mem/core/bus */
8601 +static pxa_freqs_t *pxa_valid_freqs;
8603 +/* This should be called with a valid freq point that was
8604 + * obtained via pxa_validate_speed
8606 +static pxa_freqs_t * pxa_get_freq_info( unsigned int khz)
8609 + while( pxa_valid_freqs[i].khz)
8611 + if( pxa_valid_freqs[i].khz == khz)
8612 + return &pxa_valid_freqs[i];
8616 + /* shouldn't get here */
8620 +/* find a valid frequency point */
8621 +static unsigned int pxa_validate_speed(unsigned int khz)
8624 + unsigned int vfreq = 0;
8625 + while( pxa_valid_freqs[i].khz && (khz >= pxa_valid_freqs[i].khz))
8627 + vfreq = pxa_valid_freqs[i].khz;
8633 +/* This should be called with a valid freq point that was
8634 + * obtained via pxa_validate_speed
8636 +static void pxa_setspeed(unsigned int khz)
8638 + unsigned long flags;
8639 + unsigned int unused;
8640 + void *ramstart = phys_to_virt(0xa0000000);
8641 + pxa_freqs_t *freq_info;
8643 + if( ! supported) return;
8645 + freq_info = pxa_get_freq_info( khz);
8647 + if( ! freq_info) return;
8649 + CCCR = freq_info->cccr;
8651 + printk(KERN_INFO "Changing CPU frequency to %d Mhz (PXbus=%dMhz).\n",
8652 + khz/1000, freq_info->pxbus);
8654 + local_irq_save(flags);
8655 + __asm__ __volatile__("\
8656 + ldr r4, [%1] @load MDREFR \n\
8660 + mcr p14, 0, %2, c6, c0, 0 @ set CCLKCFG[FCS] \n\
8662 + @ restart sdcke 0 / 1 \n\
8663 + bic r5, r4, #(0x00001000 | 0x00008000) @ MDREFR_E0PIN | MDREFR_E1PIN \n\
8664 + str r5, [%1] @clear \n\
8665 + str r4, [%1] @restore \n\
8667 + @ Generate refresh cycles for all banks \n\
8683 + : "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart)
8685 + local_irq_restore(flags);
8688 +static int pxa_init_freqs( void)
8691 + asm("mrc%? p15, 0, %0, c0, c0" : "=r" (cpu_ver));
8693 + if( (cpu_ver & 0xf) <= PXA250_REV_A1)
8698 + if( (cpu_ver & 0xf) <= PXA250_REV_B2)
8700 + if( freq_debug) printk(KERN_INFO "Using PXA250 frequency points.\n");
8701 + pxa_valid_freqs = pxa250_valid_freqs;
8703 + else /* C0 and above */
8705 + if( freq_debug) printk(KERN_INFO "Using PXA255 frequency points.\n");
8706 + pxa_valid_freqs = pxa255_valid_freqs;
8712 +static int __init pxa_clk_init(void)
8714 + if( pxa_init_freqs())
8716 + if( freq_debug) printk(KERN_INFO "Registering CPU frequency change support.\n");
8719 + cpufreq_init( get_clk_frequency_khz(0), PXA25x_MIN_FREQ, PXA25x_MAX_FREQ);
8720 + cpufreq_setfunctions(pxa_validate_speed, pxa_setspeed);
8724 + if( freq_debug) printk(KERN_INFO "Disabling CPU frequency change support.\n");
8725 + /* Note that we have to initialize the generic code in order to
8726 + * release a lock (cpufreq_sem). Any registration for freq changes
8727 + * (e.g. lcd driver) will get blocked otherwise.
8729 + cpufreq_init( 0, 0, 0);
8730 + cpufreq_setfunctions(pxa_validate_speed, pxa_setspeed);
8736 +module_init(pxa_clk_init);
8738 +MODULE_AUTHOR ("Intrinsyc Software Inc.");
8739 +MODULE_LICENSE("GPL");
8741 +++ linux-2.4.27/arch/arm/mach-pxa/csb226.c
8744 + * linux/arch/arm/mach-pxa/csb226.c
8746 + * (c) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
8748 + * This program is free software; you can redistribute it and/or modify
8749 + * it under the terms of the GNU General Public License as published by
8750 + * the Free Software Foundation; either version 2 of the License, or
8751 + * (at your option) any later version.
8753 + * This program is distributed in the hope that it will be useful,
8754 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8755 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8756 + * GNU General Public License for more details.
8758 + * You should have received a copy of the GNU General Public License
8759 + * along with this program; if not, write to the Free Software
8760 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8763 +#include <linux/init.h>
8764 +#include <linux/major.h>
8765 +#include <linux/fs.h>
8766 +#include <linux/interrupt.h>
8767 +#include <linux/sched.h>
8769 +#include <asm/types.h>
8770 +#include <asm/setup.h>
8771 +#include <asm/memory.h>
8772 +#include <asm/mach-types.h>
8773 +#include <asm/hardware.h>
8774 +#include <asm/irq.h>
8776 +#include <asm/mach/arch.h>
8777 +#include <asm/mach/map.h>
8778 +#include <asm/mach/irq.h>
8780 +#include <asm/arch/irq.h>
8781 +#include <asm/arch/irqs.h>
8782 +#include <asm/hardware/sa1111.h>
8784 +#include "generic.h"
8786 +static unsigned long csb226_irq_en_mask;
8788 +static void csb226_mask_and_ack_irq(unsigned int irq)
8790 + int csb226_irq = (irq - CSB226_IRQ(0));
8791 + csb226_irq_en_mask &= ~(1 << csb226_irq);
8792 + CSB226_IRQ_MASK_EN &= ~(1 << csb226_irq);
8793 + CSB226_IRQ_SET_CLR &= ~(1 << csb226_irq);
8796 +static void csb226_mask_irq(unsigned int irq)
8798 + int csb226_irq = (irq - CSB226_IRQ(0));
8799 + csb226_irq_en_mask &= ~(1 << csb226_irq);
8800 + CSB226_IRQ_MASK_EN &= ~(1 << csb226_irq);
8803 +static void csb226_unmask_irq(unsigned int irq)
8805 + int csb226_irq = (irq - CSB226_IRQ(0));
8806 + csb226_irq_en_mask |= (1 << csb226_irq);
8807 + CSB226_IRQ_MASK_EN |= (1 << csb226_irq);
8810 +void csb226_irq_demux(int irq, void *dev_id, struct pt_regs *regs)
8812 + unsigned long irq_status;
8815 + while ((irq_status = CSB226_IRQ_SET_CLR & csb226_irq_en_mask)) {
8816 + for (i = 0; i < 6; i++) {
8817 + if(irq_status & (1<<i))
8818 + do_IRQ(CSB226_IRQ(i), regs);
8823 +/* FIXME: this should not be necessary on csb226 */
8824 +static struct irqaction csb226_irq = {
8825 + name: "CSB226 FPGA",
8826 + handler: csb226_irq_demux,
8827 + flags: SA_INTERRUPT
8830 +static void __init csb226_init_irq(void)
8836 + /* setup extra csb226 irqs */
8838 + for(irq = CSB226_IRQ(0); irq <= CSB226_IRQ(5); irq++)
8840 + irq_desc[irq].valid = 1;
8841 + irq_desc[irq].probe_ok = 1;
8842 + irq_desc[irq].mask_ack = csb226_mask_and_ack_irq;
8843 + irq_desc[irq].mask = csb226_mask_irq;
8844 + irq_desc[irq].unmask = csb226_unmask_irq;
8847 + set_GPIO_IRQ_edge(GPIO_CSB226_IRQ, GPIO_FALLING_EDGE);
8848 + setup_arm_irq(IRQ_GPIO_CSB226_IRQ, &csb226_irq);
8852 +/* FIXME: not necessary on CSB226? */
8853 +static int __init csb226_init(void)
8860 +__initcall(csb226_init);
8863 +fixup_csb226(struct machine_desc *desc, struct param_struct *params,
8864 + char **cmdline, struct meminfo *mi)
8866 + SET_BANK (0, 0xa0000000, 64*1024*1024);
8869 + setup_ramdisk (1, 0, 0, 8192);
8870 + setup_initrd (__phys_to_virt(0xa1000000), 4*1024*1024);
8871 + ROOT_DEV = MKDEV(RAMDISK_MAJOR,0);
8875 +/* FIXME: shouldn't this be moved to arch/arm/mach-pxa/mm.c? [RS] */
8876 +static struct map_desc csb226_io_desc[] __initdata = {
8877 + /* virtual physical length domain r w c b */
8878 +// { 0xf4000000, 0x04000000, 0x00ffffff, DOMAIN_IO, 1, 1, 0, 0 }, /* HT4562B PS/2 controller */
8879 + { 0xf8000000, 0x08000000, 1024*1024, DOMAIN_IO, 0, 1, 0, 0 }, /* CS8900 LAN controller */
8880 +// { 0xe0000000, 0x20000000, 0x0fffffff, DOMAIN_IO, 1, 1, 0, 0 }, /* CompactFlash */
8882 + { 0xf0000000, 0x08000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* CPLD */
8883 + { 0xf1000000, 0x0c000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* LAN91C96 IO */
8884 + { 0xf1100000, 0x0e000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* LAN91C96 Attr */
8885 + { 0xf4000000, 0x10000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA1111 */
8890 +static void __init csb226_map_io(void)
8893 + iotable_init(csb226_io_desc);
8895 + /* This enables the BTUART */
8896 + CKEN |= CKEN7_BTUART;
8897 + set_GPIO_mode(GPIO42_BTRXD_MD);
8898 + set_GPIO_mode(GPIO43_BTTXD_MD);
8899 + set_GPIO_mode(GPIO44_BTCTS_MD);
8900 + set_GPIO_mode(GPIO45_BTRTS_MD);
8902 + /* This is for the CS8900 chip select */
8903 + set_GPIO_mode(GPIO78_nCS_2_MD);
8905 + /* setup sleep mode values */
8906 + PWER = 0x00000002;
8907 + PFER = 0x00000000;
8908 + PRER = 0x00000002;
8909 + PGSR0 = 0x00008000;
8910 + PGSR1 = 0x003F0202;
8911 + PGSR2 = 0x0001C000;
8912 + PCFR |= PCFR_OPDE;
8915 +MACHINE_START(CSB226, "Cogent CSB226 Development Platform")
8916 + MAINTAINER("Robert Schwebel, Pengutronix")
8917 + BOOT_MEM(0xa0000000, 0x40000000, io_p2v(0x40000000))
8918 + BOOT_PARAMS(0xa0000100)
8919 + FIXUP(fixup_csb226)
8920 + MAPIO(csb226_map_io)
8921 + INITIRQ(csb226_init_irq)
8924 +++ linux-2.4.27/arch/arm/mach-pxa/dma.c
8927 + * linux/arch/arm/mach-pxa/dma.c
8929 + * PXA DMA registration and IRQ dispatching
8931 + * Author: Nicolas Pitre
8932 + * Created: Nov 15, 2001
8933 + * Copyright: MontaVista Software Inc.
8935 + * This program is free software; you can redistribute it and/or modify
8936 + * it under the terms of the GNU General Public License version 2 as
8937 + * published by the Free Software Foundation.
8940 +#include <linux/module.h>
8941 +#include <linux/init.h>
8942 +#include <linux/kernel.h>
8943 +#include <linux/sched.h>
8944 +#include <linux/errno.h>
8946 +#include <asm/system.h>
8947 +#include <asm/irq.h>
8948 +#include <asm/hardware.h>
8949 +#include <asm/dma.h>
8952 +static struct dma_channel {
8954 + void (*irq_handler)(int, void *, struct pt_regs *);
8956 +} dma_channels[16];
8959 +int pxa_request_dma (char *name, pxa_dma_prio prio,
8960 + void (*irq_handler)(int, void *, struct pt_regs *),
8963 + unsigned long flags;
8966 + /* basic sanity checks */
8967 + if (!name || !irq_handler)
8970 + local_irq_save(flags);
8972 + /* try grabbing a DMA channel with the requested priority */
8973 + for (i = prio; i < prio + (prio == DMA_PRIO_LOW) ? 8 : 4; i++) {
8974 + if (!dma_channels[i].name) {
8981 + /* requested prio group is full, try hier priorities */
8982 + for (i = prio-1; i >= 0; i--) {
8983 + if (!dma_channels[i].name) {
8991 + DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
8992 + dma_channels[i].name = name;
8993 + dma_channels[i].irq_handler = irq_handler;
8994 + dma_channels[i].data = data;
8996 + printk (KERN_WARNING "No more available DMA channels for %s\n", name);
9000 + local_irq_restore(flags);
9004 +void pxa_free_dma (int dma_ch)
9006 + unsigned long flags;
9008 + if (!dma_channels[dma_ch].name) {
9009 + printk (KERN_CRIT __FUNCTION__
9010 + ": trying to free channel %d which is already freed\n",
9015 + local_irq_save(flags);
9016 + DCSR(dma_ch) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
9017 + dma_channels[dma_ch].name = NULL;
9018 + local_irq_restore(flags);
9021 +static void dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
9023 + int i, dint = DINT;
9025 + for (i = 0; i < 16; i++) {
9026 + if (dint & (1 << i)) {
9027 + struct dma_channel *channel = &dma_channels[i];
9028 + if (channel->name && channel->irq_handler) {
9029 + channel->irq_handler(i, channel->data, regs);
9032 + * IRQ for an unregistered DMA channel:
9033 + * let's clear the interrupts and disable it.
9035 + printk (KERN_WARNING "spurious IRQ for DMA channel %d\n", i);
9036 + DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
9042 +static int __init pxa_dma_init (void)
9046 + ret = request_irq (IRQ_DMA, dma_irq_handler, 0, "DMA", NULL);
9048 + printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n");
9052 +__initcall(pxa_dma_init);
9054 +EXPORT_SYMBOL(pxa_request_dma);
9055 +EXPORT_SYMBOL(pxa_free_dma);
9058 +++ linux-2.4.27/arch/arm/mach-pxa/generic.c
9061 + * linux/arch/arm/mach-pxa/generic.c
9063 + * Author: Nicolas Pitre
9064 + * Created: Jun 15, 2001
9065 + * Copyright: MontaVista Software Inc.
9067 + * Code common to all PXA machines.
9069 + * This program is free software; you can redistribute it and/or modify
9070 + * it under the terms of the GNU General Public License version 2 as
9071 + * published by the Free Software Foundation.
9073 + * Since this file should be linked before any other machine specific file,
9074 + * the __initcall() here will be executed first. This serves as default
9075 + * initialization stuff for PXA machines which can be overriden later if
9078 +#include <linux/config.h>
9079 +#include <linux/module.h>
9080 +#include <linux/kernel.h>
9081 +#include <linux/init.h>
9082 +#include <linux/delay.h>
9083 +#include <linux/pm.h>
9085 +#include <asm/hardware.h>
9086 +#include <asm/system.h>
9087 +#include <asm/pgtable.h>
9088 +#include <asm/mach/map.h>
9090 +#include "generic.h"
9093 + * Various clock factors driven by the CCCR register.
9096 +/* Crystal Frequency to Memory Frequency Multiplier (L) */
9097 +static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
9099 +/* Memory Frequency to Run Mode Frequency Multiplier (M) */
9100 +static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
9102 +/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
9103 +/* Note: we store the value N * 2 here. */
9104 +static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
9106 +/* Crystal clock */
9107 +#define BASE_CLK 3686400
9110 + * Get the clock frequency as reflected by CCCR and the turbo flag.
9111 + * We assume these values have been applied via a fcs.
9112 + * If info is not 0 we also display the current settings.
9114 +unsigned int get_clk_frequency_khz( int info)
9116 + unsigned long cccr, turbo;
9117 + unsigned int l, L, m, M, n2, N;
9120 + asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
9122 + l = L_clk_mult[(cccr >> 0) & 0x1f];
9123 + m = M_clk_mult[(cccr >> 5) & 0x03];
9124 + n2 = N2_clk_mult[(cccr >> 7) & 0x07];
9133 + printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
9134 + L / 1000000, (L % 1000000) / 10000, l );
9136 + printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
9137 + M / 1000000, (M % 1000000) / 10000, m );
9139 + printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
9140 + N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
9141 + (turbo & 1) ? "" : "in" );
9144 + return (turbo & 1) ? (N/1000) : (M/1000);
9147 +EXPORT_SYMBOL(get_clk_frequency_khz);
9150 + * Return the current lclk requency in units of 10kHz
9152 +unsigned int get_lclk_frequency_10khz(void)
9154 + return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
9157 +EXPORT_SYMBOL(get_lclk_frequency_10khz);
9160 + * Handy function to set GPIO alternate functions
9163 +void set_GPIO_mode(int gpio_mode)
9166 + int gpio = gpio_mode & GPIO_MD_MASK_NR;
9167 + int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
9170 + local_irq_save(flags);
9171 + if (gpio_mode & GPIO_MD_MASK_DIR)
9172 + GPDR(gpio) |= GPIO_bit(gpio);
9174 + GPDR(gpio) &= ~GPIO_bit(gpio);
9175 + gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
9176 + GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
9177 + local_irq_restore(flags);
9180 +EXPORT_SYMBOL(set_GPIO_mode);
9183 + * Note that 0xfffe0000-0xffffffff is reserved for the vector table and
9184 + * cache flush area.
9186 +static struct map_desc standard_io_desc[] __initdata = {
9187 + /* virtual physical length domain r w c b */
9188 + { 0xf6000000, 0x20000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* PCMCIA0 IO */
9189 + { 0xf7000000, 0x30000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* PCMCIA1 IO */
9190 + { 0xf8000000, 0x40000000, 0x01800000, DOMAIN_IO, 0, 1, 0, 0 }, /* Devs */
9191 + { 0xfa000000, 0x44000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* LCD */
9192 + { 0xfc000000, 0x48000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Mem Ctl */
9193 + { 0xff000000, 0x00000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* UNCACHED_PHYS_0 */
9197 +void __init pxa_map_io(void)
9199 + iotable_init(standard_io_desc);
9200 + get_clk_frequency_khz( 1);
9203 +++ linux-2.4.27/arch/arm/mach-pxa/generic.h
9206 + * linux/arch/arm/mach-pxa/generic.h
9208 + * Author: Nicolas Pitre
9209 + * Copyright: MontaVista Software Inc.
9211 + * This program is free software; you can redistribute it and/or modify
9212 + * it under the terms of the GNU General Public License version 2 as
9213 + * published by the Free Software Foundation.
9216 +extern void __init pxa_map_io(void);
9217 +extern void __init pxa_init_irq(void);
9219 +#define SET_BANK(__nr,__start,__size) \
9220 + mi->bank[__nr].start = (__start), \
9221 + mi->bank[__nr].size = (__size), \
9222 + mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27)
9225 +++ linux-2.4.27/arch/arm/mach-pxa/idp.c
9228 + * linux/arch/arm/mach-pxa/idp.c
9230 + * This program is free software; you can redistribute it and/or modify
9231 + * it under the terms of the GNU General Public License version 2 as
9232 + * published by the Free Software Foundation.
9234 + * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
9236 + * 2001-09-13: Cliff Brake <cbrake@accelent.com>
9239 +#include <linux/init.h>
9240 +#include <linux/major.h>
9241 +#include <linux/fs.h>
9242 +#include <linux/interrupt.h>
9243 +#include <linux/sched.h>
9245 +#include <asm/types.h>
9246 +#include <asm/setup.h>
9247 +#include <asm/memory.h>
9248 +#include <asm/mach-types.h>
9249 +#include <asm/hardware.h>
9250 +#include <asm/irq.h>
9252 +#include <asm/mach/arch.h>
9253 +#include <asm/mach/map.h>
9254 +#include <asm/mach/irq.h>
9256 +#include <asm/arch/irq.h>
9258 +#include "generic.h"
9260 +#define PXA_IDP_REV02
9262 +#ifndef PXA_IDP_REV02
9263 +/* shadow registers for write only registers */
9264 +unsigned int idp_cpld_led_control_shadow = 0x1;
9265 +unsigned int idp_cpld_periph_pwr_shadow = 0xd;
9266 +unsigned int ipd_cpld_cir_shadow = 0;
9267 +unsigned int idp_cpld_kb_col_high_shadow = 0;
9268 +unsigned int idp_cpld_kb_col_low_shadow = 0;
9269 +unsigned int idp_cpld_pccard_en_shadow = 0xC3;
9270 +unsigned int idp_cpld_gpioh_dir_shadow = 0;
9271 +unsigned int idp_cpld_gpioh_value_shadow = 0;
9272 +unsigned int idp_cpld_gpiol_dir_shadow = 0;
9273 +unsigned int idp_cpld_gpiol_value_shadow = 0;
9276 + * enable all LCD signals -- they should still be on
9277 + * write protect flash
9278 + * enable all serial port transceivers
9281 +unsigned int idp_control_port_shadow = ((0x7 << 21) | /* LCD power */
9282 + (0x1 << 19) | /* disable flash write enable */
9283 + (0x7 << 9)); /* enable serial port transeivers */
9287 +static int __init idp_init(void)
9289 + printk("idp_init()\n");
9293 +__initcall(idp_init);
9295 +static void __init idp_init_irq(void)
9301 +fixup_idp(struct machine_desc *desc, struct param_struct *params,
9302 + char **cmdline, struct meminfo *mi)
9304 +#ifdef PXA_IDP_REV02
9305 + SET_BANK (0, 0xa0000000, 64*1024*1024);
9307 + SET_BANK (0, 0xa0000000, 32*1024*1024);
9311 + setup_ramdisk (1, 0, 0, 8192);
9312 + setup_initrd (__phys_to_virt(0xa1000000), 4*1024*1024);
9313 + ROOT_DEV = MKDEV(RAMDISK_MAJOR,0);
9317 +static struct map_desc idp_io_desc[] __initdata = {
9318 + /* virtual physical length domain r w c b */
9321 +#ifndef PXA_IDP_REV02
9322 + { IDP_CTRL_PORT_BASE,
9323 + IDP_CTRL_PORT_PHYS,
9324 + IDP_CTRL_PORT_SIZE,
9339 + { IDP_COREVOLT_BASE,
9340 + IDP_COREVOLT_PHYS,
9341 + IDP_COREVOLT_SIZE,
9353 +static void __init idp_map_io(void)
9356 + iotable_init(idp_io_desc);
9358 + set_GPIO_IRQ_edge(IRQ_TO_GPIO(TOUCH_PANEL_IRQ), TOUCH_PANEL_IRQ_EDGE);
9359 + set_GPIO_IRQ_edge(IRQ_TO_GPIO(SMC_IRQ), GPIO_RISING_EDGE);
9362 +MACHINE_START(PXA_IDP, "Accelent Xscale IDP")
9363 + MAINTAINER("Accelent Systems Inc.")
9364 + BOOT_MEM(0xa0000000, 0x40000000, 0xfc000000)
9367 + INITIRQ(idp_init_irq)
9370 +++ linux-2.4.27/arch/arm/mach-pxa/innokom.c
9373 + * linux/arch/arm/mach-pxa/innokom.c
9375 + * (c) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
9377 + * This program is free software; you can redistribute it and/or modify
9378 + * it under the terms of the GNU General Public License as published by
9379 + * the Free Software Foundation; either version 2 of the License, or
9380 + * (at your option) any later version.
9382 + * This program is distributed in the hope that it will be useful,
9383 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9384 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9385 + * GNU General Public License for more details.
9387 + * You should have received a copy of the GNU General Public License
9388 + * along with this program; if not, write to the Free Software
9389 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
9392 +#include <linux/init.h>
9393 +#include <linux/major.h>
9394 +#include <linux/fs.h>
9395 +#include <linux/interrupt.h>
9396 +#include <linux/sched.h>
9398 +#include <asm/types.h>
9399 +#include <asm/setup.h>
9400 +#include <asm/memory.h>
9401 +#include <asm/mach-types.h>
9402 +#include <asm/hardware.h>
9403 +#include <asm/irq.h>
9405 +#include <asm/mach/arch.h>
9406 +#include <asm/mach/map.h>
9407 +#include <asm/mach/irq.h>
9409 +#include <asm/arch/irq.h>
9410 +#include <asm/arch/irqs.h>
9411 +#include <asm/hardware/sa1111.h>
9413 +#include "generic.h"
9416 +static void __init innokom_init_irq(void)
9422 +void sw_update_handler( int irq, void* dev_id,struct pt_regs* regs)
9427 +void reset_handler( int irq, void* dev_id,struct pt_regs* regs)
9432 +static int __init innokom_init(void)
9434 + int sw_irq = GPIO_2_80_TO_IRQ(11); /* software update button */
9435 + int reset_irq = GPIO_2_80_TO_IRQ(3); /* reset button */
9437 + set_GPIO_IRQ_edge(11,GPIO_FALLING_EDGE);
9438 + if (request_irq(sw_irq,sw_update_handler,SA_INTERRUPT,"software update button",NULL))
9439 + printk(KERN_INFO "innokom: can't get assigned irq %i\n",sw_irq);
9441 + set_GPIO_IRQ_edge(3,GPIO_FALLING_EDGE);
9442 + if (request_irq(reset_irq,reset_handler,SA_INTERRUPT,"reset button",NULL))
9443 + printk(KERN_INFO "innokom: can't get assigned irq %i\n",reset_irq);
9449 +__initcall(innokom_init);
9453 +fixup_innokom(struct machine_desc *desc, struct param_struct *params,
9454 + char **cmdline, struct meminfo *mi)
9456 + /* we probably want to get this information from the bootloader later */
9457 + SET_BANK (0, 0xa0000000, 64*1024*1024);
9462 +/* memory mapping */
9463 +static struct map_desc innokom_io_desc[] __initdata = {
9464 +/* virtual physical length domain r w c b */
9465 + { INNOKOM_ETH_BASE, INNOKOM_ETH_PHYS, INNOKOM_ETH_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* ETH SMSC 91111 */
9469 +static void __init innokom_map_io(void)
9472 + iotable_init(innokom_io_desc);
9474 + /* Enable the BTUART */
9475 + CKEN |= CKEN7_BTUART;
9476 + set_GPIO_mode(GPIO42_BTRXD_MD);
9477 + set_GPIO_mode(GPIO43_BTTXD_MD);
9478 + set_GPIO_mode(GPIO44_BTCTS_MD);
9479 + set_GPIO_mode(GPIO45_BTRTS_MD);
9481 + set_GPIO_mode(GPIO33_nCS_5_MD); /* SMSC network chip */
9483 + /* setup sleep mode values */
9484 + PWER = 0x00000002;
9485 + PFER = 0x00000000;
9486 + PRER = 0x00000002;
9487 + PGSR0 = 0x00008000;
9488 + PGSR1 = 0x003F0202;
9489 + PGSR2 = 0x0001C000;
9490 + PCFR |= PCFR_OPDE;
9493 +MACHINE_START(INNOKOM, "Auerswald Innokom")
9494 + MAINTAINER("Robert Schwebel, Pengutronix")
9495 + BOOT_MEM(0xa0000000, 0x40000000, io_p2v(0x40000000))
9496 + BOOT_PARAMS(0xa0000100)
9497 + FIXUP(fixup_innokom)
9498 + MAPIO(innokom_map_io)
9499 + INITIRQ(innokom_init_irq)
9502 +++ linux-2.4.27/arch/arm/mach-pxa/irq.c
9505 + * linux/arch/arm/mach-pxa/irq.c
9507 + * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
9509 + * Author: Nicolas Pitre
9510 + * Created: Jun 15, 2001
9511 + * Copyright: MontaVista Software Inc.
9513 + * This program is free software; you can redistribute it and/or modify
9514 + * it under the terms of the GNU General Public License version 2 as
9515 + * published by the Free Software Foundation.
9518 +#include <linux/init.h>
9519 +#include <linux/module.h>
9520 +#include <linux/sched.h>
9521 +#include <linux/interrupt.h>
9522 +#include <linux/ptrace.h>
9524 +#include <asm/hardware.h>
9525 +#include <asm/irq.h>
9526 +#include <asm/mach/irq.h>
9527 +#include <asm/arch/irq.h>
9529 +#include "generic.h"
9533 + * PXA GPIO edge detection for IRQs:
9534 + * IRQs are generated on Falling-Edge, Rising-Edge, or both.
9535 + * This must be called *before* the appropriate IRQ is registered.
9536 + * Use this instead of directly setting GRER/GFER.
9539 +static int GPIO_IRQ_rising_edge[3];
9540 +static int GPIO_IRQ_falling_edge[3];
9542 +void set_GPIO_IRQ_edge (int gpio_nr, int edge)
9545 + local_irq_save(flags);
9546 + set_GPIO_mode(gpio_nr | GPIO_IN);
9547 + if (edge & GPIO_FALLING_EDGE)
9548 + set_bit (gpio_nr, GPIO_IRQ_falling_edge);
9550 + clear_bit (gpio_nr, GPIO_IRQ_falling_edge);
9551 + if (edge & GPIO_RISING_EDGE)
9552 + set_bit (gpio_nr, GPIO_IRQ_rising_edge);
9554 + clear_bit (gpio_nr, GPIO_IRQ_rising_edge);
9555 + irq_desc[IRQ_GPIO(gpio_nr)].valid = 1;
9556 + local_irq_restore(flags);
9559 +EXPORT_SYMBOL(set_GPIO_IRQ_edge);
9563 + * We don't need to ACK IRQs on the PXA unless they're GPIOs
9564 + * this is for IRQs known as PXA_IRQ([10...31]).
9567 +static void pxa_mask_irq(unsigned int irq)
9569 + ICMR &= ~(1 << (irq + PXA_IRQ_SKIP));
9572 +static void pxa_unmask_irq(unsigned int irq)
9574 + ICMR |= (1 << (irq + PXA_IRQ_SKIP));
9578 + * GPIO IRQs must be acknoledged. This is for GPIO 0 and 1.
9581 +static void pxa_mask_and_ack_GPIO_0_1_irq(unsigned int irq)
9583 + ICMR &= ~(1 << (irq + PXA_IRQ_SKIP));
9584 + GEDR0 = (1 << (irq - IRQ_GPIO0));
9587 +static void pxa_mask_GPIO_0_1_irq(unsigned int irq)
9589 + ICMR &= ~(1 << (irq + PXA_IRQ_SKIP));
9592 +static void pxa_unmask_GPIO_0_1_irq(unsigned int irq)
9594 + int gpio = irq - IRQ_GPIO0;
9595 + GRER0 = (GRER0 & ~(1 << gpio))|(GPIO_IRQ_rising_edge[0] & (1 << gpio));
9596 + GFER0 = (GFER0 & ~(1 << gpio))|(GPIO_IRQ_falling_edge[0] & (1 << gpio));
9597 + ICMR |= (1 << (irq + PXA_IRQ_SKIP));
9601 + * Demux handler for GPIO 2-80 edge detect interrupts
9604 +static int GPIO_2_80_enabled[3]; /* enabled i.e. unmasked GPIO IRQs */
9605 +static int GPIO_2_80_spurious[3]; /* GPIOs that triggered when masked */
9607 +static void pxa_GPIO_2_80_demux(int irq, void *dev_id,
9608 + struct pt_regs *regs)
9610 + int i, gedr, spurious;
9612 + while ((gedr = (GEDR0 & ~3))) {
9614 + * We don't want to clear GRER/GFER when the corresponding
9615 + * IRQ is masked because we could miss a level transition
9616 + * i.e. an IRQ which need servicing as soon as it is
9617 + * unmasked. However, such situation should happen only
9618 + * during the loop below. Thus all IRQs which aren't
9619 + * enabled at this point are considered spurious. Those
9620 + * are cleared but only de-activated if they happen twice.
9622 + spurious = gedr & ~GPIO_2_80_enabled[0];
9625 + GRER0 &= ~(spurious & GPIO_2_80_spurious[0]);
9626 + GFER0 &= ~(spurious & GPIO_2_80_spurious[0]);
9627 + GPIO_2_80_spurious[0] |= spurious;
9629 + if (!gedr) continue;
9632 + for (i = 2; i < 32; ++i) {
9633 + if (gedr & (1<<i)) {
9634 + do_IRQ (IRQ_GPIO(2) + i - 2, regs);
9638 + while ((gedr = GEDR1)) {
9639 + spurious = gedr & ~GPIO_2_80_enabled[1];
9642 + GRER1 &= ~(spurious & GPIO_2_80_spurious[1]);
9643 + GFER1 &= ~(spurious & GPIO_2_80_spurious[1]);
9644 + GPIO_2_80_spurious[1] |= spurious;
9646 + if (!gedr) continue;
9649 + for (i = 0; i < 32; ++i) {
9650 + if (gedr & (1<<i)) {
9651 + do_IRQ (IRQ_GPIO(32) + i, regs);
9655 + while ((gedr = (GEDR2 & 0x0001ffff))) {
9656 + spurious = gedr & ~GPIO_2_80_enabled[2];
9659 + GRER2 &= ~(spurious & GPIO_2_80_spurious[2]);
9660 + GFER2 &= ~(spurious & GPIO_2_80_spurious[2]);
9661 + GPIO_2_80_spurious[2] |= spurious;
9663 + if (!gedr) continue;
9666 + for (i = 0; i < 17; ++i) {
9667 + if (gedr & (1<<i)) {
9668 + do_IRQ (IRQ_GPIO(64) + i, regs);
9674 +static struct irqaction GPIO_2_80_irqaction = {
9675 + name: "GPIO 2-80",
9676 + handler: pxa_GPIO_2_80_demux,
9677 + flags: SA_INTERRUPT
9680 +#define GRER_x(i) (*(&GRER0 + (i)))
9681 +#define GFER_x(i) (*(&GFER0 + (i)))
9682 +#define GEDR_x(i) (*(&GEDR0 + (i)))
9683 +#define GPLR_x(i) (*(&GPLR0 + (i)))
9685 +static void pxa_mask_and_ack_GPIO_2_80_irq(unsigned int irq)
9687 + int gpio_nr = IRQ_TO_GPIO_2_80(irq);
9688 + int mask = 1 << (gpio_nr & 0x1f);
9689 + int index = gpio_nr >> 5;
9690 + GPIO_2_80_spurious[index] &= ~mask;
9691 + GPIO_2_80_enabled[index] &= ~mask;
9692 + GEDR_x(index) = mask;
9695 +static void pxa_mask_GPIO_2_80_irq(unsigned int irq)
9697 + int gpio_nr = IRQ_TO_GPIO_2_80(irq);
9698 + int mask = 1 << (gpio_nr & 0x1f);
9699 + int index = gpio_nr >> 5;
9700 + GPIO_2_80_spurious[index] &= ~mask;
9701 + GPIO_2_80_enabled[index] &= ~mask;
9704 +static void pxa_unmask_GPIO_2_80_irq(unsigned int irq)
9706 + int gpio_nr = IRQ_TO_GPIO_2_80(irq);
9707 + int mask = 1 << (gpio_nr & 0x1f);
9708 + int index = gpio_nr >> 5;
9709 + if (GPIO_2_80_spurious[index] & mask) {
9711 + * We don't want to miss an interrupt that would have occurred
9712 + * while it was masked. Simulate it if it is the case.
9714 + int state = GPLR_x(index);
9715 + if (((state & GPIO_IRQ_rising_edge[index]) |
9716 + (~state & GPIO_IRQ_falling_edge[index])) & mask)
9718 + /* just in case it gets referenced: */
9719 + struct pt_regs dummy;
9721 + memzero(&dummy, sizeof(dummy));
9722 + do_IRQ(irq, &dummy);
9724 + /* we are being called recursively from do_IRQ() */
9728 + GPIO_2_80_enabled[index] |= mask;
9730 + (GRER_x(index) & ~mask) | (GPIO_IRQ_rising_edge[index] & mask);
9732 + (GFER_x(index) & ~mask) | (GPIO_IRQ_falling_edge[index] & mask);
9736 +void __init pxa_init_irq(void)
9740 + /* disable all IRQs */
9743 + /* all IRQs are IRQ, not FIQ */
9746 + /* clear all GPIO edge detects */
9747 + GFER0 = GFER1 = GFER2 = 0;
9748 + GRER0 = GRER1 = GRER2 = 0;
9753 + /* only unmasked interrupts kick us out of idle */
9756 + for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) {
9757 + irq_desc[irq].valid = 1;
9758 + irq_desc[irq].probe_ok = 0;
9759 + irq_desc[irq].mask_ack = pxa_mask_irq;
9760 + irq_desc[irq].mask = pxa_mask_irq;
9761 + irq_desc[irq].unmask = pxa_unmask_irq;
9765 + * Note: GPIO IRQs are initially invalid until set_GPIO_IRQ_edge()
9766 + * is called at least once.
9769 + for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
9770 + irq_desc[irq].valid = 0;
9771 + irq_desc[irq].probe_ok = 1;
9772 + irq_desc[irq].mask_ack = pxa_mask_and_ack_GPIO_0_1_irq;
9773 + irq_desc[irq].mask = pxa_mask_GPIO_0_1_irq;
9774 + irq_desc[irq].unmask = pxa_unmask_GPIO_0_1_irq;
9777 + for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(80); irq++) {
9778 + irq_desc[irq].valid = 0;
9779 + irq_desc[irq].probe_ok = 1;
9780 + irq_desc[irq].mask_ack = pxa_mask_and_ack_GPIO_2_80_irq;
9781 + irq_desc[irq].mask = pxa_mask_GPIO_2_80_irq;
9782 + irq_desc[irq].unmask = pxa_unmask_GPIO_2_80_irq;
9784 + setup_arm_irq( IRQ_GPIO_2_80, &GPIO_2_80_irqaction );
9787 +++ linux-2.4.27/arch/arm/mach-pxa/leds-cerf.c
9790 + * linux/arch/arm/mach-pxa/leds-cerf.c
9792 + * Copyright (C) 2000 John Dorsey <john+@cs.cmu.edu>
9794 + * Copyright (c) 2001 Jeff Sutherland <jeffs@accelent.com>
9796 + * Original (leds-footbridge.c) by Russell King
9798 + * This program is free software; you can redistribute it and/or modify
9799 + * it under the terms of the GNU General Public License version 2 as
9800 + * published by the Free Software Foundation.
9804 +#include <linux/config.h>
9805 +#include <linux/init.h>
9807 +#include <asm/hardware.h>
9808 +#include <asm/leds.h>
9809 +#include <asm/system.h>
9814 +#define LED_STATE_ENABLED 1
9815 +#define LED_STATE_CLAIMED 2
9817 +static unsigned int led_state;
9818 +static unsigned int hw_led_state;
9820 +void pxa_cerf_leds_event(led_event_t evt)
9822 + unsigned long flags;
9824 + local_irq_save(flags);
9828 + hw_led_state = CERF_HEARTBEAT_LED;
9829 + led_state = LED_STATE_ENABLED;
9833 + led_state &= ~LED_STATE_ENABLED;
9837 + led_state |= LED_STATE_CLAIMED;
9838 + hw_led_state = CERF_HEARTBEAT_LED;
9842 + led_state &= ~LED_STATE_CLAIMED;
9843 + hw_led_state = CERF_HEARTBEAT_LED;
9846 +#ifdef CONFIG_LEDS_TIMER
9848 + if (!(led_state & LED_STATE_CLAIMED))
9849 + hw_led_state ^= CERF_HEARTBEAT_LED;
9853 +#ifdef CONFIG_LEDS_CPU
9854 + case led_idle_start:
9855 + if (!(led_state & LED_STATE_CLAIMED))
9856 + hw_led_state |= CERF_SYS_BUSY_LED;
9859 + case led_idle_end:
9860 + if (!(led_state & LED_STATE_CLAIMED))
9861 + hw_led_state &= ~CERF_SYS_BUSY_LED;
9868 + case led_green_on:
9869 + if (led_state & LED_STATE_CLAIMED)
9870 + hw_led_state &= ~CERF_HEARTBEAT_LED;
9873 + case led_green_off:
9874 + if (led_state & LED_STATE_CLAIMED)
9875 + hw_led_state |= CERF_HEARTBEAT_LED;
9878 + case led_amber_on:
9881 + case led_amber_off:
9884 +#ifndef CONFIG_PXA_CERF_PDA
9886 + if (led_state & LED_STATE_CLAIMED)
9887 + hw_led_state &= ~CERF_SYS_BUSY_LED;
9891 + if (led_state & LED_STATE_CLAIMED)
9892 + hw_led_state |= CERF_SYS_BUSY_LED;
9899 + if (led_state & LED_STATE_ENABLED)
9901 + switch (hw_led_state) {
9903 + CERF_HEARTBEAT_LED_ON;
9904 + CERF_SYS_BUSY_LED_ON;
9906 + case 1: // turn off heartbeat, status on:
9907 + CERF_HEARTBEAT_LED_OFF;
9908 + CERF_SYS_BUSY_LED_ON;
9910 + case 2: // status off, heartbeat on:
9911 + CERF_HEARTBEAT_LED_ON;
9912 + CERF_SYS_BUSY_LED_OFF;
9914 + case 3: // turn them both off...
9915 + CERF_HEARTBEAT_LED_OFF;
9916 + CERF_SYS_BUSY_LED_OFF;
9922 + local_irq_restore(flags);
9925 +++ linux-2.4.27/arch/arm/mach-pxa/leds-idp.c
9928 + * linux/arch/arm/mach-pxa/leds-idp.c
9930 + * Copyright (C) 2000 John Dorsey <john+@cs.cmu.edu>
9932 + * Copyright (c) 2001 Jeff Sutherland <jeffs@accelent.com>
9934 + * Original (leds-footbridge.c) by Russell King
9936 + * Macros for actual LED manipulation should be in machine specific
9937 + * files in this 'mach' directory.
9941 +#include <linux/config.h>
9942 +#include <linux/init.h>
9944 +#include <asm/hardware.h>
9945 +#include <asm/leds.h>
9946 +#include <asm/system.h>
9950 +#define LED_STATE_ENABLED 1
9951 +#define LED_STATE_CLAIMED 2
9953 +static unsigned int led_state;
9954 +static unsigned int hw_led_state;
9956 +void idp_leds_event(led_event_t evt)
9958 + unsigned long flags;
9960 + local_irq_save(flags);
9964 + hw_led_state = IDP_HB_LED | IDP_BUSY_LED;
9965 + led_state = LED_STATE_ENABLED;
9969 + led_state &= ~LED_STATE_ENABLED;
9973 + led_state |= LED_STATE_CLAIMED;
9974 + hw_led_state = IDP_HB_LED | IDP_BUSY_LED;
9978 + led_state &= ~LED_STATE_CLAIMED;
9979 + hw_led_state = IDP_HB_LED | IDP_BUSY_LED;
9982 +#ifdef CONFIG_LEDS_TIMER
9984 + if (!(led_state & LED_STATE_CLAIMED))
9985 + hw_led_state ^= IDP_HB_LED;
9989 +#ifdef CONFIG_LEDS_CPU
9990 + case led_idle_start:
9991 + if (!(led_state & LED_STATE_CLAIMED))
9992 + hw_led_state |= IDP_BUSY_LED;
9995 + case led_idle_end:
9996 + if (!(led_state & LED_STATE_CLAIMED))
9997 + hw_led_state &= ~IDP_BUSY_LED;
10004 + case led_green_on:
10005 + if (led_state & LED_STATE_CLAIMED)
10006 + hw_led_state &= ~IDP_HB_LED;
10009 + case led_green_off:
10010 + if (led_state & LED_STATE_CLAIMED)
10011 + hw_led_state |= IDP_HB_LED;
10014 + case led_amber_on:
10017 + case led_amber_off:
10021 + if (led_state & LED_STATE_CLAIMED)
10022 + hw_led_state &= ~IDP_BUSY_LED;
10025 + case led_red_off:
10026 + if (led_state & LED_STATE_CLAIMED)
10027 + hw_led_state |= IDP_BUSY_LED;
10034 + if (led_state & LED_STATE_ENABLED)
10035 + IDP_WRITE_LEDS(hw_led_state);
10037 + local_irq_restore(flags);
10040 +++ linux-2.4.27/arch/arm/mach-pxa/leds-lubbock.c
10043 + * linux/arch/arm/mach-pxa/leds-lubbock.c
10045 + * Copyright (C) 2000 John Dorsey <john+@cs.cmu.edu>
10047 + * Copyright (c) 2001 Jeff Sutherland <jeffs@accelent.com>
10049 + * Original (leds-footbridge.c) by Russell King
10051 + * See leds.h for bit definitions. The first version defines D28 on the
10052 + * Lubbock dev board as the heartbeat, and D27 as the Sys_busy led.
10053 + * There's plenty more if you're interested in adding them :)
10057 +#include <linux/config.h>
10058 +#include <linux/init.h>
10060 +#include <asm/hardware.h>
10061 +#include <asm/leds.h>
10062 +#include <asm/system.h>
10067 +#define LED_STATE_ENABLED 1
10068 +#define LED_STATE_CLAIMED 2
10070 +static unsigned int led_state;
10071 +static unsigned int hw_led_state;
10073 +void lubbock_leds_event(led_event_t evt)
10075 + unsigned long flags;
10077 + local_irq_save(flags);
10081 + hw_led_state = HEARTBEAT_LED | SYS_BUSY_LED;
10082 + led_state = LED_STATE_ENABLED;
10086 + led_state &= ~LED_STATE_ENABLED;
10090 + led_state |= LED_STATE_CLAIMED;
10091 + hw_led_state = HEARTBEAT_LED | SYS_BUSY_LED;
10094 + case led_release:
10095 + led_state &= ~LED_STATE_CLAIMED;
10096 + hw_led_state = HEARTBEAT_LED | SYS_BUSY_LED;
10099 +#ifdef CONFIG_LEDS_TIMER
10101 + if (!(led_state & LED_STATE_CLAIMED))
10102 + hw_led_state ^= HEARTBEAT_LED;
10106 +#ifdef CONFIG_LEDS_CPU
10107 + case led_idle_start:
10108 + if (!(led_state & LED_STATE_CLAIMED))
10109 + hw_led_state |= SYS_BUSY_LED;
10112 + case led_idle_end:
10113 + if (!(led_state & LED_STATE_CLAIMED))
10114 + hw_led_state &= ~SYS_BUSY_LED;
10121 + case led_green_on:
10122 + if (led_state & LED_STATE_CLAIMED)
10123 + hw_led_state &= ~HEARTBEAT_LED;
10126 + case led_green_off:
10127 + if (led_state & LED_STATE_CLAIMED)
10128 + hw_led_state |= HEARTBEAT_LED;
10131 + case led_amber_on:
10134 + case led_amber_off:
10138 + if (led_state & LED_STATE_CLAIMED)
10139 + hw_led_state &= ~SYS_BUSY_LED;
10142 + case led_red_off:
10143 + if (led_state & LED_STATE_CLAIMED)
10144 + hw_led_state |= SYS_BUSY_LED;
10151 + if (led_state & LED_STATE_ENABLED)
10153 + switch (hw_led_state) {
10154 + case 0: // all on
10155 + HEARTBEAT_LED_ON;
10158 + case 1: // turn off heartbeat, status on:
10159 + HEARTBEAT_LED_OFF;
10162 + case 2: // status off, heartbeat on:
10163 + HEARTBEAT_LED_ON;
10164 + SYS_BUSY_LED_OFF;
10166 + case 3: // turn them both off...
10167 + HEARTBEAT_LED_OFF;
10168 + SYS_BUSY_LED_OFF;
10174 + local_irq_restore(flags);
10177 +++ linux-2.4.27/arch/arm/mach-pxa/leds.c
10180 + * linux/arch/arm/mach-pxa/leds.c
10182 + * xscale LEDs dispatcher
10184 + * Copyright (C) 2001 Nicolas Pitre
10186 + * Copyright (c) 2001 Jeff Sutherland, Accelent Systems Inc.
10188 +#include <linux/config.h>
10189 +#include <linux/init.h>
10191 +#include <asm/leds.h>
10192 +#include <asm/mach-types.h>
10197 +pxa_leds_init(void)
10199 + if (machine_is_lubbock())
10200 + leds_event = lubbock_leds_event;
10201 + if (machine_is_pxa_idp())
10202 + leds_event = idp_leds_event;
10203 + if (machine_is_pxa_cerf())
10204 + leds_event = pxa_cerf_leds_event;
10206 + leds_event(led_start);
10210 +__initcall(pxa_leds_init);
10212 +++ linux-2.4.27/arch/arm/mach-pxa/leds.h
10215 + * include/asm-arm/arch-pxa/leds.h
10217 + * Copyright (c) 2001 Jeff Sutherland, Accelent Systems Inc.
10219 + * blinky lights for various PXA-based systems:
10223 +extern void lubbock_leds_event(led_event_t evt);
10224 +extern void idp_leds_event(led_event_t evt);
10225 +extern void pxa_cerf_leds_event(led_event_t evt);
10227 +++ linux-2.4.27/arch/arm/mach-pxa/lubbock.c
10230 + * linux/arch/arm/mach-pxa/lubbock.c
10232 + * Support for the Intel DBPXA250 Development Platform.
10234 + * Author: Nicolas Pitre
10235 + * Created: Jun 15, 2001
10236 + * Copyright: MontaVista Software Inc.
10238 + * This program is free software; you can redistribute it and/or modify
10239 + * it under the terms of the GNU General Public License version 2 as
10240 + * published by the Free Software Foundation.
10242 +#include <linux/init.h>
10243 +#include <linux/major.h>
10244 +#include <linux/fs.h>
10245 +#include <linux/interrupt.h>
10246 +#include <linux/sched.h>
10247 +#include <linux/bitops.h>
10249 +#include <asm/types.h>
10250 +#include <asm/setup.h>
10251 +#include <asm/memory.h>
10252 +#include <asm/mach-types.h>
10253 +#include <asm/hardware.h>
10254 +#include <asm/irq.h>
10256 +#include <asm/mach/arch.h>
10257 +#include <asm/mach/map.h>
10258 +#include <asm/mach/irq.h>
10260 +#include <asm/arch/irq.h>
10261 +#include <asm/hardware/sa1111.h>
10263 +#include "generic.h"
10265 +#ifdef CONFIG_SA1111
10266 + #include "sa1111.h"
10270 +static unsigned long lubbock_irq_enabled;
10272 +static void lubbock_mask_irq(unsigned int irq)
10274 + int lubbock_irq = (irq - LUBBOCK_IRQ(0));
10275 + LUB_IRQ_MASK_EN = (lubbock_irq_enabled &= ~(1 << lubbock_irq));
10278 +static void lubbock_unmask_irq(unsigned int irq)
10280 + int lubbock_irq = (irq - LUBBOCK_IRQ(0));
10281 + /* the irq can be acknowledged only if deasserted, so it's done here */
10282 + LUB_IRQ_SET_CLR &= ~(1 << lubbock_irq);
10283 + LUB_IRQ_MASK_EN = (lubbock_irq_enabled |= (1 << lubbock_irq));
10286 +void lubbock_irq_demux(int irq, void *dev_id, struct pt_regs *regs)
10288 + unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
10290 + GEDR(0) = GPIO_bit(0); /* clear useless edge notification */
10291 + if (likely(pending))
10292 + do_IRQ( LUBBOCK_IRQ(0) + __ffs(pending), regs );
10293 + pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
10294 + } while (pending);
10297 +static struct irqaction lubbock_irq = {
10298 + name: "Lubbock FPGA",
10299 + handler: lubbock_irq_demux,
10300 + flags: SA_INTERRUPT
10303 +static void __init lubbock_init_irq(void)
10309 + /* setup extra lubbock irqs */
10310 + for(irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
10311 + irq_desc[irq].valid = 1;
10312 + irq_desc[irq].probe_ok = 1;
10313 + irq_desc[irq].mask_ack = lubbock_mask_irq;
10314 + irq_desc[irq].mask = lubbock_mask_irq;
10315 + irq_desc[irq].unmask = lubbock_unmask_irq;
10318 + set_GPIO_IRQ_edge(GPIO_LUBBOCK_IRQ, GPIO_FALLING_EDGE);
10319 + setup_arm_irq(IRQ_GPIO_LUBBOCK_IRQ, &lubbock_irq);
10322 +static int __init lubbock_init(void)
10326 + ret = sa1111_probe(LUBBOCK_SA1111_BASE);
10330 + sa1111_init_irq(LUBBOCK_SA1111_IRQ);
10334 +__initcall(lubbock_init);
10336 +static void __init
10337 +fixup_lubbock(struct machine_desc *desc, struct param_struct *params,
10338 + char **cmdline, struct meminfo *mi)
10340 + /* Some boards have 32MB some 64MB. Let's use a safe default */
10341 + SET_BANK (0, 0xa0000000, 32*1024*1024);
10342 + mi->nr_banks = 1;
10345 +static struct map_desc lubbock_io_desc[] __initdata = {
10346 + /* virtual physical length domain r w c b */
10347 + { 0xf0000000, 0x08000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* CPLD */
10348 + { 0xf1000000, 0x0c000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* LAN91C96 IO */
10349 + { 0xf1100000, 0x0e000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* LAN91C96 Attr */
10350 + { 0xf4000000, 0x10000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA1111 */
10354 +static void __init lubbock_map_io(void)
10357 + iotable_init(lubbock_io_desc);
10359 + /* This enables the BTUART */
10360 + CKEN |= CKEN7_BTUART;
10361 + set_GPIO_mode(GPIO42_BTRXD_MD);
10362 + set_GPIO_mode(GPIO43_BTTXD_MD);
10363 + set_GPIO_mode(GPIO44_BTCTS_MD);
10364 + set_GPIO_mode(GPIO45_BTRTS_MD);
10366 + /* This is for the SMC chip select */
10367 + set_GPIO_mode(GPIO79_nCS_3_MD);
10369 + /* setup sleep mode values */
10370 + PWER = 0x00000002;
10371 + PFER = 0x00000000;
10372 + PRER = 0x00000002;
10373 + PGSR0 = 0x00008000;
10374 + PGSR1 = 0x003F0202;
10375 + PGSR2 = 0x0001C000;
10376 + PCFR |= PCFR_OPDE;
10379 +MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform")
10380 + MAINTAINER("MontaVista Software Inc.")
10381 + BOOT_MEM(0xa0000000, 0x40000000, io_p2v(0x40000000))
10382 + FIXUP(fixup_lubbock)
10383 + MAPIO(lubbock_map_io)
10384 + INITIRQ(lubbock_init_irq)
10387 +++ linux-2.4.27/arch/arm/mach-pxa/pm.c
10390 + * PXA250/210 Power Management Routines
10392 + * Original code for the SA11x0:
10393 + * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
10395 + * Modified for the PXA250 by Nicolas Pitre:
10396 + * Copyright (c) 2002 Monta Vista Software, Inc.
10398 + * This program is free software; you can redistribute it and/or
10399 + * modify it under the terms of the GNU General Public License.
10402 +#include <linux/config.h>
10403 +#include <linux/init.h>
10404 +#include <linux/pm.h>
10405 +#include <linux/slab.h>
10406 +#include <linux/sched.h>
10407 +#include <linux/interrupt.h>
10408 +#include <linux/sysctl.h>
10409 +#include <linux/errno.h>
10411 +#include <asm/hardware.h>
10412 +#include <asm/memory.h>
10413 +#include <asm/system.h>
10414 +#include <asm/leds.h>
10422 +extern void pxa_cpu_suspend(void);
10423 +extern void pxa_cpu_resume(void);
10425 +#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
10426 +#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
10429 + * List of global PXA peripheral registers to preserve.
10430 + * More ones like CP and general purpose register values are preserved
10431 + * with the stack pointer in sleep.S.
10433 +enum { SLEEP_SAVE_START = 0,
10435 + SLEEP_SAVE_OSCR, SLEEP_SAVE_OIER,
10436 + SLEEP_SAVE_OSMR0, SLEEP_SAVE_OSMR1, SLEEP_SAVE_OSMR2, SLEEP_SAVE_OSMR3,
10438 + SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
10439 + SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
10440 + SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
10441 + SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR2_L,
10442 + SLEEP_SAVE_GAFR0_U, SLEEP_SAVE_GAFR1_U, SLEEP_SAVE_GAFR2_U,
10444 + SLEEP_SAVE_FFIER, SLEEP_SAVE_FFLCR, SLEEP_SAVE_FFMCR,
10445 + SLEEP_SAVE_FFSPR, SLEEP_SAVE_FFISR,
10446 + SLEEP_SAVE_FFDLL, SLEEP_SAVE_FFDLH,
10451 + SLEEP_SAVE_CKSUM,
10457 +int pm_do_suspend(void)
10459 + unsigned long sleep_save[SLEEP_SAVE_SIZE];
10460 + unsigned long checksum = 0;
10466 + leds_event(led_stop);
10468 + /* preserve current time */
10469 + RCNR = xtime.tv_sec;
10472 + * Temporary solution. This won't be necessary once
10473 + * we move pxa support into the serial/* driver
10474 + * Save the FF UART
10486 + /* save vital registers */
10494 + SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
10495 + SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
10496 + SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
10497 + SAVE(GAFR0_L); SAVE(GAFR0_U);
10498 + SAVE(GAFR1_L); SAVE(GAFR1_U);
10499 + SAVE(GAFR2_L); SAVE(GAFR2_U);
10507 + /* Note: wake up source are set up in each machine specific files */
10509 + /* clear GPIO transition detect bits */
10510 + GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
10512 + /* Clear sleep reset status */
10515 + /* set resume return address */
10516 + PSPR = virt_to_phys(pxa_cpu_resume);
10518 + /* before sleeping, calculate and save a checksum */
10519 + for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
10520 + checksum += sleep_save[i];
10521 + sleep_save[SLEEP_SAVE_CKSUM] = checksum;
10523 + /* *** go zzz *** */
10524 + pxa_cpu_suspend();
10526 + /* after sleeping, validate the checksum */
10528 + for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
10529 + checksum += sleep_save[i];
10531 + /* if invalid, display message and wait for a hardware reset */
10532 + if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) {
10533 +#ifdef CONFIG_ARCH_LUBBOCK
10534 + LUB_HEXLED = 0xbadbadc5;
10539 + /* ensure not to come back here if it wasn't intended */
10542 + /* restore registers */
10543 + RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
10544 + RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
10545 + RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
10546 + RESTORE(GAFR0_L); RESTORE(GAFR0_U);
10547 + RESTORE(GAFR1_L); RESTORE(GAFR1_U);
10548 + RESTORE(GAFR2_L); RESTORE(GAFR2_U);
10566 + * Temporary solution. This won't be necessary once
10567 + * we move pxa support into the serial/* driver.
10568 + * Restore the FF UART.
10581 + /* restore current time */
10582 + xtime.tv_sec = RCNR;
10585 + printk(KERN_DEBUG "*** made it back from resume\n");
10588 + leds_event(led_start);
10595 +unsigned long sleep_phys_sp(void *sp)
10597 + return virt_to_phys(sp);
10600 +#ifdef CONFIG_SYSCTL
10602 + * ARGH! ACPI people defined CTL_ACPI in linux/acpi.h rather than
10603 + * linux/sysctl.h.
10605 + * This means our interface here won't survive long - it needs a new
10606 + * interface. Quick hack to get this working - use sysctl id 9999.
10608 +#warning ACPI broke the kernel, this interface needs to be fixed up.
10609 +#define CTL_ACPI 9999
10610 +#define ACPI_S1_SLP_TYP 19
10613 + * Send us to sleep.
10615 +static int sysctl_pm_do_suspend(void)
10619 + retval = pm_send_all(PM_SUSPEND, (void *)3);
10621 + if (retval == 0) {
10622 + retval = pm_do_suspend();
10624 + pm_send_all(PM_RESUME, (void *)0);
10630 +static struct ctl_table pm_table[] =
10632 + {ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, (proc_handler *)&sysctl_pm_do_suspend},
10636 +static struct ctl_table pm_dir_table[] =
10638 + {CTL_ACPI, "pm", NULL, 0, 0555, pm_table},
10643 + * Initialize power interface
10645 +static int __init pm_init(void)
10647 + register_sysctl_table(pm_dir_table, 1);
10651 +__initcall(pm_init);
10655 +++ linux-2.4.27/arch/arm/mach-pxa/pxa_usb.h
10660 + * Public interface to the pxa USB core. For use by client modules
10661 + * like usb-eth and usb-char.
10664 + * Frank Becker (Intrinsyc) - derived from sa1100_usb.h
10668 +#ifndef _PXA_USB_H
10669 +#define _PXA_USB_H
10670 +#include <asm/byteorder.h>
10672 +typedef void (*usb_callback_t)(int flag, int size);
10674 +/* in usb_ctl.c (see also descriptor methods at bottom of file) */
10676 +// Open the USB client for client and initialize data structures
10677 +// to default values, but _do not_ start UDC.
10678 +int pxa_usb_open( const char * client_name );
10680 +// Start UDC running
10681 +int pxa_usb_start( void );
10683 +// Immediately stop udc, fire off completion routines w/-EINTR
10684 +int pxa_usb_stop( void ) ;
10686 +// Disconnect client from usb core
10687 +int pxa_usb_close( void ) ;
10689 +// set notify callback for when core reaches configured state
10690 +// return previous pointer (if any)
10691 +typedef void (*usb_notify_t)(void);
10692 +usb_notify_t pxa_set_configured_callback( usb_notify_t callback );
10694 +/* in usb_send.c */
10695 +int pxa_usb_xmitter_avail( void );
10696 +int pxa_usb_send(char *buf, int len, usb_callback_t callback);
10697 +void sa110a_usb_send_reset(void);
10699 +/* in usb_recev.c */
10700 +int pxa_usb_recv(char *buf, int len, usb_callback_t callback);
10701 +void pxa_usb_recv_reset(void);
10703 +//////////////////////////////////////////////////////////////////////////////
10704 +// Descriptor Management
10705 +//////////////////////////////////////////////////////////////////////////////
10707 +#define DescriptorHeader \
10709 + __u8 bDescriptorType
10712 +// --- Device Descriptor -------------------
10715 + DescriptorHeader;
10716 + __u16 bcdUSB; /* USB specification revision number in BCD */
10717 + __u8 bDeviceClass; /* USB class for entire device */
10718 + __u8 bDeviceSubClass; /* USB subclass information for entire device */
10719 + __u8 bDeviceProtocol; /* USB protocol information for entire device */
10720 + __u8 bMaxPacketSize0; /* Max packet size for endpoint zero */
10721 + __u16 idVendor; /* USB vendor ID */
10722 + __u16 idProduct; /* USB product ID */
10723 + __u16 bcdDevice; /* vendor assigned device release number */
10724 + __u8 iManufacturer; /* index of manufacturer string */
10725 + __u8 iProduct; /* index of string that describes product */
10726 + __u8 iSerialNumber; /* index of string containing device serial number */
10727 + __u8 bNumConfigurations; /* number fo configurations */
10728 +} __attribute__ ((packed)) device_desc_t;
10730 +// --- Configuration Descriptor ------------
10733 + DescriptorHeader;
10734 + __u16 wTotalLength; /* total # of bytes returned in the cfg buf 4 this cfg */
10735 + __u8 bNumInterfaces; /* number of interfaces in this cfg */
10736 + __u8 bConfigurationValue; /* used to uniquely ID this cfg */
10737 + __u8 iConfiguration; /* index of string describing configuration */
10738 + __u8 bmAttributes; /* bitmap of attributes for ths cfg */
10739 + __u8 MaxPower; /* power draw in 2ma units */
10740 +} __attribute__ ((packed)) config_desc_t;
10744 + USB_CONFIG_REMOTEWAKE=0x20,
10745 + USB_CONFIG_SELFPOWERED=0x40,
10746 + USB_CONFIG_BUSPOWERED=0x80
10750 +#define USB_POWER( x) ((x)>>1) /* convert mA to descriptor units of A for MaxPower */
10752 +// --- Interface Descriptor ---------------
10755 + DescriptorHeader;
10756 + __u8 bInterfaceNumber; /* Index uniquely identfying this interface */
10757 + __u8 bAlternateSetting; /* ids an alternate setting for this interface */
10758 + __u8 bNumEndpoints; /* number of endpoints in this interface */
10759 + __u8 bInterfaceClass; /* USB class info applying to this interface */
10760 + __u8 bInterfaceSubClass; /* USB subclass info applying to this interface */
10761 + __u8 bInterfaceProtocol; /* USB protocol info applying to this interface */
10762 + __u8 iInterface; /* index of string describing interface */
10763 +} __attribute__ ((packed)) intf_desc_t;
10765 +// --- Endpoint Descriptor ---------------
10768 + DescriptorHeader;
10769 + __u8 bEndpointAddress; /* 0..3 ep num, bit 7: 0 = 0ut 1= in */
10770 + __u8 bmAttributes; /* 0..1 = 0: ctrl, 1: isoc, 2: bulk 3: intr */
10771 + __u16 wMaxPacketSize; /* data payload size for this ep in this cfg */
10772 + __u8 bInterval; /* polling interval for this ep in this cfg */
10773 +} __attribute__ ((packed)) ep_desc_t;
10775 +// bEndpointAddress:
10781 +#define USB_EP_ADDRESS(a,d) (((a)&0xf) | ((d) << 7))
10790 +// --- String Descriptor -------------------
10793 + DescriptorHeader;
10794 + __u16 bString[1]; /* unicode string .. actaully 'n' __u16s */
10795 +} __attribute__ ((packed)) string_desc_t;
10797 +/*=======================================================
10798 + * Handy helpers when working with above
10801 +// these are x86-style 16 bit "words" ...
10802 +#define make_word_c( w ) __constant_cpu_to_le16(w)
10803 +#define make_word( w ) __cpu_to_le16(w)
10805 +// descriptor types
10807 + USB_DESC_DEVICE = 1,
10808 + USB_DESC_CONFIG = 2,
10809 + USB_DESC_STRING = 3,
10810 + USB_DESC_INTERFACE = 4,
10811 + USB_DESC_ENDPOINT = 5
10815 +/*=======================================================
10816 + * Default descriptor layout for SA-1100 and SA-1110 UDC
10839 +} /*endpoint_type*/;
10841 +/* "config descriptor buffer" - that is, one config,
10842 + ..one interface and 2 endpoints */
10844 + config_desc_t cfg;
10845 + intf_desc_t intf;
10848 +} __attribute__ ((packed));
10850 +/* all SA device descriptors */
10852 + device_desc_t dev; /* device descriptor */
10853 + struct cdb b; /* bundle of descriptors for this cfg */
10854 +} __attribute__ ((packed)) desc_t;
10857 +/*=======================================================
10861 +/* Get the address of the statically allocated desc_t structure
10862 + in the usb core driver. Clients can modify this between
10863 + the time they call pxa_usb_open() and pxa_usb_start()
10866 +pxa_usb_get_descriptor_ptr( void );
10869 +/* Set a pointer to the string descriptor at "index". The driver
10870 + ..has room for 8 string indicies internally. Index zero holds
10871 + ..a LANGID code and is set to US English by default. Inidices
10872 + ..1-7 are available for use in the config descriptors as client's
10873 + ..see fit. This pointer is assumed to be good as long as the
10874 + ..SA usb core is open (so statically allocate them). Returnes -EINVAL
10875 + ..if index out of range */
10876 +int pxa_usb_set_string_descriptor( int index, string_desc_t * p );
10878 +/* reverse of above */
10880 +pxa_usb_get_string_descriptor( int index );
10882 +/* kmalloc() a string descriptor and convert "p" to unicode in it */
10884 +pxa_usb_kmalloc_string_descriptor( const char * p );
10886 +#endif /* _PXA_USB_H */
10888 +++ linux-2.4.27/arch/arm/mach-pxa/sa1111.c
10890 +#include "../mach-sa1100/sa1111.c"
10894 +++ linux-2.4.27/arch/arm/mach-pxa/sa1111.h
10896 +#include "../mach-sa1100/sa1111.h"
10899 +++ linux-2.4.27/arch/arm/mach-pxa/sleep.S
10902 + * Low-level PXA250/210 sleep/wakeUp support
10904 + * Initial SA1110 code:
10905 + * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
10907 + * Adapted for PXA by Nicolas Pitre:
10908 + * Copyright (c) 2002 Monta Vista Software, Inc.
10910 + * This program is free software; you can redistribute it and/or
10911 + * modify it under the terms of the GNU General Public License.
10914 +#include <linux/config.h>
10915 +#include <linux/linkage.h>
10916 +#include <asm/assembler.h>
10917 +#include <asm/hardware.h>
10922 + * pxa_cpu_suspend()
10924 + * Forces CPU into sleep state
10927 +ENTRY(pxa_cpu_suspend)
10930 + stmfd sp!, {r2 - r12, lr} @ save registers on stack
10932 + @ get coprocessor registers
10933 + mrc p15, 0, r4, c15, c1, 0 @ CP access reg
10934 + mrc p15, 0, r5, c13, c0, 0 @ PID
10935 + mrc p15, 0, r6, c3, c0, 0 @ domain ID
10936 + mrc p15, 0, r7, c2, c0, 0 @ translation table base addr
10937 + mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg
10938 + mrc p15, 0, r9, c1, c0, 0 @ control reg
10940 + @ store them plus current virtual stack ptr on stack
10942 + stmfd sp!, {r4 - r10}
10944 + @ preserve phys address of stack
10947 + ldr r1, =sleep_save_sp
10950 + @ clean data cache
10951 + bl cpu_xscale_cache_clean_invalidate_all
10953 + @ Put the processor to sleep
10954 + @ (also workaround for sighting 28071)
10956 + @ prepare value for sleep mode
10957 + mov r1, #3 @ sleep mode
10959 + @ prepare to put SDRAM into self-refresh manually
10962 + orr r5, r5, #MDREFR_SLFRSH
10964 + @ prepare pointer to physical address 0 (virtual mapping in generic.c)
10965 + mov r2, #UNCACHED_PHYS_0
10967 + @ align execution to a cache line
10974 + @ All needed values are now in registers.
10975 + @ These last instructions should be in cache
10977 + @ put SDRAM into self-refresh
10980 + @ force address lines low by reading at physical address 0
10983 + @ enter sleep mode
10984 + mcr p14, 0, r1, c7, c0, 0
10987 + b 20b @ loop waiting for sleep
10990 + * cpu_pxa_resume()
10992 + * entry point from bootloader into kernel during resume
10994 + * Note: Yes, part of the following code is located into the .data section.
10995 + * This is to allow sleep_save_sp to be accessed with a relative load
10996 + * while we can't rely on any MMU translation. We could have put
10997 + * sleep_save_sp in the .text section as well, but some setups might
10998 + * insist on it to be truely read-only.
11003 +ENTRY(pxa_cpu_resume)
11004 + mov r0, #I_BIT | F_BIT | MODE_SVC @ set SVC, irqs off
11007 + ldr r0, sleep_save_sp @ stack phys addr
11008 + ldr r2, =resume_after_mmu @ its absolute virtual address
11009 + ldmfd r0, {r4 - r9, sp} @ CP regs + virt stack ptr
11012 + mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
11013 + mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB
11015 +#ifdef CONFIG_XSCALE_CACHE_ERRATA
11016 + bic r9, r9, #0x0004 @ see cpu_xscale_proc_init
11019 + mcr p15, 0, r4, c15, c1, 0 @ CP access reg
11020 + mcr p15, 0, r5, c13, c0, 0 @ PID
11021 + mcr p15, 0, r6, c3, c0, 0 @ domain ID
11022 + mcr p15, 0, r7, c2, c0, 0 @ translation table base addr
11023 + mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg
11024 + b resume_turn_on_mmu @ cache align execution
11027 +resume_turn_on_mmu:
11028 + mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, caches, etc.
11030 + @ Let us ensure we jump to resume_after_mmu only when the mcr above
11031 + @ actually took effect. They call it the "cpwait" operation.
11032 + mrc p15, 0, r1, c2, c0, 0 @ queue a dependency on CP15
11033 + sub pc, r2, r1, lsr #32 @ jump to virtual addr
11039 + .word 0 @ preserve stack phys ptr here
11043 +#ifdef CONFIG_XSCALE_CACHE_ERRATA
11044 + bl cpu_xscale_proc_init
11046 + ldmfd sp!, {r2, r3}
11048 + ldmfd sp!, {r4 - r12, pc} @ return to caller
11052 +++ linux-2.4.27/arch/arm/mach-pxa/trizeps2.c
11055 + * linux/arch/arm/mach-pxa/trizeps2.c
11057 + * Support for the Keith&Koep MT6N Development Platform.
11059 + * Author: Luc De Cock
11060 + * Created: Jan 13, 2003
11061 + * Copyright: Teradyne DS, Ltd.
11063 + * This program is free software; you can redistribute it and/or modify
11064 + * it under the terms of the GNU General Public License version 2 as
11065 + * published by the Free Software Foundation.
11067 +#include <linux/init.h>
11068 +#include <linux/major.h>
11069 +#include <linux/fs.h>
11070 +#include <linux/interrupt.h>
11071 +#include <linux/sched.h>
11073 +#include <asm/types.h>
11074 +#include <asm/setup.h>
11075 +#include <asm/memory.h>
11076 +#include <asm/mach-types.h>
11077 +#include <asm/hardware.h>
11078 +#include <asm/irq.h>
11080 +#include <asm/mach/arch.h>
11081 +#include <asm/mach/map.h>
11082 +#include <asm/mach/irq.h>
11084 +#include <asm/arch/irq.h>
11086 +#include "generic.h"
11088 +static unsigned long trizeps2_irq_en_mask;
11089 +unsigned short trizeps2_bcr_shadow = 0x50; // 0x70
11092 +static void __init trizeps2_init_irq(void)
11098 + set_GPIO_IRQ_edge(GPIO_ETHERNET_IRQ, GPIO_RISING_EDGE);
11101 +static int __init trizeps2_init(void)
11103 + /* Configure the BCR register */
11104 + unsigned short *bcr = (unsigned short *) TRIZEPS2_BCR_BASE;
11106 + *bcr = trizeps2_bcr_shadow;
11110 +__initcall(trizeps2_init);
11112 +static void __init
11113 +fixup_trizeps2(struct machine_desc *desc, struct param_struct *params,
11114 + char **cmdline, struct meminfo *mi)
11116 +#ifdef TRIZEPS2_MEM_64MB
11117 + SET_BANK (0, 0xa0000000, 64*1024*1024);
11119 + SET_BANK (0, 0xa0000000, 32*1024*1024);
11121 + mi->nr_banks = 1;
11124 +static struct map_desc trizeps2_io_desc[] __initdata = {
11125 + /* virtual physical length domain r w c b */
11126 + { 0xf0000000, 0x0e000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* BCR */
11127 + { 0xf0100000, 0x0c000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* PCMCIA STATUS */
11128 + { 0xf1000000, 0x0c800000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* LAN91C96 IO */
11129 + { 0xf1100000, 0x0e000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* LAN91C96 Attr */
11130 + { 0xf2000000, 0x0d800000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* TTL-IO */
11134 +static void __init trizeps2_map_io(void)
11137 + iotable_init(trizeps2_io_desc);
11139 + /* This is for the SMC chip select */
11140 + set_GPIO_mode(GPIO79_nCS_3_MD);
11142 + /* setup sleep mode values */
11143 + PWER = 0x00000002;
11144 + PFER = 0x00000000;
11145 + PRER = 0x00000002;
11146 + PGSR0 = 0x00008000;
11147 + PGSR1 = 0x003F0202;
11148 + PGSR2 = 0x0001C000;
11149 + PCFR |= PCFR_OPDE;
11152 +MACHINE_START(TRIZEPS2, "Keith-n-Koep MT6N Development Platform")
11153 + MAINTAINER("Luc De Cock")
11154 + BOOT_MEM(0xa0000000, 0x40000000, io_p2v(0x40000000))
11155 + FIXUP(fixup_trizeps2)
11156 + MAPIO(trizeps2_map_io)
11157 + INITIRQ(trizeps2_init_irq)
11160 +++ linux-2.4.27/arch/arm/mach-pxa/usb-char.c
11163 + * (C) Copyright 2000-2001 Extenex Corporation
11165 + * This program is free software; you can redistribute it and/or modify
11166 + * it under the terms of the GNU General Public License as published by
11167 + * the Free Software Foundation; either version 2 of the License, or
11168 + * (at your option) any later version.
11170 + * This program is distributed in the hope that it will be useful,
11171 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
11172 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11173 + * GNU General Public License for more details.
11175 + * You should have received a copy of the GNU General Public License
11176 + * along with this program; if not, write to the Free Software
11177 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
11181 + * Miscellaneous character device interface for SA1100 USB function
11185 + * The SA1100 function driver ported from the Compaq Itsy project
11186 + * has an interface, usb-eth.c, to feed network packets over the
11187 + * usb wire and into the Linux TCP/IP stack.
11189 + * This file replaces that one with a simple character device
11190 + * interface that allows unstructured "byte pipe" style reads and
11191 + * writes over the USB bulk endpoints by userspace programs.
11193 + * A new define, CONFIG_SA1100_USB_NETLINK, has been created that,
11194 + * when set, (the default) causes the ethernet interface to be used.
11195 + * When not set, this more pedestrian character interface is linked
11198 + * Please see linux/Documentation/arm/SA1100/SA1100_USB for details.
11200 + * ward.willats@extenex.com
11203 + * - Can't dma into ring buffer directly with pci_map/unmap usb_recv
11204 + * uses and get bytes out at the same time DMA is going on. Investigate:
11205 + * a) changing usb_recv to use alloc_consistent() at client request; or
11206 + * b) non-ring-buffer based data structures. In the meantime, I am using
11207 + * a bounce buffer. Simple, but wasteful.
11210 +#include <linux/module.h>
11211 +#include <linux/config.h>
11212 +#include <linux/miscdevice.h>
11213 +#include <linux/slab.h>
11214 +#include <linux/init.h>
11215 +#include <linux/cache.h>
11216 +#include <linux/poll.h>
11217 +#include <linux/circ_buf.h>
11218 +#include <linux/timer.h>
11220 +#include <asm/io.h>
11221 +#include <asm/semaphore.h>
11222 +#include <asm/proc/page.h>
11223 +#include <asm/mach-types.h>
11225 +#include "usb-char.h"
11226 +#include "pxa_usb.h"
11230 +//////////////////////////////////////////////////////////////////////////////
11232 +//////////////////////////////////////////////////////////////////////////////
11234 +#define VERSION "0.4"
11237 +#define VERBOSITY 1
11240 +# define PRINTK(x, a...) printk (x, ## a)
11242 +# define PRINTK(x, a...) /**/
11245 +//////////////////////////////////////////////////////////////////////////////
11246 +// Globals - Macros - Enums - Structures
11247 +//////////////////////////////////////////////////////////////////////////////
11249 +#define MIN( a, b ) ((a)<(b)?(a):(b))
11252 +typedef int bool; enum { false = 0, true = 1 };
11254 +static const char pszMe[] = "usbchr: ";
11256 +static wait_queue_head_t wq_read;
11257 +static wait_queue_head_t wq_write;
11258 +static wait_queue_head_t wq_poll;
11260 +/* Serialze multiple writers onto the transmit hardware
11261 +.. since we sleep the writer during transmit to stay in
11262 +.. sync. (Multiple writers don't make much sense, but..) */
11263 +static DECLARE_MUTEX( xmit_sem );
11265 +// size of usb DATA0/1 packets. 64 is standard maximum
11266 +// for bulk transport, though most hosts seem to be able
11267 +// to handle larger.
11268 +#define TX_PACKET_SIZE 64
11269 +#define RX_PACKET_SIZE 64
11270 +#define RBUF_SIZE (4*PAGE_SIZE)
11272 +static struct wcirc_buf {
11276 +} rx_ring = { NULL, 0, 0 };
11279 + unsigned long cnt_rx_complete;
11280 + unsigned long cnt_rx_errors;
11281 + unsigned long bytes_rx;
11282 + unsigned long cnt_tx_timeouts;
11283 + unsigned long cnt_tx_errors;
11284 + unsigned long bytes_tx;
11288 +static char * tx_buf = NULL;
11289 +static char * packet_buffer = NULL;
11290 +static int sending = 0;
11291 +static int usb_ref_count = 0;
11292 +static int last_tx_result = 0;
11293 +static int last_rx_result = 0;
11294 +static int last_tx_size = 0;
11295 +static struct timer_list tx_timer;
11297 +//////////////////////////////////////////////////////////////////////////////
11299 +//////////////////////////////////////////////////////////////////////////////
11300 +static char * what_the_f( int e );
11301 +static void free_txrx_buffers( void );
11302 +static void twiddle_descriptors( void );
11303 +static void free_string_descriptors( void ) ;
11304 +static int usbc_open( struct inode *pInode, struct file *pFile );
11305 +static void rx_done_callback_packet_buffer( int flag, int size );
11307 +static void tx_timeout( unsigned long );
11308 +static void tx_done_callback( int flag, int size );
11310 +static ssize_t usbc_read( struct file *, char *, size_t, loff_t * );
11311 +static ssize_t usbc_write( struct file *, const char *, size_t, loff_t * );
11312 +static unsigned int usbc_poll( struct file *pFile, poll_table * pWait );
11313 +static int usbc_ioctl( struct inode *pInode, struct file *pFile,
11314 + unsigned int nCmd, unsigned long argument );
11315 +static int usbc_close( struct inode *pInode, struct file *pFile );
11317 +#ifdef CONFIG_SA1100_EXTENEX1
11318 +static void extenex_configured_notify_proc( void );
11320 +//////////////////////////////////////////////////////////////////////////////
11321 +// Private Helpers
11322 +//////////////////////////////////////////////////////////////////////////////
11324 +static char * what_the_f( int e )
11332 + p = "ENODEV - usb not in config state";
11335 + p = "EBUSY - another request on the hardware";
11341 + p = "EINTR - interrupted\n";
11344 + p = "EPIPE - zero length xfer\n";
11353 +static void free_txrx_buffers( void )
11355 + if ( rx_ring.buf != NULL ) {
11356 + kfree( rx_ring.buf );
11357 + rx_ring.buf = NULL;
11359 + if ( packet_buffer != NULL ) {
11360 + kfree( packet_buffer );
11361 + packet_buffer = NULL;
11363 + if ( tx_buf != NULL ) {
11369 +/* twiddle_descriptors()
11370 + * It is between open() and start(). Setup descriptors.
11372 +static void twiddle_descriptors( void )
11374 + desc_t * pDesc = pxa_usb_get_descriptor_ptr();
11375 + string_desc_t * pString;
11377 + pDesc->b.ep1.wMaxPacketSize = make_word_c( RX_PACKET_SIZE );
11378 + pDesc->b.ep1.bmAttributes = USB_EP_BULK;
11379 + pDesc->b.ep2.wMaxPacketSize = make_word_c( TX_PACKET_SIZE );
11380 + pDesc->b.ep2.bmAttributes = USB_EP_BULK;
11382 + if ( machine_is_extenex1() ) {
11383 +#ifdef CONFIG_SA1100_EXTENEX1
11384 + pDesc->dev.idVendor = make_word_c( 0xC9F );
11385 + pDesc->dev.idProduct = 1;
11386 + pDesc->dev.bcdDevice = make_word_c( 0x0001 );
11387 + pDesc->b.cfg.bmAttributes = USB_CONFIG_SELFPOWERED;
11388 + pDesc->b.cfg.MaxPower = 0;
11390 + pString = pxa_usb_kmalloc_string_descriptor( "Extenex" );
11392 + pxa_usb_set_string_descriptor( 1, pString );
11393 + pDesc->dev.iManufacturer = 1;
11396 + pString = pxa_usb_kmalloc_string_descriptor( "Handheld Theater" );
11398 + pxa_usb_set_string_descriptor( 2, pString );
11399 + pDesc->dev.iProduct = 2;
11402 + pString = pxa_usb_kmalloc_string_descriptor( "00000000" );
11404 + pxa_usb_set_string_descriptor( 3, pString );
11405 + pDesc->dev.iSerialNumber = 3;
11408 + pString = pxa_usb_kmalloc_string_descriptor( "HHT Bulk Transfer" );
11410 + pxa_usb_set_string_descriptor( 4, pString );
11411 + pDesc->b.intf.iInterface = 4;
11413 + pxa_set_configured_callback( extenex_configured_notify_proc );
11418 +static void free_string_descriptors( void )
11420 + if ( machine_is_extenex1() ) {
11421 + string_desc_t * pString;
11423 + for( i = 1 ; i <= 4 ; i++ ) {
11424 + pString = pxa_usb_get_string_descriptor( i );
11426 + kfree( pString );
11431 +//////////////////////////////////////////////////////////////////////////////
11433 +//////////////////////////////////////////////////////////////////////////////
11434 +static void kick_start_rx( void )
11436 + if ( usb_ref_count ) {
11437 + int total_space = CIRC_SPACE( rx_ring.in, rx_ring.out, RBUF_SIZE );
11438 + if ( total_space >= RX_PACKET_SIZE ) {
11439 + pxa_usb_recv( packet_buffer,
11441 + rx_done_callback_packet_buffer
11447 + * rx_done_callback_packet_buffer()
11448 + * We have completed a DMA xfer into the temp packet buffer.
11452 + * on init, -EAGAIN
11453 + * on reset, -EINTR
11455 + * on short packet -EPIPE
11458 +rx_done_callback_packet_buffer( int flag, int size )
11460 + charstats.cnt_rx_complete++;
11462 + if ( flag == 0 || flag == -EPIPE ) {
11465 + charstats.bytes_rx += size;
11467 + n = CIRC_SPACE_TO_END( rx_ring.in, rx_ring.out, RBUF_SIZE );
11468 + n = MIN( n, size );
11471 + memcpy( &rx_ring.buf[ rx_ring.in ], packet_buffer, n );
11472 + rx_ring.in = (rx_ring.in + n) & (RBUF_SIZE-1);
11473 + memcpy( &rx_ring.buf[ rx_ring.in ], packet_buffer + n, size );
11474 + rx_ring.in = (rx_ring.in + size) & (RBUF_SIZE-1);
11476 + wake_up_interruptible( &wq_read );
11477 + wake_up_interruptible( &wq_poll );
11479 + last_rx_result = 0;
11483 + } else if ( flag != -EAGAIN ) {
11484 + charstats.cnt_rx_errors++;
11485 + last_rx_result = flag;
11486 + wake_up_interruptible( &wq_read );
11487 + wake_up_interruptible( &wq_poll );
11489 + else /* init, start a read */
11494 +static void tx_timeout( unsigned long unused )
11496 + printk( "%stx timeout\n", pszMe );
11497 + pxa_usb_send_reset();
11498 + charstats.cnt_tx_timeouts++;
11502 +// on init, -EAGAIN
11503 +// on reset, -EINTR
11505 +static void tx_done_callback( int flags, int size )
11507 + if ( flags == 0 )
11508 + charstats.bytes_tx += size;
11510 + charstats.cnt_tx_errors++;
11511 + last_tx_size = size;
11512 + last_tx_result = flags;
11514 + wake_up_interruptible( &wq_write );
11515 + wake_up_interruptible( &wq_poll );
11519 +//////////////////////////////////////////////////////////////////////////////
11521 +//////////////////////////////////////////////////////////////////////////////
11523 +static int usbc_open( struct inode *pInode, struct file *pFile )
11527 + PRINTK( KERN_DEBUG "%sopen()\n", pszMe );
11529 + /* start usb core */
11530 + retval = pxa_usb_open( "usb-char" );
11531 + if ( retval ) return retval;
11533 + /* allocate memory */
11534 + if ( usb_ref_count == 0 ) {
11535 + tx_buf = (char*) kmalloc( TX_PACKET_SIZE, GFP_KERNEL | GFP_DMA );
11536 + if ( tx_buf == NULL ) {
11537 + printk( "%sARGHH! COULD NOT ALLOCATE TX BUFFER\n", pszMe );
11538 + goto malloc_fail;
11541 + (char*) kmalloc( RBUF_SIZE, GFP_KERNEL );
11543 + if ( rx_ring.buf == NULL ) {
11544 + printk( "%sARGHH! COULD NOT ALLOCATE RX BUFFER\n", pszMe );
11545 + goto malloc_fail;
11549 + (char*) kmalloc( RX_PACKET_SIZE, GFP_KERNEL | GFP_DMA );
11551 + if ( packet_buffer == NULL ) {
11552 + printk( "%sARGHH! COULD NOT ALLOCATE RX PACKET BUFFER\n", pszMe );
11553 + goto malloc_fail;
11555 + rx_ring.in = rx_ring.out = 0;
11556 + memset( &charstats, 0, sizeof( charstats ) );
11558 + last_tx_result = 0;
11559 + last_tx_size = 0;
11562 + /* modify default descriptors */
11563 + twiddle_descriptors();
11565 + retval = pxa_usb_start();
11567 + printk( "%sAGHH! Could not USB core\n", pszMe );
11568 + free_txrx_buffers();
11571 + usb_ref_count++; /* must do _before_ kick_start() */
11572 + MOD_INC_USE_COUNT;
11577 + free_txrx_buffers();
11582 + * Read endpoint. Note that you can issue a read to an
11583 + * unconfigured endpoint. Eventually, the host may come along
11584 + * and configure underneath this module and data will appear.
11586 +static ssize_t usbc_read( struct file *pFile, char *pUserBuffer,
11587 + size_t stCount, loff_t *pPos )
11591 + DECLARE_WAITQUEUE( wait, current );
11593 + PRINTK( KERN_DEBUG "%sread()\n", pszMe );
11595 + local_irq_save( flags );
11596 + if ( last_rx_result == 0 ) {
11597 + local_irq_restore( flags );
11598 + } else { /* an error happended and receiver is paused */
11599 + local_irq_restore( flags );
11600 + last_rx_result = 0;
11604 + add_wait_queue( &wq_read, &wait );
11606 + ssize_t bytes_avail;
11607 + ssize_t bytes_to_end;
11609 + set_current_state( TASK_INTERRUPTIBLE );
11611 + /* snap ring buf state */
11612 + local_irq_save( flags );
11613 + bytes_avail = CIRC_CNT( rx_ring.in, rx_ring.out, RBUF_SIZE );
11614 + bytes_to_end = CIRC_CNT_TO_END( rx_ring.in, rx_ring.out, RBUF_SIZE );
11615 + local_irq_restore( flags );
11617 + if ( bytes_avail != 0 ) {
11618 + ssize_t bytes_to_move = MIN( stCount, bytes_avail );
11619 + retval = 0; // will be bytes transfered
11620 + if ( bytes_to_move != 0 ) {
11621 + size_t n = MIN( bytes_to_end, bytes_to_move );
11622 + if ( copy_to_user( pUserBuffer,
11623 + &rx_ring.buf[ rx_ring.out ],
11625 + retval = -EFAULT;
11628 + bytes_to_move -= n;
11630 + // might go 1 char off end, so wrap
11631 + rx_ring.out = ( rx_ring.out + n ) & (RBUF_SIZE-1);
11632 + if ( copy_to_user( pUserBuffer + n,
11633 + &rx_ring.buf[ rx_ring.out ],
11636 + retval = -EFAULT;
11639 + rx_ring.out += bytes_to_move; // cannot wrap
11640 + retval += bytes_to_move;
11645 + else if ( last_rx_result ) {
11646 + retval = last_rx_result;
11649 + else if ( pFile->f_flags & O_NONBLOCK ) { // no data, can't sleep
11650 + retval = -EAGAIN;
11653 + else if ( signal_pending( current ) ) { // no data, can sleep, but signal
11654 + retval = -ERESTARTSYS;
11657 + schedule(); // no data, can sleep
11659 + set_current_state( TASK_RUNNING );
11660 + remove_wait_queue( &wq_read, &wait );
11662 + if ( retval < 0 )
11663 + printk( "%sread error %d - %s\n", pszMe, retval, what_the_f( retval ) );
11668 + * Write endpoint. This routine attempts to break the passed in buffer
11669 + * into usb DATA0/1 packet size chunks and send them to the host.
11670 + * (The lower-level driver tries to do this too, but easier for us
11671 + * to manage things here.)
11673 + * We are at the mercy of the host here, in that it must send an IN
11674 + * token to us to pull this data back, so hopefully some higher level
11675 + * protocol is expecting traffic to flow in that direction so the host
11676 + * is actually polling us. To guard against hangs, a 5 second timeout
11679 + * This routine takes some care to only report bytes sent that have
11680 + * actually made it across the wire. Thus we try to stay in lockstep
11681 + * with the completion routine and only have one packet on the xmit
11682 + * hardware at a time. Multiple simultaneous writers will get
11683 + * "undefined" results.
11686 +static ssize_t usbc_write( struct file *pFile, const char * pUserBuffer,
11687 + size_t stCount, loff_t *pPos )
11689 + ssize_t retval = 0;
11690 + ssize_t stSent = 0;
11692 + DECLARE_WAITQUEUE( wait, current );
11694 + PRINTK( KERN_DEBUG "%swrite() %d bytes\n", pszMe, stCount );
11696 + down( &xmit_sem ); // only one thread onto the hardware at a time
11698 + while( stCount != 0 && retval == 0 ) {
11699 + int nThisTime = MIN( TX_PACKET_SIZE, stCount );
11700 + copy_from_user( tx_buf, pUserBuffer, nThisTime );
11701 + sending = nThisTime;
11702 + retval = pxa_usb_send( tx_buf, nThisTime, tx_done_callback );
11703 + if ( retval < 0 ) {
11704 + char * p = what_the_f( retval );
11705 + printk( "%sCould not queue xmission. rc=%d - %s\n",
11706 + pszMe, retval, p );
11710 + /* now have something on the diving board */
11711 + add_wait_queue( &wq_write, &wait );
11712 + tx_timer.expires = jiffies + ( HZ * 5 );
11713 + add_timer( &tx_timer );
11715 + set_current_state( TASK_INTERRUPTIBLE );
11716 + if ( sending == 0 ) { /* it jumped into the pool */
11717 + del_timer( &tx_timer );
11718 + retval = last_tx_result;
11719 + if ( retval == 0 ) {
11720 + stSent += last_tx_size;
11721 + pUserBuffer += last_tx_size;
11722 + stCount -= last_tx_size;
11725 + printk( "%sxmission error rc=%d - %s\n",
11726 + pszMe, retval, what_the_f(retval) );
11729 + else if ( signal_pending( current ) ) {
11730 + del_timer( &tx_timer );
11731 + printk( "%ssignal\n", pszMe );
11732 + retval = -ERESTARTSYS;
11737 + set_current_state( TASK_RUNNING );
11738 + remove_wait_queue( &wq_write, &wait );
11743 + if ( 0 == retval )
11748 +static unsigned int usbc_poll( struct file *pFile, poll_table * pWait )
11750 + unsigned int retval = 0;
11752 + PRINTK( KERN_DEBUG "%poll()\n", pszMe );
11754 + poll_wait( pFile, &wq_poll, pWait );
11756 + if ( CIRC_CNT( rx_ring.in, rx_ring.out, RBUF_SIZE ) )
11757 + retval |= POLLIN | POLLRDNORM;
11758 + if ( pxa_usb_xmitter_avail() )
11759 + retval |= POLLOUT | POLLWRNORM;
11763 +static int usbc_ioctl( struct inode *pInode, struct file *pFile,
11764 + unsigned int nCmd, unsigned long argument )
11770 + case USBC_IOC_FLUSH_RECEIVER:
11771 + pxa_usb_recv_reset();
11772 + rx_ring.in = rx_ring.out = 0;
11775 + case USBC_IOC_FLUSH_TRANSMITTER:
11776 + pxa_usb_send_reset();
11779 + case USBC_IOC_FLUSH_ALL:
11780 + pxa_usb_recv_reset();
11781 + rx_ring.in = rx_ring.out = 0;
11782 + pxa_usb_send_reset();
11786 + retval = -ENOIOCTLCMD;
11794 +static int usbc_close( struct inode *pInode, struct file * pFile )
11796 + PRINTK( KERN_DEBUG "%sclose()\n", pszMe );
11797 + if ( --usb_ref_count == 0 ) {
11798 + down( &xmit_sem );
11800 + free_txrx_buffers();
11801 + free_string_descriptors();
11802 + del_timer( &tx_timer );
11806 + MOD_DEC_USE_COUNT;
11810 +#ifdef CONFIG_SA1100_EXTENEX1
11811 +#include "../../../drivers/char/ex_gpio.h"
11812 +void extenex_configured_notify_proc( void )
11814 + if ( exgpio_play_string( "440,1:698,1" ) == -EAGAIN )
11815 + printk( "%sWanted to BEEP but ex_gpio not open\n", pszMe );
11818 +//////////////////////////////////////////////////////////////////////////////
11820 +//////////////////////////////////////////////////////////////////////////////
11822 +static struct file_operations usbc_fops = {
11823 + owner: THIS_MODULE,
11826 + write: usbc_write,
11828 + ioctl: usbc_ioctl,
11829 + release: usbc_close,
11832 +static struct miscdevice usbc_misc_device = {
11833 + USBC_MINOR, "usb_char", &usbc_fops
11840 +int __init usbc_init( void )
11844 + if ( (rc = misc_register( &usbc_misc_device )) != 0 ) {
11845 + printk( KERN_WARNING "%sCould not register device 10, "
11846 + "%d. (%d)\n", pszMe, USBC_MINOR, rc );
11850 + // initialize wait queues
11851 + init_waitqueue_head( &wq_read );
11852 + init_waitqueue_head( &wq_write );
11853 + init_waitqueue_head( &wq_poll );
11855 + // initialize tx timeout timer
11856 + init_timer( &tx_timer );
11857 + tx_timer.function = tx_timeout;
11859 + printk( KERN_INFO "USB Function Character Driver Interface"
11860 + " - %s, (C) 2001, Extenex Corp.\n", VERSION
11866 +void __exit usbc_exit( void )
11870 +EXPORT_NO_SYMBOLS;
11872 +module_init(usbc_init);
11873 +module_exit(usbc_exit);
11877 +// end: usb-char.c
11882 +++ linux-2.4.27/arch/arm/mach-pxa/usb-char.h
11885 + * Copyright (C) 2001 Extenex Corporation
11889 + * Character device emulation client for SA-1100 client usb core.
11894 +#ifndef _USB_CHAR_H
11895 +#define _USB_CHAR_H
11897 +#define USBC_MAJOR 10 /* miscellaneous character device */
11898 +#define USBC_MINOR 240 /* in the "reserved for local use" range */
11900 +#define USBC_MAGIC 0x8E
11902 +/* zap everything in receive ring buffer */
11903 +#define USBC_IOC_FLUSH_RECEIVER _IO( USBC_MAGIC, 0x01 )
11905 +/* reset transmitter */
11906 +#define USBC_IOC_FLUSH_TRANSMITTER _IO( USBC_MAGIC, 0x02 )
11908 +/* do both of above */
11909 +#define USBC_IOC_FLUSH_ALL _IO( USBC_MAGIC, 0x03 )
11916 +#endif /* _USB_CHAR_H */
11919 +++ linux-2.4.27/arch/arm/mach-pxa/usb-eth.c
11922 + * Ethernet driver for the PXA USB client function
11923 + * Copyright (c) 2001 by Nicolas Pitre
11925 + * This code was loosely inspired by the original initial ethernet test driver
11926 + * Copyright (c) Compaq Computer Corporation, 1999
11928 + * This program is free software; you can redistribute it and/or modify
11929 + * it under the terms of the GNU General Public License version 2 as
11930 + * published by the Free Software Foundation.
11932 + * This is still work in progress...
11934 + * 19/02/2001 - Now we are compatible with generic usbnet driver. green@iXcelerator.com
11935 + * 09/03/2001 - Dropped 'framing' scheme, as it seems to cause a lot of problems with little benefit.
11936 + * Now, since we do not know what size of packet we are receiving
11937 + * last usb packet in sequence will always be less than max packet
11938 + * receive endpoint can accept.
11939 + * Now the only way to check correct start of frame is to compare
11940 + * MAC address. Also now we are stalling on each receive error.
11942 + * 15/03/2001 - Using buffer to get data from UDC. DMA needs to have 8 byte
11943 + * aligned buffer, but this breaks IP code (unaligned access).
11945 + * 01/04/2001 - stall endpoint operations appeared to be very unstable, so
11946 + * they are disabled now.
11948 + * 03/06/2001 - Readded "zerocopy" receive path (tunable).
11952 +// Define DMA_NO_COPY if you want data to arrive directly into the
11953 +// receive network buffers, instead of arriving into bounce buffer
11954 +// and then get copied to network buffer.
11955 +// This does not work correctly right now.
11956 +#undef DMA_NO_COPY
11958 +#include <linux/module.h>
11959 +#include <linux/init.h>
11960 +#include <linux/sched.h>
11961 +#include <linux/kernel.h>
11962 +#include <linux/errno.h>
11963 +#include <linux/timer.h>
11965 +#include <linux/netdevice.h>
11966 +#include <linux/etherdevice.h>
11967 +#include <linux/skbuff.h>
11968 +#include <linux/random.h>
11970 +#include "pxa_usb.h"
11973 +#define ETHERNET_VENDOR_ID 0x49f
11974 +#define ETHERNET_PRODUCT_ID 0x505A
11975 +#define MAX_PACKET 32768
11976 +#define MIN(a, b) (((a) < (b)) ? (a) : (b))
11978 +// Should be global, so that insmod can change these
11982 +static struct usbe_info_t {
11983 + struct net_device *dev;
11985 + struct net_device_stats stats;
11988 +static char usb_eth_name[16] = "usbf";
11989 +static struct net_device usb_eth_device;
11990 +static struct sk_buff *cur_tx_skb, *next_tx_skb;
11991 +static struct sk_buff *cur_rx_skb, *next_rx_skb;
11992 +static volatile int terminating;
11993 +#ifndef DMA_NO_COPY
11994 +static char *dmabuf; // we need that, as dma expect it's buffers to be aligned on 8 bytes boundary
11997 +static int usb_change_mtu (struct net_device *net, int new_mtu)
11999 + if (new_mtu <= sizeof (struct ethhdr) || new_mtu > MAX_PACKET)
12001 + // no second zero-length packet read wanted after mtu-sized packets
12002 + if (((new_mtu + sizeof (struct ethhdr)) % usb_rsize) == 0)
12005 + net->mtu = new_mtu;
12009 +static struct sk_buff *
12010 +usb_new_recv_skb(void)
12012 + struct sk_buff *skb = alloc_skb( 2 + sizeof (struct ethhdr) + usb_eth_device.mtu,GFP_ATOMIC);
12015 + skb_reserve(skb, 2);
12020 +static u8 bcast_hwaddr[ETH_ALEN]={0xff,0xff,0xff,0xff,0xff,0xff};
12022 +usb_recv_callback(int flag, int size)
12024 + struct sk_buff *skb;
12029 + skb = cur_rx_skb;
12031 + /* flag validation */
12033 + if ( skb_tailroom (skb) < size ) { // hey! we are overloaded!!!
12034 + usbe_info.stats.rx_over_errors++;
12037 +#ifndef DMA_NO_COPY
12038 + memcpy(skb->tail,dmabuf,size);
12040 + skb_put(skb, size);
12042 + if (flag == -EIO) {
12043 + usbe_info.stats.rx_errors++;
12050 + * If the real size of the packet is divisible by usb_rsize
12051 + * an extra byte will be added. Thus size == usb_rsize
12052 + * should only happen if more data is to come.
12054 + /* validate packet length */
12055 + if (size == usb_rsize ) {
12056 + /* packet not complete yet */
12061 + * At this point skb is non null if we have a complete packet.
12062 + * If so take a fresh skb right away and restart USB receive without
12063 + * further delays, then process the packet. Otherwise resume USB
12064 + * receive on the current skb and exit.
12068 + cur_rx_skb = next_rx_skb;
12069 +#ifndef DMA_NO_COPY
12070 + pxa_usb_recv(dmabuf, usb_rsize,
12071 + usb_recv_callback);
12073 + pxa_usb_recv(cur_rx_skb->tail, MIN(usb_rsize, skb_tailroom (cur_rx_skb)),
12074 + usb_recv_callback);
12079 + next_rx_skb = usb_new_recv_skb();
12080 + if (!next_rx_skb) {
12082 + * We can't aford loosing buffer space...
12083 + * So we drop the current packet and recycle its skb.
12085 + printk("%s: can't allocate new skb\n", __FUNCTION__);
12086 + usbe_info.stats.rx_dropped++;
12087 + skb_trim(skb, 0);
12088 + next_rx_skb = skb;
12091 + if ( skb->len >= sizeof(struct ethhdr)) {
12092 + if (memcmp(skb->data,usb_eth_device.dev_addr,ETH_ALEN) && memcmp(skb->data,bcast_hwaddr,ETH_ALEN) ) {
12093 + // This frame is not for us. nor it is broadcast
12094 + usbe_info.stats.rx_frame_errors++;
12103 + for (i = 0; i < skb->len; i++)
12105 + printk("%02X ", skb->data[i]);
12106 + if( (i%8)==7) printk("\n");
12116 +// FIXME: eth_copy_and_csum "small" packets to new SKB (small < ~200 bytes) ?
12118 + skb->dev = &usb_eth_device;
12119 + skb->protocol = eth_type_trans (skb, &usb_eth_device);
12120 + usbe_info.stats.rx_packets++;
12121 + usbe_info.stats.rx_bytes += skb->len;
12122 + skb->ip_summed = CHECKSUM_NONE;
12123 + status = netif_rx (skb);
12124 + if (status != NET_RX_SUCCESS)
12125 + printk("netif_rx failed with code %d\n",status);
12128 +//printk("ERROR... tailroom=%d size=%d len=%d flag=%d\n", skb_tailroom(skb), size, skb->len, flag);
12130 + * Error due to HW addr mismatch, or IO error.
12131 + * Recycle the current skb and reset USB reception.
12133 + skb_trim(cur_rx_skb, 0);
12134 +// if ( flag == -EINTR || flag == -EAGAIN ) // only if we are coming out of stall
12135 +#ifndef DMA_NO_COPY
12136 + pxa_usb_recv(dmabuf, usb_rsize, usb_recv_callback);
12138 + pxa_usb_recv(cur_rx_skb->tail, MIN(usb_rsize, skb_tailroom (cur_rx_skb)), usb_recv_callback);
12145 +usb_send_callback(int flag, int size)
12147 + struct net_device *dev = usbe_info.dev;
12148 + struct net_device_stats *stats;
12149 + struct sk_buff *skb=cur_tx_skb;
12155 + stats = &usbe_info.stats;
12158 + stats->tx_packets++;
12159 + stats->tx_bytes += size;
12162 + stats->tx_errors++;
12165 + stats->tx_dropped++;
12169 + cur_tx_skb = next_tx_skb;
12170 + next_tx_skb = NULL;
12171 + dev_kfree_skb_irq(skb);
12175 + dev->trans_start = jiffies;
12176 + ret = pxa_usb_send(cur_tx_skb->data, cur_tx_skb->len, usb_send_callback);
12178 + /* If the USB core can't accept the packet, we drop it. */
12179 + dev_kfree_skb_irq(cur_tx_skb);
12180 + cur_tx_skb = NULL;
12181 + usbe_info.stats.tx_carrier_errors++;
12183 + netif_wake_queue(dev);
12187 +usb_eth_xmit(struct sk_buff *skb, struct net_device *dev)
12192 + if (next_tx_skb) {
12193 + printk("%s: called with next_tx_skb != NULL\n", __FUNCTION__);
12197 + if (skb_shared (skb)) {
12198 + struct sk_buff *skb2 = skb_unshare(skb, GFP_ATOMIC);
12200 + usbe_info.stats.tx_dropped++;
12201 + dev_kfree_skb(skb);
12207 + if ((skb->len % usb_wsize) == 0) {
12208 + skb->len++; // other side will ignore this one, anyway.
12211 + save_flags_cli(flags);
12212 + if (cur_tx_skb) {
12213 + next_tx_skb = skb;
12214 + netif_stop_queue(dev);
12216 + cur_tx_skb = skb;
12217 + dev->trans_start = jiffies;
12218 + ret = pxa_usb_send(skb->data, skb->len, usb_send_callback);
12220 + /* If the USB core can't accept the packet, we drop it. */
12221 + dev_kfree_skb(skb);
12222 + cur_tx_skb = NULL;
12223 + usbe_info.stats.tx_carrier_errors++;
12226 + restore_flags(flags);
12231 +usb_xmit_timeout(struct net_device *dev )
12233 + pxa_usb_send_reset();
12234 + dev->trans_start = jiffies;
12235 + netif_wake_queue(dev);
12240 +usb_eth_open(struct net_device *dev)
12243 + rc = pxa_usb_open( "usb-eth" );
12245 + string_desc_t * pstr;
12246 + desc_t * pd = pxa_usb_get_descriptor_ptr();
12248 + pd->b.ep1.wMaxPacketSize = make_word( usb_rsize );
12249 + pd->b.ep2.wMaxPacketSize = make_word( usb_wsize );
12250 + pd->dev.idVendor = ETHERNET_VENDOR_ID;
12251 + pd->dev.idProduct = ETHERNET_PRODUCT_ID;
12252 + pstr = pxa_usb_kmalloc_string_descriptor( "PXA USB NIC" );
12254 + pxa_usb_set_string_descriptor( 1, pstr );
12255 + pd->dev.iProduct = 1;
12257 + rc = pxa_usb_start();
12263 + cur_tx_skb = next_tx_skb = NULL;
12264 + cur_rx_skb = usb_new_recv_skb();
12265 + next_rx_skb = usb_new_recv_skb();
12266 + if (!cur_rx_skb || !next_rx_skb) {
12267 + printk("%s: can't allocate new skb\n", __FUNCTION__);
12269 + kfree_skb(cur_rx_skb);
12271 + kfree_skb(next_rx_skb);
12278 + MOD_INC_USE_COUNT;
12279 +#ifndef DMA_NO_COPY
12280 + pxa_usb_recv(dmabuf, usb_rsize, usb_recv_callback);
12282 + pxa_usb_recv(cur_rx_skb->tail, MIN(usb_rsize, skb_tailroom (cur_rx_skb)),
12283 + usb_recv_callback);
12291 +usb_eth_release(struct net_device *dev)
12293 + string_desc_t * pstr;
12296 + pxa_usb_send_reset();
12297 + pxa_usb_recv_reset();
12299 + kfree_skb(cur_tx_skb);
12301 + kfree_skb(next_tx_skb);
12303 + kfree_skb(cur_rx_skb);
12305 + kfree_skb(next_rx_skb);
12309 + if ( (pstr = pxa_usb_get_string_descriptor(1)) != NULL )
12312 + MOD_DEC_USE_COUNT;
12316 +static struct net_device_stats *
12317 +usb_eth_stats(struct net_device *dev)
12319 + struct usbe_info_t *priv = (struct usbe_info_t*) dev->priv;
12320 + struct net_device_stats *stats=NULL;
12323 + stats = &priv->stats;
12328 +usb_eth_probe(struct net_device *dev)
12330 + u8 node_id [ETH_ALEN];
12332 + get_random_bytes (node_id, sizeof node_id);
12333 + node_id [0] &= 0xfe; // clear multicast bit
12336 + * Assign the hardware address of the board:
12337 + * generate it randomly, as there can be many such
12338 + * devices on the bus.
12340 + memcpy (dev->dev_addr, node_id, sizeof node_id);
12342 + dev->open = usb_eth_open;
12343 + dev->change_mtu = usb_change_mtu;
12344 + dev->stop = usb_eth_release;
12345 + dev->hard_start_xmit = usb_eth_xmit;
12346 + dev->get_stats = usb_eth_stats;
12347 + dev->watchdog_timeo = 1*HZ;
12348 + dev->tx_timeout = usb_xmit_timeout;
12349 + dev->priv = &usbe_info;
12351 + usbe_info.dev = dev;
12353 + /* clear the statistics */
12354 + memset(&usbe_info.stats, 0, sizeof(struct net_device_stats));
12356 + ether_setup(dev);
12357 + dev->flags &= ~IFF_MULTICAST;
12358 + dev->flags &= ~IFF_BROADCAST;
12359 + //dev->flags |= IFF_NOARP;
12365 +MODULE_PARM(usb_rsize, "1i");
12366 +MODULE_PARM_DESC(usb_rsize, "number of bytes in packets from host to pxa");
12367 +MODULE_PARM(usb_wsize, "1i");
12368 +MODULE_PARM_DESC(usb_wsize, "number of bytes in packets from pxa to host");
12372 +usb_eth_init(void)
12374 +#ifndef DMA_NO_COPY
12375 + dmabuf = kmalloc( usb_rsize, GFP_KERNEL | GFP_DMA );
12379 + strncpy(usb_eth_device.name, usb_eth_name, IFNAMSIZ);
12380 + usb_eth_device.init = usb_eth_probe;
12381 + if (register_netdev(&usb_eth_device) != 0)
12384 + printk( KERN_INFO "USB Function Ethernet Driver Interface\n");
12389 +static void __exit
12390 +usb_eth_cleanup(void)
12392 +#ifndef DMA_NO_COPY
12395 + unregister_netdev(&usb_eth_device);
12398 +module_init(usb_eth_init);
12399 +module_exit(usb_eth_cleanup);
12401 +++ linux-2.4.27/arch/arm/mach-pxa/usb_ctl.c
12404 + * Copyright (C) Compaq Computer Corporation, 1998, 1999
12405 + * Copyright (C) Extenex Corporation, 2001
12406 + * Copyright (C) Intrinsyc, Inc., 2002
12408 + * PXA USB controller core driver.
12410 + * This file provides interrupt routing and overall coordination
12411 + * of the endpoints.
12414 + * linux/Documentation/arm/SA1100/SA1100_USB
12418 + * Frank Becker (Intrinsyc) - derived from sa1100 usb_ctl.c
12421 +#include <linux/config.h>
12422 +#include <linux/module.h>
12423 +#include <linux/init.h>
12424 +#include <linux/kernel.h>
12425 +#include <linux/sched.h>
12426 +#include <linux/proc_fs.h>
12427 +#include <linux/tqueue.h>
12428 +#include <linux/delay.h>
12429 +#include <linux/slab.h>
12430 +#include <asm/io.h>
12431 +#include <asm/dma.h>
12432 +#include <asm/irq.h>
12433 +#include <asm/mach-types.h>
12435 +#include "pxa_usb.h"
12436 +#include "usb_ctl.h"
12441 +static unsigned int usb_debug = DEBUG;
12443 +#define usb_debug 0 /* gcc will remove all the debug code for us */
12446 +//////////////////////////////////////////////////////////////////////////////
12448 +//////////////////////////////////////////////////////////////////////////////
12450 +int usbctl_next_state_on_event( int event );
12451 +static void udc_int_hndlr(int, void *, struct pt_regs *);
12452 +static void initialize_descriptors( void );
12453 +static void soft_connect_hook( int enable );
12454 +static void udc_disable(void);
12455 +static void udc_enable(void);
12457 +#if CONFIG_PROC_FS
12458 +#define PROC_NODE_NAME "driver/pxausb"
12459 +static int usbctl_read_proc(char *page, char **start, off_t off,
12460 + int count, int *eof, void *data);
12463 +//////////////////////////////////////////////////////////////////////////////
12465 +//////////////////////////////////////////////////////////////////////////////
12466 +static const char pszMe[] = "usbctl: ";
12467 +struct usb_info_t usbd_info; /* global to ep0, usb_recv, usb_send */
12469 +/* device descriptors */
12470 +static desc_t desc;
12472 +#define MAX_STRING_DESC 8
12473 +static string_desc_t * string_desc_array[ MAX_STRING_DESC ];
12474 +static string_desc_t sd_zero; /* special sd_zero holds language codes */
12476 +// called when configured
12477 +static usb_notify_t configured_callback = NULL;
12480 + kStateZombie = 0,
12481 + kStateZombieSuspend = 1,
12482 + kStateDefault = 2,
12483 + kStateDefaultSuspend = 3,
12485 + kStateAddrSuspend = 5,
12486 + kStateConfig = 6,
12487 + kStateConfigSuspend = 7
12491 + * FIXME: The PXA UDC handles several host device requests without user
12492 + * notification/intervention. The table could be collapsed quite a bit...
12494 +static int device_state_machine[8][6] = {
12495 +// suspend reset resume adddr config deconfig
12496 +/* zombie */ { kStateZombieSuspend , kStateDefault, kStateZombie , kError , kError , kError },
12497 +/* zom sus */ { kStateZombieSuspend , kStateDefault, kStateZombie , kError , kError , kError },
12498 +/* default */ { kStateDefaultSuspend, kStateDefault, kStateDefault, kStateAddr, kStateConfig, kError },
12499 +/* def sus */ { kStateDefaultSuspend, kStateDefault, kStateDefault, kError , kError , kError },
12500 +/* addr */ { kStateAddrSuspend , kStateDefault, kStateAddr , kError , kStateConfig, kError },
12501 +/* addr sus */{ kStateAddrSuspend , kStateDefault, kStateAddr , kError , kError , kError },
12502 +/* config */ { kStateConfigSuspend , kStateDefault, kStateConfig , kError , kError , kStateDefault },
12503 +/* cfg sus */ { kStateConfigSuspend , kStateDefault, kStateConfig , kError , kError , kError }
12506 +/* "device state" is the usb device framework state, as opposed to the
12507 + "state machine state" which is whatever the driver needs and is much
12508 + more fine grained
12510 +static int sm_state_to_device_state[8] = {
12511 +// zombie zom suspend
12512 +USB_STATE_POWERED, USB_STATE_SUSPENDED,
12513 +// default default sus
12514 +USB_STATE_DEFAULT, USB_STATE_SUSPENDED,
12516 +USB_STATE_ADDRESS, USB_STATE_SUSPENDED,
12517 +// config config sus
12518 +USB_STATE_CONFIGURED, USB_STATE_SUSPENDED
12521 +static char * state_names[8] =
12522 +{ "zombie", "zombie suspended",
12523 + "default", "default suspended",
12524 + "address", "address suspended",
12525 + "configured", "config suspended"
12528 +static char * event_names[6] =
12529 +{ "suspend", "reset", "resume",
12530 + "address assigned", "configure", "de-configure"
12533 +static char * device_state_names[] =
12534 +{ "not attached", "attached", "powered", "default",
12535 + "address", "configured", "suspended" };
12537 +static int sm_state = kStateZombie;
12539 +//////////////////////////////////////////////////////////////////////////////
12541 +//////////////////////////////////////////////////////////////////////////////
12543 +/* The UDCCR reg contains mask and interrupt status bits,
12544 + * so using '|=' isn't safe as it may ack an interrupt.
12547 +void udc_set_mask_UDCCR( int mask )
12549 + UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
12552 +void udc_clear_mask_UDCCR( int mask)
12554 + UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
12557 +void udc_ack_int_UDCCR( int mask)
12559 + /* udccr contains the bits we dont want to change */
12560 + __u32 udccr = UDCCR & UDCCR_MASK_BITS;
12562 + UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
12566 +udc_int_hndlr(int irq, void *dev_id, struct pt_regs *regs)
12568 + __u32 status = UDCCR;
12569 + __u32 ir0_status = USIR0;
12570 + __u32 ir1_status = USIR1;
12571 + __u32 uicr0 = UICR0;
12572 + __u32 uicr1 = UICR1;
12575 + udc_set_mask_UDCCR( UDCCR_REM | UDCCR_SRM);
12579 + if( usb_debug > 2)
12581 + printk("%s--- udc_int_hndlr\n"
12582 + "UDCCR=0x%08x UDCCS0=0x%08x UDCCS1=0x%08x UDCCS2=0x%08x\n"
12583 + "USIR0=0x%08x USIR1=0x%08x UICR0=0x%08x UICR1=0x%08x\n",
12584 + pszMe, status, UDCCS0, UDCCS1, UDCCS2, ir0_status, ir1_status, uicr0, uicr1);
12587 + /* SUSpend Interrupt Request */
12588 + if ( status & UDCCR_SUSIR )
12590 + udc_ack_int_UDCCR( UDCCR_SUSIR);
12591 + if( usb_debug) printk("%sSuspend...\n", pszMe);
12592 + usbctl_next_state_on_event( kEvSuspend );
12595 + /* RESume Interrupt Request */
12596 + if ( status & UDCCR_RESIR )
12598 + udc_ack_int_UDCCR( UDCCR_RESIR);
12599 + if( usb_debug) printk("%sResume...\n", pszMe);
12600 + usbctl_next_state_on_event( kEvResume );
12603 + /* ReSeT Interrupt Request - UDC has been reset */
12604 + if ( status & UDCCR_RSTIR )
12606 + /* clear the reset interrupt */
12607 + udc_ack_int_UDCCR( UDCCR_RSTIR);
12609 + /* check type of reset */
12610 + if( (UDCCR & UDCCR_UDA) == 0)
12612 + /* reset assertion took place, nothing to do */
12613 + if( usb_debug) printk("%sReset assertion...\n", pszMe);
12616 + /* ok, it's a reset negation, go on with reset */
12617 + else if ( usbctl_next_state_on_event( kEvReset ) != kError )
12619 + /* starting reset sequence now... */
12620 + if( usb_debug) printk("%sResetting\n", pszMe);
12623 + ep_bulk_in1_reset();
12624 + ep_bulk_out1_reset();
12626 + usbctl_next_state_on_event( kEvConfig );
12630 + printk("%sUnexpected reset\n", pszMe);
12636 + if (ir0_status & USIR0_IR0)
12639 + /* transmit bulk */
12640 + if (ir0_status & USIR0_IR1)
12641 + ep_bulk_in1_int_hndlr(ir0_status);
12643 + /* receive bulk */
12644 + if ( ir0_status & USIR0_IR2)
12645 + ep_bulk_out1_int_hndlr(ir0_status);
12647 + while (UDCCS2 & UDCCS_BO_RNE)
12649 + if( usb_debug) printk("More Bulk-out data...\n");
12650 + ep_bulk_out1_int_hndlr(ir0_status);
12656 + udc_clear_mask_UDCCR( UDCCR_SRM | UDCCR_REM); /* enable suspend/resume, reset */
12658 + /* clear all endpoint ints */
12662 + if( usb_debug > 2)
12664 + printk("%sudc_int_hndlr\n"
12665 + "UDCCR=0x%08x UDCCS0=0x%08x UDCCS1=0x%08x UDCCS2=0x%08x\n"
12666 + "USIR0=0x%08x USIR1=0x%08x UICR0=0x%08x UICR1=0x%08x\n",
12667 + pszMe, UDCCR, UDCCS0, UDCCS1, UDCCS2, USIR0, USIR1, UICR0, UICR1);
12671 +//////////////////////////////////////////////////////////////////////////////
12672 +// Public Interface
12673 +//////////////////////////////////////////////////////////////////////////////
12675 +/* Open PXA usb core on behalf of a client, but don't start running */
12678 +pxa_usb_open( const char * client )
12680 + if ( usbd_info.client_name != NULL )
12682 + printk( "%sUnable to register %s (%s already registered).\n",
12683 + pszMe, client, usbd_info.client_name );
12687 + usbd_info.client_name = (char*) client;
12688 + memset(&usbd_info.stats, 0, sizeof(struct usb_stats_t));
12689 + memset(string_desc_array, 0, sizeof(string_desc_array));
12691 + /* hack to start in zombie suspended state */
12692 + sm_state = kStateZombieSuspend;
12693 + usbd_info.state = USB_STATE_SUSPENDED;
12695 + /* create descriptors for enumeration */
12696 + initialize_descriptors();
12698 + printk( "%s%s registered.\n", pszMe, client );
12702 +/* Start running. Must have called usb_open (above) first */
12704 +pxa_usb_start( void )
12706 + if ( usbd_info.client_name == NULL ) {
12707 + printk( "%s%s - no client registered\n",
12708 + pszMe, __FUNCTION__ );
12712 + /* start UDC internal machinery running */
12716 + /* flush DMA and fire through some -EAGAINs */
12717 + ep_bulk_out1_init( usbd_info.dmach_rx );
12718 + ep_bulk_in1_init( usbd_info.dmach_tx );
12720 + /* give endpoint notification we are starting */
12721 + ep_bulk_out1_state_change_notify( USB_STATE_SUSPENDED );
12722 + ep_bulk_in1_state_change_notify( USB_STATE_SUSPENDED );
12724 + /* enable any platform specific hardware */
12725 + soft_connect_hook( 1 );
12727 + /* enable suspend/resume, reset */
12728 + udc_clear_mask_UDCCR( UDCCR_SRM | UDCCR_REM);
12729 + /* enable ep0, ep1, ep2 */
12730 + UICR0 &= ~(UICR0_IM0 | UICR0_IM1 | UICR0_IM2);
12732 + if( usb_debug) printk( "%sStarted %s\n", pszMe, usbd_info.client_name );
12736 +/* Stop USB core from running */
12738 +pxa_usb_stop( void )
12740 + if ( usbd_info.client_name == NULL ) {
12741 + printk( "%s%s - no client registered\n",
12742 + pszMe, __FUNCTION__ );
12745 + /* mask everything */
12746 + /* disable suspend/resume, reset */
12747 + udc_set_mask_UDCCR( UDCCR_SRM | UDCCR_REM);
12748 + /* disable ep0, ep1, ep2 */
12749 + UICR0 |= (UICR0_IM0 | UICR0_IM1 | UICR0_IM2);
12751 + ep_bulk_out1_reset();
12752 + ep_bulk_in1_reset();
12755 + if( usb_debug) printk( "%sStopped %s\n", pszMe, usbd_info.client_name );
12759 +/* Tell PXA core client is through using it */
12761 +pxa_usb_close( void )
12763 + if ( usbd_info.client_name == NULL ) {
12764 + printk( "%s%s - no client registered\n",
12765 + pszMe, __FUNCTION__ );
12768 + printk( "%s%s closed.\n", pszMe, (char*)usbd_info.client_name );
12769 + usbd_info.client_name = NULL;
12773 +/* set a proc to be called when device is configured */
12774 +usb_notify_t pxa_set_configured_callback( usb_notify_t func )
12776 + usb_notify_t retval = configured_callback;
12777 + configured_callback = func;
12781 +/*====================================================
12782 + * Descriptor Manipulation.
12783 + * Use these between open() and start() above to setup
12784 + * the descriptors for your device.
12788 +/* get pointer to static default descriptor */
12790 +pxa_usb_get_descriptor_ptr( void ) { return &desc; }
12792 +/* optional: set a string descriptor */
12794 +pxa_usb_set_string_descriptor( int i, string_desc_t * p )
12797 + if ( i < MAX_STRING_DESC ) {
12798 + string_desc_array[i] = p;
12801 + retval = -EINVAL;
12806 +/* optional: get a previously set string descriptor */
12808 +pxa_usb_get_string_descriptor( int i )
12810 + return ( i < MAX_STRING_DESC )
12811 + ? string_desc_array[i]
12816 +/* optional: kmalloc and unicode up a string descriptor */
12818 +pxa_usb_kmalloc_string_descriptor( const char * p )
12820 + string_desc_t * pResult = NULL;
12823 + int len = strlen( p );
12824 + int uni_len = len * sizeof( __u16 );
12825 + pResult = (string_desc_t*) kmalloc( uni_len + 2, GFP_KERNEL ); /* ugh! */
12826 + if ( pResult != NULL ) {
12828 + pResult->bLength = uni_len + 2;
12829 + pResult->bDescriptorType = USB_DESC_STRING;
12830 + for( i = 0; i < len ; i++ ) {
12831 + pResult->bString[i] = make_word( (__u16) p[i] );
12838 +//////////////////////////////////////////////////////////////////////////////
12839 +// Exports to rest of driver
12840 +//////////////////////////////////////////////////////////////////////////////
12842 +/* called by the int handler here and the two endpoint files when interesting
12843 + .."events" happen */
12846 +usbctl_next_state_on_event( int event )
12848 + int next_state = device_state_machine[ sm_state ][ event ];
12849 + if ( next_state != kError )
12851 + int next_device_state = sm_state_to_device_state[ next_state ];
12852 + if( usb_debug) printk( "%s%s --> [%s] --> %s. Device in %s state.\n",
12853 + pszMe, state_names[ sm_state ], event_names[ event ],
12854 + state_names[ next_state ], device_state_names[ next_device_state ] );
12856 + sm_state = next_state;
12857 + if ( usbd_info.state != next_device_state )
12859 + if ( configured_callback != NULL
12861 + next_device_state == USB_STATE_CONFIGURED
12863 + usbd_info.state != USB_STATE_SUSPENDED
12865 + configured_callback();
12867 + usbd_info.state = next_device_state;
12869 + ep_bulk_out1_state_change_notify( next_device_state );
12870 + ep_bulk_in1_state_change_notify( next_device_state );
12875 + printk( "%s%s --> [%s] --> ??? is an error.\n",
12876 + pszMe, state_names[ sm_state ], event_names[ event ] );
12878 + return next_state;
12881 +//////////////////////////////////////////////////////////////////////////////
12882 +// Private Helpers
12883 +//////////////////////////////////////////////////////////////////////////////
12885 +/* setup default descriptors */
12888 +initialize_descriptors(void)
12890 + desc.dev.bLength = sizeof( device_desc_t );
12891 + desc.dev.bDescriptorType = USB_DESC_DEVICE;
12892 + desc.dev.bcdUSB = 0x100; /* 1.0 */
12893 + desc.dev.bDeviceClass = 0xFF; /* vendor specific */
12894 + desc.dev.bDeviceSubClass = 0;
12895 + desc.dev.bDeviceProtocol = 0;
12896 + desc.dev.bMaxPacketSize0 = 16; /* ep0 max fifo size */
12897 + desc.dev.idVendor = 0; /* vendor ID undefined */
12898 + desc.dev.idProduct = 0; /* product */
12899 + desc.dev.bcdDevice = 0; /* vendor assigned device release num */
12900 + desc.dev.iManufacturer = 0; /* index of manufacturer string */
12901 + desc.dev.iProduct = 0; /* index of product description string */
12902 + desc.dev.iSerialNumber = 0; /* index of string holding product s/n */
12903 + desc.dev.bNumConfigurations = 1;
12905 + desc.b.cfg.bLength = sizeof( config_desc_t );
12906 + desc.b.cfg.bDescriptorType = USB_DESC_CONFIG;
12907 + desc.b.cfg.wTotalLength = make_word_c( sizeof(struct cdb) );
12908 + desc.b.cfg.bNumInterfaces = 1;
12909 + desc.b.cfg.bConfigurationValue = 1;
12910 + desc.b.cfg.iConfiguration = 0;
12911 + desc.b.cfg.bmAttributes = USB_CONFIG_BUSPOWERED;
12912 + desc.b.cfg.MaxPower = USB_POWER( 500 );
12914 + desc.b.intf.bLength = sizeof( intf_desc_t );
12915 + desc.b.intf.bDescriptorType = USB_DESC_INTERFACE;
12916 + desc.b.intf.bInterfaceNumber = 0; /* unique intf index*/
12917 + desc.b.intf.bAlternateSetting = 0;
12918 + desc.b.intf.bNumEndpoints = 2;
12919 + desc.b.intf.bInterfaceClass = 0xFF; /* vendor specific */
12920 + desc.b.intf.bInterfaceSubClass = 0;
12921 + desc.b.intf.bInterfaceProtocol = 0;
12922 + desc.b.intf.iInterface = 0;
12926 + * The host usbnet driver expects EP1=out EP2=in. On the PXA UDC EP1=in, EP2=out
12928 + desc.b.ep1.bLength = sizeof( ep_desc_t );
12929 + desc.b.ep1.bDescriptorType = USB_DESC_ENDPOINT;
12930 + desc.b.ep1.bEndpointAddress = USB_EP_ADDRESS( 1, USB_IN );
12931 + desc.b.ep1.bmAttributes = USB_EP_BULK;
12932 + desc.b.ep1.wMaxPacketSize = make_word_c( 64 );
12933 + desc.b.ep1.bInterval = 0;
12935 + desc.b.ep2.bLength = sizeof( ep_desc_t );
12936 + desc.b.ep2.bDescriptorType = USB_DESC_ENDPOINT;
12937 + desc.b.ep2.bEndpointAddress = USB_EP_ADDRESS( 2, USB_OUT );
12938 + desc.b.ep2.bmAttributes = USB_EP_BULK;
12939 + desc.b.ep2.wMaxPacketSize = make_word_c( 64 );
12940 + desc.b.ep2.bInterval = 0;
12942 +// FIXME: Add support for all endpoint...
12944 + /* set language */
12945 + /* See: http://www.usb.org/developers/data/USB_LANGIDs.pdf */
12946 + sd_zero.bDescriptorType = USB_DESC_STRING;
12947 + sd_zero.bLength = sizeof( string_desc_t );
12948 + sd_zero.bString[0] = make_word_c( 0x409 ); /* American English */
12949 + pxa_usb_set_string_descriptor( 0, &sd_zero );
12952 +/* soft_connect_hook()
12953 + * Some devices have platform-specific circuitry to make USB
12954 + * not seem to be plugged in, even when it is. This allows
12955 + * software to control when a device 'appears' on the USB bus
12956 + * (after Linux has booted and this driver has loaded, for
12957 + * example). If you have such a circuit, control it here.
12960 +soft_connect_hook( int enable )
12964 +/* disable the UDC at the source */
12968 + soft_connect_hook( 0 );
12969 + /* clear UDC-enable */
12970 + udc_clear_mask_UDCCR( UDCCR_UDE);
12972 + /* Disable clock for USB device */
12973 + CKEN &= ~CKEN11_USB;
12977 +/* enable the udc at the source */
12981 + /* Enable clock for USB device */
12982 + CKEN |= CKEN11_USB;
12984 + /* try to clear these bits before we enable the udc */
12985 + udc_ack_int_UDCCR( UDCCR_SUSIR);
12986 + udc_ack_int_UDCCR( UDCCR_RSTIR);
12987 + udc_ack_int_UDCCR( UDCCR_RESIR);
12989 + /* set UDC-enable */
12990 + udc_set_mask_UDCCR( UDCCR_UDE);
12991 + if( (UDCCR & UDCCR_UDA) == 0)
12993 + /* There's a reset on the bus,
12994 + * clear the interrupt bit and keep going
12996 + udc_ack_int_UDCCR( UDCCR_RSTIR);
12999 + /* "USB test mode" to work around errata 40-42 (stepping a0, a1)
13000 + * which could result in missing packets and interrupts.
13001 + * Supposedly this turns off double buffering for all endpoints.
13003 + if( usb_debug) printk( "USB RES1=%x RES2=%x RES3=%x\n", UDC_RES1, UDC_RES2, UDC_RES3);
13006 + if( usb_debug) printk( "USB RES1=%x RES2=%x RES3=%x\n", UDC_RES1, UDC_RES2, UDC_RES3);
13009 +//////////////////////////////////////////////////////////////////////////////
13010 +// Proc Filesystem Support
13011 +//////////////////////////////////////////////////////////////////////////////
13013 +#if CONFIG_PROC_FS
13015 +#define SAY( fmt, args... ) p += sprintf(p, fmt, ## args )
13016 +#define SAYV( num ) p += sprintf(p, num_fmt, "Value", num )
13017 +#define SAYC( label, yn ) p += sprintf(p, yn_fmt, label, yn )
13018 +#define SAYS( label, v ) p += sprintf(p, cnt_fmt, label, v )
13020 +static int usbctl_read_proc(char *page, char **start, off_t off,
13021 + int count, int *eof, void *data)
13023 + const char * num_fmt = "%25.25s: %8.8lX\n";
13024 + const char * cnt_fmt = "%25.25s: %lu\n";
13025 + const char * yn_fmt = "%25.25s: %s\n";
13026 + const char * yes = "YES";
13027 + const char * no = "NO";
13032 + SAY( "PXA USB Controller Core\n" );
13033 + SAY( "Active Client: %s\n", usbd_info.client_name ? usbd_info.client_name : "none");
13034 + SAY( "USB state: %s (%s) %d\n",
13035 + device_state_names[ sm_state_to_device_state[ sm_state ] ],
13036 + state_names[ sm_state ],
13039 + SAYS( "ep0 bytes read", usbd_info.stats.ep0_bytes_read );
13040 + SAYS( "ep0 bytes written", usbd_info.stats.ep0_bytes_written );
13041 + SAYS( "ep0 FIFO read failures", usbd_info.stats.ep0_fifo_write_failures );
13042 + SAYS( "ep0 FIFO write failures", usbd_info.stats.ep0_fifo_write_failures );
13047 + SAY( "\nUDC Control Register\n" );
13049 + SAYC( "UDC Enabled", ( v & UDCCR_UDE ) ? yes : no );
13050 + SAYC( "UDC Active", ( v & UDCCR_UDA ) ? yes : no );
13051 + SAYC( "Suspend/Resume interrupts masked", ( v & UDCCR_SRM ) ? yes : no );
13052 + SAYC( "Reset interrupts masked", ( v & UDCCR_REM ) ? yes : no );
13053 + SAYC( "Reset pending", ( v & UDCCR_RSTIR ) ? yes : no );
13054 + SAYC( "Suspend pending", ( v & UDCCR_SUSIR ) ? yes : no );
13055 + SAYC( "Resume pending", ( v & UDCCR_RESIR ) ? yes : no );
13057 + len = ( p - page ) - off;
13060 + *eof = ( len <=count ) ? 1 : 0;
13061 + *start = page + off;
13065 +#endif /* CONFIG_PROC_FS */
13068 +static void irq_handler(int channel, void *data, struct pt_regs *regs)
13070 + if( channel == usbd_info.dmach_rx)
13072 + printk( "USB receive DMA\n");
13074 + else if( channel == usbd_info.dmach_tx)
13076 + printk( "USB transmit DMA\n");
13080 + printk( "USB unknown DMA channel\n");
13085 +//////////////////////////////////////////////////////////////////////////////
13086 +// Module Initialization and Shutdown
13087 +//////////////////////////////////////////////////////////////////////////////
13090 + * Module load time. Allocate dma and interrupt resources. Setup /proc fs
13091 + * entry. Leave UDC disabled.
13093 +int __init usbctl_init( void )
13099 + memset( &usbd_info, 0, sizeof( usbd_info ) );
13101 +#if CONFIG_PROC_FS
13102 + create_proc_read_entry ( PROC_NODE_NAME, 0, NULL, usbctl_read_proc, NULL);
13106 + /* setup rx dma */
13107 + usbd_info.dmach_rx = pxa_request_dma("USB receive", DMA_PRIO_MEDIUM, irq_handler, 0 /*data; DMA_Ser0UDCRd*/);
13108 + if (usbd_info.dmach_rx < 0) {
13109 + printk("%sunable to register for rx dma rc=%d\n", pszMe, usbd_info.dmach_rx );
13113 + /* setup tx dma */
13114 + usbd_info.dmach_tx = pxa_request_dma("USB receive", DMA_PRIO_MEDIUM, irq_handler, 0 /*data; DMA_Ser0UDCRd*/);
13115 + if (usbd_info.dmach_tx < 0) {
13116 + printk("%sunable to register for tx dma rc=%d\n",pszMe,usbd_info.dmach_tx);
13121 + /* now allocate the IRQ. */
13122 + retval = request_irq(IRQ_USB, udc_int_hndlr, SA_INTERRUPT, "PXA USB core", NULL);
13124 + printk("%sCouldn't request USB irq rc=%d\n",pszMe, retval);
13128 + printk( "PXA USB Controller Core Initialized\n");
13133 + pxa_free_dma(usbd_info.dmach_tx);
13134 + usbd_info.dmach_tx = 0;
13136 + pxa_free_dma(usbd_info.dmach_rx);
13137 + usbd_info.dmach_rx = 0;
13144 + * Release DMA and interrupt resources
13146 +void __exit usbctl_exit( void )
13148 + printk("Unloading PXA USB Controller\n");
13152 +#if CONFIG_PROC_FS
13153 + remove_proc_entry ( PROC_NODE_NAME, NULL);
13156 + pxa_free_dma(usbd_info.dmach_rx);
13157 + pxa_free_dma(usbd_info.dmach_tx);
13158 + free_irq(IRQ_USB, NULL);
13161 +module_init( usbctl_init );
13162 +module_exit( usbctl_exit );
13164 +EXPORT_SYMBOL( pxa_usb_open );
13165 +EXPORT_SYMBOL( pxa_usb_start );
13166 +EXPORT_SYMBOL( pxa_usb_stop );
13167 +EXPORT_SYMBOL( pxa_usb_close );
13168 +EXPORT_SYMBOL( pxa_usb_get_descriptor_ptr );
13169 +EXPORT_SYMBOL( pxa_usb_set_string_descriptor );
13170 +EXPORT_SYMBOL( pxa_usb_get_string_descriptor );
13171 +EXPORT_SYMBOL( pxa_usb_kmalloc_string_descriptor );
13173 +++ linux-2.4.27/arch/arm/mach-pxa/usb_ctl.h
13176 + * Copyright (C) Compaq Computer Corporation, 1998, 1999
13177 + * Copyright (C) Extenex Corporation 2001
13178 + * Copyright (C) Intrinsyc, Inc., 2002
13182 + * PRIVATE interface used to share info among components of the PXA USB
13183 + * core: usb_ctl, usb_ep0, usb_recv and usb_send. Clients of the USB core
13184 + * should use pxa_usb.h.
13187 + * Frank Becker (Intrinsyc) - derived from sa1100 usb_ctl.h
13191 +#ifndef _USB_CTL_H
13192 +#define _USB_CTL_H
13194 +/* Interrupt mask bits and UDC enable bit */
13195 +#define UDCCR_MASK_BITS (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
13198 + * These states correspond to those in the USB specification v1.0
13199 + * in chapter 8, Device Framework.
13202 + USB_STATE_NOTATTACHED =0,
13203 + USB_STATE_ATTACHED =1,
13204 + USB_STATE_POWERED =2,
13205 + USB_STATE_DEFAULT =3,
13206 + USB_STATE_ADDRESS =4,
13207 + USB_STATE_CONFIGURED =5,
13208 + USB_STATE_SUSPENDED =6
13211 +struct usb_stats_t {
13212 + unsigned long ep0_fifo_write_failures;
13213 + unsigned long ep0_bytes_written;
13214 + unsigned long ep0_fifo_read_failures;
13215 + unsigned long ep0_bytes_read;
13220 + char * client_name;
13221 + dmach_t dmach_tx, dmach_rx;
13223 + unsigned char address;
13224 + struct usb_stats_t stats;
13227 +/* in usb_ctl.c */
13228 +extern struct usb_info_t usbd_info;
13231 + * Function Prototypes
13242 +int usbctl_next_state_on_event( int event );
13244 +/* endpoint zero */
13245 +void ep0_reset(void);
13246 +void ep0_int_hndlr(void);
13249 +void ep_bulk_out1_state_change_notify( int new_state );
13250 +int ep_bulk_out1_recv(void);
13251 +int ep_bulk_out1_init(int chn);
13252 +void ep_bulk_out1_int_hndlr(int status);
13253 +void ep_bulk_out1_reset(void);
13254 +void ep_bulk_out1_stall(void);
13257 +void ep_bulk_in1_state_change_notify( int new_state );
13258 +void ep_bulk_in1_reset(void);
13259 +int ep_bulk_in1_init(int chn);
13260 +void ep_bulk_in1_int_hndlr(int status);
13261 +void ep_bulk_in1_stall(void);
13263 +#endif /* _USB_CTL_H */
13265 +++ linux-2.4.27/arch/arm/mach-pxa/usb_ep0.c
13268 + * Copyright (C) Extenex Corporation 2001
13269 + * Copyright (C) Compaq Computer Corporation, 1998, 1999
13270 + * Copyright (C) Intrinsyc, Inc., 2002
13272 + * PXA USB controller driver - Endpoint zero management
13275 + * linux/Documentation/arm/SA1100/SA1100_USB
13279 + * Frank Becker (Intrinsyc) - derived from sa1100 usb_ctl.c
13283 +#include <linux/config.h>
13284 +#include <linux/module.h>
13285 +#include <linux/init.h>
13286 +#include <linux/proc_fs.h>
13287 +#include <linux/tqueue.h>
13288 +#include <linux/delay.h>
13289 +#include <linux/sched.h>
13290 +#include <linux/slab.h>
13291 +#include <asm/io.h>
13292 +#include <asm/dma.h>
13293 +#include <asm/irq.h>
13295 +#include "pxa_usb.h" /* public interface */
13296 +#include "usb_ctl.h" /* private stuff */
13297 +#include "usb_ep0.h"
13300 +// 1 == lots of trace noise, 0 = only "important' stuff
13301 +#define VERBOSITY 0
13303 +enum { true = 1, false = 0 };
13306 +#define MIN( a, b ) ((a)<(b)?(a):(b))
13309 +#if 1 && !defined( ASSERT )
13310 +# define ASSERT(expr) \
13312 + printk( "Assertion failed! %s,%s,%s,line=%d\n",\
13313 +#expr,__FILE__,__FUNCTION__,__LINE__); \
13316 +# define ASSERT(expr)
13320 +#define PRINTKD(fmt, args...) printk( fmt , ## args)
13322 +#define PRINTKD(fmt, args...)
13325 +static EP0_state ep0_state = EP0_IDLE;
13327 +/***************************************************************************
13329 + ***************************************************************************/
13330 +/* "setup handlers" -- the main functions dispatched to by the
13331 + .. isr. These represent the major "modes" of endpoint 0 operation */
13332 +static void sh_setup_begin(void); /* setup begin (idle) */
13333 +static void sh_write( void ); /* writing data */
13334 +static int read_fifo( usb_dev_request_t * p );
13335 +static void write_fifo( void );
13336 +static void get_descriptor( usb_dev_request_t * pReq );
13337 +static void queue_and_start_write( void * p, int req, int act );
13339 +/***************************************************************************
13341 + ***************************************************************************/
13343 +inline int type_code_from_request( __u8 by ) { return (( by >> 4 ) & 3); }
13345 +/* print string descriptor */
13346 +static inline void psdesc( string_desc_t * p )
13349 + int nchars = ( p->bLength - 2 ) / sizeof( __u16 );
13351 + for( i = 0 ; i < nchars ; i++ ) {
13352 + printk( "%c", (char) p->bString[i] );
13358 +/* "pcs" == "print control status" */
13359 +static inline void pcs( void )
13361 + __u32 foo = UDCCS0;
13362 + printk( "%08x: %s %s %s %s %s %s\n",
13364 + foo & UDCCS0_SA ? "SA" : "",
13365 + foo & UDCCS0_OPR ? "OPR" : "",
13366 + foo & UDCCS0_RNE ? "RNE" : "",
13367 + foo & UDCCS0_SST ? "SST" : "",
13368 + foo & UDCCS0_FST ? "FST" : "",
13369 + foo & UDCCS0_DRWF ? "DRWF" : ""
13372 +static inline void preq( usb_dev_request_t * pReq )
13374 + static char * tnames[] = { "dev", "intf", "ep", "oth" };
13375 + static char * rnames[] = { "std", "class", "vendor", "???" };
13377 + switch( pReq->bRequest ) {
13378 + case GET_STATUS: psz = "get stat"; break;
13379 + case CLEAR_FEATURE: psz = "clr feat"; break;
13380 + case SET_FEATURE: psz = "set feat"; break;
13381 + case SET_ADDRESS: psz = "set addr"; break;
13382 + case GET_DESCRIPTOR: psz = "get desc"; break;
13383 + case SET_DESCRIPTOR: psz = "set desc"; break;
13384 + case GET_CONFIGURATION: psz = "get cfg"; break;
13385 + case SET_CONFIGURATION: psz = "set cfg"; break;
13386 + case GET_INTERFACE: psz = "get intf"; break;
13387 + case SET_INTERFACE: psz = "set intf"; break;
13388 + case SYNCH_FRAME: psz = "synch frame"; break;
13389 + default: psz = "unknown"; break;
13391 + printk( "- [%s: %s req to %s. dir=%s]\n", psz,
13392 + rnames[ (pReq->bmRequestType >> 5) & 3 ],
13393 + tnames[ pReq->bmRequestType & 3 ],
13394 + ( pReq->bmRequestType & 0x80 ) ? "in" : "out" );
13398 +static inline void pcs( void ){}
13399 +static inline void preq( usb_dev_request_t *x){}
13402 +/***************************************************************************
13404 + ***************************************************************************/
13405 +static const char pszMe[] = "usbep0: ";
13407 +/* pointer to current setup handler */
13408 +static void (*current_handler)(void) = sh_setup_begin;
13410 +/* global write struct to keep write
13411 + ..state around across interrupts */
13413 + unsigned char *p;
13417 +/***************************************************************************
13419 + ***************************************************************************/
13421 +/* reset received from HUB (or controller just went nuts and reset by itself!)
13422 + so udc core has been reset, track this state here */
13423 +void ep0_reset(void)
13425 + PRINTKD( "%sep0_reset\n", pszMe);
13426 + /* reset state machine */
13427 + current_handler = sh_setup_begin;
13429 + wr.bytes_left = 0;
13430 + usbd_info.address=0;
13433 +/* handle interrupt for endpoint zero */
13434 +void ep0_int_hndlr( void )
13436 + PRINTKD( "%sep0_int_hndlr\n", pszMe);
13438 + (*current_handler)();
13441 +/***************************************************************************
13443 + ***************************************************************************/
13445 + * sh_setup_begin()
13446 + * This setup handler is the "idle" state of endpoint zero. It looks for OPR
13447 + * (OUT packet ready) to see if a setup request has been been received from the
13451 +static void sh_setup_begin( void )
13453 + usb_dev_request_t req;
13454 + int request_type;
13456 + __u32 cs_reg_in = UDCCS0;
13458 + PRINTKD( "%ssh_setup_begin\n", pszMe);
13460 + /* Be sure out packet ready, otherwise something is wrong */
13461 + if ( (cs_reg_in & UDCCS0_OPR) == 0 ) {
13462 + /* we can get here early...if so, we'll int again in a moment */
13463 + PRINTKD( "%ssetup begin: no OUT packet available. Exiting\n", pszMe );
13467 + if( ((cs_reg_in & UDCCS0_SA) == 0) && (ep0_state == EP0_IN_DATA_PHASE))
13469 + PRINTKD( "%ssetup begin: premature status\n", pszMe );
13471 + /* premature status, reset tx fifo and go back to idle state*/
13472 + UDCCS0 = UDCCS0_OPR | UDCCS0_FTF;
13474 + ep0_state = EP0_IDLE;
13478 + if( (UDCCS0 & UDCCS0_RNE) == 0)
13480 + /* zero-length OUT? */
13481 + printk( "%ssetup begin: zero-length OUT?\n", pszMe );
13485 + /* read the setup request */
13486 + n = read_fifo( &req );
13487 + if ( n != sizeof( req ) ) {
13488 + printk( "%ssetup begin: fifo READ ERROR wanted %d bytes got %d. "
13489 + " Stalling out...\n",
13490 + pszMe, sizeof( req ), n );
13491 + /* force stall, serviced out */
13492 + UDCCS0 = UDCCS0_FST;
13496 + /* Is it a standard request? (not vendor or class request) */
13497 + request_type = type_code_from_request( req.bmRequestType );
13498 + if ( request_type != 0 ) {
13499 + printk( "%ssetup begin: unsupported bmRequestType: %d ignored\n",
13500 + pszMe, request_type );
13506 + unsigned char * pdb = (unsigned char *) &req;
13507 + PRINTKD( "%2.2X %2.2X %2.2X %2.2X %2.2X %2.2X %2.2X %2.2X ",
13508 + pdb[0], pdb[1], pdb[2], pdb[3], pdb[4], pdb[5], pdb[6], pdb[7]
13515 + switch( req.bRequest ) {
13517 + case SET_ADDRESS:
13518 + PRINTKD( "%sSET_ADDRESS handled by UDC\n", pszMe);
13520 +#if 0 /* NOT_NEEDED */
13522 + case SET_FEATURE:
13523 + PRINTKD( "%sSET_FEATURE handled by UDC\n", pszMe);
13526 + case CLEAR_FEATURE:
13527 + PRINTKD( "%sCLEAR_FEATURE handled by UDC\n", pszMe);
13530 + case GET_CONFIGURATION:
13531 + PRINTKD( "%sGET_CONFIGURATION handled by UDC\n", pszMe );
13535 + PRINTKD( "%s%sGET_STATUS handled by UDC\n", pszMe );
13538 + case GET_INTERFACE:
13539 + PRINTKD( "%sGET_INTERFACE handled by UDC\n", pszMe);
13542 + case SYNCH_FRAME:
13543 + PRINTKD( "%sSYNCH_FRAME handled by UDC\n", pszMe );
13547 + case GET_DESCRIPTOR:
13548 + PRINTKD( "%sGET_DESCRIPTOR\n", pszMe );
13549 + get_descriptor( &req );
13552 + case SET_INTERFACE:
13553 + PRINTKD( "%sSET_INTERFACE TODO...\n", pszMe);
13556 + case SET_DESCRIPTOR:
13557 + PRINTKD( "%sSET_DESCRIPTOR TODO...\n", pszMe );
13560 + case SET_CONFIGURATION:
13561 + PRINTKD( "%sSET_CONFIGURATION %d\n", pszMe, req.wValue);
13564 + * FIXME: Something is not quite right here... I only ever get a
13565 + * de-configure from the host. Ignoring it for now, since usb
13566 + * ethernet won't do anything unless usb is 'configured'.
13570 + switch( req.wValue)
13574 + usbctl_next_state_on_event( kEvConfig );
13577 + /* de-configured */
13578 + usbctl_next_state_on_event( kEvDeConfig );
13581 + PRINTKD( "%sSET_CONFIGURATION: unknown configuration value (%d)\n", pszMe, req.wValue);
13587 + printk("%sunknown request 0x%x\n", pszMe, req.bRequest);
13589 + } /* switch( bRequest ) */
13598 + * Due to UDC bugs we push everything into the fifo in one go.
13599 + * Using interrupts just didn't work right...
13600 + * This should be ok, since control request are small.
13602 +static void sh_write()
13604 + PRINTKD( "sh_write\n" );
13608 + } while( ep0_state != EP0_END_XFER);
13611 +/***************************************************************************
13612 + Other Private Subroutines
13613 + ***************************************************************************/
13615 + * queue_and_start_write()
13616 + * data == data to send
13617 + * req == bytes host requested
13618 + * act == bytes we actually have
13620 + * Sets up the global "wr"-ite structure and load the outbound FIFO
13624 +static void queue_and_start_write( void * data, int req, int act )
13626 + PRINTKD( "write start: bytes requested=%d actual=%d\n", req, act);
13628 + wr.p = (unsigned char*) data;
13629 + wr.bytes_left = MIN( act, req );
13631 + ep0_state = EP0_IN_DATA_PHASE;
13638 + * Stick bytes in the endpoint zero FIFO.
13641 +static void write_fifo( void )
13643 + int bytes_this_time = MIN( wr.bytes_left, EP0_FIFO_SIZE );
13644 + int bytes_written = 0;
13646 + while( bytes_this_time-- ) {
13647 +// PRINTKD( "%2.2X ", *wr.p );
13651 + wr.bytes_left -= bytes_written;
13653 + usbd_info.stats.ep0_bytes_written += bytes_written;
13655 + if( (wr.bytes_left==0))
13657 + wr.p = NULL; /* be anal */
13659 + if(bytes_written < EP0_FIFO_SIZE)
13664 + /* We always end the transfer with a short or zero length packet */
13665 + ep0_state = EP0_END_XFER;
13666 + current_handler = sh_setup_begin;
13668 + /* Let the packet go... */
13669 + UDCCS0 = UDCCS0_IPR;
13671 + /* Wait until we get to status-stage, then ack.
13673 + * When the UDC sets the UDCCS0[OPR] bit, an interrupt
13674 + * is supposed to be generated (see 12.5.1 step 14ff, PXA Dev Manual).
13675 + * That approach didn't work out. Usually a new SETUP command was
13676 + * already in the fifo. I tried many approaches but was always losing
13677 + * at least some OPR interrupts. Thus the polling below...
13683 + if( (UDCCS0 & UDCCS0_OPR))
13685 + /* clear OPR, generate ack */
13686 + UDCCS0 = UDCCS0_OPR;
13693 + PRINTKD( "write fifo: count=%d UDCCS0=%x UDCCS0=%x\n", count, udccs0, UDCCS0);
13696 + /* something goes poopy if I dont wait here ... */
13699 + PRINTKD( "write fifo: bytes sent=%d, bytes left=%d\n", bytes_written, wr.bytes_left);
13704 + * Read bytes out of FIFO and put in request.
13705 + * Called to do the initial read of setup requests
13706 + * from the host. Return number of bytes read.
13709 +static int read_fifo( usb_dev_request_t * request )
13711 + int bytes_read = 0;
13712 + unsigned char * pOut = (unsigned char*) request;
13714 + int udccs0 = UDCCS0;
13716 + if( (udccs0 & SETUP_READY) == SETUP_READY)
13718 + /* ok it's a setup command */
13719 + while( UDCCS0 & UDCCS0_RNE)
13721 + if( bytes_read >= sizeof( usb_dev_request_t))
13723 + /* We've already read enought o fill usb_dev_request_t.
13724 + * Our tummy is full. Go barf...
13726 + printk( "%sread_fifo(): read failure\n", pszMe );
13727 + usbd_info.stats.ep0_fifo_read_failures++;
13735 + PRINTKD( "read_fifo %d bytes\n", bytes_read );
13737 + /* clear SA & OPR */
13738 + UDCCS0 = SETUP_READY;
13740 + usbd_info.stats.ep0_bytes_read += bytes_read;
13741 + return bytes_read;
13745 + * get_descriptor()
13746 + * Called from sh_setup_begin to handle data return
13747 + * for a GET_DESCRIPTOR setup request.
13749 +static void get_descriptor( usb_dev_request_t * pReq )
13751 + string_desc_t * pString;
13752 + ep_desc_t * pEndpoint = 0;
13754 + desc_t * pDesc = pxa_usb_get_descriptor_ptr();
13755 + int type = pReq->wValue >> 8;
13756 + int idx = pReq->wValue & 0xFF;
13758 +// PRINTKD( "%sget_descriptor for %d\n", pszMe, type );
13760 + case USB_DESC_DEVICE:
13761 + queue_and_start_write( &pDesc->dev,
13763 + pDesc->dev.bLength );
13766 + // return config descriptor buffer, cfg, intf, 2 ep
13767 + case USB_DESC_CONFIG:
13768 + queue_and_start_write( &pDesc->b,
13770 + sizeof( struct cdb ) );
13773 + // not quite right, since doesn't do language code checking
13774 + case USB_DESC_STRING:
13775 + pString = pxa_usb_get_string_descriptor( idx );
13777 + if ( idx != 0 ) { // if not language index
13778 + printk( "%sReturn string %d: ", pszMe, idx );
13779 + psdesc( pString );
13781 + queue_and_start_write( pString,
13783 + pString->bLength );
13786 + printk("%sunkown string index %d Stall.\n", pszMe, idx );
13790 + case USB_DESC_INTERFACE:
13791 + if ( idx == pDesc->b.intf.bInterfaceNumber ) {
13792 + queue_and_start_write( &pDesc->b.intf,
13794 + pDesc->b.intf.bLength );
13798 + case USB_DESC_ENDPOINT: /* correct? 21Feb01ww */
13800 + pEndpoint = &pDesc->b.ep1; //[BULK_IN1];
13801 + else if ( idx == 2 )
13802 + pEndpoint = &pDesc->b.ep2; //[BULK_OUT1];
13804 + pEndpoint = NULL;
13805 + if ( pEndpoint ) {
13806 + queue_and_start_write( pEndpoint,
13808 + pEndpoint->bLength );
13810 + printk("%sunkown endpoint index %d Stall.\n", pszMe, idx );
13816 + printk("%sunknown descriptor type %d. Stall.\n", pszMe, type );
13822 +/* end usb_ep0.c - who needs this comment? */
13824 +++ linux-2.4.27/arch/arm/mach-pxa/usb_ep0.h
13827 + * Copyright (C) Intrinsyc, Inc., 2002
13829 + * usb_ep0.h - PXA USB controller driver.
13830 + * Endpoint zero management
13833 + * linux/Documentation/arm/SA1100/SA1100_USB
13837 + * Frank Becker (Intrinsyc) -
13841 +#ifndef __USB_EP0_H
13842 +#define __USB_EP0_H
13844 +#define EP0_FIFO_SIZE 16
13845 +#define SETUP_READY (UDCCS0_SA | UDCCS0_OPR)
13847 +/*================================================
13848 + * USB Protocol Stuff
13851 +/* Request Codes */
13854 + CLEAR_FEATURE =1,
13855 + /* reserved =2 */
13857 + /* reserved =4 */
13859 + GET_DESCRIPTOR =6,
13860 + SET_DESCRIPTOR =7,
13861 + GET_CONFIGURATION =8,
13862 + SET_CONFIGURATION =9,
13863 + GET_INTERFACE =10,
13864 + SET_INTERFACE =11,
13870 + EP0_IN_DATA_PHASE,
13872 + EP0_OUT_DATA_PHASE
13875 +/* USB Device Requests */
13878 + __u8 bmRequestType;
13883 +} usb_dev_request_t __attribute__ ((packed));
13885 +/* Data extraction from usb_request_t fields */
13887 + kTargetDevice =0,
13888 + kTargetInterface=1,
13889 + kTargetEndpoint =2
13893 +++ linux-2.4.27/arch/arm/mach-pxa/usb_recv.c
13896 + * Generic receive layer for the PXA USB client function
13898 + * This code was loosely inspired by the original version which was
13899 + * Copyright (c) Compaq Computer Corporation, 1998-1999
13900 + * Copyright (c) 2001 by Nicolas Pitre
13902 + * This program is free software; you can redistribute it and/or modify
13903 + * it under the terms of the GNU General Public License version 2 as
13904 + * published by the Free Software Foundation.
13907 + * Frank Becker (Intrinsyc) - derived from sa1100 usb_recv.c
13909 + * TODO: Add support for DMA.
13913 +#include <linux/module.h>
13914 +#include <linux/pci.h>
13915 +#include <linux/errno.h>
13916 +#include <asm/dma.h>
13917 +#include <asm/system.h>
13919 +#include "pxa_usb.h"
13920 +#include "usb_ctl.h"
13923 +static unsigned int usb_debug = DEBUG;
13925 +#define usb_debug 0 /* gcc will remove all the debug code for us */
13928 +static char *ep_bulk_out1_buf;
13929 +static int ep_bulk_out1_len;
13930 +static int ep_bulk_out1_remain;
13931 +static usb_callback_t ep_bulk_out1_callback;
13932 +static int rx_pktsize;
13935 +ep_bulk_out1_start(void)
13937 + /* disable DMA */
13938 + UDCCS2 &= ~UDCCS_BO_DME;
13940 + /* enable interrupts for endpoint 2 (bulk out) */
13941 + UICR0 &= ~UICR0_IM2;
13945 +ep_bulk_out1_done(int flag)
13947 + int size = ep_bulk_out1_len - ep_bulk_out1_remain;
13949 + if (!ep_bulk_out1_len)
13952 + ep_bulk_out1_len = 0;
13953 + if (ep_bulk_out1_callback) {
13954 + ep_bulk_out1_callback(flag, size);
13959 +ep_bulk_out1_state_change_notify( int new_state )
13964 +ep_bulk_out1_stall( void )
13966 + /* SET_FEATURE force stall at UDC */
13967 + UDCCS2 |= UDCCS_BO_FST;
13971 +ep_bulk_out1_init(int chn)
13973 + desc_t * pd = pxa_usb_get_descriptor_ptr();
13974 + rx_pktsize = __le16_to_cpu( pd->b.ep1.wMaxPacketSize );
13975 + ep_bulk_out1_done(-EAGAIN);
13980 +ep_bulk_out1_reset(void)
13982 + desc_t * pd = pxa_usb_get_descriptor_ptr();
13983 + rx_pktsize = __le16_to_cpu( pd->b.ep1.wMaxPacketSize );
13984 + UDCCS2 &= ~UDCCS_BO_FST;
13985 + ep_bulk_out1_done(-EINTR);
13989 +ep_bulk_out1_int_hndlr(int udcsr)
13991 + int status = UDCCS2;
13992 + if( usb_debug) printk("ep_bulk_out1_int_hndlr: UDCCS2=%x\n", status);
13994 + if( (status & (UDCCS_BO_RNE | UDCCS_BO_RSP)) == UDCCS_BO_RSP)
13996 + /* zero-length packet */
13999 + if( status & UDCCS_BO_RNE)
14003 + char *buf = ep_bulk_out1_buf + ep_bulk_out1_len - ep_bulk_out1_remain;
14005 + /* bytes in FIFO */
14006 + len = (UBCR2 & 0xff) +1;
14008 + if( usb_debug) printk("usb_recv: "
14009 + "len=%d out1_len=%d out1_remain=%d\n",
14010 + len,ep_bulk_out1_len,ep_bulk_out1_remain);
14012 + if( len > ep_bulk_out1_remain)
14014 + /* FIXME: if this happens, we need a temporary overflow buffer */
14015 + printk("usb_recv: Buffer overwrite warning...\n");
14016 + len = ep_bulk_out1_remain;
14019 + /* read data out of fifo */
14020 + for( i=0; i<len; i++)
14022 + *buf++ = UDDR2 & 0xff;
14025 + ep_bulk_out1_remain -= len;
14026 + ep_bulk_out1_done((len) ? 0 : -EPIPE);
14029 + /* ack RPC - FIXME: '|=' we may ack SST here, too */
14030 + UDCCS2 |= UDCCS_BO_RPC;
14035 +pxa_usb_recv(char *buf, int len, usb_callback_t callback)
14039 + if (ep_bulk_out1_len)
14042 + local_irq_save(flags);
14043 + ep_bulk_out1_buf = buf;
14044 + ep_bulk_out1_len = len;
14045 + ep_bulk_out1_callback = callback;
14046 + ep_bulk_out1_remain = len;
14047 + ep_bulk_out1_start();
14048 + local_irq_restore(flags);
14054 +pxa_usb_recv_reset(void)
14056 + ep_bulk_out1_reset();
14060 +pxa_usb_recv_stall(void)
14062 + ep_bulk_out1_stall();
14065 +EXPORT_SYMBOL(pxa_usb_recv_stall);
14066 +EXPORT_SYMBOL(pxa_usb_recv);
14067 +EXPORT_SYMBOL(pxa_usb_recv_reset);
14069 +++ linux-2.4.27/arch/arm/mach-pxa/usb_send.c
14072 + * Generic xmit layer for the PXA USB client function
14074 + * This code was loosely inspired by the original version which was
14075 + * Copyright (c) Compaq Computer Corporation, 1998-1999
14076 + * Copyright (c) 2001 by Nicolas Pitre
14078 + * This program is free software; you can redistribute it and/or modify
14079 + * it under the terms of the GNU General Public License version 2 as
14080 + * published by the Free Software Foundation.
14083 + * Frank Becker (Intrinsyc) - derived from sa1100 usb_send.c
14085 + * TODO: Add support for DMA.
14089 +#include <linux/module.h>
14090 +#include <linux/pci.h>
14091 +#include <linux/errno.h>
14092 +#include <asm/hardware.h>
14093 +#include <asm/dma.h>
14094 +#include <asm/system.h>
14095 +#include <asm/byteorder.h>
14097 +#include "pxa_usb.h"
14098 +#include "usb_ctl.h"
14101 +static unsigned int usb_debug = DEBUG;
14103 +#define usb_debug 0 /* gcc will remove all the debug code for us */
14106 +static char *ep_bulk_in1_buf;
14107 +static int ep_bulk_in1_len;
14108 +static int ep_bulk_in1_remain;
14109 +static usb_callback_t ep_bulk_in1_callback;
14110 +static int tx_pktsize;
14112 +/* device state is changing, async */
14114 +ep_bulk_in1_state_change_notify( int new_state )
14118 +/* set feature stall executing, async */
14120 +ep_bulk_in1_stall( void )
14122 + UDCCS1 |= UDCCS_BI_FST;
14126 +ep_bulk_in1_send_packet(void)
14129 + char *buf = ep_bulk_in1_buf + ep_bulk_in1_len - ep_bulk_in1_remain;
14130 + int out_size = tx_pktsize;
14132 + if( usb_debug) printk( "ep_bulk_in1_send_packet: UICR0=%x UDCCS1=%x\n", UICR0, UDCCS1);
14134 + if( out_size > ep_bulk_in1_remain)
14136 + out_size = ep_bulk_in1_remain;
14139 + for( i=0; i<out_size; i++)
14144 + UDCCS1 = UDCCS_BI_TPC;
14145 + if( out_size < tx_pktsize)
14147 + /* short packet */
14148 + UDCCS1 = UDCCS_BI_TSP;
14150 + ep_bulk_in1_remain -= out_size;
14152 + if( usb_debug) printk( "ep_bulk_in1_send_packet: "
14153 + "UICR0=%x UDCCS1=%x send bytes=%d left=%d\n",
14154 + UICR0, UDCCS1, out_size, ep_bulk_in1_remain);
14158 +ep_bulk_in1_start(void)
14160 + if (!ep_bulk_in1_len)
14163 + UICR0 &= ~UICR0_IM1;
14165 + ep_bulk_in1_send_packet();
14169 +ep_bulk_in1_done(int flag)
14171 + int size = ep_bulk_in1_len - ep_bulk_in1_remain;
14172 + if (ep_bulk_in1_len) {
14173 + ep_bulk_in1_len = 0;
14174 + if (ep_bulk_in1_callback)
14175 + ep_bulk_in1_callback(flag, size);
14180 +ep_bulk_in1_init(int chn)
14182 + desc_t * pd = pxa_usb_get_descriptor_ptr();
14183 + tx_pktsize = __le16_to_cpu( pd->b.ep2.wMaxPacketSize );
14184 + ep_bulk_in1_done(-EAGAIN);
14189 +ep_bulk_in1_reset(void)
14191 + desc_t * pd = pxa_usb_get_descriptor_ptr();
14192 + tx_pktsize = __le16_to_cpu( pd->b.ep2.wMaxPacketSize );
14193 + UDCCS1 &= ~UDCCS_BI_FST;
14194 + ep_bulk_in1_done(-EINTR);
14198 +ep_bulk_in1_int_hndlr(int usir0)
14200 + int status = UDCCS1;
14202 + if (ep_bulk_in1_remain != 0) {
14203 + /* more data to go */
14204 + ep_bulk_in1_start();
14206 + if( status & UDCCS_BI_TPC)
14208 + UDCCS1 = UDCCS_BI_TPC;
14210 + ep_bulk_in1_done(0);
14215 +pxa_usb_send(char *buf, int len, usb_callback_t callback)
14219 + if( usb_debug) printk( "pxa_usb_send: "
14220 + "data len=%d state=%d blen=%d\n",
14221 + len, usbd_info.state, ep_bulk_in1_len);
14223 + if (usbd_info.state != USB_STATE_CONFIGURED)
14226 + if (ep_bulk_in1_len)
14229 + local_irq_save(flags);
14230 + ep_bulk_in1_buf = buf;
14231 + ep_bulk_in1_len = len;
14232 + ep_bulk_in1_callback = callback;
14233 + ep_bulk_in1_remain = len;
14234 + ep_bulk_in1_start();
14235 + local_irq_restore(flags);
14242 +pxa_usb_send_reset(void)
14244 + ep_bulk_in1_reset();
14248 +pxa_usb_xmitter_avail( void )
14250 + if (usbd_info.state != USB_STATE_CONFIGURED)
14252 + if (ep_bulk_in1_len)
14258 +EXPORT_SYMBOL(pxa_usb_xmitter_avail);
14259 +EXPORT_SYMBOL(pxa_usb_send);
14260 +EXPORT_SYMBOL(pxa_usb_send_reset);
14261 --- linux-2.4.27/arch/arm/mach-sa1100/sa1111-ohci.c~2.4.27-vrs1-pxa1
14262 +++ linux-2.4.27/arch/arm/mach-sa1100/sa1111-ohci.c
14264 * address as its return value, and the DMA address via
14265 * the dma_addr_t pointer.
14267 - vbuf = consistent_alloc(GFP_KERNEL | GFP_DMA, 4, &dma_buf);
14268 + vbuf = consistent_alloc(GFP_KERNEL | GFP_DMA, 4, &dma_buf, 0);
14270 SADTSA = (unsigned long)dma_buf;
14272 --- linux-2.4.27/arch/arm/mach-sa1100/sa1111.c~2.4.27-vrs1-pxa1
14273 +++ linux-2.4.27/arch/arm/mach-sa1100/sa1111.c
14274 @@ -243,9 +243,15 @@
14275 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
14276 * (SA-1110 Developer's Manual, section 9.1.2.1)
14278 +#if CONFIG_ARCH_SA1100
14279 GAFR |= GPIO_32_768kHz;
14280 GPDR |= GPIO_32_768kHz;
14281 TUCR = TUCR_3_6864MHz;
14282 +#elif CONFIG_ARCH_PXA
14283 + set_GPIO_mode(GPIO11_3_6MHz_MD);
14285 +#error missing clock setup
14289 * Turn VCO on, and disable PLL Bypass.
14290 @@ -300,6 +306,8 @@
14294 +#ifdef CONFIG_ARCH_SA1100
14297 * Disable the memory bus request/grant signals on the SA1110 to
14298 * ensure that we don't receive spurious memory requests. We set
14299 @@ -341,5 +349,7 @@
14300 local_irq_restore(flags);
14305 EXPORT_SYMBOL(sa1111_wake);
14306 EXPORT_SYMBOL(sa1111_doze);
14307 --- linux-2.4.27/arch/arm/mm/Makefile~2.4.27-vrs1-pxa1
14308 +++ linux-2.4.27/arch/arm/mm/Makefile
14310 p-$(CONFIG_CPU_ARM1026) += proc-arm1026.o
14311 p-$(CONFIG_CPU_SA110) += proc-sa110.o
14312 p-$(CONFIG_CPU_SA1100) += proc-sa110.o
14313 +p-$(CONFIG_CPU_XSCALE) += proc-xscale.o
14315 # Integrator follows "new style"
14316 # Soon, others will do too, and we can get rid of this
14317 --- linux-2.4.27/arch/arm/mm/consistent.c~2.4.27-vrs1-pxa1
14318 +++ linux-2.4.27/arch/arm/mm/consistent.c
14321 * Note that this does *not* zero the allocated area!
14323 -void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle)
14324 +void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle,
14325 + unsigned long cache_flags)
14327 struct page *page, *end, *free;
14328 unsigned long order;
14332 *dma_handle = page_to_bus(page);
14333 - ret = __ioremap(page_to_pfn(page) << PAGE_SHIFT, size, 0);
14334 + ret = __ioremap(page_to_pfn(page) << PAGE_SHIFT, size, cache_flags);
14338 @@ -106,7 +107,7 @@
14342 - return consistent_alloc(gfp, size, handle);
14343 + return consistent_alloc(gfp, size, handle, 0);
14347 --- linux-2.4.27/arch/arm/mm/init.c~2.4.27-vrs1-pxa1
14348 +++ linux-2.4.27/arch/arm/mm/init.c
14350 static unsigned long totalram_pages;
14351 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
14352 extern char _stext, _text, _etext, _end, __init_begin, __init_end;
14353 +#ifdef CONFIG_XIP_KERNEL
14354 +extern char _endtext, _sdata;
14356 extern unsigned long phys_initrd_start;
14357 extern unsigned long phys_initrd_size;
14359 @@ -347,7 +350,11 @@
14360 * Register the kernel text and data with bootmem.
14361 * Note that this can only be in node 0.
14363 +#ifdef CONFIG_XIP_KERNEL
14364 + reserve_bootmem_node(pgdat, __pa(&_sdata), &_end - &_sdata);
14366 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext);
14369 #ifdef CONFIG_CPU_32
14371 @@ -601,8 +608,13 @@
14372 unsigned int codepages, datapages, initpages;
14375 +#ifndef CONFIG_XIP_KERNEL
14376 codepages = &_etext - &_text;
14377 datapages = &_end - &_etext;
14379 + codepages = &_endtext - &_text;
14380 + datapages = &_end - &_sdata;
14382 initpages = &__init_end - &__init_begin;
14384 high_memory = (void *)__va(meminfo.end);
14385 @@ -658,11 +670,13 @@
14387 void free_initmem(void)
14389 +#ifndef CONFIG_XIP_KERNEL
14390 if (!machine_is_integrator()) {
14391 free_area((unsigned long)(&__init_begin),
14392 (unsigned long)(&__init_end),
14398 #ifdef CONFIG_BLK_DEV_INITRD
14399 --- linux-2.4.27/arch/arm/mm/mm-armv.c~2.4.27-vrs1-pxa1
14400 +++ linux-2.4.27/arch/arm/mm/mm-armv.c
14401 @@ -356,6 +356,19 @@
14405 +#ifdef CONFIG_XIP_KERNEL
14406 + p->physical = KERNEL_XIP_BASE_PHYS;
14407 + p->virtual = KERNEL_XIP_BASE_VIRT;
14408 + p->length = PGDIR_SIZE * 8;
14409 + p->domain = DOMAIN_KERNEL;
14410 + p->prot_read = 0; /* r=0, b=0 --> read-only for kernel mode */
14411 + p->prot_write = 0;
14412 + p->cacheable = 1;
14413 + p->bufferable = 1;
14419 * Go through the initial mappings, but clear out any
14420 * pgdir entries that are not in the description.
14421 @@ -386,7 +399,7 @@
14422 init_maps->prot_read = 0;
14423 init_maps->prot_write = 0;
14424 init_maps->cacheable = 1;
14425 - init_maps->bufferable = 0;
14426 + init_maps->bufferable = 1;
14428 create_mapping(init_maps);
14431 +++ linux-2.4.27/arch/arm/mm/proc-xscale.S
14434 + * linux/arch/arm/mm/proc-xscale.S
14436 + * Author: Nicolas Pitre
14437 + * Created: November 2000
14438 + * Copyright: (C) 2000, 2001 MontaVista Software Inc.
14440 + * This program is free software; you can redistribute it and/or modify
14441 + * it under the terms of the GNU General Public License version 2 as
14442 + * published by the Free Software Foundation.
14444 + * MMU functions for the Intel XScale CPUs
14447 + * some contributions by Brett Gaines <brett.w.gaines@intel.com>
14448 + * Copyright 2001 by Intel Corp.
14451 + * Completely revisited, many important fixes
14452 + * Nicolas Pitre <nico@cam.org>
14455 +#include <linux/config.h>
14456 +#include <linux/linkage.h>
14457 +#include <asm/assembler.h>
14458 +#include <asm/constants.h>
14459 +#include <asm/procinfo.h>
14460 +#include <asm/hardware.h>
14461 +#include <asm/proc/pgtable.h>
14464 + * Some knobs for cache allocation policy.
14465 + * Allocate on write may or may not be beneficial depending on the memory
14466 + * usage pattern of your main application. Write through cache is definitely
14467 + * a performance loss in most cases, but might be used for special purposes.
14469 +#define PMD_CACHE_WRITE_ALLOCATE 1
14470 +#define PTE_CACHE_WRITE_ALLOCATE 1
14471 +#define CACHE_WRITE_THROUGH 0
14474 + * There are errata that say that dirty status bits in the cache may get
14475 + * corrupted. The workaround significantly affects performance, and the bug
14476 + * _might_ just not be that visible or critical to you, so it is configurable.
14477 + * Let's hope a future core revision will tell us this was only a bad dream.
14478 + * But in the mean time the risk and tradeoff is yours to decide....
14480 +#ifdef CONFIG_XSCALE_CACHE_ERRATA
14481 +#undef CACHE_WRITE_THROUGH
14482 +#define CACHE_WRITE_THROUGH 1
14486 + * This is the maximum size of an area which will be flushed. If the area
14487 + * is larger than this, then we flush the whole cache
14489 +#define MAX_AREA_SIZE 32768
14492 + * the cache line size of the I and D cache
14494 +#define CACHELINESIZE 32
14497 + * the size of the data cache
14499 +#define CACHESIZE 32768
14502 + * and the page size
14504 +#define PAGESIZE 4096
14507 + * Virtual address used to allocate the cache when flushed
14509 + * This must be an address range which is _never_ used. It should
14510 + * apparently have a mapping in the corresponding page table for
14511 + * compatibility with future CPUs that _could_ require it. For instance we
14514 + * This must be aligned on a 2*CACHESIZE boundary. The code selects one of
14515 + * the 2 areas in alternance each time the clean_d_cache macro is used.
14516 + * Without this the XScale core exhibits cache eviction problems and no one
14519 + * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
14521 +#define CLEAN_ADDR 0xfffe0000
14524 + * This macro is used to wait for a CP15 write and is needed
14525 + * when we have to ensure that the last operation to the co-pro
14526 + * was completed before continuing with operation.
14528 + .macro cpwait, rd
14529 + mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
14530 + mov \rd, \rd @ wait for completion
14531 + sub pc, pc, #4 @ flush instruction pipeline
14534 + .macro cpwait_ret, lr, rd
14535 + mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
14536 + sub pc, \lr, \rd, LSR #32 @ wait for completion and
14537 + @ flush instruction pipeline
14540 +#if !CACHE_WRITE_THROUGH
14543 + * This macro cleans the entire dcache using line allocate.
14544 + * The main loop has been unrolled to reduce loop overhead.
14545 + * rd and rs are two scratch registers.
14547 + .macro clean_d_cache, rd, rs
14548 + ldr \rs, =clean_addr
14550 + eor \rd, \rd, #CACHESIZE
14552 + add \rs, \rd, #CACHESIZE
14553 +1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
14554 + add \rd, \rd, #CACHELINESIZE
14555 + mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
14556 + add \rd, \rd, #CACHELINESIZE
14557 + mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
14558 + add \rd, \rd, #CACHELINESIZE
14559 + mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
14560 + add \rd, \rd, #CACHELINESIZE
14565 + .macro clean_d_line, rd
14566 + mcr p15, 0, \rd, c7, c10, 1
14570 +clean_addr: .word CLEAN_ADDR
14575 + * If cache is write-through, there is no need to clean it.
14576 + * Simply invalidating will do.
14579 + .macro clean_d_cache, rd, rs
14580 + mcr p15, 0, \rd, c7, c6, 0
14583 + /* let's try to skip this needless operations at least within loops */
14584 + .macro clean_d_line, rd
14592 + * cpu_xscale_data_abort()
14594 + * obtain information about current aborted instruction.
14595 + * Note: we read user space. This means we might cause a data
14596 + * abort here if the I-TLB and D-TLB aren't seeing the same
14597 + * picture. Unfortunately, this does happen. We live with it.
14599 + * r2 = address of aborted instruction
14600 + * r3 = saved SPSR
14603 + * r0 = address of abort
14604 + * r1 = FSR, bit 11 = write
14608 +ENTRY(cpu_xscale_data_abort)
14609 + mrc p15, 0, r1, c5, c0, 0 @ get FSR
14610 + mrc p15, 0, r0, c6, c0, 0 @ get FAR
14611 + ldr r3, [r2] @ read aborted instruction
14612 + bic r1, r1, #1 << 11 @ clear bits 11 of FSR
14613 + tst r3, #1 << 20 @ check write
14614 + orreq r1, r1, #1 << 11
14618 + * cpu_xscale_check_bugs()
14620 +ENTRY(cpu_xscale_check_bugs)
14622 + bic ip, ip, #F_BIT
14626 +#ifndef CONFIG_XSCALE_CACHE_ERRATA
14628 + * cpu_xscale_proc_init()
14630 + * Nothing too exciting at the moment
14632 +ENTRY(cpu_xscale_proc_init)
14636 + * We enable the cache here, but we make sure all the status bits for dirty
14637 + * lines are cleared as well (see PXA250 erratum #120).
14639 +ENTRY(cpu_xscale_proc_init)
14640 + @ enable data cache
14642 + ldmia r0, {r1, r2}
14645 + stmia r0, {r1, r2}
14646 + mcr p15, 0, r1, c1, c0, 0
14649 + @ invalidate data cache
14650 + mcr p15, 0, r0, c7, c6, 0
14652 + @ fill main cache with write-through lines
14653 + bic r0, pc, #0x1f
14654 + add r1, r0, #CACHESIZE
14655 +1: ldr r2, [r0], #32
14659 + @ enable test feature to force all fills to the mini-cache
14661 + mcr p15, 0, r1, c15, c15, 3
14663 + @ fill mini-cache with write-through lines (2kbytes, 64 lines)
14664 + add r1, r0, #2048
14665 +2: ldr r2, [r0], #32
14669 + @ disable test feature to force all fills to the mini-cache
14671 + mcr p15, 0, r1, c15, c15, 3
14673 + @ invalidate data cache again
14674 + mcr p15, 0, r1, c7, c6, 0
14677 +cr_p: .long SYMBOL_NAME(cr_alignment)
14681 + * cpu_xscale_proc_fin()
14683 +ENTRY(cpu_xscale_proc_fin)
14684 + str lr, [sp, #-4]!
14685 + mov r0, #F_BIT|I_BIT|SVC_MODE
14687 + mrc p15, 0, r0, c1, c0, 0 @ ctrl register
14688 + bic r0, r0, #0x1800 @ ...IZ...........
14689 + bic r0, r0, #0x0006 @ .............CA.
14690 + mcr p15, 0, r0, c1, c0, 0 @ disable caches
14691 + bl cpu_xscale_cache_clean_invalidate_all @ clean caches
14695 + * cpu_xscale_reset(loc)
14697 + * Perform a soft reset of the system. Put the CPU into the
14698 + * same state as it would be if it had been reset, and branch
14699 + * to what would be the reset vector.
14701 + * loc: location to jump to for soft reset
14704 +ENTRY(cpu_xscale_reset)
14705 + mov r1, #F_BIT|I_BIT|SVC_MODE
14706 + msr cpsr_c, r1 @ reset CPSR
14707 + mrc p15, 0, r1, c1, c0, 0 @ ctrl register
14708 + bic r1, r1, #0x0086 @ ........B....CA.
14709 + bic r1, r1, #0x1900 @ ...IZ..S........
14710 + mcr p15, 0, r1, c1, c0, 0 @ ctrl register
14711 + mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
14712 + bic r1, r1, #0x0001 @ ...............M
14713 + mcr p15, 0, r1, c1, c0, 0 @ ctrl register
14714 + @ CAUTION: MMU turned off from this point. We count on the pipeline
14715 + @ already containing those two last instructions to survive.
14716 + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
14720 + * cpu_xscale_do_idle(type)
14722 + * Cause the processor to idle
14727 + * 2 = switch to slow processor clock
14728 + * 3 = switch to fast processor clock
14730 + * For now we do nothing but go to idle mode for every case
14732 + * XScale supports clock switching, but using idle mode support
14733 + * allows external hardware to react to system state changes.
14737 +ENTRY(cpu_xscale_do_idle)
14739 + mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
14742 +/* ================================= CACHE ================================ */
14745 + * cpu_xscale_cache_clean_invalidate_all (void)
14747 + * clean and invalidate all cache lines
14750 + * 1. We should preserve r0 at all times.
14751 + * 2. Even if this function implies cache "invalidation" by its name,
14752 + * we don't need to actually use explicit invalidation operations
14753 + * since the goal is to discard all valid references from the cache
14754 + * and the cleaning of it already has that effect.
14755 + * 3. Because of 2 above and the fact that kernel space memory is always
14756 + * coherent across task switches there is no need to worry about
14757 + * inconsistencies due to interrupts, ence no irq disabling.
14760 +ENTRY(cpu_xscale_cache_clean_invalidate_all)
14762 +cpu_xscale_cache_clean_invalidate_all_r2:
14763 + clean_d_cache r0, r1
14765 + mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
14766 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
14770 + * cpu_xscale_cache_clean_invalidate_range(start, end, flags)
14772 + * clean and invalidate all cache lines associated with this area of memory
14774 + * start: Area start address
14775 + * end: Area end address
14776 + * flags: nonzero for I cache as well
14779 +ENTRY(cpu_xscale_cache_clean_invalidate_range)
14780 + bic r0, r0, #CACHELINESIZE - 1 @ round down to cache line
14782 + cmp r3, #MAX_AREA_SIZE
14783 + bhi cpu_xscale_cache_clean_invalidate_all_r2
14784 +1: clean_d_line r0 @ Clean D cache line
14785 + mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
14786 + add r0, r0, #CACHELINESIZE
14790 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
14793 +1: mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
14794 + add r0, r0, #CACHELINESIZE
14797 + mcr p15, 0, ip, c7, c5, 6 @ Invalidate BTB
14801 + * cpu_xscale_flush_ram_page(page)
14803 + * clean all cache lines associated with this memory page
14805 + * page: page to clean
14808 +ENTRY(cpu_xscale_flush_ram_page)
14809 +#if !CACHE_WRITE_THROUGH
14810 + mov r1, #PAGESIZE
14811 +1: mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
14812 + add r0, r0, #CACHELINESIZE
14813 + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
14814 + add r0, r0, #CACHELINESIZE
14815 + subs r1, r1, #2 * CACHELINESIZE
14818 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
14821 +/* ================================ D-CACHE =============================== */
14824 + * cpu_xscale_dcache_invalidate_range(start, end)
14826 + * throw away all D-cached data in specified region without an obligation
14827 + * to write them back. Note however that on XScale we must clean all
14828 + * entries also due to hardware errata (80200 A0 & A1 only).
14830 + * start: virtual start address
14831 + * end: virtual end address
14834 +ENTRY(cpu_xscale_dcache_invalidate_range)
14835 + mrc p15, 0, r2, c0, c0, 0 @ Read part no.
14836 + eor r2, r2, #0x69000000
14837 + eor r2, r2, #0x00052000 @ 80200 XX part no.
14838 + bics r2, r2, #0x1 @ Clear LSB in revision field
14840 + beq cpu_xscale_cache_clean_invalidate_range @ An 80200 A0 or A1
14842 + tst r0, #CACHELINESIZE - 1
14843 + mcrne p15, 0, r0, c7, c10, 1 @ Clean D cache line
14844 + tst r1, #CACHELINESIZE - 1
14845 + mcrne p15, 0, r1, c7, c10, 1 @ Clean D cache line
14846 + bic r0, r0, #CACHELINESIZE - 1 @ round down to cache line
14847 +1: mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
14848 + add r0, r0, #CACHELINESIZE
14854 + * cpu_xscale_dcache_clean_range(start, end)
14856 + * For the specified virtual address range, ensure that all caches contain
14857 + * clean data, such that peripheral accesses to the physical RAM fetch
14860 + * start: virtual start address
14861 + * end: virtual end address
14864 +ENTRY(cpu_xscale_dcache_clean_range)
14865 +#if !CACHE_WRITE_THROUGH
14866 + bic r0, r0, #CACHELINESIZE - 1
14868 + cmp r2, #MAX_AREA_SIZE
14870 + bhi cpu_xscale_cache_clean_invalidate_all_r2
14872 +1: mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
14873 + add r0, r0, #CACHELINESIZE
14874 + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
14875 + add r0, r0, #CACHELINESIZE
14879 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
14883 + * cpu_xscale_clean_dcache_page(page)
14885 + * Cleans a single page of dcache so that if we have any future aliased
14886 + * mappings, they will be consistent at the time that they are created.
14889 + * 1. we don't need to flush the write buffer in this case. [really? -Nico]
14890 + * 2. we don't invalidate the entries since when we write the page
14891 + * out to disk, the entries may get reloaded into the cache.
14894 +ENTRY(cpu_xscale_dcache_clean_page)
14895 +#if !CACHE_WRITE_THROUGH
14896 + mov r1, #PAGESIZE
14897 +1: mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
14898 + add r0, r0, #CACHELINESIZE
14899 + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
14900 + add r0, r0, #CACHELINESIZE
14901 + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
14902 + add r0, r0, #CACHELINESIZE
14903 + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
14904 + add r0, r0, #CACHELINESIZE
14905 + subs r1, r1, #4 * CACHELINESIZE
14908 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
14912 + * cpu_xscale_dcache_clean_entry(addr)
14914 + * Clean the specified entry of any caches such that the MMU
14915 + * translation fetches will obtain correct data.
14917 + * addr: cache-unaligned virtual address
14920 +ENTRY(cpu_xscale_dcache_clean_entry)
14921 + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
14922 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
14925 +/* ================================ I-CACHE =============================== */
14928 + * cpu_xscale_icache_invalidate_range(start, end)
14930 + * invalidate a range of virtual addresses from the Icache
14932 + * start: virtual start address
14933 + * end: virtual end address
14935 + * Note: This is vaguely defined as supposed to bring the dcache and the
14936 + * icache in sync by the way this function is used.
14939 +ENTRY(cpu_xscale_icache_invalidate_range)
14940 + bic r0, r0, #CACHELINESIZE - 1
14941 +1: clean_d_line r0 @ Clean D cache line
14942 + mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
14943 + add r0, r0, #CACHELINESIZE
14946 + mcr p15, 0, ip, c7, c5, 6 @ Invalidate BTB
14947 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
14951 + * cpu_xscale_icache_invalidate_page(page)
14953 + * invalidate all Icache lines associated with this area of memory
14955 + * page: page to invalidate
14958 +ENTRY(cpu_xscale_icache_invalidate_page)
14959 + mov r1, #PAGESIZE
14960 +1: mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
14961 + add r0, r0, #CACHELINESIZE
14962 + mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
14963 + add r0, r0, #CACHELINESIZE
14964 + mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
14965 + add r0, r0, #CACHELINESIZE
14966 + mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
14967 + add r0, r0, #CACHELINESIZE
14968 + subs r1, r1, #4 * CACHELINESIZE
14970 + mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
14973 +/* ================================ CACHE LOCKING============================
14975 + * The XScale MicroArchitecture implements support for locking entries into
14976 + * the data and instruction cache. The following functions implement the core
14977 + * low level instructions needed to accomplish the locking. The developer's
14978 + * manual states that the code that performs the locking must be in non-cached
14979 + * memory. To accomplish this, the code in xscale-cache-lock.c copies the
14980 + * following functions from the cache into a non-cached memory region that
14981 + * is allocated through consistent_alloc().
14986 + * xscale_icache_lock
14988 + * r0: starting address to lock
14989 + * r1: end address to lock
14991 +ENTRY(xscale_icache_lock)
14994 + bic r0, r0, #CACHELINESIZE - 1
14995 + mcr p15, 0, r0, c9, c1, 0 @ lock into cache
14996 + cmp r0, r1 @ are we done?
14997 + add r0, r0, #CACHELINESIZE @ advance to next cache line
15002 + * xscale_icache_unlock
15004 +ENTRY(xscale_icache_unlock)
15005 + mcr p15, 0, r0, c9, c1, 1 @ Unlock icache
15009 + * xscale_dcache_lock
15011 + * r0: starting address to lock
15012 + * r1: end address to lock
15014 +ENTRY(xscale_dcache_lock)
15015 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
15017 + mcr p15, 0, r2, c9, c2, 0 @ Put dcache in lock mode
15018 + cpwait ip @ Wait for completion
15021 + orr r3, r2, #F_BIT | I_BIT
15024 + mcr p15, 0, r0, c7, c10, 1 @ Write back line if it is dirty
15025 + mcr p15, 0, r0, c7, c6, 1 @ Flush/invalidate line
15027 + ldr ip, [r0], #CACHELINESIZE @ Preload 32 bytes into cache from
15028 + @ location [r0]. Post-increment
15029 + @ r3 to next cache line
15030 + cmp r0, r1 @ Are we done?
15033 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
15035 + mcr p15, 0, r2, c9, c2, 0 @ Get out of lock mode
15036 + cpwait_ret lr, ip
15039 + * xscale_dcache_unlock
15041 +ENTRY(xscale_dcache_unlock)
15042 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
15043 + mcr p15, 0, ip, c9, c2, 1 @ Unlock cache
15047 + * Needed to determine the length of the code that needs to be copied.
15050 +ENTRY(xscale_cache_dummy)
15053 +/* ================================== TLB ================================= */
15056 + * cpu_xscale_tlb_invalidate_all()
15058 + * Invalidate all TLB entries
15061 +ENTRY(cpu_xscale_tlb_invalidate_all)
15062 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
15063 + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
15064 + cpwait_ret lr, ip
15067 + * cpu_xscale_tlb_invalidate_range(start, end)
15069 + * invalidate TLB entries covering the specified range
15071 + * start: range start address
15072 + * end: range end address
15075 +ENTRY(cpu_xscale_tlb_invalidate_range)
15076 + bic r0, r0, #(PAGESIZE - 1) & 0x00ff
15077 + bic r0, r0, #(PAGESIZE - 1) & 0xff00
15079 + cmp r3, #256 * PAGESIZE @ arbitrary, should be tuned
15080 + bhi cpu_xscale_tlb_invalidate_all
15081 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
15082 +1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
15083 + mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
15084 + add r0, r0, #PAGESIZE
15087 + cpwait_ret lr, ip
15090 + * cpu_xscale_tlb_invalidate_page(page, flags)
15092 + * invalidate the TLB entries for the specified page.
15094 + * page: page to invalidate
15095 + * flags: non-zero if we include the I TLB
15098 +ENTRY(cpu_xscale_tlb_invalidate_page)
15099 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
15101 + mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
15102 + mcrne p15, 0, r3, c8, c5, 1 @ invalidate I TLB entry
15103 + cpwait_ret lr, ip
15105 +/* ================================ TLB LOCKING==============================
15107 + * The XScale MicroArchitecture implements support for locking entries into
15108 + * the Instruction and Data TLBs. The following functions provide the
15109 + * low level support for supporting these under Linux. xscale-lock.c
15110 + * implements some higher level management code. Most of the following
15111 + * is taken straight out of the Developer's Manual.
15115 + * Lock I-TLB entry
15117 + * r0: Virtual address to translate and lock
15120 +ENTRY(xscale_itlb_lock)
15122 + orr r3, r2, #F_BIT | I_BIT
15123 + msr cpsr_c, r3 @ Disable interrupts
15124 + mcr p15, 0, r0, c8, c5, 1 @ Invalidate I-TLB entry
15125 + mcr p15, 0, r0, c10, c4, 0 @ Translate and lock
15126 + msr cpsr_c, r2 @ Restore interrupts
15127 + cpwait_ret lr, ip
15130 + * Lock D-TLB entry
15132 + * r0: Virtual address to translate and lock
15135 +ENTRY(xscale_dtlb_lock)
15137 + orr r3, r2, #F_BIT | I_BIT
15138 + msr cpsr_c, r3 @ Disable interrupts
15139 + mcr p15, 0, r0, c8, c6, 1 @ Invalidate D-TLB entry
15140 + mcr p15, 0, r0, c10, c8, 0 @ Translate and lock
15141 + msr cpsr_c, r2 @ Restore interrupts
15142 + cpwait_ret lr, ip
15145 + * Unlock all I-TLB entries
15148 +ENTRY(xscale_itlb_unlock)
15149 + mcr p15, 0, ip, c10, c4, 1 @ Unlock I-TLB
15150 + mcr p15, 0, ip, c8, c5, 0 @ Invalidate I-TLB
15151 + cpwait_ret lr, ip
15154 + * Unlock all D-TLB entries
15156 +ENTRY(xscale_dtlb_unlock)
15157 + mcr p15, 0, ip, c10, c8, 1 @ Unlock D-TBL
15158 + mcr p15, 0, ip, c8, c6, 0 @ Invalidate D-TLB
15159 + cpwait_ret lr, ip
15161 +/* =============================== PageTable ============================== */
15164 + * cpu_xscale_set_pgd(pgd)
15166 + * Set the translation base pointer to be as described by pgd.
15168 + * pgd: new page tables
15171 +ENTRY(cpu_xscale_set_pgd)
15172 + clean_d_cache r1, r2
15173 + mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
15174 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
15175 + mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
15176 + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
15177 + cpwait_ret lr, ip
15180 + * cpu_xscale_set_pmd(pmdp, pmd)
15182 + * Set a level 1 translation table entry, and clean it out of
15183 + * any caches such that the MMUs can load it correctly.
15185 + * pmdp: pointer to PMD entry
15186 + * pmd: PMD value to store
15189 +ENTRY(cpu_xscale_set_pmd)
15190 +#if PMD_CACHE_WRITE_ALLOCATE && !CACHE_WRITE_THROUGH
15191 + and r2, r1, #PMD_TYPE_MASK|PMD_SECT_CACHEABLE|PMD_SECT_BUFFERABLE
15192 + cmp r2, #PMD_TYPE_SECT|PMD_SECT_CACHEABLE|PMD_SECT_BUFFERABLE
15193 + orreq r1, r1, #PMD_SECT_TEX(1)
15194 +#elif CACHE_WRITE_THROUGH
15195 + and r2, r1, #PMD_TYPE_MASK|PMD_SECT_CACHEABLE|PMD_SECT_BUFFERABLE
15196 + cmp r2, #PMD_TYPE_SECT|PMD_SECT_CACHEABLE|PMD_SECT_BUFFERABLE
15197 + biceq r1, r1, #PMD_SECT_BUFFERABLE
15201 + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
15202 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
15206 + * cpu_xscale_set_pte(ptep, pte)
15208 + * Set a PTE and flush it out
15210 + * Errata 40: must set memory to write-through for user read-only pages.
15213 +ENTRY(cpu_xscale_set_pte)
15214 + str r1, [r0], #-1024 @ linux version
15216 + bic r2, r1, #0xff0
15217 + orr r2, r2, #PTE_TYPE_EXT @ extended page
15219 + eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
15221 + tst r3, #L_PTE_USER | L_PTE_EXEC @ User or Exec?
15222 + orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
15224 + tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
15225 + orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
15226 + @ combined with user -> user r/w
15229 + @ Handle the X bit. We want to set this bit for the minicache
15230 + @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
15231 + @ and we have a writeable, cacheable region. If we ignore the
15232 + @ U and E bits, we can allow user space to use the minicache as
15235 + @ X = C & ~W & ~B
15236 + @ | C & W & B & write_allocate
15238 + eor ip, r1, #L_PTE_CACHEABLE
15239 + tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
15240 +#if PTE_CACHE_WRITE_ALLOCATE && !CACHE_WRITE_THROUGH
15241 + eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
15242 + tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
15244 + orreq r2, r2, #PTE_EXT_TEX(1)
15246 +#if CACHE_WRITE_THROUGH
15247 + tst r1, #L_PTE_CACHEABLE
15248 + bicne r2, r2, #L_PTE_BUFFERABLE @ clear B only if C is set
15251 + @ Errata 40: The B bit must be cleared for a user read-only
15252 + @ cacheable page.
15254 + @ B = B & ~((U|E) & C & ~W)
15256 + and ip, r1, #L_PTE_USER | L_PTE_EXEC | L_PTE_WRITE | L_PTE_CACHEABLE
15257 + teq ip, #L_PTE_USER | L_PTE_CACHEABLE
15258 + teqne ip, #L_PTE_EXEC | L_PTE_CACHEABLE
15259 + teqne ip, #L_PTE_USER | L_PTE_EXEC | L_PTE_CACHEABLE
15260 + biceq r2, r2, #PTE_BUFFERABLE
15263 + tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
15264 + movne r2, #0 @ no -> fault
15266 + str r2, [r0] @ hardware version
15268 + @ We try to map 64K page entries when possible.
15269 + @ We do that for kernel space only since the usage pattern from
15270 + @ the setting of VM area is quite simple. User space is not worth
15271 + @ the implied complexity because of ever randomly changing PTEs
15272 + @ (page aging, swapout, etc) requiring constant coherency checks.
15273 + @ Since PTEs are usually set in increasing order, we test the
15274 + @ possibility for a large page only when given the last PTE of a
15276 + tsteq r1, #L_PTE_USER
15277 + andeq r1, r0, #(15 << 2)
15278 + teqeq r1, #(15 << 2)
15282 + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
15283 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
15286 + @ See if we have 16 identical PTEs but with consecutive base addresses
15287 +1: bic r3, r2, #0x0000f000
15288 + mov r1, #0x0000f000
15292 + subs r1, r1, #0x00001000
15293 + ldr r2, [r0, #-4]!
15298 + @ Now create our LARGE PTE from the current EXT one.
15299 + bic r3, r3, #PTE_TYPE_MASK
15300 + orr r3, r3, #PTE_TYPE_LARGE
15301 + and r2, r3, #0x30 @ EXT_AP --> LARGE_AP0
15302 + orr r2, r2, r2, lsl #2 @ add LARGE_AP1
15303 + orr r2, r2, r2, lsl #4 @ add LARGE_AP3 + LARGE_AP2
15304 + and r1, r3, #0x3c0 @ EXT_TEX
15305 + bic r3, r3, #0x3c0
15306 + orr r2, r2, r1, lsl #(12 - 6) @ --> LARGE_TEX
15307 + orr r2, r2, r3 @ add remaining bits
15309 + @ then put it in the pagetable
15311 +3: strd r2, [r0], #8
15312 + tst r0, #(15 << 2)
15315 + @ Then sync the 2 corresponding cache lines
15316 + sub r0, r0, #(16 << 2)
15317 + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
15318 +4: orr r0, r0, #(15 << 2)
15319 + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
15321 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
15330 + .asciz "XScale-80200"
15333 + .asciz "XScale-PXA210"
15336 + .asciz "XScale-PXA250"
15339 + .asciz "XScale-PXA255"
15343 + .section ".text.init", #alloc, #execinstr
15346 + mov r0, #F_BIT|I_BIT|SVC_MODE
15348 + mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
15349 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
15350 + mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
15351 + mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
15352 + mov r0, #0x1f @ Domains 0, 1 = client
15353 + mcr p15, 0, r0, c3, c0, 0 @ load domain access register
15354 + mov r0, #1 @ Allow user space to access
15355 + mcr p15, 0, r0, c15, c1, 0 @ ... CP 0 only.
15356 +#if CACHE_WRITE_THROUGH
15361 + mcr p15, 0, r0, c1, c1, 0 @ set auxiliary control reg
15362 + mrc p15, 0, r0, c1, c0, 0 @ get control register
15363 + bic r0, r0, #0x0200 @ ......R.........
15364 + bic r0, r0, #0x0082 @ ........B.....A.
15365 + orr r0, r0, #0x0005 @ .............C.M
15366 + orr r0, r0, #0x3900 @ ..VIZ..S........
15367 +#ifdef CONFIG_XSCALE_CACHE_ERRATA
15368 + bic r0, r0, #0x0004 @ see cpu_xscale_proc_init
15375 + * Purpose : Function pointers used to access above functions - all calls
15376 + * come through these
15379 + .type xscale_processor_functions, #object
15380 +ENTRY(xscale_processor_functions)
15381 + .word cpu_xscale_data_abort
15382 + .word cpu_xscale_check_bugs
15383 + .word cpu_xscale_proc_init
15384 + .word cpu_xscale_proc_fin
15385 + .word cpu_xscale_reset
15386 + .word cpu_xscale_do_idle
15389 + .word cpu_xscale_cache_clean_invalidate_all
15390 + .word cpu_xscale_cache_clean_invalidate_range
15391 + .word cpu_xscale_flush_ram_page
15394 + .word cpu_xscale_dcache_invalidate_range
15395 + .word cpu_xscale_dcache_clean_range
15396 + .word cpu_xscale_dcache_clean_page
15397 + .word cpu_xscale_dcache_clean_entry
15400 + .word cpu_xscale_icache_invalidate_range
15401 + .word cpu_xscale_icache_invalidate_page
15404 + .word cpu_xscale_tlb_invalidate_all
15405 + .word cpu_xscale_tlb_invalidate_range
15406 + .word cpu_xscale_tlb_invalidate_page
15409 + .word cpu_xscale_set_pgd
15410 + .word cpu_xscale_set_pmd
15411 + .word cpu_xscale_set_pte
15412 + .size xscale_processor_functions, . - xscale_processor_functions
15414 + .type cpu_80200_info, #object
15416 + .long cpu_manu_name
15417 + .long cpu_80200_name
15418 + .size cpu_80200_info, . - cpu_80200_info
15420 + .type cpu_pxa210_info, #object
15422 + .long cpu_manu_name
15423 + .long cpu_pxa210_name
15424 + .size cpu_pxa210_info, . - cpu_pxa210_info
15426 + .type cpu_pxa250_info, #object
15428 + .long cpu_manu_name
15429 + .long cpu_pxa250_name
15430 + .size cpu_pxa250_info, . - cpu_pxa250_info
15432 + .type cpu_pxa255_info, #object
15434 + .long cpu_manu_name
15435 + .long cpu_pxa255_name
15436 + .size cpu_pxa255_info, . - cpu_pxa255_info
15438 + .type cpu_arch_name, #object
15441 + .size cpu_arch_name, . - cpu_arch_name
15443 + .type cpu_elf_name, #object
15446 + .size cpu_elf_name, . - cpu_elf_name
15449 + .section ".proc.info", #alloc, #execinstr
15451 + .type __80200_proc_info,#object
15452 +__80200_proc_info:
15455 +#if CACHE_WRITE_THROUGH
15461 + .long cpu_arch_name
15462 + .long cpu_elf_name
15463 + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_XSCALE
15464 + .long cpu_80200_info
15465 + .long xscale_processor_functions
15466 + .size __80200_proc_info, . - __80200_proc_info
15468 + .type __pxa210_proc_info,#object
15469 +__pxa210_proc_info:
15472 +#if CACHE_WRITE_THROUGH
15478 + .long cpu_arch_name
15479 + .long cpu_elf_name
15480 + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_XSCALE
15481 + .long cpu_pxa210_info
15482 + .long xscale_processor_functions
15483 + .size __pxa210_proc_info, . - __pxa210_proc_info
15485 + .type __pxa250_proc_info,#object
15486 +__pxa250_proc_info:
15489 +#if CACHE_WRITE_THROUGH
15495 + .long cpu_arch_name
15496 + .long cpu_elf_name
15497 + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_XSCALE
15498 + .long cpu_pxa250_info
15499 + .long xscale_processor_functions
15500 + .size __pxa250_proc_info, . - __pxa250_proc_info
15502 + .type __pxa255_proc_info,#object
15503 +__pxa255_proc_info:
15506 +#if CACHE_WRITE_THROUGH
15512 + .long cpu_arch_name
15513 + .long cpu_elf_name
15514 + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_XSCALE
15515 + .long cpu_pxa255_info
15516 + .long xscale_processor_functions
15517 + .size __pxa255_proc_info, . - __pxa255_proc_info
15520 +++ linux-2.4.27/arch/arm/vmlinux-armv-xip.lds.in
15523 + * ld script to make ARM Linux kernel
15525 + * (C) Copyright 2001 Lineo Japan, Inc.
15527 + * May be copied or modified under the terms of the GNU General Public
15528 + * License. See linux/COPYING for more information.
15530 + * Based on arch/arm/vmlinux-armv.lds.in
15532 + * taken from the i386 version by Russell King
15533 + * Written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>
15540 + .init : { /* Init code and data */
15542 + __init_begin = .;
15544 + __proc_info_begin = .;
15546 + __proc_info_end = .;
15547 + __arch_info_begin = .;
15549 + __arch_info_end = .;
15550 + __tagtable_begin = .;
15552 + __tagtable_end = .;
15554 + __setup_start = .;
15557 + __initcall_start = .;
15558 + *(.initcall.init)
15559 + __initcall_end = .;
15564 + /DISCARD/ : { /* Exit code and data */
15567 + *(.exitcall.exit)
15570 + .text : { /* Real text segment */
15571 + _text = .; /* Text and read-only data */
15575 + *(.text.lock) /* out-of-line lock text */
15581 + *(.got) /* Global offset table */
15584 + _etext = .; /* End of text section */
15588 + __ex_table : { /* Exception table */
15589 + __start___ex_table = .;
15591 + __stop___ex_table = .;
15594 + __ksymtab : { /* Kernel symbol table */
15595 + __start___ksymtab = .;
15597 + __stop___ksymtab = .;
15610 + * first, the init task union, aligned
15611 + * to an 8192 byte boundary.
15616 + * then the cacheline aligned data
15619 + *(.data.cacheline_aligned)
15622 + * and the usual data section
15633 + __bss_start = .; /* BSS */
15638 + /* Stabs debugging sections. */
15639 + .stab 0 : { *(.stab) }
15640 + .stabstr 0 : { *(.stabstr) }
15641 + .stab.excl 0 : { *(.stab.excl) }
15642 + .stab.exclstr 0 : { *(.stab.exclstr) }
15643 + .stab.index 0 : { *(.stab.index) }
15644 + .stab.indexstr 0 : { *(.stab.indexstr) }
15645 + .comment 0 : { *(.comment) }
15647 --- linux-2.4.27/drivers/Makefile~2.4.27-vrs1-pxa1
15648 +++ linux-2.4.27/drivers/Makefile
15650 subdir-$(CONFIG_NUBUS) += nubus
15651 subdir-$(CONFIG_TC) += tc
15652 subdir-$(CONFIG_VT) += video
15653 +subdir-$(CONFIG_MMC) += mmc
15654 subdir-$(CONFIG_MAC) += macintosh
15655 subdir-$(CONFIG_PPC32) += macintosh
15656 subdir-$(CONFIG_USB) += usb
15657 --- linux-2.4.27/drivers/char/Config.in~2.4.27-vrs1-pxa1
15658 +++ linux-2.4.27/drivers/char/Config.in
15659 @@ -253,6 +253,7 @@
15660 dep_tristate ' DC21285 watchdog' CONFIG_21285_WATCHDOG $CONFIG_FOOTBRIDGE
15661 dep_tristate ' NetWinder WB83C977 watchdog' CONFIG_977_WATCHDOG $CONFIG_ARCH_NETWINDER
15662 dep_tristate ' SA1100 watchdog' CONFIG_SA1100_WATCHDOG $CONFIG_ARCH_SA1100
15663 + dep_tristate ' PXA250/210 watchdog' CONFIG_SA1100_WATCHDOG $CONFIG_ARCH_PXA
15664 dep_tristate ' EPXA watchdog' CONFIG_EPXA_WATCHDOG $CONFIG_ARCH_CAMELOT
15665 dep_tristate ' Omaha watchdog' CONFIG_OMAHA_WATCHDOG $CONFIG_ARCH_OMAHA
15666 dep_tristate ' AT91RM9200 watchdog' CONFIG_AT91_WATCHDOG $CONFIG_ARCH_AT91RM9200
15667 @@ -334,6 +335,9 @@
15668 if [ "$CONFIG_ARCH_SA1100" = "y" ]; then
15669 tristate 'SA1100 Real Time Clock' CONFIG_SA1100_RTC
15671 +if [ "$CONFIG_ARCH_PXA" = "y" ]; then
15672 + tristate 'PXA250/210 Real Time Clock' CONFIG_PXA_RTC
15674 if [ "$CONFIG_ARCH_OMAHA" = "y" ]; then
15675 tristate 'Omaha Real Time Clock' CONFIG_OMAHA_RTC
15677 @@ -416,4 +420,8 @@
15678 dep_tristate 'HP OB600 C/CT Pop-up mouse support' CONFIG_OBMOUSE $CONFIG_INPUT_MOUSEDEV
15681 +if [ "$CONFIG_ARCH_TRIZEPS2" = "y" ]; then
15682 + tristate ' MT6N TTL I/O suport' CONFIG_TRIZEPS2_TTLIO
15686 --- linux-2.4.27/drivers/char/Makefile~2.4.27-vrs1-pxa1
15687 +++ linux-2.4.27/drivers/char/Makefile
15688 @@ -281,6 +281,7 @@
15689 obj-$(CONFIG_MIPS_RTC) += mips_rtc.o
15690 obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o
15691 obj-$(CONFIG_SA1100_RTC) += sa1100-rtc.o
15692 +obj-$(CONFIG_PXA_RTC) += sa1100-rtc.o
15693 obj-$(CONFIG_OMAHA_RTC) += omaha-rtc.o
15694 ifeq ($(CONFIG_PPC),)
15695 obj-$(CONFIG_NVRAM) += nvram.o
15697 +++ linux-2.4.27/drivers/char/mt6n_ttl.c
15700 + * Trizeps-2 MT6N development board TTL-IO interface for Linux
15702 + * Copyright (C) 2003 Luc De Cock
15704 + * This driver allows use of the TTL-IO interface on the MT6N
15705 + * from user space. It exports the /dev/ttlio interface supporting
15706 + * some ioctl() and also the /proc/driver/ttlio pseudo-file
15707 + * for status information.
15709 + * The ioctls can be used to set individual TTL output lines.
15710 + * Only ioctls are supported.
15712 + * This program is free software; you can redistribute it and/or
15713 + * modify it under the terms of the GNU General Public License
15714 + * as published by the Free Software Foundation; either version
15715 + * 2 of the License, or (at your option) any later version.
15717 + * Based on other minimal char device drivers, like Alan's
15718 + * watchdog, Ted's random, Paul's rtc, etc. etc.
15720 + * 1.00 Luc De Cock: initial version.
15723 +#define TTLIO_VERSION "1.00"
15726 +#include <linux/config.h>
15727 +#include <linux/module.h>
15728 +#include <linux/kernel.h>
15729 +#include <linux/types.h>
15730 +#include <linux/miscdevice.h>
15731 +#include <linux/fcntl.h>
15732 +#include <linux/init.h>
15733 +#include <linux/poll.h>
15734 +#include <linux/proc_fs.h>
15736 +#include <asm/io.h>
15737 +#include <asm/uaccess.h>
15738 +#include <asm/system.h>
15739 +#include <asm/hardware.h>
15740 +#include <asm/irq.h>
15742 +/* Writing to the register sets the output lines
15743 +* Reading from the register returns the status of the input lines
15745 +static unsigned short *ttlio_base = (unsigned short *) TRIZEPS2_TTLIO_BASE;
15746 +static unsigned short ttlio_shadow = 0;
15748 +/* interrupt stuff */
15749 +static struct fasync_struct *ttlio_async_queue;
15750 +static DECLARE_WAIT_QUEUE_HEAD(ttlio_wait);
15751 +static int ttlio_irq_arrived = 0;
15752 +static spinlock_t ttlio_lock;
15753 +static unsigned short ttlio_in = 0;
15754 +static volatile unsigned long teller = 0;
15757 +static int ttlio_ioctl(struct inode *inode, struct file *file,
15758 + unsigned int cmd, unsigned long arg);
15760 +static int ttlio_read_proc(char *page, char **start, off_t off,
15761 + int count, int *eof, void *data);
15764 +static void ttlio_interrupt(int irq, void *dev_id, struct pt_regs *regs)
15766 + ttlio_in = *ttlio_base;
15768 + ttlio_irq_arrived = 1;
15771 + /* wake up the waiting process */
15772 + wake_up_interruptible(&ttlio_wait);
15773 + kill_fasync(&ttlio_async_queue, SIGIO, POLL_IN);
15777 + * Now all the various file operations that we export.
15780 +static int ttlio_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
15781 + unsigned long arg)
15783 + unsigned long ttlio_val;
15786 + case TTLIO_RESET: /* clear all lines */
15791 + case TTLIO_GET: /* get state of TTL input lines */
15793 + ttlio_val = *ttlio_base;
15794 + return put_user(ttlio_val, (unsigned long *)arg);
15796 + case TTLIO_SET: /* set state of TTL output lines */
15798 + unsigned long user_val;
15799 + if (copy_from_user(&user_val, arg, sizeof(unsigned long)))
15801 + ttlio_shadow |= (unsigned short) user_val;
15802 + *ttlio_base = ttlio_shadow;
15805 + case TTLIO_UNSET: /* unset (clear) state of TTL output lines */
15807 + unsigned long user_val;
15808 + if (copy_from_user(&user_val, arg, sizeof(unsigned long)))
15810 + ttlio_shadow &= ~((unsigned short) user_val);
15811 + *ttlio_base = ttlio_shadow;
15814 + case 100: /* get counter */
15816 + return put_user(teller, (unsigned long *)arg);
15818 + case 101: /* reset counter */
15829 +static ssize_t ttlio_read(struct file *file, char *buf,
15830 + size_t count, loff_t *ppos)
15832 + DECLARE_WAITQUEUE(wait, current);
15833 + unsigned short data;
15836 + if (count < sizeof(unsigned short))
15839 + if (file->f_flags & O_NONBLOCK) {
15840 + spin_lock_irq(&ttlio_lock);
15841 + data = *ttlio_base;
15842 + spin_unlock_irq(&ttlio_lock);
15843 + retval = put_user(data, (unsigned short *) buf);
15845 + retval = sizeof(unsigned short);
15848 + /* blocking read: wait for interrupt */
15849 + add_wait_queue(&ttlio_wait, &wait);
15850 + set_current_state(TASK_INTERRUPTIBLE);
15852 + spin_lock_irq(&ttlio_lock);
15853 + data = *ttlio_base;
15854 + if (ttlio_irq_arrived) {
15855 + ttlio_irq_arrived = 0;
15858 + spin_unlock_irq(&ttlio_lock);
15860 + if (signal_pending(current)) {
15861 + retval = -ERESTARTSYS;
15867 + spin_unlock_irq(&ttlio_lock);
15868 + retval = put_user(data, (unsigned short *)buf);
15870 + retval = sizeof(unsigned short);
15873 + set_current_state(TASK_RUNNING);
15874 + remove_wait_queue(&ttlio_wait, &wait);
15878 +static ssize_t ttlio_write(struct file *file,
15879 + const char *buf, size_t count, loff_t *ppos)
15881 + unsigned short content;
15883 + if (count < sizeof(unsigned short))
15886 + if (copy_from_user (&content, buf, sizeof(unsigned short)))
15889 + ttlio_shadow = content;
15890 + *ttlio_base = ttlio_shadow;
15892 + *ppos += sizeof(unsigned short);
15894 + return sizeof(unsigned short);
15897 +static int ttlio_open(struct inode *inode, struct file *file)
15899 + ttlio_irq_arrived = 0;
15903 +static int ttlio_fasync(int fd, struct file *filp, int on)
15905 + return fasync_helper(fd, filp, on, &ttlio_async_queue);
15908 +static unsigned int ttlio_poll(struct file *file, poll_table *wait)
15910 + poll_wait(file, &ttlio_wait, wait);
15911 + return ttlio_irq_arrived ? 0 : POLLIN | POLLRDNORM;
15914 +static loff_t ttlio_llseek(struct file *file, loff_t offset, int origin)
15920 + * The various file operations we support.
15923 +static struct file_operations ttlio_fops = {
15924 + owner: THIS_MODULE,
15925 + llseek: ttlio_llseek,
15926 + read: ttlio_read,
15927 + poll: ttlio_poll,
15928 + write: ttlio_write,
15929 + ioctl: ttlio_ioctl,
15930 + open: ttlio_open,
15931 + fasync: ttlio_fasync,
15934 +static struct miscdevice ttlio_dev = {
15940 +static int __init ttlio_init(void)
15942 + printk(KERN_INFO "MT6N TTL-I/O driver (release %s)\n",
15945 + misc_register(&ttlio_dev);
15946 + create_proc_read_entry ("driver/ttlio", 0, 0, ttlio_read_proc, NULL);
15948 + set_GPIO_IRQ_edge(GPIO_TTLIO_IRQ, GPIO_FALLING_EDGE);
15949 + if (request_irq(TTLIO_IRQ, ttlio_interrupt, SA_INTERRUPT, "ttlio irq", NULL)) {
15950 + printk(KERN_ERR "ttlio: irq %d already in use\n", TTLIO_IRQ);
15956 +static void __exit ttlio_exit(void)
15958 + free_irq(TTLIO_IRQ, NULL);
15959 + remove_proc_entry ("driver/ttlio", NULL);
15960 + misc_deregister(&ttlio_dev);
15963 +module_init(ttlio_init);
15964 +module_exit(ttlio_exit);
15965 +EXPORT_NO_SYMBOLS;
15968 + * Info exported via "/proc/driver/ttlio".
15971 +static int ttlio_proc_output(char *buf)
15974 + unsigned short val;
15979 + p += sprintf(p, "input : ");
15980 + /* write the state of the input lines */
15981 + val = *ttlio_base;
15982 + for (i = 0; i < 8*sizeof(unsigned short); i++) {
15983 + *p++ = (val & 1) ? '1' : '0';
15987 + p += sprintf(p, "\noutput: ");
15988 + /* write the state of the output lines */
15989 + val = ttlio_shadow;
15990 + for (i = 0; i < 8*sizeof(unsigned short); i++) {
15991 + *p++ = (val & 1) ? '1' : '0';
15995 + p += sprintf(p, "\n");
16000 +static int ttlio_read_proc(char *page, char **start, off_t off,
16001 + int count, int *eof, void *data)
16003 + int len = ttlio_proc_output (page);
16004 + if (len <= off+count) *eof = 1;
16005 + *start = page + off;
16007 + if (len > count) len = count;
16008 + if (len < 0) len = 0;
16012 +MODULE_AUTHOR("Luc De Cock");
16013 +MODULE_DESCRIPTION("MT6N TTL-I/O driver");
16014 +MODULE_LICENSE("GPL");
16015 --- linux-2.4.27/drivers/char/sa1100-rtc.c~2.4.27-vrs1-pxa1
16016 +++ linux-2.4.27/drivers/char/sa1100-rtc.c
16019 * Real Time Clock interface for Linux on StrongARM SA1100
16020 + * and XScale PXA250/210.
16022 * Copyright (c) 2000 Nils Faerber
16024 @@ -470,5 +471,5 @@
16025 module_exit(rtc_exit);
16027 MODULE_AUTHOR("Nils Faerber <nils@@kernelconcepts.de>");
16028 -MODULE_DESCRIPTION("SA1100 Realtime Clock Driver (RTC)");
16029 +MODULE_DESCRIPTION("SA1100/PXA Realtime Clock Driver (RTC)");
16031 --- linux-2.4.27/drivers/char/sa1100_wdt.c~2.4.27-vrs1-pxa1
16032 +++ linux-2.4.27/drivers/char/sa1100_wdt.c
16035 - * Watchdog driver for the SA11x0
16036 + * Watchdog driver for the SA11x0/PXA
16038 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
16039 * Based on SoftDog driver by Alan Cox <alan@redhat.com>
16040 @@ -35,13 +35,20 @@
16042 #define TIMER_MARGIN 60 /* (secs) Default is 1 minute */
16044 -static int sa1100_margin = TIMER_MARGIN; /* in seconds */
16045 +static int timer_margin = TIMER_MARGIN; /* in seconds */
16046 static int sa1100wdt_users;
16047 static int pre_margin;
16049 -MODULE_PARM(sa1100_margin,"i");
16050 +MODULE_PARM(timer_margin,"i");
16053 +static void sa1100dog_ping( void)
16055 + /* reload counter with (new) margin */
16056 + pre_margin=3686400 * timer_margin;
16057 + OSMR3 = OSCR + pre_margin;
16061 * Allow only one person to hold it open
16064 if(test_and_set_bit(1,&sa1100wdt_users))
16067 - /* Activate SA1100 Watchdog timer */
16068 - pre_margin=3686400 * sa1100_margin;
16069 - OSMR3 = OSCR + pre_margin;
16070 + sa1100dog_ping();
16075 unsigned int cmd, unsigned long arg)
16077 static struct watchdog_info ident = {
16078 - identity: "SA1100 Watchdog",
16079 + identity: "PXA/SA1100 Watchdog",
16080 + options: WDIOF_SETTIMEOUT,
16081 + firmware_version: 0,
16087 @@ -108,6 +116,16 @@
16088 case WDIOC_KEEPALIVE:
16089 OSMR3 = OSCR + pre_margin;
16091 + case WDIOC_SETTIMEOUT:
16092 + if (get_user(new_margin, (int *)arg))
16094 + if (new_margin < 1)
16096 + timer_margin = new_margin;
16097 + sa1100dog_ping();
16099 + case WDIOC_GETTIMEOUT:
16100 + return put_user(timer_margin, (int *)arg);
16104 @@ -123,7 +141,11 @@
16105 static struct miscdevice sa1100dog_miscdev=
16108 - "SA1100 watchdog",
16109 +#if defined(CONFIG_SA1100_WATCHDOG)
16110 + "SA1100_watchdog",
16111 +#elif defined(CONFIG_PXA_WATCHDOG)
16117 @@ -136,7 +158,7 @@
16121 - printk("SA1100 Watchdog Timer: timer margin %d sec\n", sa1100_margin);
16122 + printk("SA1100/PXA Watchdog Timer: timer margin %d sec\n", timer_margin);
16126 --- linux-2.4.27/drivers/char/serial.c~2.4.27-vrs1-pxa1
16127 +++ linux-2.4.27/drivers/char/serial.c
16128 @@ -133,6 +133,16 @@
16132 +#ifdef CONFIG_ARCH_PXA
16133 +#define pxa_port(x) ((x) == PORT_PXA)
16134 +#define pxa_buggy_port(x) ({ \
16135 + int cpu_ver; asm("mrc%? p15, 0, %0, c0, c0" : "=r" (cpu_ver)); \
16136 + ((x) == PORT_PXA && (cpu_ver & ~1) == 0x69052100); })
16138 +#define pxa_port(x) (0)
16139 +#define pxa_buggy_port(x) (0)
16142 /* Set of debugging defines */
16144 #undef SERIAL_DEBUG_INTR
16145 @@ -311,6 +321,7 @@
16146 { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO |
16148 { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO },
16149 + { "PXA UART", 32, UART_CLEAR_FIFO | UART_USE_FIFO },
16153 @@ -424,6 +435,9 @@
16154 case SERIAL_IO_MEM:
16155 return readb((unsigned long) info->iomem_base +
16156 (offset<<info->iomem_reg_shift));
16157 + case SERIAL_IO_MEM32:
16158 + return readl((unsigned long) info->iomem_base +
16159 + (offset<<info->iomem_reg_shift));
16161 return inb(info->port + offset);
16163 @@ -443,6 +457,10 @@
16164 writeb(value, (unsigned long) info->iomem_base +
16165 (offset<<info->iomem_reg_shift));
16167 + case SERIAL_IO_MEM32:
16168 + writel(value, (unsigned long) info->iomem_base +
16169 + (offset<<info->iomem_reg_shift));
16172 outb(value, info->port+offset);
16174 @@ -1306,6 +1324,16 @@
16178 +#ifdef CONFIG_ARCH_PXA
16179 + if (state->type == PORT_PXA) {
16180 + switch ((long)state->iomem_base) {
16181 + case (long)&FFUART: CKEN |= CKEN6_FFUART; break;
16182 + case (long)&BTUART: CKEN |= CKEN7_BTUART; break;
16183 + case (long)&STUART: CKEN |= CKEN5_STUART; break;
16189 * Clear the FIFO buffers and disable them
16190 * (they will be reenabled in change_speed())
16191 @@ -1403,6 +1431,8 @@
16193 if (state->irq != 0)
16194 info->MCR |= UART_MCR_OUT2;
16195 + if (pxa_buggy_port(state->type) && state->irq != 0)
16196 + info->MCR ^= UART_MCR_OUT2;
16198 info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */
16199 serial_outp(info, UART_MCR, info->MCR);
16200 @@ -1411,6 +1441,8 @@
16201 * Finally, enable interrupts
16203 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
16204 + if (pxa_port(state->type))
16205 + info->IER |= UART_IER_UUE | UART_IER_RTOIE;
16206 serial_outp(info, UART_IER, info->IER); /* enable interrupts */
16208 #ifdef CONFIG_SERIAL_MANY_PORTS
16209 @@ -1542,6 +1574,8 @@
16212 info->MCR &= ~UART_MCR_OUT2;
16213 + if (pxa_buggy_port(state->type))
16214 + info->MCR ^= UART_MCR_OUT2;
16215 info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */
16217 /* disable break condition */
16218 @@ -1567,6 +1601,20 @@
16219 state->baud_base = SERIAL_RSA_BAUD_BASE_LO;
16222 +#ifdef CONFIG_ARCH_PXA
16223 + if (state->type == PORT_PXA
16224 +#ifdef CONFIG_SERIAL_CONSOLE
16225 + && sercons.index != info->line
16228 + switch ((long)state->iomem_base) {
16229 + case (long)&FFUART: CKEN &= ~CKEN6_FFUART; break;
16230 + case (long)&BTUART: CKEN &= ~CKEN7_BTUART; break;
16231 + case (long)&STUART: CKEN &= ~CKEN5_STUART; break;
16237 (void)serial_in(info, UART_RX); /* read data port to reset things */
16239 @@ -1857,6 +1905,8 @@
16240 save_flags(flags); cli();
16241 info->IER |= UART_IER_THRI;
16242 serial_out(info, UART_IER, info->IER);
16243 + if (pxa_buggy_port(info->state->type))
16244 + rs_interrupt_single(info->state->irq, NULL, NULL);
16245 restore_flags(flags);
16248 @@ -1933,6 +1983,11 @@
16249 && !(info->IER & UART_IER_THRI)) {
16250 info->IER |= UART_IER_THRI;
16251 serial_out(info, UART_IER, info->IER);
16252 + if (pxa_buggy_port(info->state->type)) {
16253 + save_flags(flags); cli();
16254 + rs_interrupt_single(info->state->irq, NULL, NULL);
16255 + restore_flags(flags);
16260 @@ -1990,6 +2045,8 @@
16261 /* Make sure transmit interrupts are on */
16262 info->IER |= UART_IER_THRI;
16263 serial_out(info, UART_IER, info->IER);
16264 + if (pxa_buggy_port(info->state->type))
16265 + rs_interrupt_single(info->state->irq, NULL, NULL);
16269 @@ -5517,7 +5574,6 @@
16270 for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
16271 state->magic = SSTATE_MAGIC;
16273 - state->type = PORT_UNKNOWN;
16274 state->custom_divisor = 0;
16275 state->close_delay = 5*HZ/10;
16276 state->closing_wait = 30*HZ;
16277 @@ -5531,14 +5587,18 @@
16278 state->irq = irq_cannonicalize(state->irq);
16280 state->io_type = SERIAL_IO_HUB6;
16281 - if (state->port && check_region(state->port,8))
16282 + if (state->port && check_region(state->port,8)) {
16283 + state->type = PORT_UNKNOWN;
16287 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
16290 - if (state->flags & ASYNC_BOOT_AUTOCONF)
16291 + if (state->flags & ASYNC_BOOT_AUTOCONF) {
16292 + state->type = PORT_UNKNOWN;
16296 for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
16297 if (state->type == PORT_UNKNOWN)
16298 @@ -5858,6 +5918,8 @@
16300 ier = serial_in(info, UART_IER);
16301 serial_out(info, UART_IER, 0x00);
16302 + if (pxa_port(info->state->type))
16303 + serial_out(info, UART_IER, UART_IER_UUE);
16306 * Now, do each character
16307 @@ -6009,6 +6071,8 @@
16308 serial_out(info, UART_DLM, quot >> 8); /* MS of divisor */
16309 serial_out(info, UART_LCR, cval); /* reset DLAB */
16310 serial_out(info, UART_IER, 0);
16311 + if (pxa_port(info->state->type))
16312 + serial_out(info, UART_IER, UART_IER_UUE);
16313 serial_out(info, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
16316 --- linux-2.4.27/drivers/i2c/Config.in~2.4.27-vrs1-pxa1
16317 +++ linux-2.4.27/drivers/i2c/Config.in
16322 + if [ "$CONFIG_ARCH_PXA" = "y" ]; then
16323 + dep_tristate 'PXA I2C Algorithm' CONFIG_I2C_PXA_ALGO $CONFIG_I2C
16324 + dep_tristate 'PXA I2C Adapter' CONFIG_I2C_PXA_ADAP $CONFIG_I2C_PXA_ALGO
16327 if [ "$CONFIG_ALL_PPC" = "y" ] ; then
16328 dep_tristate 'Keywest I2C interface in Apple Core99 machines' CONFIG_I2C_KEYWEST $CONFIG_I2C
16330 --- linux-2.4.27/drivers/i2c/Makefile~2.4.27-vrs1-pxa1
16331 +++ linux-2.4.27/drivers/i2c/Makefile
16334 export-objs := i2c-core.o i2c-algo-bit.o i2c-algo-pcf.o \
16335 i2c-algo-ite.o i2c-algo-sibyte.o i2c-algo-sgi.o \
16337 + i2c-proc.o i2c-algo-pxa.o
16339 # Init order: core, chardev, bit adapters, pcf adapters
16342 obj-$(CONFIG_I2C_ALGO_SIBYTE) += i2c-algo-sibyte.o i2c-sibyte.o
16343 obj-$(CONFIG_I2C_MAX1617) += i2c-max1617.o
16344 obj-$(CONFIG_I2C_ALGO_SGI) += i2c-algo-sgi.o
16346 +obj-$(CONFIG_I2C_PXA_ALGO) += i2c-algo-pxa.o
16347 +obj-$(CONFIG_I2C_PXA_ADAP) += i2c-adap-pxa.o
16350 # This is needed for automatic patch generation: sensors code starts here
16351 # This is needed for automatic patch generation: sensors code ends here
16353 +++ linux-2.4.27/drivers/i2c/i2c-adap-pxa.c
16358 + * I2C adapter for the PXA I2C bus access.
16360 + * Copyright (C) 2002 Intrinsyc Software Inc.
16362 + * This program is free software; you can redistribute it and/or modify
16363 + * it under the terms of the GNU General Public License version 2 as
16364 + * published by the Free Software Foundation.
16367 + * Apr 2002: Initial version [CS]
16368 + * Jun 2002: Properly seperated algo/adap [FB]
16369 + * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
16370 + * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
16373 +#include <linux/kernel.h>
16374 +#include <linux/module.h>
16376 +#include <linux/i2c.h>
16377 +#include <linux/i2c-id.h>
16378 +#include <linux/init.h>
16379 +#include <linux/time.h>
16380 +#include <linux/sched.h>
16381 +#include <linux/delay.h>
16382 +#include <linux/errno.h>
16384 +#include <asm/hardware.h>
16385 +#include <asm/irq.h>
16386 +#include <asm/arch/irqs.h> /* for IRQ_I2C */
16388 +#include "i2c-pxa.h"
16391 + * Set this to zero to remove all debug statements via dead code elimination.
16396 +static unsigned int i2c_debug = DEBUG;
16398 +#define i2c_debug 0
16401 +static int irq = 0;
16402 +static volatile int i2c_pending = 0; /* interrupt pending when 1 */
16403 +static volatile int bus_error = 0;
16404 +static volatile int tx_finished = 0;
16405 +static volatile int rx_finished = 0;
16407 +static wait_queue_head_t i2c_wait;
16408 +static void i2c_pxa_transfer( int lastbyte, int receive, int midbyte);
16410 +/* place a byte in the transmit register */
16411 +static void i2c_pxa_write_byte(u8 value)
16416 +/* read byte in the receive register */
16417 +static u8 i2c_pxa_read_byte(void)
16419 + return (u8) (0xff & IDBR);
16422 +static void i2c_pxa_start(void)
16424 + unsigned long icr = ICR;
16425 + icr |= ICR_START;
16426 + icr &= ~(ICR_STOP | ICR_ALDIE | ICR_ACKNAK);
16429 + bus_error=0; /* clear any bus_error from previous txfers */
16430 + tx_finished=0; /* clear rx and tx interrupts from previous txfers */
16435 +static void i2c_pxa_repeat_start(void)
16437 + unsigned long icr = ICR;
16438 + icr |= ICR_START;
16439 + icr &= ~(ICR_STOP | ICR_ALDIE);
16442 + bus_error=0; /* clear any bus_error from previous txfers */
16443 + tx_finished=0; /* clear rx and tx interrupts from previous txfers */
16448 +static void i2c_pxa_stop(void)
16450 + unsigned long icr = ICR;
16452 + icr &= ~(ICR_START);
16456 +static void i2c_pxa_midbyte(void)
16458 + unsigned long icr = ICR;
16459 + icr &= ~(ICR_START | ICR_STOP);
16463 +static void i2c_pxa_abort(void)
16465 + unsigned long timeout = jiffies + HZ/4;
16467 +#ifdef PXA_ABORT_MA
16468 + while ((long)(timeout - jiffies) > 0 && (ICR & ICR_TB)) {
16469 + set_current_state(TASK_INTERRUPTIBLE);
16470 + schedule_timeout(1);
16476 + while ((long)(timeout - jiffies) > 0 && (IBMR & 0x1) == 0) {
16477 + i2c_pxa_transfer( 1, I2C_RECEIVE, 1);
16478 + set_current_state(TASK_INTERRUPTIBLE);
16479 + schedule_timeout(1);
16482 + ICR &= ~(ICR_MA | ICR_START | ICR_STOP);
16485 +static int i2c_pxa_wait_bus_not_busy( void)
16487 + int timeout = DEF_TIMEOUT;
16489 + while (timeout-- && (ISR & ISR_IBB)) {
16490 + udelay(100); /* wait for 100 us */
16493 + return (timeout<=0);
16496 +static void i2c_pxa_wait_for_ite(void){
16497 + unsigned long flags;
16499 + save_flags_cli(flags);
16500 + if (i2c_pending == 0) {
16501 + interruptible_sleep_on_timeout(&i2c_wait, I2C_SLEEP_TIMEOUT );
16504 + restore_flags(flags);
16510 +static int i2c_pxa_wait_for_int( int wait_type)
16512 + int timeout = DEF_TIMEOUT;
16515 + printk(KERN_INFO"i2c_pxa_wait_for_int: Bus error on enter\n");
16517 + printk(KERN_INFO"i2c_pxa_wait_for_int: Receive interrupt on enter\n");
16519 + printk(KERN_INFO"i2c_pxa_wait_for_int: Transmit interrupt on enter\n");
16522 + if (wait_type == I2C_RECEIVE){ /* wait on receive */
16525 + i2c_pxa_wait_for_ite();
16526 + } while (!(rx_finished) && timeout-- && !signal_pending(current));
16531 + printk("Error: i2c-algo-pxa.o: received a tx"
16532 + " interrupt while waiting on a rx in wait_for_int");
16535 + } else { /* wait on transmit */
16538 + i2c_pxa_wait_for_ite();
16539 + } while (!(tx_finished) && timeout-- && !signal_pending(current));
16544 + printk("Error: i2c-algo-pxa.o: received a rx"
16545 + " interrupt while waiting on a tx in wait_for_int");
16550 + udelay(ACK_DELAY); /* this is needed for the bus error */
16557 + if( i2c_debug > 2)printk("wait_for_int: error - no ack.\n");
16558 + return BUS_ERROR;
16561 + if (signal_pending(current)) {
16562 + return (-ERESTARTSYS);
16563 + } else if (timeout < 0) {
16564 + if( i2c_debug > 2)printk("wait_for_int: timeout.\n");
16570 +static void i2c_pxa_transfer( int lastbyte, int receive, int midbyte)
16574 + if( receive==I2C_RECEIVE) ICR |= ICR_ACKNAK;
16577 + else if( midbyte)
16579 + i2c_pxa_midbyte();
16584 +static void i2c_pxa_reset( void)
16587 + printk("Resetting I2C Controller Unit\n");
16590 + /* abort any transfer currently under way */
16593 + /* reset according to 9.8 */
16595 + ISR = I2C_ISR_INIT;
16598 + /* set the global I2C clock on */
16599 + CKEN |= CKEN14_I2C;
16601 + /* set our slave address */
16602 + ISAR = I2C_PXA_SLAVE_ADDR;
16604 + /* set control register values */
16605 + ICR = I2C_ICR_INIT;
16607 + /* clear any leftover states from prior transmissions */
16608 + i2c_pending = rx_finished = tx_finished = bus_error = 0;
16610 + /* enable unit */
16615 +static void i2c_pxa_handler(int this_irq, void *dev_id, struct pt_regs *regs)
16617 + int status, wakeup = 0;
16620 + if (status & ISR_BED){
16621 + (ISR) |= ISR_BED;
16622 + bus_error=ISR_BED;
16625 + if (status & ISR_ITE){
16626 + (ISR) |= ISR_ITE;
16627 + tx_finished=ISR_ITE;
16630 + if (status & ISR_IRF){
16631 + (ISR) |= ISR_IRF;
16632 + rx_finished=ISR_IRF;
16637 + wake_up_interruptible(&i2c_wait);
16641 +static int i2c_pxa_resource_init( void)
16643 + init_waitqueue_head(&i2c_wait);
16645 + if (request_irq(IRQ_I2C, &i2c_pxa_handler, SA_INTERRUPT, "I2C_PXA", 0) < 0) {
16648 + printk(KERN_INFO "I2C: Failed to register I2C irq %i\n", IRQ_I2C);
16657 +static void i2c_pxa_resource_release( void)
16661 + disable_irq(irq);
16667 +static void i2c_pxa_inc_use(struct i2c_adapter *adap)
16670 + MOD_INC_USE_COUNT;
16674 +static void i2c_pxa_dec_use(struct i2c_adapter *adap)
16677 + MOD_DEC_USE_COUNT;
16681 +static int i2c_pxa_client_register(struct i2c_client *client)
16686 +static int i2c_pxa_client_unregister(struct i2c_client *client)
16691 +static struct i2c_algo_pxa_data i2c_pxa_data = {
16692 + write_byte: i2c_pxa_write_byte,
16693 + read_byte: i2c_pxa_read_byte,
16695 + start: i2c_pxa_start,
16696 + repeat_start: i2c_pxa_repeat_start,
16697 + stop: i2c_pxa_stop,
16698 + abort: i2c_pxa_abort,
16700 + wait_bus_not_busy: i2c_pxa_wait_bus_not_busy,
16701 + wait_for_interrupt: i2c_pxa_wait_for_int,
16702 + transfer: i2c_pxa_transfer,
16703 + reset: i2c_pxa_reset,
16706 + timeout: DEF_TIMEOUT,
16709 +static struct i2c_adapter i2c_pxa_ops = {
16710 + name: "PXA-I2C-Adapter",
16711 + id: I2C_ALGO_PXA,
16712 + algo_data: &i2c_pxa_data,
16713 + inc_use: i2c_pxa_inc_use,
16714 + dec_use: i2c_pxa_dec_use,
16715 + client_register: i2c_pxa_client_register,
16716 + client_unregister: i2c_pxa_client_unregister,
16720 +extern int i2c_pxa_add_bus(struct i2c_adapter *);
16721 +extern int i2c_pxa_del_bus(struct i2c_adapter *);
16723 +static int __init i2c_adap_pxa_init(void)
16725 + if( i2c_pxa_resource_init() == 0) {
16727 + if (i2c_pxa_add_bus(&i2c_pxa_ops) < 0) {
16728 + i2c_pxa_resource_release();
16729 + printk(KERN_INFO "I2C: Failed to add bus\n");
16736 + printk(KERN_INFO "I2C: Successfully added bus\n");
16741 +static void i2c_adap_pxa_exit(void)
16743 + i2c_pxa_del_bus( &i2c_pxa_ops);
16744 + i2c_pxa_resource_release();
16746 + printk(KERN_INFO "I2C: Successfully removed bus\n");
16749 +module_init(i2c_adap_pxa_init);
16750 +module_exit(i2c_adap_pxa_exit);
16752 +++ linux-2.4.27/drivers/i2c/i2c-algo-pxa.c
16757 + * I2C algorithm for the PXA I2C bus access.
16758 + * Byte driven algorithm similar to pcf.
16760 + * Copyright (C) 2002 Intrinsyc Software Inc.
16762 + * This program is free software; you can redistribute it and/or modify
16763 + * it under the terms of the GNU General Public License version 2 as
16764 + * published by the Free Software Foundation.
16767 + * Apr 2002: Initial version [CS]
16768 + * Jun 2002: Properly seperated algo/adap [FB]
16769 + * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
16770 + * Jan 2003: allow SMBUS_QUICK as valid msg [FB]
16773 +#include <linux/kernel.h>
16774 +#include <linux/module.h>
16776 +#include <linux/init.h>
16777 +#include <linux/delay.h>
16778 +#include <linux/errno.h>
16779 +#include <linux/i2c.h> /* struct i2c_msg and others */
16780 +#include <linux/i2c-id.h>
16782 +#include "i2c-pxa.h"
16785 + * Set this to zero to remove all the debug statements via dead code elimination.
16790 +static unsigned int i2c_debug = DEBUG;
16792 +#define i2c_debug 0
16795 +static int pxa_scan = 1;
16797 +static int i2c_pxa_valid_messages( struct i2c_msg msgs[], int num)
16800 + if (num < 1 || num > MAX_MESSAGES){
16802 + printk(KERN_INFO "Invalid number of messages (max=%d, num=%d)\n",
16803 + MAX_MESSAGES, num);
16807 + /* check consistency of our messages */
16808 + for (i=0;i<num;i++){
16809 + if (&msgs[i]==NULL){
16810 + if( i2c_debug) printk(KERN_INFO "Msgs is NULL\n");
16813 + if (msgs[i].len < 0 || msgs[i].buf == NULL){
16814 + if( i2c_debug)printk(KERN_INFO "Length is less than zero");
16823 +static int i2c_pxa_readbytes(struct i2c_adapter *i2c_adap, char *buf,
16824 + int count, int last)
16827 + int i, timeout=0;
16828 + struct i2c_algo_pxa_data *adap = i2c_adap->algo_data;
16830 + /* increment number of bytes to read by one -- read dummy byte */
16831 + for (i = 0; i <= count; i++) {
16833 + /* set ACK to NAK for last received byte ICR[ACKNAK] = 1
16834 + only if not a repeated start */
16836 + if ((i == count) && last) {
16837 + adap->transfer( last, I2C_RECEIVE, 0);
16839 + adap->transfer( 0, I2C_RECEIVE, 1);
16842 + timeout = adap->wait_for_interrupt(I2C_RECEIVE);
16845 + if (timeout==BUS_ERROR){
16846 + printk(KERN_INFO "i2c_pxa_readbytes: bus error -> forcing reset\n");
16848 + return I2C_RETRY;
16851 + if (timeout == -ERESTARTSYS) {
16857 + printk(KERN_INFO "i2c_pxa_readbytes: timeout -> forcing reset\n");
16860 + return I2C_RETRY;
16866 + buf[i - 1] = adap->read_byte();
16868 + adap->read_byte(); /* dummy read */
16874 +static int i2c_pxa_sendbytes(struct i2c_adapter *i2c_adap, const char *buf,
16875 + int count, int last)
16878 + struct i2c_algo_pxa_data *adap = i2c_adap->algo_data;
16879 + int wrcount, timeout;
16881 + for (wrcount=0; wrcount<count; ++wrcount) {
16883 + adap->write_byte(buf[wrcount]);
16884 + if ((wrcount==(count-1)) && last) {
16885 + adap->transfer( last, I2C_TRANSMIT, 0);
16887 + adap->transfer( 0, I2C_TRANSMIT, 1);
16890 + timeout = adap->wait_for_interrupt(I2C_TRANSMIT);
16893 + if (timeout==BUS_ERROR) {
16894 + printk(KERN_INFO "i2c_pxa_sendbytes: bus error -> forcing reset.\n");
16896 + return I2C_RETRY;
16899 + if (timeout == -ERESTARTSYS) {
16905 + printk(KERN_INFO "i2c_pxa_sendbytes: timeout -> forcing reset\n");
16908 + return I2C_RETRY;
16911 + return (wrcount);
16915 +static inline int i2c_pxa_set_ctrl_byte(struct i2c_algo_pxa_data * adap, struct i2c_msg *msg)
16917 + u16 flags = msg->flags;
16919 + addr = (u8) ( (0x7f & msg->addr) << 1 );
16920 + if (flags & I2C_M_RD )
16922 + if (flags & I2C_M_REV_DIR_ADDR )
16924 + adap->write_byte(addr);
16928 +static int i2c_pxa_do_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num)
16930 + struct i2c_algo_pxa_data * adap;
16931 + struct i2c_msg *pmsg=NULL;
16933 + int ret=0, timeout;
16935 + adap = i2c_adap->algo_data;
16937 + timeout = adap->wait_bus_not_busy();
16940 + return I2C_RETRY;
16943 + for (i = 0;ret >= 0 && i < num; i++) {
16944 + int last = i + 1 == num;
16947 + ret = i2c_pxa_set_ctrl_byte(adap,pmsg);
16953 + adap->repeat_start();
16956 + adap->transfer(0, I2C_TRANSMIT, 0);
16958 + /* Wait for ITE (transmit empty) */
16959 + timeout = adap->wait_for_interrupt(I2C_TRANSMIT);
16962 + /* Check for ACK (bus error) */
16963 + if (timeout==BUS_ERROR){
16964 + printk(KERN_INFO "i2c_pxa_do_xfer: bus error -> forcing reset\n");
16966 + return I2C_RETRY;
16969 + if (timeout == -ERESTARTSYS) {
16975 + printk(KERN_INFO "i2c_pxa_do_xfer: timeout -> forcing reset\n");
16978 + return I2C_RETRY;
16980 +/* FIXME: handle arbitration... */
16982 + /* Check for bus arbitration loss */
16983 + if (adap->arbitration_loss()){
16984 + printk("Arbitration loss detected \n");
16986 + return I2C_RETRY;
16991 + if (pmsg->flags & I2C_M_RD) {
16992 + /* read bytes into buffer*/
16993 + ret = i2c_pxa_readbytes(i2c_adap, pmsg->buf, pmsg->len, last);
16995 + if (ret != pmsg->len) {
16996 + printk(KERN_INFO"i2c_pxa_do_xfer: read %d/%d bytes.\n",
16999 + printk(KERN_INFO"i2c_pxa_do_xfer: read %d bytes.\n",ret);
17002 + } else { /* Write */
17003 + ret = i2c_pxa_sendbytes(i2c_adap, pmsg->buf, pmsg->len, last);
17005 + if (ret != pmsg->len) {
17006 + printk(KERN_INFO"i2c_pxa_do_xfer: wrote %d/%d bytes.\n",
17009 + printk(KERN_INFO"i2c_pxa_do_xfer: wrote %d bytes.\n",ret);
17022 +static int i2c_pxa_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num)
17024 + int retval = i2c_pxa_valid_messages( msgs, num);
17028 + for (i=i2c_adap->retries; i>=0; i--){
17029 + int retval = i2c_pxa_do_xfer(i2c_adap,msgs,num);
17030 + if (retval!=I2C_RETRY){
17033 + if( i2c_debug)printk(KERN_INFO"Retrying transmission \n");
17036 + if( i2c_debug)printk(KERN_INFO"Retried %i times\n",i2c_adap->retries);
17037 + return -EREMOTEIO;
17043 +struct i2c_algorithm i2c_pxa_algorithm = {
17044 + name: "PXA-I2C-Algorithm",
17045 + id: I2C_ALGO_PXA,
17046 + master_xfer: i2c_pxa_xfer,
17047 + smbus_xfer: NULL,
17048 + slave_send: NULL,
17049 + slave_recv: NULL,
17050 + algo_control: NULL,
17054 + * registering functions to load algorithms at runtime
17056 +int i2c_pxa_add_bus(struct i2c_adapter *i2c_adap)
17058 + struct i2c_algo_pxa_data *adap = i2c_adap->algo_data;
17060 + printk(KERN_INFO"I2C: Adding %s.\n", i2c_adap->name);
17062 + i2c_adap->algo = &i2c_pxa_algorithm;
17064 + MOD_INC_USE_COUNT;
17066 + /* register new adapter to i2c module... */
17067 + i2c_add_adapter(i2c_adap);
17074 + printk(KERN_INFO "I2C: Scanning bus ");
17075 + for (i = 0x02; i < 0xff; i+=2) {
17076 + if( i==(I2C_PXA_SLAVE_ADDR<<1)) continue;
17078 + if (adap->wait_bus_not_busy()) {
17079 + printk(KERN_INFO "I2C: scanning bus %s - TIMEOUTed.\n",
17083 + adap->write_byte(i);
17085 + adap->transfer(0, I2C_TRANSMIT, 0);
17087 + if ((adap->wait_for_interrupt(I2C_TRANSMIT) != BUS_ERROR)) {
17088 + printk("(%02x)",i>>1);
17094 + udelay(adap->udelay);
17101 +int i2c_pxa_del_bus(struct i2c_adapter *i2c_adap)
17104 + if ((res = i2c_del_adapter(i2c_adap)) < 0)
17107 + MOD_DEC_USE_COUNT;
17109 + printk(KERN_INFO "I2C: Removing %s.\n", i2c_adap->name);
17114 +static int __init i2c_algo_pxa_init (void)
17116 + printk(KERN_INFO "I2C: PXA algorithm module loaded.\n");
17120 +EXPORT_SYMBOL(i2c_pxa_add_bus);
17121 +EXPORT_SYMBOL(i2c_pxa_del_bus);
17123 +MODULE_PARM(pxa_scan, "i");
17124 +MODULE_PARM_DESC(pxa_scan, "Scan for active chips on the bus");
17126 +MODULE_AUTHOR("Intrinsyc Software Inc.");
17127 +MODULE_LICENSE("GPL");
17129 +module_init(i2c_algo_pxa_init);
17131 +++ linux-2.4.27/drivers/i2c/i2c-pxa.h
17136 + * Copyright (C) 2002 Intrinsyc Software Inc.
17138 + * This program is free software; you can redistribute it and/or modify
17139 + * it under the terms of the GNU General Public License version 2 as
17140 + * published by the Free Software Foundation.
17143 +#ifndef _I2C_PXA_H_
17144 +#define _I2C_PXA_H_
17146 +struct i2c_algo_pxa_data
17148 + void (*write_byte) (u8 value);
17149 + u8 (*read_byte) (void);
17150 + void (*start) (void);
17151 + void (*repeat_start) (void);
17152 + void (*stop) (void);
17153 + void (*abort) (void);
17154 + int (*wait_bus_not_busy) (void);
17155 + int (*wait_for_interrupt) (int wait_type);
17156 + void (*transfer) (int lastbyte, int receive, int midbyte);
17157 + void (*reset) (void);
17163 +#define DEF_TIMEOUT 3
17164 +#define BUS_ERROR (-EREMOTEIO)
17165 +#define ACK_DELAY 0 /* time to delay before checking bus error */
17166 +#define MAX_MESSAGES 65536 /* maximum number of messages to send */
17168 +#define I2C_SLEEP_TIMEOUT 2 /* time to sleep for on i2c transactions */
17169 +#define I2C_RETRY (-2000) /* an error has occurred retry transmit */
17170 +#define I2C_TRANSMIT 1
17171 +#define I2C_RECEIVE 0
17172 +#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */
17173 +#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) /* ICR initialization value */
17174 +/* ICR initialize bit values
17176 +* 15. FM 0 (100 Khz operation)
17177 +* 14. UR 0 (No unit reset)
17178 +* 13. SADIE 0 (Disables the unit from interrupting on slave addresses
17179 +* matching its slave address)
17180 +* 12. ALDIE 0 (Disables the unit from interrupt when it loses arbitration
17182 +* 11. SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode)
17183 +* 10. BEIE 1 (Enable interrupts from detected bus errors, no ACK sent)
17184 +* 9. IRFIE 1 (Enable interrupts from full buffer received)
17185 +* 8. ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty)
17186 +* 7. GCD 1 (Disables i2c unit response to general call messages as a slave)
17187 +* 6. IUE 0 (Disable unit until we change settings)
17188 +* 5. SCLE 1 (Enables the i2c clock output for master mode (drives SCL)
17189 +* 4. MA 0 (Only send stop with the ICR stop bit)
17190 +* 3. TB 0 (We are not transmitting a byte initially)
17191 +* 2. ACKNAK 0 (Send an ACK after the unit receives a byte)
17192 +* 1. STOP 0 (Do not send a STOP)
17193 +* 0. START 0 (Do not send a START)
17197 +#define I2C_ISR_INIT 0x7FF /* status register init */
17198 +/* I2C status register init values
17200 + * 10. BED 1 (Clear bus error detected)
17201 + * 9. SAD 1 (Clear slave address detected)
17202 + * 7. IRF 1 (Clear IDBR Receive Full)
17203 + * 6. ITE 1 (Clear IDBR Transmit Empty)
17204 + * 5. ALD 1 (Clear Arbitration Loss Detected)
17205 + * 4. SSD 1 (Clear Slave Stop Detected)
17209 --- linux-2.4.27/drivers/misc/Config.in~2.4.27-vrs1-pxa1
17210 +++ linux-2.4.27/drivers/misc/Config.in
17212 dep_tristate 'Support for UCB1200 / UCB1300' CONFIG_MCP_UCB1200 $CONFIG_MCP
17213 dep_tristate ' Audio / Telephony interface support' CONFIG_MCP_UCB1200_AUDIO $CONFIG_MCP_UCB1200 $CONFIG_SOUND
17214 dep_tristate ' Touchscreen interface support' CONFIG_MCP_UCB1200_TS $CONFIG_MCP_UCB1200
17215 +dep_tristate ' UCB1400 Touchscreen support' CONFIG_MCP_UCB1400_TS $CONFIG_ARCH_PXA $CONFIG_SOUND
17218 --- linux-2.4.27/drivers/misc/Makefile~2.4.27-vrs1-pxa1
17219 +++ linux-2.4.27/drivers/misc/Makefile
17220 @@ -11,13 +11,15 @@
17224 -export-objs := mcp-core.o mcp-sa1100.o ucb1x00-core.o
17225 +export-objs := mcp-core.o mcp-sa1100.o mcp-pxa.o \
17228 -obj-$(CONFIG_MCP) += mcp-core.o
17229 -obj-$(CONFIG_MCP_SA1100) += mcp-sa1100.o
17230 +obj-$(CONFIG_MCP_SA1100) += mcp-core.o mcp-sa1100.o
17231 obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o
17232 obj-$(CONFIG_MCP_UCB1200_AUDIO) += ucb1x00-audio.o
17233 obj-$(CONFIG_MCP_UCB1200_TS) += ucb1x00-ts.o
17234 +obj-$(CONFIG_MCP_UCB1400_TS) += mcp-pxa.o ucb1x00-core.o ucb1x00-ts.o
17235 +obj-$(CONFIG_PXA_CERF_PDA) += cerf_ucb1400gpio.o
17237 include $(TOPDIR)/Rules.make
17240 +++ linux-2.4.27/drivers/misc/cerf_ucb1400gpio.c
17243 + * cerf_ucb1400gpio.c
17245 + * UCB1400 GPIO control stuff for the cerf.
17247 + * Copyright (C) 2002 Intrinsyc Software Inc.
17249 + * This program is free software; you can redistribute it and/or modify
17250 + * it under the terms of the GNU General Public License version 2 as
17251 + * published by the Free Software Foundation.
17254 + * Mar 2002: Initial version [FB]
17255 + * Jun 2002: Removed ac97 dependency [FB]
17258 +#include <linux/config.h>
17259 +#include <linux/module.h>
17260 +#include <linux/kernel.h>
17261 +#include <linux/sched.h>
17262 +#include <linux/errno.h>
17263 +#include <linux/string.h>
17264 +#include <linux/ctype.h>
17265 +#include <linux/mm.h>
17266 +#include <linux/init.h>
17267 +#include <linux/delay.h>
17269 +#include <asm/system.h>
17270 +#include <asm/hardware.h>
17271 +#include <asm/io.h>
17272 +#include <asm/irq.h>
17273 +#include <asm/uaccess.h>
17275 +#include "ucb1x00.h"
17278 + * Set this to zero to remove all the debug statements via
17279 + * dead code elimination.
17281 +#define DEBUGGING 0
17284 +static unsigned int ucb_debug = DEBUGGING;
17286 +#define ucb_debug 0
17294 +void cerf_ucb1400gpio_lcd_enable( void)
17296 + struct ucb1x00 * ucb = ucb1x00_get();
17297 + if( ucb_debug > 2) printk( KERN_INFO "Enabling LCD.\n");
17298 + /* Enable [not] LCD_RESET to enable the LCD display */
17299 + ucb1x00_io_set_dir( ucb, 0, UCB1400_GPIO_LCD_RESET);
17300 + ucb1x00_io_write( ucb, UCB1400_GPIO_LCD_RESET, 0);
17302 + /* Enable the Contrast circuit */
17303 + ucb1x00_io_set_dir( ucb, 0, UCB1400_GPIO_CONT_ENA);
17304 + ucb1x00_io_write( ucb, UCB1400_GPIO_CONT_ENA, 0);
17307 +void cerf_ucb1400gpio_lcd_disable( void)
17309 + struct ucb1x00 * ucb = ucb1x00_get();
17310 + if( ucb_debug > 2) printk( KERN_INFO "Disabling LCD.\n");
17311 + /* Disable the Contrast circuit */
17312 + ucb1x00_io_set_dir( ucb, 0, UCB1400_GPIO_CONT_ENA);
17313 + ucb1x00_io_write( ucb, 0, UCB1400_GPIO_CONT_ENA);
17315 + /* Disable [not] LCD_RESET to enable the LCD display */
17316 + ucb1x00_io_set_dir( ucb, 0, UCB1400_GPIO_LCD_RESET);
17317 + ucb1x00_io_write( ucb, 0, UCB1400_GPIO_LCD_RESET);
17320 +void cerf_ucb1400gpio_lcd_contrast_step( int direction)
17322 + struct ucb1x00 * ucb = ucb1x00_get();
17323 + // Assert the chip select and the up modifier
17324 + ucb1x00_io_set_dir( ucb, 0,
17325 + (UCB1400_GPIO_CONT_CS |
17326 + UCB1400_GPIO_CONT_DOWN |
17327 + UCB1400_GPIO_CONT_INC));
17329 + if( direction == DOWN)
17331 + if( ucb_debug > 3)
17332 + printk(KERN_INFO "cerf_ucb1400gpio_lcd_contrast_step: "
17333 + "stepping up\n");
17335 + ucb1x00_io_write( ucb, UCB1400_GPIO_CONT_DOWN, 0);
17339 + if( ucb_debug > 3)
17340 + printk(KERN_INFO "cerf_ucb1400gpio_lcd_contrast_step: "
17341 + "stepping down\n");
17343 + ucb1x00_io_write( ucb, 0, UCB1400_GPIO_CONT_DOWN);
17346 + ucb1x00_io_write( ucb, 0, UCB1400_GPIO_CONT_CS);
17348 + // Assert the line up, down then up again
17349 + ucb1x00_io_write( ucb, 0, UCB1400_GPIO_CONT_INC);
17351 + ucb1x00_io_write( ucb, UCB1400_GPIO_CONT_INC, 0);
17353 + ucb1x00_io_write( ucb, 0, UCB1400_GPIO_CONT_INC);
17355 + // Deassert the chip select and the up modifier
17356 + ucb1x00_io_write( ucb, 0, UCB1400_GPIO_CONT_DOWN);
17357 + ucb1x00_io_write( ucb, UCB1400_GPIO_CONT_CS, 0);
17362 +void cerf_ucb1400gpio_irda_enable( void)
17364 + struct ucb1x00 * ucb = ucb1x00_get();
17365 + printk( KERN_INFO "Enabling IRDA.\n");
17366 + /* Enable IRDA (active low) */
17367 + ucb1x00_io_set_dir( ucb, 0, UCB1400_GPIO_IRDA_ENABLE);
17368 + ucb1x00_io_write( ucb, 0, UCB1400_GPIO_IRDA_ENABLE);
17371 +void cerf_ucb1400gpio_irda_disable( void)
17373 + struct ucb1x00 * ucb = ucb1x00_get();
17374 + printk( KERN_INFO "Disabling IRDA.\n");
17375 + /* Disable IRDA (active low) */
17376 + ucb1x00_io_set_dir( ucb, 0, UCB1400_GPIO_IRDA_ENABLE);
17377 + ucb1x00_io_write( ucb, UCB1400_GPIO_IRDA_ENABLE, 0);
17382 +void cerf_ucb1400gpio_bt_enable( void)
17384 + struct ucb1x00 * ucb = ucb1x00_get();
17385 + printk( KERN_INFO "Enabling Bluetooth.\n");
17386 + /* Enable BT (active low) */
17387 + ucb1x00_io_set_dir( ucb, 0, UCB1400_GPIO_BT_ENABLE);
17388 + ucb1x00_io_write( ucb, 0, UCB1400_GPIO_BT_ENABLE);
17391 +void cerf_ucb1400gpio_bt_disable( void)
17393 + struct ucb1x00 * ucb = ucb1x00_get();
17394 + printk( KERN_INFO "Disabling Bluetooth.\n");
17395 + /* Disable BT (active low) */
17396 + ucb1x00_io_set_dir( ucb, 0, UCB1400_GPIO_BT_ENABLE);
17397 + ucb1x00_io_write( ucb, UCB1400_GPIO_BT_ENABLE, 0);
17402 +/* -- Enable Bluetooth and IRDA automatically via pseudo module -- */
17403 +#if defined(CONFIG_BLUEZ) || defined(CONFIG_IRDA)
17404 +static int __init cerf_ucb1400gpio_module_init (void)
17406 +#ifdef CONFIG_BLUEZ
17407 + cerf_ucb1400gpio_bt_enable();
17410 +#ifdef CONFIG_IRDA
17411 + cerf_ucb1400gpio_irda_enable();
17416 +static void __exit cerf_ucb1400gpio_module_exit (void)
17418 +#ifdef CONFIG_BLUEZ
17419 + cerf_ucb1400gpio_bt_disable();
17422 +#ifdef CONFIG_IRDA
17423 + cerf_ucb1400gpio_irda_disable();
17427 +module_init(cerf_ucb1400gpio_module_init);
17428 +module_exit(cerf_ucb1400gpio_module_exit);
17432 +++ linux-2.4.27/drivers/misc/mcp-pxa.c
17435 + * linux/drivers/misc/mcp-pxa.c
17437 + * 2002-01-10 Jeff Sutherland <jeffs@accelent.com>
17439 + * This program is free software; you can redistribute it and/or modify
17440 + * it under the terms of the GNU General Public License as published by
17441 + * the Free Software Foundation; either version 2 of the License.
17443 + * NOTE: This is a quick hack to gain access to the aclink codec's
17444 + * touch screen facility. Its audio is handled by a separate
17445 + * (non-mcp) driver at the present time.
17448 +#include <linux/module.h>
17449 +#include <linux/types.h>
17450 +#include <linux/ac97_codec.h>
17455 +extern int pxa_ac97_get(struct ac97_codec **codec);
17456 +extern void pxa_ac97_put(void);
17459 +struct mcp *mcp_get(void)
17461 + struct ac97_codec *codec;
17462 + if (pxa_ac97_get(&codec) < 0)
17464 + return (struct mcp *)codec;
17467 +void mcp_reg_write(struct mcp *mcp, unsigned int reg, unsigned int val)
17469 + struct ac97_codec *codec = (struct ac97_codec *)mcp;
17470 + codec->codec_write(codec, reg, val);
17473 +unsigned int mcp_reg_read(struct mcp *mcp, unsigned int reg)
17475 + struct ac97_codec *codec = (struct ac97_codec *)mcp;
17476 + return codec->codec_read(codec, reg);
17479 +void mcp_enable(struct mcp *mcp)
17482 + * Should we do something here to make sure the aclink
17483 + * codec is alive???
17484 + * A: not for now --NP
17488 +void mcp_disable(struct mcp *mcp)
17491 --- linux-2.4.27/drivers/misc/mcp.h~2.4.27-vrs1-pxa1
17492 +++ linux-2.4.27/drivers/misc/mcp.h
17493 @@ -10,16 +10,22 @@
17497 +#ifdef CONFIG_ARCH_SA1100
17498 +#include <asm/dma.h>
17502 struct module *owner;
17505 unsigned int sclk_rate;
17506 unsigned int rw_timeout;
17507 +#ifdef CONFIG_ARCH_SA1100
17508 dma_device_t dma_audio_rd;
17509 dma_device_t dma_audio_wr;
17510 dma_device_t dma_telco_rd;
17511 dma_device_t dma_telco_wr;
17513 void (*set_telecom_divisor)(struct mcp *, unsigned int);
17514 void (*set_audio_divisor)(struct mcp *, unsigned int);
17515 void (*reg_write)(struct mcp *, unsigned int, unsigned int);
17516 --- linux-2.4.27/drivers/misc/ucb1x00-core.c~2.4.27-vrs1-pxa1
17517 +++ linux-2.4.27/drivers/misc/ucb1x00-core.c
17518 @@ -23,12 +23,18 @@
17519 #include <linux/errno.h>
17520 #include <linux/interrupt.h>
17521 #include <linux/pm.h>
17522 +#include <linux/tqueue.h>
17523 +#include <linux/config.h>
17525 -#include <asm/dma.h>
17526 -#include <asm/hardware.h>
17527 #include <asm/irq.h>
17528 #include <asm/mach-types.h>
17530 +#ifdef CONFIG_ARCH_SA1100
17531 +#include <asm/arch/assabet.h>
17532 #include <asm/arch/shannon.h>
17535 +#include <asm/hardware.h>
17537 #include "ucb1x00.h"
17539 @@ -155,6 +161,10 @@
17541 * If called for a synchronised ADC conversion, it may sleep
17542 * with the ADC semaphore held.
17544 + * See ucb1x00.h for definition of the UCB_ADC_DAT macro. It
17545 + * addresses a bug in the ucb1200/1300 which, of course, Philips
17546 + * decided to finally fix in the ucb1400 ;-) -jws
17548 unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync)
17550 @@ -218,22 +228,75 @@
17551 * Since we need to read an internal register, we must re-enable
17552 * SIBCLK to talk to the chip. We leave the clock running until
17553 * we have finished processing all interrupts from the chip.
17555 + * A restriction with interrupts exists when using the ucb1400, as
17556 + * the codec read/write routines may sleep while waiting for codec
17557 + * access completion and uses semaphores for access control to the
17558 + * AC97 bus. A complete codec read cycle could take anywhere from
17559 + * 60 to 100uSec so we *definitely* don't want to spin inside the
17560 + * interrupt handler waiting for codec access. So, we handle the
17561 + * interrupt by scheduling a RT kernel thread to run in process
17562 + * context instead of interrupt context.
17564 -static void ucb1x00_irq(int irqnr, void *devid, struct pt_regs *regs)
17566 +static int ucb1x00_thread(void *_ucb)
17568 - struct ucb1x00 *ucb = devid;
17569 + struct task_struct *tsk = current;
17570 + DECLARE_WAITQUEUE(wait, tsk);
17571 + struct ucb1x00 *ucb = _ucb;
17572 struct ucb1x00_irq *irq;
17573 unsigned int isr, i;
17575 - ucb1x00_enable(ucb);
17576 - isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS);
17577 - ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr);
17578 - ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
17579 + ucb->rtask = tsk;
17581 - for (i = 0, irq = ucb->irq_handler; i < 16 && isr; i++, isr >>= 1, irq++)
17582 - if (isr & 1 && irq->fn)
17583 - irq->fn(i, irq->devid);
17584 - ucb1x00_disable(ucb);
17586 + reparent_to_init();
17588 + tsk->policy = SCHED_FIFO;
17589 + tsk->rt_priority = 1;
17590 + strcpy(tsk->comm, "kUCB1x00d");
17592 + /* only want to receive SIGKILL */
17593 + spin_lock_irq(&tsk->sigmask_lock);
17594 + siginitsetinv(&tsk->blocked, sigmask(SIGKILL));
17595 + recalc_sigpending(tsk);
17596 + spin_unlock_irq(&tsk->sigmask_lock);
17598 + add_wait_queue(&ucb->irq_wait, &wait);
17599 + set_task_state(tsk, TASK_INTERRUPTIBLE);
17600 + complete(&ucb->complete);
17603 + if (signal_pending(tsk))
17605 + enable_irq(ucb->irq);
17608 + ucb1x00_enable(ucb);
17609 + isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS);
17610 + ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr);
17611 + ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
17613 + for (i = 0, irq = ucb->irq_handler;
17615 + i++, isr >>= 1, irq++)
17616 + if (isr & 1 && irq->fn)
17617 + irq->fn(i, irq->devid);
17618 + ucb1x00_disable(ucb);
17620 + set_task_state(tsk, TASK_INTERRUPTIBLE);
17623 + remove_wait_queue(&ucb->irq_wait, &wait);
17624 + ucb->rtask = NULL;
17625 + complete_and_exit(&ucb->complete, 0);
17628 +static void ucb1x00_irq(int irqnr, void *devid, struct pt_regs *regs)
17630 + struct ucb1x00 *ucb = devid;
17631 + disable_irq(irqnr);
17632 + wake_up(&ucb->irq_wait);
17636 @@ -291,6 +354,11 @@
17637 spin_lock_irqsave(&ucb->lock, flags);
17639 ucb1x00_enable(ucb);
17641 + /* This prevents spurious interrupts on the UCB1400 */
17642 + ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 1 << idx);
17643 + ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
17645 if (edges & UCB_RISING) {
17646 ucb->irq_ris_enbl |= 1 << idx;
17647 ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
17648 @@ -456,6 +524,7 @@
17649 unsigned int irq_gpio_pin = 0;
17650 int irq, default_irq = NO_IRQ;
17652 +#ifdef CONFIG_ARCH_SA1100
17653 if (machine_is_adsbitsy())
17654 default_irq = IRQ_GPCIN4;
17656 @@ -514,12 +583,40 @@
17660 +#endif /* CONFIG_ARCH_SA1100 */
17662 +#ifdef CONFIG_ARCH_PXA_IDP
17663 + if (machine_is_pxa_idp()) {
17664 + default_irq = TOUCH_PANEL_IRQ;
17665 + irq_gpio_pin = IRQ_TO_GPIO_2_80(TOUCH_PANEL_IRQ);
17666 + GPDR(irq_gpio_pin) &= ~GPIO_bit(irq_gpio_pin);
17670 +#ifdef CONFIG_ARCH_TRIZEPS2
17671 + if (machine_is_trizeps2()) {
17672 + default_irq = TOUCH_PANEL_IRQ;
17673 + irq_gpio_pin = IRQ_TO_GPIO_2_80(TOUCH_PANEL_IRQ);
17674 + GPDR(irq_gpio_pin) &= ~GPIO_bit(irq_gpio_pin);
17679 +#ifdef CONFIG_PXA_CERF_PDA
17680 + if (machine_is_pxa_cerf()) {
17681 + irq_gpio_pin = CERF_GPIO_UCB1400_IRQ;
17686 * Eventually, this will disappear.
17689 +#ifdef CONFIG_ARCH_PXA_IDP
17690 + set_GPIO_IRQ_edge(irq_gpio_pin, GPIO_FALLING_EDGE);
17692 set_GPIO_IRQ_edge(irq_gpio_pin, GPIO_RISING_EDGE);
17695 irq = ucb1x00_detect_irq(ucb);
17696 if (irq != NO_IRQ) {
17697 if (default_irq != NO_IRQ && irq != default_irq)
17698 @@ -541,21 +638,7 @@
17700 struct ucb1x00 *my_ucb;
17703 - * ucb1x00_get - get the UCB1x00 structure describing a chip
17704 - * @ucb: UCB1x00 structure describing chip
17706 - * Return the UCB1x00 structure describing a chip.
17708 - * FIXME: Currently very noddy indeed, which currently doesn't
17709 - * matter since we only support one chip.
17711 -struct ucb1x00 *ucb1x00_get(void)
17716 -static int __init ucb1x00_init(void)
17717 +static int ucb1x00_init_helper(void)
17721 @@ -568,23 +651,28 @@
17723 id = mcp_reg_read(mcp, UCB_ID);
17725 - if (id != UCB_ID_1200 && id != UCB_ID_1300) {
17726 + if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_1400) {
17727 printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id);
17731 + /* distinguish between UCB1400 revs 1B and 2A */
17732 + if (id == UCB_ID_1400 && mcp_reg_read(mcp, 0x00) == 0x002a)
17733 + id = UCB_ID_1400_BUGGY;
17735 my_ucb = kmalloc(sizeof(struct ucb1x00), GFP_KERNEL);
17740 +#ifdef CONFIG_ARCH_SA1100
17741 if (machine_is_shannon()) {
17742 /* reset the codec */
17743 GPDR |= SHANNON_GPIO_CODEC_RESET;
17744 GPCR = SHANNON_GPIO_CODEC_RESET;
17745 GPSR = SHANNON_GPIO_CODEC_RESET;
17750 memset(my_ucb, 0, sizeof(struct ucb1x00));
17752 @@ -599,13 +687,12 @@
17756 + init_waitqueue_head(&my_ucb->irq_wait);
17757 ret = request_irq(my_ucb->irq, ucb1x00_irq, 0, "UCB1x00", my_ucb);
17759 printk(KERN_ERR "ucb1x00: unable to grab irq%d: %d\n",
17768 @@ -616,16 +703,55 @@
17769 my_ucb->pmdev->data = my_ucb;
17772 + init_completion(&my_ucb->complete);
17773 + ret = kernel_thread(ucb1x00_thread, my_ucb, CLONE_FS | CLONE_FILES);
17775 + wait_for_completion(&my_ucb->complete);
17780 + free_irq(my_ucb->irq, my_ucb);
17791 + * ucb1x00_get - get the UCB1x00 structure describing a chip
17792 + * @ucb: UCB1x00 structure describing chip
17794 + * Return the UCB1x00 structure describing a chip.
17796 + * FIXME: Currently very noddy indeed, which currently doesn't
17797 + * matter since we only support one chip.
17799 +struct ucb1x00 *ucb1x00_get(void)
17801 + if( !my_ucb) ucb1x00_init_helper();
17806 +static int __init ucb1x00_init(void)
17808 + /* check if driver is already initialized */
17809 + if( my_ucb) return 0;
17811 + return ucb1x00_init_helper();
17814 static void __exit ucb1x00_exit(void)
17816 + send_sig(SIGKILL, my_ucb->rtask, 1);
17817 + wait_for_completion(&my_ucb->complete);
17818 free_irq(my_ucb->irq, my_ucb);
17823 module_init(ucb1x00_init);
17824 --- linux-2.4.27/drivers/misc/ucb1x00-ts.c~2.4.27-vrs1-pxa1
17825 +++ linux-2.4.27/drivers/misc/ucb1x00-ts.c
17828 * Define this if you want the UCB1x00 stuff to talk to the input layer
17830 +#ifdef CONFIG_INPUT
17839 struct pm_dev *pmdev;
17842 - wait_queue_head_t irq_wait;
17843 + struct semaphore irq_wait;
17844 struct semaphore sem;
17845 struct completion init_exit;
17846 struct task_struct *rtask;
17847 @@ -259,6 +263,11 @@
17848 input_report_abs(&ts->idev, ABS_PRESSURE, pressure);
17851 +static inline void ucb1x00_ts_event_release(struct ucb1x00_ts *ts)
17853 + input_report_abs(&ts->idev, ABS_PRESSURE, 0);
17856 static int ucb1x00_ts_open(struct input_dev *idev)
17858 struct ucb1x00_ts *ts = (struct ucb1x00_ts *)idev;
17859 @@ -304,10 +313,15 @@
17861 static inline void ucb1x00_ts_mode_int(struct ucb1x00_ts *ts)
17863 - ucb1x00_reg_write(ts->ucb, UCB_TS_CR,
17864 - UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
17865 - UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
17866 - UCB_TS_CR_MODE_INT);
17867 + if (ts->ucb->id == UCB_ID_1400_BUGGY)
17868 + ucb1x00_reg_write(ts->ucb, UCB_TS_CR,
17869 + UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
17870 + UCB_TS_CR_MODE_INT);
17872 + ucb1x00_reg_write(ts->ucb, UCB_TS_CR,
17873 + UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
17874 + UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
17875 + UCB_TS_CR_MODE_INT);
17879 @@ -397,13 +411,13 @@
17881 * This is a RT kernel thread that handles the ADC accesses
17882 * (mainly so we can use semaphores in the UCB1200 core code
17883 - * to serialise accesses to the ADC).
17884 + * to serialise accesses to the ADC). The UCB1400 access
17885 + * functions are expected to be able to sleep as well.
17887 static int ucb1x00_thread(void *_ts)
17889 struct ucb1x00_ts *ts = _ts;
17890 struct task_struct *tsk = current;
17891 - DECLARE_WAITQUEUE(wait, tsk);
17895 @@ -429,10 +443,8 @@
17899 - add_wait_queue(&ts->irq_wait, &wait);
17901 unsigned int x, y, p, val;
17902 - signed long timeout;
17906 @@ -457,8 +469,6 @@
17907 val = ucb1x00_reg_read(ts->ucb, UCB_TS_CR);
17909 if (val & (UCB_TS_CR_TSPX_LOW | UCB_TS_CR_TSMX_LOW)) {
17910 - set_task_state(tsk, TASK_INTERRUPTIBLE);
17912 ucb1x00_enable_irq(ts->ucb, UCB_IRQ_TSPX, UCB_FALLING);
17913 ucb1x00_disable(ts->ucb);
17915 @@ -471,7 +481,15 @@
17919 - timeout = MAX_SCHEDULE_TIMEOUT;
17921 + * Since ucb1x00_enable_irq() might sleep due
17922 + * to the way the UCB1400 regs are accessed, we
17923 + * can't use set_task_state() before that call,
17924 + * and not changing state before enabling the
17925 + * interrupt is racy. A semaphore solves all
17926 + * those issues quite nicely.
17928 + down_interruptible(&ts->irq_wait);
17930 ucb1x00_disable(ts->ucb);
17932 @@ -486,16 +504,13 @@
17935 set_task_state(tsk, TASK_INTERRUPTIBLE);
17936 - timeout = HZ / 100;
17937 + schedule_timeout(HZ / 100);
17940 - schedule_timeout(timeout);
17941 if (signal_pending(tsk))
17945 - remove_wait_queue(&ts->irq_wait, &wait);
17948 ucb1x00_ts_evt_clear(ts);
17949 complete_and_exit(&ts->init_exit, 0);
17950 @@ -509,7 +524,7 @@
17952 struct ucb1x00_ts *ts = id;
17953 ucb1x00_disable_irq(ts->ucb, UCB_IRQ_TSPX, UCB_FALLING);
17954 - wake_up(&ts->irq_wait);
17955 + up(&ts->irq_wait);
17958 static int ucb1x00_ts_startup(struct ucb1x00_ts *ts)
17959 @@ -525,7 +540,7 @@
17961 panic("ucb1x00: rtask running?");
17963 - init_waitqueue_head(&ts->irq_wait);
17964 + sema_init(&ts->irq_wait, 0);
17965 ret = ucb1x00_hook_irq(ts->ucb, UCB_IRQ_TSPX, ucb1x00_ts_irq, ts);
17968 @@ -585,7 +600,7 @@
17972 - wake_up(&ts->irq_wait);
17973 + up(&ts->irq_wait);
17977 --- linux-2.4.27/drivers/misc/ucb1x00.h~2.4.27-vrs1-pxa1
17978 +++ linux-2.4.27/drivers/misc/ucb1x00.h
17983 +#ifdef CONFIG_ARCH_PXA
17985 +/* ucb1400 aclink register mappings: */
17987 +#define UCB_IO_DATA 0x5a
17988 +#define UCB_IO_DIR 0x5c
17989 +#define UCB_IE_RIS 0x5e
17990 +#define UCB_IE_FAL 0x60
17991 +#define UCB_IE_STATUS 0x62
17992 +#define UCB_IE_CLEAR 0x62
17993 +#define UCB_TS_CR 0x64
17994 +#define UCB_ADC_CR 0x66
17995 +#define UCB_ADC_DATA 0x68
17996 +#define UCB_ID 0x7e /* 7c is mfr id, 7e part id (from aclink spec) */
17998 +#define UCB_ADC_DAT(x) ((x) & 0x3ff)
18002 +/* ucb1x00 SIB register mappings: */
18004 #define UCB_IO_DATA 0x00
18005 #define UCB_IO_DIR 0x01
18006 +#define UCB_IE_RIS 0x02
18007 +#define UCB_IE_FAL 0x03
18008 +#define UCB_IE_STATUS 0x04
18009 +#define UCB_IE_CLEAR 0x04
18010 +#define UCB_TC_A 0x05
18011 +#define UCB_TC_B 0x06
18012 +#define UCB_AC_A 0x07
18013 +#define UCB_AC_B 0x08
18014 +#define UCB_TS_CR 0x09
18015 +#define UCB_ADC_CR 0x0a
18016 +#define UCB_ADC_DATA 0x0b
18017 +#define UCB_ID 0x0c
18018 +#define UCB_MODE 0x0d
18020 +#define UCB_ADC_DAT(x) (((x) & 0x7fe0) >> 5)
18025 #define UCB_IO_0 (1 << 0)
18026 #define UCB_IO_1 (1 << 1)
18028 #define UCB_IO_8 (1 << 8)
18029 #define UCB_IO_9 (1 << 9)
18031 -#define UCB_IE_RIS 0x02
18032 -#define UCB_IE_FAL 0x03
18033 -#define UCB_IE_STATUS 0x04
18034 -#define UCB_IE_CLEAR 0x04
18035 #define UCB_IE_ADC (1 << 11)
18036 #define UCB_IE_TSPX (1 << 12)
18037 #define UCB_IE_TSMX (1 << 13)
18040 #define UCB_IRQ_TSPX 12
18042 -#define UCB_TC_A 0x05
18043 #define UCB_TC_A_LOOP (1 << 7) /* UCB1200 */
18044 #define UCB_TC_A_AMPL (1 << 7) /* UCB1300 */
18046 -#define UCB_TC_B 0x06
18047 #define UCB_TC_B_VOICE_ENA (1 << 3)
18048 #define UCB_TC_B_CLIP (1 << 4)
18049 #define UCB_TC_B_ATT (1 << 6)
18050 @@ -49,14 +82,11 @@
18051 #define UCB_TC_B_IN_ENA (1 << 14)
18052 #define UCB_TC_B_OUT_ENA (1 << 15)
18054 -#define UCB_AC_A 0x07
18055 -#define UCB_AC_B 0x08
18056 #define UCB_AC_B_LOOP (1 << 8)
18057 #define UCB_AC_B_MUTE (1 << 13)
18058 #define UCB_AC_B_IN_ENA (1 << 14)
18059 #define UCB_AC_B_OUT_ENA (1 << 15)
18061 -#define UCB_TS_CR 0x09
18062 #define UCB_TS_CR_TSMX_POW (1 << 0)
18063 #define UCB_TS_CR_TSPX_POW (1 << 1)
18064 #define UCB_TS_CR_TSMY_POW (1 << 2)
18066 #define UCB_TS_CR_TSPX_LOW (1 << 12)
18067 #define UCB_TS_CR_TSMX_LOW (1 << 13)
18069 -#define UCB_ADC_CR 0x0a
18070 #define UCB_ADC_SYNC_ENA (1 << 0)
18071 #define UCB_ADC_VREFBYP_CON (1 << 1)
18072 #define UCB_ADC_INP_TSPX (0 << 2)
18073 @@ -87,15 +116,13 @@
18074 #define UCB_ADC_START (1 << 7)
18075 #define UCB_ADC_ENA (1 << 15)
18077 -#define UCB_ADC_DATA 0x0b
18078 #define UCB_ADC_DAT_VAL (1 << 15)
18079 -#define UCB_ADC_DAT(x) (((x) & 0x7fe0) >> 5)
18081 -#define UCB_ID 0x0c
18082 #define UCB_ID_1200 0x1004
18083 #define UCB_ID_1300 0x1005
18084 +#define UCB_ID_1400 0x4304
18085 +#define UCB_ID_1400_BUGGY 0x4303 /* fake ID */
18087 -#define UCB_MODE 0x0d
18088 #define UCB_MODE_DYN_VFLAG_ENA (1 << 12)
18089 #define UCB_MODE_AUD_OFF_CAN (1 << 13)
18091 @@ -115,6 +142,9 @@
18093 struct semaphore adc_sem;
18094 spinlock_t io_lock;
18095 + wait_queue_head_t irq_wait;
18096 + struct completion complete;
18097 + struct task_struct *rtask;
18102 +++ linux-2.4.27/drivers/mmc/Config.in
18104 +mainmenu_option next_comment
18105 +comment 'MMC device drivers'
18106 +tristate 'Multi Media Card support' CONFIG_MMC
18107 +if [ "$CONFIG_MMC" = "y" -o "$CONFIG_MMC" = "m" ]; then
18108 + dep_tristate 'PXA250 MMC driver' CONFIG_MMC_PXA $CONFIG_MMC
18109 + dep_tristate 'MMC block driver' CONFIG_MMC_BLOCK $CONFIG_MMC
18110 + if [ "$CONFIG_MMC_BLOCK" = "y" -o "$CONFIG_MMC_BLOCK" = "m" ]; then
18111 + bool ' MMC partitioning support' CONFIG_MMC_PARTITIONS
18117 +++ linux-2.4.27/drivers/mmc/Makefile
18120 +# Makefile for MMC drivers
18123 +export-objs := mmc_core.o
18125 +obj-$(CONFIG_MMC) += mmc_core.o # mmc_test.o
18126 +obj-$(CONFIG_MMC_BLOCK) += mmc_block.o
18127 +obj-$(CONFIG_MMC_PXA) += mmc_pxa.o
18128 +# EXTRA_CFLAGS += -DCONFIG_MMC_DEBUG -DCONFIG_MMC_DEBUG_VERBOSE=2
18130 +O_TARGET := mmcdrivers.o
18132 +include $(TOPDIR)/Rules.make
18134 +++ linux-2.4.27/drivers/mmc/error.h
18137 + * linux/include/linux/mmc/error.h
18139 + * Author: Vladimir Shebordaev
18140 + * Copyright: MontaVista Software Inc.
18142 + * $Id: error.h,v 0.2 2002/07/11 16:27:01 ted Exp ted $
18144 + * This program is free software; you can redistribute it and/or modify
18145 + * it under the terms of the GNU General Public License version 2 as
18146 + * published by the Free Software Foundation.
18148 +#ifndef __MMC_ERROR_H__
18149 +#define __MMC_ERROR_H__
18151 +/* MMC protocol card error codes */
18152 +#define MMC_CARD_STATUS_OUT_OF_RANGE (1<<31)
18153 +#define MMC_CARD_STATUS_ADDRESS_ERROR (1<<30)
18154 +#define MMC_CARD_STATUS_BLOCK_LEN_ERROR (1<<29)
18155 +#define MMC_CARD_STATUS_ERASE_SEQ_ERROR (1<<28)
18156 +#define MMC_CARD_STATUS_ERASE_PARAM (1<<27)
18157 +#define MMC_CARD_STATUS_WP_VIOLATION (1<<26)
18158 +#define MMC_CARD_STATUS_CARD_IS_LOCKED (1<<25)
18159 +#define MMC_CARD_STATUS_LOCK_UNLOCK_FAILED (1<<24)
18160 +#define MMC_CARD_STATUS_COM_CRC_ERROR (1<<23)
18161 +#define MMC_CARD_STATUS_ILLEGAL_COMMAND (1<<22)
18162 +#define MMC_CARD_STATUS_CARD_ECC_FAILED (1<<21)
18163 +#define MMC_CARD_STATUS_CC_ERROR (1<<20)
18164 +#define MMC_CARD_STATUS_ERROR (1<<19)
18165 +#define MMC_CARD_STATUS_UNDERRUN (1<<18)
18166 +#define MMC_CARD_STATUS_OVERRUN (1<<17)
18167 +#define MMC_CARD_STATUS_CID_CSD_OVERWRITE (1<<16)
18168 +#define MMC_CARD_STATUS_ERASE_RESET (1<<13)
18170 +#define MMC_ERROR( fmt, args... ) printk( KERN_ERR "%s(): " fmt, __FUNCTION__, ##args )
18173 + * Error codes returned by MMC subsystem functions and
18174 + * error reporting function prototypes
18177 +/* controller errors */
18178 + MMC_ERROR_GENERIC = -10000,
18179 + MMC_ERROR_CRC_WRITE_ERROR = -10001,
18180 + MMC_ERROR_CRC_READ_ERROR = -10002,
18181 + MMC_ERROR_RES_CRC_ERROR = -10003,
18182 + MMC_ERROR_READ_TIME_OUT = -10004,
18183 + MMC_ERROR_TIME_OUT_RESPONSE = -10005,
18184 + MMC_ERROR_INVAL = -10006,
18185 +/* protocol errors reported in card status (R1 response) */
18186 + MMC_ERROR_OUT_OF_RANGE = -10007,
18187 + MMC_ERROR_ADDRESS_ERROR = -10008,
18188 + MMC_ERROR_BLOCK_LEN_ERROR = -10009,
18189 + MMC_ERROR_ERASE_SEQ_ERROR = -10010,
18190 + MMC_ERROR_ERASE_PARAM = -10011,
18191 + MMC_ERROR_WP_VIOLATION = -10012,
18192 + MMC_ERROR_CARD_IS_LOCKED = -10013,
18193 + MMC_ERROR_LOCK_UNLOCK_FAILED = -10014,
18194 + MMC_ERROR_COM_CRC_ERROR = -10015,
18195 + MMC_ERROR_ILLEGAL_COMMAND = -10016,
18196 + MMC_ERROR_CARD_ECC_FAILED = -10017,
18197 + MMC_ERROR_CC_ERROR = -10018,
18198 + MMC_ERROR_ERROR = -10019,
18199 + MMC_ERROR_UNDERRUN = -10020,
18200 + MMC_ERROR_OVERRUN = -10021,
18201 + MMC_ERROR_CID_CSD_OVERWRITE = -10022,
18202 + /* FIXME: incomplete */
18203 + MMC_ERROR_ERASE_RESET = -10025
18205 +#endif /* __MMC_ERROR_H__ */
18207 +++ linux-2.4.27/drivers/mmc/mmc.h
18210 + * linux/drivers/mmc/mmc.h
18212 + * Author: Vladimir Shebordaev
18213 + * Copyright: MontaVista Software Inc.
18215 + * $Id: mmc.h,v 0.3.1.8 2002/09/18 12:58:00 ted Exp ted $
18217 + * This program is free software; you can redistribute it and/or modify
18218 + * it under the terms of the GNU General Public License version 2 as
18219 + * published by the Free Software Foundation.
18221 +#ifndef __MMC_P_H__
18222 +#define __MMC_P_H__
18226 +#include <linux/types.h>
18227 +#include <linux/slab.h>
18229 +#include <linux/spinlock.h>
18231 +#ifdef CONFIG_PROC_FS
18232 +#include <linux/proc_fs.h>
18235 +#include <asm/semaphore.h>
18236 +#include <mmc/types.h>
18237 +#include <mmc/mmc.h>
18239 +#include "types.h"
18241 +#include "error.h"
18243 +#define MMC_CONTROLLERS_MAX (4)
18244 +#define MMC_CARDS_MAX (16)
18247 +#define MMC_TEST_MAJOR (240)
18248 +#define MMC_TEST_TRANSFER_MODE_DEFAULT MMC_TRANSFER_MODE_BLOCK_SINGLE
18250 +/* block device */
18251 +#define MMC_BLOCK_MAJOR (241) /* FIXME: MMC_MAJOR */
18252 +#define MMC_BLOCK_DEVICES_MAX (1<<MINORBITS) /* FIXME */
18253 +#define MMC_BLOCK_SECT_SIZE (512) /* FIXME */
18254 +#define MMC_BLOCK_PARTNBITS (3)
18256 +/* Device minor number encoding:
18258 + * [5:3] - card slot number
18259 + * [2:0] - partition number
18261 +#define MMC_MINOR_HOST_SHIFT (6)
18262 +#define MMC_MINOR_CARD_MASK (0x07)
18265 + * MMC controller abstraction
18267 +enum _mmc_controller_state {
18268 + MMC_CONTROLLER_ABSENT = 0,
18269 + MMC_CONTROLLER_FOUND,
18270 + MMC_CONTROLLER_INITIALIZED,
18271 + MMC_CONTROLLER_UNPLUGGED
18279 +enum _mmc_buftype {
18284 +struct _mmc_data_transfer_req_rec {
18285 + mmc_dir_t cmd; /* read or write operation requested */
18286 + mmc_transfer_mode_t mode; /* requested data transfer mode */
18287 + mmc_buftype_t type; /* whether supplied buffer resides in user or kernel space */
18288 + char *buf; /* poiner to the caller's buffer */
18289 + ssize_t cnt; /* number of bytes to transfer */
18290 + loff_t addr; /* card address */
18291 + ssize_t blksz; /* block size as for CSD[READ_BL_LEN] or CSD[WRITE_BL_LEN] */
18292 + ssize_t nob; /* number of blocks to transfer */
18295 +struct _mmc_controller_tmpl_rec {
18296 + struct module *owner; /* driver module */
18299 + const ssize_t block_size_max; /* max acceptable block size */
18300 + const ssize_t nob_max; /* max blocks per one data transfer */
18302 + int (*probe)( mmc_controller_t ); /* hardware probe */
18303 + int (*init)( mmc_controller_t ); /* initialize, e.g. request irq, DMA and allocate buffers */
18304 + void (*remove)( mmc_controller_t ); /* free resources */
18305 +#if 0 /* CONFIG_HOTPLUG */
18306 + void (*attach)( void ); /|* controller hotplug callbacks *|/
18307 + void (*detach)( void );
18310 + int (*suspend)( mmc_controller_t ); /* power management callbacks */
18311 + void (*resume)( mmc_controller_t );
18314 +/* MMC protocol macros, v3.4, p.120 */
18315 + int (*init_card_stack)( mmc_controller_t );
18316 + int (*update_acq)( mmc_controller_t ); /* update card stack management data */
18317 + int (*single_card_acq)( mmc_controller_t );
18318 + int (*check_card_stack)( mmc_controller_t );
18319 + int (*setup_card)( mmc_controller_t, mmc_card_t );
18320 + int (*stream_read)( mmc_controller_t, mmc_data_transfer_req_t );
18321 + int (*read_block)( mmc_controller_t, mmc_data_transfer_req_t );
18322 + int (*read_mblock)( mmc_controller_t, mmc_data_transfer_req_t );
18323 + int (*stream_write)( mmc_controller_t, mmc_data_transfer_req_t );
18324 + int (*write_block)( mmc_controller_t, mmc_data_transfer_req_t );
18325 + int (*write_mblock)( mmc_controller_t, mmc_data_transfer_req_t );
18327 + int (*sg_io)( mmc_controller_t, sg_list_t );
18330 + * 1) erase group macros
18331 + * int (*erase_group)( mmc_controller_t, mmc_erase_group_info_t );
18332 + * 2) write protection macros;
18333 + * int (*set_write_prot)( mmc_controller_t, mmc_write_protection_info_t )
18334 + * 3) lock/password management macros;
18338 +#ifndef MMC_CTRLR_BLKSZ_DEFAULT
18339 +#define MMC_CTRLR_BLKSZ_DEFAULT (512)
18342 +#ifndef MMC_CTRLR_NOB_DEFAULT
18343 +#define MMC_CTRLR_NOB_DEFAULT (1)
18346 +struct _mmc_card_rec {
18347 +/* public card interface */
18348 + struct _mmc_card_info_rec info; /* see <linux/mmc/mmc.h> */
18350 +/* private kernel specific data */
18351 + mmc_state_t state; /* card's state as per last operation */
18352 + mmc_card_t next; /* link to the stack */
18353 + mmc_controller_t ctrlr; /* back reference to the controller */
18354 + int usage; /* reference count */
18355 + int slot; /* card's number for device reference */
18356 +/* TODO: async I/O queue */
18357 +#ifdef CONFIG_PROC_FS
18358 + proc_dir_entry_t proc;
18359 + char proc_name[16];
18361 + unsigned long card_data[0] /* card specific data */
18362 + __attribute__((aligned (sizeof(unsigned long))));
18365 +struct _mmc_card_stack_rec {
18366 + mmc_card_t first; /* first card on the stack */
18367 + mmc_card_t last; /* last card on the stack */
18368 + mmc_card_t selected; /* currently selected card */
18372 +struct _mmc_controller_rec {
18373 + mmc_controller_state_t state; /* found, initialized, unplugged... */
18374 + int usage; /* reference count */
18375 + int slot; /* host's number for device reference */
18376 + semaphore_t io_sem; /* I/O serialization */
18377 + rwsemaphore_t update_sem; /* card stack check/update serialization */
18379 + mmc_controller_tmpl_t tmpl; /* methods provided by the driver */
18380 + mmc_card_stack_rec_t stack; /* card stack management data */
18382 + u32 rca_next; /* next RCA to assign */
18383 + int slot_next; /* next slot number to assign */
18384 +#ifdef CONFIG_PROC_FS
18385 + char proc_name[16];
18386 + proc_dir_entry_t proc;
18388 + unsigned long host_data[0] /* driver can request some extra space */
18389 + __attribute__((aligned (sizeof(unsigned long))));
18393 + * MMC core interface
18395 +enum _mmc_reg_type {
18396 + MMC_REG_TYPE_USER = 1,
18397 + MMC_REG_TYPE_HOST,
18398 + MMC_REG_TYPE_CARD
18401 +struct _mmc_notifier_rec {
18402 + struct _mmc_notifier_rec *next;
18403 + mmc_notifier_fn_t add;
18404 + mmc_notifier_fn_t remove;
18407 +enum _mmc_response {
18408 + MMC_NORESPONSE = 1,
18417 +#ifndef __MMC_CORE_IMPLEMENTATION__
18418 +#define EXTERN extern
18420 +#define EXTERN /* empty */
18423 +EXTERN void *mmc_register( mmc_reg_type_t, void *, size_t );
18424 +EXTERN void mmc_unregister( mmc_reg_type_t, void * );
18425 +EXTERN int mmc_update_card_stack( int );
18427 +EXTERN mmc_card_t mmc_get_card( int, int );/* get reference to the card */
18428 +EXTERN void mmc_put_card( mmc_card_t ); /* release card reference */
18430 +EXTERN int mmc_notify_add( mmc_card_t ); /* user notification */
18431 +EXTERN int mmc_notify_remove( mmc_card_t );
18433 +EXTERN ssize_t mmc_read( mmc_card_t, mmc_transfer_mode_t, char *, size_t, loff_t * ); /* generic read */
18434 +EXTERN ssize_t mmc_write( mmc_card_t, mmc_transfer_mode_t, const char *, size_t, loff_t * ); /* generic write */
18435 +EXTERN int mmc_ioctl( mmc_card_t, unsigned int, unsigned long ); /* generic ioctl */
18437 + * TODO: [?m.b. ioctl()] to erase, lock and write protect
18439 + * 2) mmc_write_prot
18444 +static inline mmc_card_t __mmc_card_alloc( size_t extra )
18446 + mmc_card_t ret = kmalloc( sizeof( mmc_card_rec_t ) + extra, GFP_KERNEL );
18449 + memset( ret, 0, sizeof( mmc_card_rec_t ) + extra );
18455 +static inline void __mmc_card_free( mmc_card_t card )
18462 +static inline mmc_card_stack_t __mmc_card_stack_init( mmc_card_stack_t stack )
18464 + mmc_card_stack_t ret = NULL;
18466 + memset( stack, 0, sizeof( mmc_card_stack_rec_t ) );
18472 +static inline mmc_card_stack_t __mmc_card_stack_add( mmc_card_stack_t stack, mmc_card_t card )
18474 + mmc_card_stack_t ret = NULL;
18476 + if ( stack && card ) {
18477 + card->next = NULL;
18479 + if ( stack->first ) {
18480 + stack->last->next = card;
18481 + stack->last = card;
18483 + stack->first = stack->last = card;
18491 +static inline mmc_card_stack_t __mmc_card_stack_remove( mmc_card_stack_t stack, mmc_card_t card )
18493 + mmc_card_stack_t ret = NULL;
18494 + register mmc_card_t prev;
18495 + int found = FALSE;
18497 + if ( !stack || !card )
18500 + if ( stack->ncards > 0 ) {
18501 + if ( stack->first == card ) {
18502 + stack->first = stack->first->next;
18503 + if ( stack->last == card )
18504 + stack->last = stack->last->next;
18507 + for ( prev = stack->first; prev; prev = prev->next )
18508 + if ( prev->next == card ) {
18513 + if ( prev->next == stack->last )
18514 + stack->last = prev->next;
18515 + prev->next = prev->next->next;
18527 +static inline void __mmc_card_stack_free( mmc_card_stack_t stack )
18529 + mmc_card_t card, next;
18531 + if ( stack && (stack->ncards > 0) ) {
18532 + card = stack->first;
18534 + next = card->next;
18538 + __mmc_card_stack_init( stack );
18542 +static inline int __mmc_card_stack_foreach( mmc_card_stack_t stack, mmc_notifier_fn_t fn, int unplugged_also )
18545 + register mmc_card_t card = NULL;
18547 + if ( stack && fn ) {
18548 + for ( card = stack->first; card; card = card->next )
18549 + if ( (card->state != MMC_CARD_STATE_UNPLUGGED)
18550 + || unplugged_also )
18551 + if ( fn( card ) ) {
18552 + ret = -card->slot;
18561 + * Debugging macros
18563 +#ifdef CONFIG_MMC_DEBUG
18565 +#define MMC_DEBUG_LEVEL0 (0) /* major */
18566 +#define MMC_DEBUG_LEVEL1 (1)
18567 +#define MMC_DEBUG_LEVEL2 (2) /* device */
18568 +#define MMC_DEBUG_LEVEL3 (3) /* protocol */
18569 +#define MMC_DEBUG_LEVEL4 (4) /* everything */
18571 +#define MMC_DEBUG(n, args...) \
18572 +if (n <= CONFIG_MMC_DEBUG_VERBOSE) { \
18573 + printk(KERN_INFO __FUNCTION__ "(): " args); \
18575 +#define __ENTER0( ) MMC_DEBUG( MMC_DEBUG_LEVEL2, "entry\n" );
18576 +#define __LEAVE0( ) MMC_DEBUG( MMC_DEBUG_LEVEL2, "exit\n" );
18577 +#define __ENTER( format, args... ) MMC_DEBUG( MMC_DEBUG_LEVEL2, "entry: " format "\n", args );
18578 +#define __LEAVE( format, args... ) MMC_DEBUG( MMC_DEBUG_LEVEL2, "exit: " format "\n", args );
18580 +#define MMC_DUMP_CSD( card ) MMC_DEBUG( MMC_DEBUG_LEVEL3, \
18581 +"CSD register:\n" \
18582 +" csd_structure=%u\n" \
18583 +" spec_vers=%u\n" \
18586 +" tran_speed=%x\n" \
18588 +" read_bl_len=%u\n" \
18589 +" read_bl_partial=%u\n" \
18590 +" write_blk_misalign=%u\n" \
18591 +" read_blk_misalign=%u\n" \
18594 +" vdd_r_curr_min=%u\n" \
18595 +" vdd_r_curr_max=%u\n" \
18596 +" vdd_w_curr_min=%u\n" \
18597 +" vdd_w_curr_max=%u\n" \
18598 +" c_size_mult=%u\n" \
18599 +" erase_grp_size=%u\n" \
18600 +" erase_grp_mult=%u\n" \
18601 +" wp_grp_size=%u\n" \
18602 +" wp_grp_enable=%u\n" \
18603 +" default_ecc=%u\n" \
18604 +" r2w_factor=%u\n" \
18605 +" write_bl_len=%u\n" \
18606 +" write_bl_partial=%u\n" \
18607 +" content_prot_app=%u\n" \
18608 +" file_format_grp=%u\n" \
18610 +" perm_write_protect=%d\n" \
18611 +" tmp_write_protect=%d\n" \
18612 +" file_format=%d\n" \
18614 +card->info.csd.csd_structure, \
18615 +card->info.csd.spec_vers, \
18616 +card->info.csd.taac, \
18617 +card->info.csd.nsac, \
18618 +card->info.csd.tran_speed, \
18619 +card->info.csd.ccc, \
18620 +card->info.csd.read_bl_len, \
18621 +card->info.csd.read_bl_partial, \
18622 +card->info.csd.write_blk_misalign, \
18623 +card->info.csd.read_blk_misalign, \
18624 +card->info.csd.dsr_imp, \
18625 +card->info.csd.c_size, \
18626 +card->info.csd.vdd_r_curr_min, \
18627 +card->info.csd.vdd_r_curr_max, \
18628 +card->info.csd.vdd_w_curr_min, \
18629 +card->info.csd.vdd_w_curr_max, \
18630 +card->info.csd.c_size_mult, \
18631 +card->info.csd.erase_grp_size, \
18632 +card->info.csd.erase_grp_mult, \
18633 +card->info.csd.wp_grp_size, \
18634 +card->info.csd.wp_grp_enable, \
18635 +card->info.csd.default_ecc, \
18636 +card->info.csd.r2w_factor, \
18637 +card->info.csd.write_bl_len, \
18638 +card->info.csd.write_bl_partial, \
18639 +card->info.csd.content_prot_app, \
18640 +card->info.csd.file_format_grp, \
18641 +card->info.csd.copy, \
18642 +card->info.csd.perm_write_protect, \
18643 +card->info.csd.tmp_write_protect, \
18644 +card->info.csd.file_format, \
18645 +card->info.csd.ecc );
18647 +#else /* CONFIG_MMC_DEBUG */
18648 +#define MMC_DEBUG(n, args...) /* empty */
18649 +#define __ENTER0( ) /* empty */
18650 +#define __LEAVE0( ) /* empty */
18651 +#define __ENTER( args... ) /* empty */
18652 +#define __LEAVE( args... ) /* empty */
18653 +#define MMC_DUMP_CSD( card ) /* empty */
18654 +#endif /* CONFIG_MMC_DEBUG */
18657 + * Miscellaneous defines
18659 +#ifndef MMC_DUMP_R1
18660 +#define MMC_DUMP_R1( ctrlr ) /* empty */
18662 +#ifndef MMC_DUMP_R2
18663 +#define MMC_DUMP_R2( ctrlr ) /* empty */
18665 +#ifndef MMC_DUMP_R3
18666 +#define MMC_DUMP_R3( ctrlr ) /* empty */
18669 +#endif /* __KERNEL__ */
18671 +#endif /* __MMC_P_H__ */
18673 +++ linux-2.4.27/drivers/mmc/mmc_block.c
18676 + * linux/drivers/mmc/mmc_block.c
18677 + * driver for the block device on the MMC card
18679 + * Author: Vladimir Shebordaev
18680 + * Copyright: MontaVista Software Inc.
18682 + * $Id: mmc_block.c,v 0.3.1.16 2002/09/27 17:36:09 ted Exp ted $
18684 + * This program is free software; you can redistribute it and/or modify
18685 + * it under the terms of the GNU General Public License version 2 as
18686 + * published by the Free Software Foundation.
18688 +#include <linux/version.h>
18689 +#include <linux/config.h>
18690 +#include <linux/types.h>
18691 +#include <linux/module.h>
18692 +#include <linux/init.h>
18693 +#include <linux/devfs_fs_kernel.h>
18694 +#include <linux/kernel.h>
18695 +#include <linux/slab.h>
18696 +#include <linux/hdreg.h>
18697 +#include <linux/blkpg.h>
18698 +#include <asm/uaccess.h>
18700 +#include <mmc/types.h>
18701 +#include <mmc/mmc.h>
18703 +#include "types.h"
18705 +#include "error.h"
18707 +#define MAJOR_NR MMC_BLOCK_MAJOR
18708 +#define MAJOR_NAME "mmc"
18709 +#define DEVICE_NAME "mmc_block"
18710 +#define DEVICE_REQUEST mmc_block_request
18711 +#define DEVICE_NR(device) (device)
18712 +#define DEVICE_ON(device)
18713 +#define DEVICE_OFF(device)
18714 +#define DEVICE_NO_RANDOM
18715 +#include <linux/blk.h>
18716 +/* for old kernels... */
18717 +#ifndef QUEUE_EMPTY
18718 +#define QUEUE_EMPTY (!CURRENT)
18720 +#if LINUX_VERSION_CODE < 0x20300
18721 +#define QUEUE_PLUGGED (blk_dev[MAJOR_NR].plug_tq.sync)
18723 +#define QUEUE_PLUGGED (blk_dev[MAJOR_NR].request_queue.plugged)
18727 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,14)
18728 +#define BLK_INC_USE_COUNT MOD_INC_USE_COUNT
18729 +#define BLK_DEC_USE_COUNT MOD_DEC_USE_COUNT
18731 +#define BLK_INC_USE_COUNT do {} while(0)
18732 +#define BLK_DEC_USE_COUNT do {} while(0)
18735 +#define MMC_BLOCK_RAW_DEVICE( device ) ((device>>MMC_BLOCK_PARTNBITS)<<MMC_BLOCK_PARTNBITS)
18736 +#define MMC_BLOCK_MKDEV( host, slot ) \
18737 + MKDEV( MMC_BLOCK_MAJOR, \
18738 + (host<<MMC_MINOR_HOST_SHIFT) \
18739 + | (slot<<MMC_BLOCK_PARTNBITS) )
18741 +typedef struct _mmc_block_device mmc_block_device_rec_t;
18742 +typedef struct _mmc_block_device *mmc_block_device_t;
18744 +struct _mmc_block_device {
18753 +static int mmc_block_blk_sizes[1<<MINORBITS];
18754 +static int mmc_block_blk_blksizes[1<<MINORBITS];
18755 +static int mmc_block_hardsect_sizes[1<<MINORBITS];
18756 +static struct hd_struct mmc_block_partitions[1<<MINORBITS];
18758 +/* Accessed under device table lock */
18759 +static gendisk_rec_t mmc_block_gendisk = {
18760 + major: MMC_BLOCK_MAJOR,
18761 + major_name: MAJOR_NAME,
18762 + minor_shift: MMC_BLOCK_PARTNBITS,
18763 + max_p: (1<<MMC_BLOCK_PARTNBITS),
18764 + sizes: mmc_block_blk_sizes,
18765 + part: mmc_block_partitions
18768 +static mmc_block_device_rec_t mmc_block_device[1<<MINORBITS];
18769 +static rwsemaphore_t mmc_block_device_sem;
18771 +static inline void __mmc_block_rdlock_devices( void )
18773 + down_read( &mmc_block_device_sem );
18776 +static inline void __mmc_block_rdunlock_devices( void )
18778 + up_read( &mmc_block_device_sem );
18781 +static inline void __mmc_block_wrlock_devices( void )
18783 + down_write( &mmc_block_device_sem );
18786 +static inline void __mmc_block_wrunlock_devices( void )
18788 + up_write( &mmc_block_device_sem );
18791 +static inline void __mmc_block_lock_device( kdev_t rdev )
18793 + __mmc_block_rdlock_devices();
18794 + down( &mmc_block_device[MINOR( rdev )].sem );
18797 +static inline void __mmc_block_unlock_device( kdev_t rdev )
18799 + up( &mmc_block_device[MINOR( rdev )].sem );
18800 + __mmc_block_rdunlock_devices();
18803 +static inline void __mmc_block_device_init( int minor )
18805 + mmc_block_device_t dev = &mmc_block_device[minor];
18808 + dev->card = NULL;
18809 + dev->host = minor >> MMC_MINOR_HOST_SHIFT;
18810 + dev->slot = (minor & MMC_MINOR_CARD_MASK)>>MMC_BLOCK_PARTNBITS;
18811 + dev->rdev = MKDEV( MMC_BLOCK_MAJOR, minor );
18814 +static inline int __mmc_block_validate_device( kdev_t rdev )
18817 + int minor = MINOR( rdev );
18819 + if ( mmc_block_device[minor].card
18820 + && (mmc_block_gendisk.part[minor].nr_sects > 0) )
18826 +static inline int __mmc_block_invalidate_card( mmc_card_t card, int invalidate )
18832 + __ENTER( "card = 0x%p", card );
18834 + if ( card && card->ctrlr ) {
18837 + start = MMC_BLOCK_MKDEV( card->ctrlr->slot, card->slot );
18838 + minor = MINOR( start );
18840 + __mmc_block_wrlock_devices();
18841 + for ( i = mmc_block_gendisk.max_p - 1; i >= 0; --i ) {
18842 + if ( invalidate )
18843 + invalidate_device( start + i, 0 );
18845 + __mmc_block_device_init( minor + i );
18847 + mmc_block_gendisk.part[minor + i].nr_sects = 0;
18848 + mmc_block_gendisk.part[minor + i].start_sect = 0;
18850 + __mmc_block_wrunlock_devices();
18853 + __LEAVE( "ret=%d", ret );
18857 +static inline int mmc_block_invalidate_card( int host, int slot, int invalidate )
18863 + __ENTER( "host=%d slot=%d", host, slot );
18865 + if ( (host >= 0) && (slot >= 0) ) {
18867 + mmc_card_t card = NULL;
18869 + start = MMC_BLOCK_MKDEV( host, slot );
18870 + minor = MINOR( start );
18872 + __mmc_block_wrlock_devices();
18873 + for ( i = mmc_block_gendisk.max_p - 1; i >= 0; --i ) {
18875 + card = mmc_block_device[minor + i].card;
18877 + if ( invalidate )
18878 + invalidate_device( start + i, 0 );
18880 + __mmc_block_device_init( minor + i );
18882 + mmc_block_gendisk.part[minor + i].nr_sects = 0;
18883 + mmc_block_gendisk.part[minor + i].start_sect = 0;
18886 + mmc_put_card( card );
18887 + __mmc_block_wrunlock_devices();
18890 + __LEAVE( "ret=%d", ret );
18894 +/* Get device reference locked for writing */
18895 +static inline mmc_block_device_t __mmc_block_get_device( kdev_t rdev )
18897 + mmc_block_device_t ret = NULL;
18898 + u8 minor = MINOR( rdev );
18899 + int host_no, card_no;
18901 + __ENTER( "rdev=%x:%x", MAJOR( rdev ), MINOR( rdev ) );
18903 + host_no = minor >> MMC_MINOR_HOST_SHIFT;
18904 + if ( host_no >= MMC_CONTROLLERS_MAX )
18907 + card_no = (minor & MMC_MINOR_CARD_MASK)>>MMC_BLOCK_PARTNBITS;
18908 + if ( card_no >= MMC_CARDS_MAX )
18911 + __mmc_block_lock_device( rdev );
18912 + if ( __mmc_block_validate_device( rdev ) ) {
18913 + __mmc_block_unlock_device( rdev );
18917 + ret = &mmc_block_device[minor];
18918 + MMC_DEBUG( MMC_DEBUG_LEVEL2, "(%x:%x) card=%p, dusage=%d\n",
18919 + MAJOR( ret->rdev ), MINOR( ret->rdev ),
18920 + ret->card, ret->usage );
18922 + __LEAVE( "ret=0x%p", ret );
18926 +/* Unlocks the device */
18927 +static inline void __mmc_block_put_device( mmc_block_device_t dev )
18932 + MMC_DEBUG( MMC_DEBUG_LEVEL2, "(%x:%x) card=%p, dusage=%d\n",
18933 + MAJOR( dev->rdev ), MINOR( dev->rdev ),
18934 + dev->card, dev->usage );
18935 + __mmc_block_unlock_device( dev->rdev );
18941 +/* Atomically increases use count of the valid device */
18942 +static inline mmc_block_device_t mmc_block_get_device( kdev_t rdev )
18944 + mmc_block_device_t ret = NULL;
18948 + ret = __mmc_block_get_device( rdev );
18953 + __mmc_block_put_device( ret );
18955 + __LEAVE( "ret=0x%p dusage=%d card=0x%p cusage=%d",
18956 + ret, ret ? ret->usage : -1,
18957 + ret ? ret->card : NULL,
18958 + ret ? (ret->card ? ret->card->usage : -1) : -1 );
18962 +/* Check is there references to the card */
18963 +static inline int __mmc_block_check_card( kdev_t rdev )
18966 + int start = MINOR( MMC_BLOCK_RAW_DEVICE( rdev ) );
18969 + for ( i = 0; i < mmc_block_gendisk.max_p; i++ )
18970 + if ( mmc_block_device[start + i].usage > 0 ) {
18978 +/* Atomically decreases device use count */
18979 +static inline void mmc_block_put_device( mmc_block_device_t dev )
18984 + int invalidate = FALSE;
18986 + __mmc_block_get_device( dev->rdev );
18987 + if ( dev->usage > 0 )
18990 + if ( dev->usage ) {
18991 + __mmc_block_put_device( dev );
18996 + mmc_card_t card = NULL;
18998 + invalidate = __mmc_block_check_card( dev->rdev );
18999 + if ( invalidate ) {
19000 + host = dev->card->ctrlr->slot;
19001 + slot = dev->card->slot;
19003 + if ( dev->card ) {
19004 + card = dev->card;
19005 + mmc_put_card( dev->card );
19006 + dev->card = NULL;
19009 + __mmc_block_put_device( dev );
19011 + if ( invalidate )
19012 + __mmc_block_invalidate_card( card, TRUE );
19020 +static int mmc_block_open( struct inode *inode, struct file *file )
19022 + int ret = -ENODEV;
19023 + mmc_block_device_t dev = NULL;
19027 + if ( !inode || !file )
19030 + BLK_INC_USE_COUNT;
19032 + check_disk_change( inode->i_rdev );
19034 + dev = mmc_block_get_device( inode->i_rdev );
19038 + dev = __mmc_block_get_device( inode->i_rdev );
19042 + if ( file->f_mode & FMODE_WRITE ) { /* FIXME */
19043 + if ( dev->usage > 1 ) {
19045 + __mmc_block_put_device( dev );
19046 + mmc_block_put_device( dev );
19051 + __mmc_block_put_device( dev );
19054 + file->private_data = dev;
19059 + BLK_DEC_USE_COUNT;
19061 + __LEAVE( "ret=%d", ret );
19065 +static int mmc_block_release( struct inode *inode, struct file *file )
19067 + int ret = -EINVAL;
19068 + mmc_block_device_t dev = NULL;
19070 + __ENTER( "inode=0x%p file=0x%p rdev=(%x:%x)", inode, file,
19071 + inode ? MAJOR( inode->i_rdev ) : 0xff,
19072 + inode ? MINOR( inode->i_rdev ) : 0xff );
19074 + if ( !file && !inode )
19078 + dev = file->private_data;
19080 + dev = __mmc_block_get_device( inode->i_rdev );
19083 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "invalid device\n" );
19088 + mmc_block_put_device( dev );
19089 + file->private_data = NULL;
19092 + int invalidate = FALSE;
19094 + if ( dev->usage > 0 )
19097 + if ( dev->usage ) {
19098 + __mmc_block_put_device( dev );
19103 + mmc_card_t card = NULL;
19105 + invalidate = __mmc_block_check_card( dev->rdev );
19106 + if ( invalidate ) {
19107 + host = dev->card->ctrlr->slot;
19108 + slot = dev->card->slot;
19110 + if ( dev->card ) {
19111 + card = dev->card;
19112 + mmc_put_card( dev->card );
19113 + dev->card = NULL;
19116 + __mmc_block_put_device( dev );
19118 + if ( invalidate )
19119 + __mmc_block_invalidate_card( card, TRUE );
19125 + BLK_DEC_USE_COUNT;
19132 +static int mmc_block_check_disk_change( kdev_t rdev )
19136 + mmc_block_device_t dev = &mmc_block_device[MINOR( rdev )];
19138 + __mmc_block_lock_device( rdev );
19139 + if ( !dev->card )
19141 + __mmc_block_unlock_device( rdev );
19148 +static int mmc_block_revalidate( kdev_t rdev )
19152 + mmc_block_device_t dev;
19153 + kdev_t start = MMC_BLOCK_RAW_DEVICE( rdev );
19154 + int minor = MINOR( start );
19160 + (void)mmc_update_card_stack( MINOR( start )>>MMC_MINOR_HOST_SHIFT );
19162 + __mmc_block_wrlock_devices();
19164 + dev = &mmc_block_device[minor];
19165 + host = dev->host;
19166 + slot = dev->slot;
19168 + if ( dev->card ) { /* card has not been changed actually */
19169 + __mmc_block_wrunlock_devices();
19173 + card = mmc_get_card( host, slot );
19175 + MMC_DEBUG( MMC_DEBUG_LEVEL2, "failed to get card: "
19176 + "host=%d, slot=%d\n", host, slot );
19177 + __mmc_block_wrunlock_devices();
19180 + dev->card = card;
19182 + __mmc_block_wrunlock_devices();
19184 + __mmc_block_rdlock_devices(); /* handle the request for sector 0 */
19185 + grok_partitions( &mmc_block_gendisk, MINOR( start ),
19186 + mmc_block_gendisk.max_p,
19187 + card->info.capacity>>9 /* sectors */
19189 + __mmc_block_rdunlock_devices();
19191 + __mmc_block_wrlock_devices();
19192 + for ( i = start + mmc_block_gendisk.max_p - 1; i >= 0; --i ) {
19193 + int minor = MINOR( i );
19195 + dev = &mmc_block_device[minor];
19196 + if ( mmc_block_gendisk.part[minor].nr_sects > 0 )
19197 + dev->card = card;
19199 + __mmc_block_wrunlock_devices();
19202 + __LEAVE( "ret=%d", ret );
19206 +static void mmc_block_handle_request( void )
19208 + struct request *request;
19209 + mmc_block_device_t dev;
19213 + unsigned int result = 0;
19219 + request = CURRENT;
19220 + spin_unlock_irq( &io_request_lock );
19222 + minor = MINOR( request->rq_dev );
19223 + dev = __mmc_block_get_device( request->rq_dev );
19225 + MMC_DEBUG( MMC_DEBUG_LEVEL2, "invalid device (%x:%x)\n",
19226 + MAJOR( request->rq_dev ), minor );
19231 + card = dev->card;
19232 + (void)__mmc_block_put_device( dev );
19234 + MMC_DEBUG( MMC_DEBUG_LEVEL2,
19235 +// printk( KERN_INFO __FUNCTION__"(): "
19236 + "request %p: cmd %i sec %li (nr. %li)\n",
19237 + CURRENT, CURRENT->cmd, CURRENT->sector,
19238 + CURRENT->current_nr_sectors );
19240 + if ( request->current_nr_sectors >
19241 + mmc_block_gendisk.part[minor].nr_sects )
19244 + // Handle the request
19245 + // TODO: handle clusterred requests in multiple block transfer mode
19246 + buf = request->buffer;
19247 + pos = (mmc_block_gendisk.part[minor].start_sect +
19248 + request->sector) * MMC_BLOCK_SECT_SIZE;
19250 + switch ( request->cmd )
19256 + ret = mmc_read( card,
19257 + (request->current_nr_sectors > 1) ?
19258 + MMC_TRANSFER_MODE_BLOCK_MULTIPLE :
19259 + MMC_TRANSFER_MODE_BLOCK_SINGLE,
19261 + request->current_nr_sectors
19262 + * MMC_BLOCK_SECT_SIZE, /* FIXME */
19269 + i < request->current_nr_sectors;
19271 + ret = mmc_read( card,
19272 + MMC_TRANSFER_MODE_BLOCK_SINGLE,
19274 + MMC_BLOCK_SECT_SIZE, /* FIXME */
19286 + // TODO: Read only device
19288 + ret = mmc_write( card,
19289 + (request->current_nr_sectors > 1) ?
19290 + MMC_TRANSFER_MODE_BLOCK_MULTIPLE :
19291 + MMC_TRANSFER_MODE_BLOCK_SINGLE,
19293 + request->current_nr_sectors
19294 + * MMC_BLOCK_SECT_SIZE, /* FIXME */
19301 + i < request->current_nr_sectors;
19303 + ret = mmc_write( card,
19304 + MMC_TRANSFER_MODE_BLOCK_SINGLE,
19306 + MMC_BLOCK_SECT_SIZE, /* FIXME */
19319 + __LEAVE( "result=%d", result );
19320 + spin_lock_irq( &io_request_lock );
19321 + end_request( result );
19325 +static volatile int leaving = 0;
19326 +static DECLARE_MUTEX_LOCKED( thread_sem );
19327 +static DECLARE_WAIT_QUEUE_HEAD( thr_wq );
19328 +static pid_t thr_id = -1;
19330 +int mmc_block_thread( void *arg )
19332 + struct task_struct *task = current;
19333 + DECLARE_WAITQUEUE(wait, task);
19337 + task->session = 1;
19339 + task->flags |= PF_MEMALLOC;
19340 + strcpy( task->comm, "mmcblockd" );
19341 + task->tty = NULL;
19342 + spin_lock_irq( &task->sigmask_lock );
19343 + sigfillset( &task->blocked );
19344 + recalc_sigpending( task );
19345 + spin_unlock_irq( &task->sigmask_lock );
19347 + exit_files( task );
19348 + exit_sighand( task );
19351 + while ( !leaving ) {
19352 + add_wait_queue( &thr_wq, &wait);
19353 + set_current_state( TASK_INTERRUPTIBLE );
19354 + spin_lock_irq( &io_request_lock );
19355 + if ( QUEUE_EMPTY || QUEUE_PLUGGED ) {
19356 + spin_unlock_irq( &io_request_lock );
19358 + remove_wait_queue( &thr_wq, &wait );
19360 + remove_wait_queue( &thr_wq, &wait );
19361 + set_current_state( TASK_RUNNING );
19362 + mmc_block_handle_request(); /* handle the request */
19363 + spin_unlock_irq( &io_request_lock );
19367 + up( &thread_sem );
19373 +#if LINUX_VERSION_CODE < 0x20300
19374 +#define RQFUNC_ARG void
19376 +#define RQFUNC_ARG request_queue_t *q
19379 +static void mmc_block_request( RQFUNC_ARG )
19381 + wake_up( &thr_wq );
19384 +static int mmc_block_ioctl( struct inode * inode, struct file * file,
19385 + unsigned int cmd, unsigned long arg )
19387 + int ret = -ENODEV;
19388 + mmc_block_device_t dev;
19393 + if ( !inode || !file ) {
19397 + minor = MINOR( inode->i_rdev );
19399 + dev = __mmc_block_get_device( inode->i_rdev );
19401 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "invalid device\n" );
19405 + card = dev->card;
19406 + __mmc_block_put_device( dev );
19409 + case BLKGETSIZE: /* Return device size */
19411 + unsigned long value;
19413 + __mmc_block_rdlock_devices();
19414 + value = mmc_block_gendisk.part[minor].nr_sects;
19415 + __mmc_block_rdunlock_devices();
19417 + if ( put_user( value, (unsigned long *) arg) ) {
19424 +#ifdef BLKGETSIZE64
19425 + case BLKGETSIZE64:
19427 + unsigned long value;
19429 + __mmc_block_rdlock_devices();
19430 + value = mmc_block_gendisk.part[minor].nr_sects;
19431 + __mmc_block_rdunlock_devices();
19433 + if ( put_user( (u64)value, (u64 *) arg) ) {
19441 + case HDIO_GETGEO:
19443 + struct hd_geometry geo;
19445 + ret = !access_ok( VERIFY_WRITE, arg, sizeof( geo ) );
19454 + __mmc_block_rdlock_devices();
19455 + geo.cylinders = mmc_block_gendisk.part[minor].nr_sects;
19456 + geo.start = mmc_block_gendisk.part[minor].start_sect;
19457 + __mmc_block_rdunlock_devices();
19459 + if ( copy_to_user( (int *)arg, &geo, sizeof( geo ) ) ) {
19467 + if ( !capable( CAP_SYS_ADMIN ) ) {
19471 + (void)mmc_block_revalidate( inode->i_rdev );
19475 + ret = blk_ioctl( inode->i_rdev, cmd, arg );
19482 + __LEAVE( "ret=%d", ret );
19486 +#if LINUX_VERSION_CODE < 0x20326
19487 +static struct file_operations mmc_block_fops =
19489 + open: mmc_block_open,
19490 + ioctl: mmc_block_ioctl,
19491 + release: mmc_block_release,
19492 + check_media_change: mmc_block_check_disk_change,
19493 + revalidate: mmc_block_revalidate,
19494 + read: block_read,
19495 + write: block_write
19498 +static struct block_device_operations mmc_block_fops =
19500 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,14)
19501 + owner: THIS_MODULE,
19503 + open: mmc_block_open,
19504 + release: mmc_block_release,
19505 + ioctl: mmc_block_ioctl,
19506 + check_media_change: mmc_block_check_disk_change,
19507 + revalidate: mmc_block_revalidate
19512 +static int mmc_block_notify_add( mmc_card_t card )
19515 + mmc_block_device_t dev;
19521 + if ( !card || !card->ctrlr )
19524 + start = MMC_BLOCK_MKDEV( card->ctrlr->slot, card->slot );
19525 + dev = &mmc_block_device[MINOR( start )];
19527 + __mmc_block_wrlock_devices();
19528 + if ( !dev->card ) {
19529 + dev->card = card;
19532 + __mmc_block_wrunlock_devices();
19537 + /* allow to read partition table */
19538 + __mmc_block_rdlock_devices();
19539 + grok_partitions( &mmc_block_gendisk, MINOR( start ),
19540 + mmc_block_gendisk.max_p,
19541 + card->info.capacity>>9 /* sectors */
19543 + __mmc_block_rdunlock_devices();
19545 + __mmc_block_wrlock_devices();
19546 + for ( i = start + mmc_block_gendisk.max_p - 1; i >= 0; --i ) {
19547 + minor = MINOR( i );
19548 + dev = &mmc_block_device[minor];
19549 + if ( mmc_block_gendisk.part[minor].nr_sects > 0 )
19550 + dev->card = card;
19552 + __mmc_block_wrunlock_devices();
19555 + __LEAVE( "ret=%d", ret );
19560 +static int mmc_block_notify_remove( mmc_card_t card )
19564 + __ENTER( "card=0x%p", card );
19566 + if ( card && card->ctrlr )
19567 + ret = __mmc_block_invalidate_card( card, FALSE );
19569 + __LEAVE( "ret=%d", ret );
19573 +static mmc_notifier_rec_t mmc_block_notifier = {
19574 + add: mmc_block_notify_add,
19575 + remove: mmc_block_notify_remove
19578 +static int __init mmc_block_module_init( void )
19580 + int ret = -ENODEV;
19585 + init_rwsem( &mmc_block_device_sem );
19587 + if ( devfs_register_blkdev( MAJOR_NR, MAJOR_NAME, &mmc_block_fops ) ) {
19588 + MMC_ERROR( "Can't allocate major number %d for MMC block devices.\n", MMC_BLOCK_MAJOR );
19593 + for ( i = 0; i < (1<<MINORBITS); i++ ) {
19594 + __mmc_block_device_init( i );
19595 + init_MUTEX( &mmc_block_device[i].sem );
19597 + /* We fill it in at open() time. */
19598 + mmc_block_blk_sizes[i] = 0;
19599 + mmc_block_blk_blksizes[i] = BLOCK_SIZE;
19600 + mmc_block_hardsect_sizes[i] = 0;
19603 + init_waitqueue_head( &thr_wq );
19604 + /* Allow the block size to default to BLOCK_SIZE. */
19605 + blksize_size[MAJOR_NR] = mmc_block_blk_blksizes;
19606 + hardsect_size[MAJOR_NR] = mmc_block_hardsect_sizes;
19607 + /* Gendisk stuff */
19608 + memset( mmc_block_partitions, 0, sizeof( mmc_block_partitions ) );
19609 + add_gendisk( &mmc_block_gendisk );
19611 +/* FIXME: per controller request queue, I/O and card stack update threads */
19612 + blk_init_queue( BLK_DEFAULT_QUEUE( MAJOR_NR ), &mmc_block_request );
19613 + thr_id = kernel_thread( mmc_block_thread, NULL,
19614 + CLONE_FS|CLONE_FILES|CLONE_SIGHAND );
19616 + if ( !mmc_register( MMC_REG_TYPE_USER, &mmc_block_notifier, 0 ) ) {
19617 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "failed to register with MMC core\n" );
19624 + if ( thr_id != -1 ) {
19625 +/* quit the thread */
19627 + wake_up(&thr_wq);
19629 + down(&thread_sem);
19631 + blksize_size[MAJOR_NR] = NULL;
19632 + blk_size[MAJOR_NR] = NULL;
19633 + hardsect_size[MAJOR_NR] = NULL;
19639 +static void __exit mmc_block_module_cleanup( void )
19641 +/* quit the thread */
19643 + wake_up(&thr_wq);
19645 + down(&thread_sem);
19647 + mmc_unregister( MMC_REG_TYPE_USER, &mmc_block_notifier );
19648 + del_gendisk( &mmc_block_gendisk );
19649 + devfs_unregister_blkdev( MAJOR_NR, MAJOR_NAME );
19651 + blk_cleanup_queue( BLK_DEFAULT_QUEUE( MAJOR_NR ) );
19652 + blksize_size[MAJOR_NR] = NULL;
19653 + blk_size[MAJOR_NR] = NULL;
19654 + hardsect_size[MAJOR_NR] = NULL;
19657 +EXPORT_NO_SYMBOLS;
19659 +module_init( mmc_block_module_init );
19660 +module_exit( mmc_block_module_cleanup );
19663 +MODULE_LICENSE("GPL");
19665 +++ linux-2.4.27/drivers/mmc/mmc_core.c
19668 + * linux/drivers/mmc/mmc_core.c
19669 + * MultiMediaCard subsystem core implementation
19671 + * Author: Vladimir Shebordaev
19672 + * Copyright: MontaVista Software Inc.
19674 + * $Id: mmc_core.c,v 0.3.1.14 2002/09/27 17:36:09 ted Exp ted $
19676 + * This program is free software; you can redistribute it and/or modify
19677 + * it under the terms of the GNU General Public License version 2 as
19678 + * published by the Free Software Foundation.
19680 +#include <linux/version.h>
19681 +#include <linux/config.h>
19682 +#include <linux/init.h>
19683 +#include <linux/module.h>
19684 +#include <linux/errno.h>
19686 +#include <linux/slab.h>
19687 +#include <asm/uaccess.h>
19688 +#include <asm/semaphore.h>
19691 +#include <linux/pm.h>
19694 +#include <mmc/types.h>
19695 +#include <mmc/mmc.h>
19696 +#include <mmc/ioctl.h>
19698 +#include "types.h"
19700 +#define __MMC_CORE_IMPLEMENTATION__
19703 +/* MMC controllers registered in the system */
19704 +static mmc_controller_t mmc_controller[MMC_CONTROLLERS_MAX];
19705 +static int mmc_ncontrollers = 0;
19706 +static rwsemaphore_t mmc_controller_sem; /* controller table lock */
19708 +static struct pm_dev *mmc_pm_dev = NULL;
19711 +/* users' notification list */
19712 +static mmc_notifier_t mmc_notifier = NULL;
19713 +static rwsemaphore_t mmc_notifier_sem; /* notifiers' list lock */
19714 +#ifdef CONFIG_PROC_FS
19715 +static proc_dir_entry_t mmc_proc_dir = NULL;
19718 +/************************************************
19719 + * service function prototypes and declarations *
19720 + ************************************************/
19721 +static inline int mmc_acquire_io( mmc_controller_t ctrlr, mmc_card_t card )
19727 + if ( !card || !ctrlr ) {
19731 +#ifdef CONFIG_HOTPLUG
19732 +/* TODO: account for controller removal */
19734 + down( &ctrlr->io_sem );
19736 + down_read( &ctrlr->update_sem ); /* FIXME */
19737 + if ( card->state != MMC_CARD_STATE_UNPLUGGED )
19739 + up_read( &ctrlr->update_sem );
19742 + up( &ctrlr->io_sem );
19748 + __LEAVE( "ret=%d", ret );
19752 +static inline void mmc_release_io( mmc_controller_t ctrlr, mmc_card_t card )
19755 +#ifdef CONFIG_HOTPLUG
19756 +/* TODO: account for controller removal */
19758 + if ( !card && !ctrlr ) { /* FIXME */
19759 + MMC_DEBUG( MMC_DEBUG_LEVEL2, "bad card reference\n" );
19762 + up( &ctrlr->io_sem );
19767 +/* TODO: there should be a separate context to be awaken
19768 + * by the card intertion interrupt; called under ctrlr->update_sem
19769 + * held down by now */
19770 +static int __mmc_update_card_stack( mmc_controller_t ctrlr )
19773 + mmc_card_t card, prev;
19777 + if ( !ctrlr || !ctrlr->tmpl )
19780 + /* check unplugged cards first... */
19781 + if ( (ret = ctrlr->tmpl->check_card_stack( ctrlr )) )
19784 + /* unregister unplugged cards and free 'em immediately */
19785 + if ( ctrlr->stack.ncards > 0 ) {
19786 + prev = ctrlr->stack.first;
19787 + /* process the stack tail first */
19788 + if ( prev->next ) {
19789 + card = prev->next;
19791 + if ( card->state == MMC_CARD_STATE_UNPLUGGED ) {
19792 + if ( ctrlr->stack.selected == card )
19793 + ctrlr->stack.selected = NULL;
19794 +#ifdef CONFIG_PROC_FS
19795 + if ( card->proc ) {
19796 + remove_proc_entry( card->proc_name, ctrlr->proc );
19797 + card->proc = NULL;
19800 + ctrlr->slot_next = card->slot; /* FIXME */
19801 + prev->next = card->next;
19802 + if ( ctrlr->stack.last == card )
19803 + ctrlr->stack.last = prev;
19804 + /* FIXME: controller use count */
19805 + mmc_notify_remove( card );
19806 + --ctrlr->stack.ncards;
19807 + if ( (ctrlr->usage > 0) && ctrlr->tmpl->owner ) {
19809 + MMC_DEBUG( MMC_DEBUG_LEVEL2,
19810 + "'%s' use count "
19811 + "decreased (%d)\n",
19812 + ctrlr->tmpl->name,
19814 + __MOD_DEC_USE_COUNT(
19815 + ctrlr->tmpl->owner );
19817 + __mmc_card_free( card );
19819 + card = prev->next;
19823 + /* then the head */
19824 + card = ctrlr->stack.first;
19825 + if ( card && (card->state == MMC_CARD_STATE_UNPLUGGED) ) {
19826 + if ( ctrlr->stack.selected == card )
19827 + ctrlr->stack.selected = NULL;
19828 +#ifdef CONFIG_PROC_FS
19829 + if ( card->proc ) {
19830 + remove_proc_entry( card->proc_name, ctrlr->proc );
19831 + card->proc = NULL;
19834 + ctrlr->slot_next = card->slot; /* FIXME */
19835 + mmc_notify_remove( card ); /* FIXME: should unregister here */
19836 + ctrlr->stack.first = card->next;
19837 + if ( ctrlr->stack.last == card )
19838 + ctrlr->stack.last = NULL;
19839 + /* FIXME: controller use count */
19840 + --ctrlr->stack.ncards;
19841 + if ( (ctrlr->usage > 0) && ctrlr->tmpl->owner ) {
19843 + MMC_DEBUG( MMC_DEBUG_LEVEL2, "'%s' use count "
19844 + "decreased (%d)\n", ctrlr->tmpl->name,
19846 + __MOD_DEC_USE_COUNT( ctrlr->tmpl->owner );
19848 + __mmc_card_free( card );
19851 + MMC_DEBUG( MMC_DEBUG_LEVEL2, "after stack check: ncards=%d"
19852 + " first=0x%x last=0x%x\n", ctrlr->stack.ncards,
19853 + ctrlr->stack.first, ctrlr->stack.last );
19854 + /* ...then add newly inserted ones */
19855 + if ( (ret = ctrlr->tmpl->update_acq( ctrlr )) )
19859 + __LEAVE( "ret=%d", ret );
19864 + * 1) check error code returned by controller; it's up to
19865 + * controller to detect error conditions reported by the card
19866 + * and to abort data transfer requests properly (e.g. send
19867 + * CMD12(STOP_TRANSMISSION) to abort ADDRESS_ERROR multiple
19868 + * block transfers)
19869 + * 2) arrange for card stack update when necessary
19870 + * (all pending i/o requests must be held pending,
19871 + * update procedure must start immediately after
19872 + * error has been detected)
19874 +static inline int __mmc_check_error( mmc_card_t card, int err )
19877 + mmc_controller_t ctrlr;
19881 + if ( !card || !card->ctrlr )
19884 + ctrlr = card->ctrlr;
19888 + /* bus error occurred */
19889 + case MMC_ERROR_CRC_WRITE_ERROR:
19890 + case MMC_ERROR_CRC_READ_ERROR:
19891 + case MMC_ERROR_RES_CRC_ERROR:
19892 + case MMC_ERROR_READ_TIME_OUT:
19893 + case MMC_ERROR_TIME_OUT_RESPONSE:
19894 + down_write( &ctrlr->update_sem ); /* FIXME */
19895 + if ( !__mmc_update_card_stack( ctrlr ) )
19897 + up_write( &ctrlr->update_sem );
19903 + __LEAVE( "ret=%d", ret );
19907 +static inline void __mmc_free_controller( mmc_controller_t ctrlr )
19910 + if ( ctrlr->stack.ncards > 0 )
19911 + __mmc_card_stack_free( &ctrlr->stack );
19916 +#ifdef CONFIG_PROC_FS
19917 +static int mmc_proc_read_card_info( char *page, char **start, off_t off, int count, int *eof, void *data )
19919 + int ret = -EINVAL;
19920 + mmc_card_t card = (mmc_card_t)data;
19926 + down_read( &card->ctrlr->update_sem );
19927 +/* TODO: proc report
19928 + * Type: RO, RW or IO (by CCC)
19929 + * MID: 0x%02x card->info.cid.mid
19930 + * OID: 0x%04x card->info.cid.oid
19931 + * PNM: %s card->info.pnm
19932 + * PRV: %s card->info.prv
19933 + * PSN: 0x%08x card->info.cid.psn
19934 + * MDT: %s card->info.mdt
19935 + * Capacity: card->info.capacity (Bytes)
19938 + cp += sprintf( cp, "Capacity: %dKb.\n\n", (card->info.capacity>>10) );
19940 + cp += sprintf( cp, "Type : %s\n", card->info.type );
19941 + cp += sprintf( cp, "MID : 0x%02x\n", card->info.cid.mid );
19942 + cp += sprintf( cp, "OID : 0x%04x\n", card->info.cid.oid );
19943 + cp += sprintf( cp, "PNM : %s\n", card->info.pnm );
19944 + cp += sprintf( cp, "PRV : %s\n", card->info.prv );
19945 + cp += sprintf( cp, "PSN : 0x%08x\n", card->info.cid.psn );
19946 + cp += sprintf( cp, "MDT : %s\n", card->info.mdt );
19947 + cp += sprintf( cp, "Capacity: %dKB\n",
19948 + (card->info.capacity>>10) );
19950 + up_read( &card->ctrlr->update_sem );
19958 +/*************************************
19959 + * MMC core interface implementation *
19960 + *************************************/
19961 +int mmc_notify_add( mmc_card_t card )
19964 + mmc_notifier_t notifier;
19968 + for ( notifier = mmc_notifier; notifier;
19969 + notifier = notifier->next )
19970 + if ( notifier->add )
19971 + if ( (ret = notifier->add( card )) )
19974 + __LEAVE( "ret=%d", ret );
19977 +EXPORT_SYMBOL( mmc_notify_add );
19979 +int mmc_notify_remove( mmc_card_t card )
19982 + mmc_notifier_t notifier;
19986 + for ( notifier = mmc_notifier; notifier;
19987 + notifier = notifier->next )
19988 + if ( notifier->remove )
19989 + if ( (ret = notifier->remove( card )) )
19992 + __LEAVE( "ret=%d", ret );
19995 +EXPORT_SYMBOL( mmc_notify_remove );
19997 +int mmc_update_card_stack( int host )
19999 + int ret = -EINVAL;
20000 + mmc_controller_t ctrlr;
20004 + if ( (host < 0) || (host >= MMC_CONTROLLERS_MAX) )
20007 + down_read( &mmc_controller_sem );
20008 + if ( (ctrlr = mmc_controller[host]) ) {
20009 + down_write( &ctrlr->update_sem );
20010 + (void)__mmc_update_card_stack( ctrlr );
20011 + up_write( &ctrlr->update_sem );
20013 + up_read( &mmc_controller_sem );
20016 + __LEAVE( "ret=%d", ret );
20019 +EXPORT_SYMBOL( mmc_update_card_stack );
20021 +ssize_t mmc_read( mmc_card_t card, mmc_transfer_mode_t mode, char *buf, size_t size, loff_t *paddr )
20023 + ssize_t ret = -EIO;
20024 + mmc_controller_t ctrlr;
20025 + mmc_data_transfer_req_rec_t transfer;
20037 + __ENTER( "card=%p usage=%d mode=%d buf=%p size=%d addr=%x",
20038 + card, card->usage, mode, buf, size, *paddr );
20040 + ctrlr = card->ctrlr;
20041 + if ( (ret = mmc_acquire_io( ctrlr, card )) )
20044 + memset( &transfer, 0, sizeof( mmc_data_transfer_req_rec_t ) );
20045 + transfer.cmd = MMC_READ;
20046 + transfer.mode = mode;
20047 + transfer.type = MMC_USER; /* FIXME: buffer cache */
20048 + transfer.buf = buf;
20049 + transfer.addr = *paddr;
20050 + transfer.cnt = size;
20052 +/* max block size defined by CSD[read_bl_len] */
20053 + transfer.blksz = card->info.read_bl_len;
20054 + transfer.nob = size / transfer.blksz;
20055 + if ( (size - (transfer.nob * transfer.blksz)) > 0 )
20058 +/* TODO: controller may restrict maximum block size; set block size
20059 + * and number of blocks that their accumulated length fit to
20060 + * CSD[READ_BL_LEN] not to bother with block misalignment in multiple
20061 + * block transfers */
20062 + ctrlr = card->ctrlr;
20063 + if ( transfer.blksz > ctrlr->tmpl->block_size_max ) {
20064 + ret = -EINVAL; /* FIXME */
20068 + if ( ctrlr->stack.selected != card ) {
20069 + if ( (ret = ctrlr->tmpl->setup_card( ctrlr, card )) )
20071 + ctrlr->stack.selected = card;
20075 + case MMC_TRANSFER_MODE_STREAM:
20076 + if ( !ctrlr->tmpl->stream_read ) {
20080 +/* TODO: The max clock frequency for stream read operation is given by
20081 + the following formula:
20082 + max speed = min ( TRAN_SPEED, 8*2^(READ_BL_LEN) - NSAC/TAAC )
20084 + If the card is not able to sustain data transfer it will set the
20085 + UNDERRUN error bit in the status register, abort the transmission
20086 + and wait in the Data state for a stop command
20088 + ret = ctrlr->tmpl->stream_read( ctrlr, &transfer );
20091 + case MMC_TRANSFER_MODE_BLOCK_SINGLE:
20092 + if ( !ctrlr->tmpl->read_block ) {
20096 +/* TODO: buffer size and data alignment (v3.4, p.29):
20097 + if CSD[READ_BL_PARTIAL] is set, smaller blocks whose starting
20098 + and ending address are entirely contained within one physical
20099 + block (as defined by CSD[READ_BL_LEN]) may also be transmitted
20101 + transfer.type = MMC_KERNEL; /* FIXME */
20102 + ret = ctrlr->tmpl->read_block( ctrlr, &transfer );
20105 + case MMC_TRANSFER_MODE_BLOCK_MULTIPLE:
20106 + if ( !ctrlr->tmpl->read_mblock ) {
20111 + if ( transfer.nob > ctrlr->tmpl->nob_max ) {
20115 +/* TODO: buffer size and data alignment (v3.4, p.29):
20116 + if the host uses patrial blocks whose accumulated length is
20117 + not block aligned and block misalignment is not allowed, the
20118 + card should detect a block misalignment error condition at the
20119 + beginning of the first misaligned block
20121 + transfer.type = MMC_KERNEL; /* FIXME */
20122 + ret = ctrlr->tmpl->read_mblock( card->ctrlr, &transfer );
20126 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "request for unknown transfer type\n" );
20130 + ret = __mmc_check_error( card, ret );
20131 + if ( ret >= 0 ) {
20132 + ret = size - transfer.cnt;
20136 + mmc_release_io( ctrlr, card );
20138 + __LEAVE("ret=%d", ret);
20141 +EXPORT_SYMBOL( mmc_read );
20143 +ssize_t mmc_write( mmc_card_t card, mmc_transfer_mode_t mode, const char *buf, size_t size, loff_t *paddr )
20145 + ssize_t ret = -ESPIPE;
20146 + mmc_controller_t ctrlr;
20147 + mmc_data_transfer_req_rec_t transfer;
20159 + __ENTER( "card=%p usage=%d mode=%d buf=%p size=%d addr=%llx",
20160 + card, card->usage, mode, buf, size, *paddr );
20162 + ctrlr = card->ctrlr;
20163 + if ( (ret = mmc_acquire_io( ctrlr, card )) )
20166 + memset( &transfer, 0, sizeof( mmc_data_transfer_req_rec_t ) );
20167 + transfer.cmd = MMC_WRITE;
20168 + transfer.mode = mode;
20169 + transfer.type = MMC_USER; /* FIXME: buffer cache */
20170 + transfer.buf = (char *)buf;
20171 + transfer.addr = *paddr;
20172 + transfer.cnt = size;
20174 +/* max block size defined by CSD[write_bl_len] */
20175 + transfer.blksz = card->info.write_bl_len;
20176 + transfer.nob = size / transfer.blksz;
20177 + if ( (size - (transfer.nob * transfer.blksz)) > 0 )
20180 +/* TODO: controller may restrict maximum block size; set block size
20181 + * and number of blocks that their accumulated length fit to
20182 + * CSD[WRITE_BL_LEN] not to bother with block misalignment in multiple
20183 + * block transfers */
20184 + ctrlr = card->ctrlr;
20185 + if ( transfer.blksz > ctrlr->tmpl->block_size_max ) {
20186 + ret = -EINVAL; /* FIXME */
20190 + if ( ctrlr->stack.selected != card ) {
20191 + if ( (ret = ctrlr->tmpl->setup_card( ctrlr, card )) )
20193 + ctrlr->stack.selected = card;
20196 + transfer.cmd = MMC_WRITE;
20197 + transfer.mode = mode;
20198 + transfer.type = MMC_USER;
20200 + case MMC_TRANSFER_MODE_STREAM:
20201 + if ( !ctrlr->tmpl->stream_write ) {
20205 + ret = ctrlr->tmpl->stream_write( ctrlr, &transfer );
20208 + case MMC_TRANSFER_MODE_BLOCK_SINGLE:
20209 + if ( !ctrlr->tmpl->write_block ) {
20213 + transfer.type = MMC_KERNEL; /* FIXME */
20214 + ret = ctrlr->tmpl->write_block( ctrlr, &transfer );
20217 + case MMC_TRANSFER_MODE_BLOCK_MULTIPLE:
20218 + if ( !ctrlr->tmpl->write_mblock ) {
20222 + transfer.type = MMC_KERNEL; /* FIXME */
20223 + ret = ctrlr->tmpl->write_mblock( card->ctrlr, &transfer );
20227 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "request for unknown transfer type\n" );
20231 + ret = __mmc_check_error( card, ret ); /* FIXME */
20232 + if ( ret >= 0 ) {
20233 + ret = size - transfer.cnt;
20237 + mmc_release_io( ctrlr, card );
20239 + __LEAVE( "ret=%d", ret );
20242 +EXPORT_SYMBOL( mmc_write );
20244 +int mmc_ioctl( mmc_card_t card, unsigned int cmd, unsigned long arg )
20246 + int ret = -EINVAL;
20247 + mmc_controller_t ctrlr;
20250 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "bad card reference\n" )
20254 + ctrlr = card->ctrlr;
20255 + if ( mmc_acquire_io( ctrlr, card ) ) {
20261 + case IOCMMCGCARDESC:
20262 + if ( copy_to_user( (void *)arg, &card->info, sizeof( mmc_card_info_rec_t ) ) )
20266 + * 1. TODO: erase region
20267 + * 2. TODO: set/unset write protection, lock/password
20270 + ret = -ENOIOCTLCMD;
20273 + mmc_release_io( ctrlr, card );
20277 +EXPORT_SYMBOL( mmc_ioctl );
20282 +mmc_card_t mmc_get_card( int host, int slot )
20284 + mmc_card_t ret = NULL;
20285 + mmc_controller_t ctrlr = NULL;
20288 + __ENTER( "host=%d, card=%d", host, slot );
20290 + if ( ((host < 0) || (host >= MMC_CONTROLLERS_MAX))
20291 + && ((slot < 0) || (slot >= MMC_CARDS_MAX)) )
20294 + down_read( &mmc_controller_sem );
20296 + if ( (ctrlr = mmc_controller[host]) ) {
20297 + down_write( &ctrlr->update_sem );
20298 + if ( ctrlr->stack.ncards > 0 ) {
20299 + ret = ctrlr->stack.first;
20302 + if ( (ret->slot == slot) && (ret->state !=
20303 + MMC_CARD_STATE_UNPLUGGED) ) {
20311 + if ( ctrlr->tmpl->owner ) {
20313 + MMC_DEBUG( MMC_DEBUG_LEVEL2,
20314 + "'%s' use count increased (%d)\n",
20315 + ctrlr->tmpl->name, ctrlr->usage );
20316 + __MOD_INC_USE_COUNT( ctrlr->tmpl->owner );
20322 + up_write( &ctrlr->update_sem );
20324 + up_read( &mmc_controller_sem );
20326 + __LEAVE("ret=0x%p usage=%d", ret, ret ? ret->usage : -1 );
20329 +EXPORT_SYMBOL( mmc_get_card );
20331 +void mmc_put_card( mmc_card_t card )
20333 + mmc_card_t tmp = NULL;
20334 + mmc_controller_t ctrlr;
20337 + __ENTER( "card=0x%p", card );
20342 + ctrlr = card->ctrlr;
20344 + down_read( &mmc_controller_sem );
20345 + if ( !ctrlr || (ctrlr != mmc_controller[ctrlr->slot]) ) {
20346 + MMC_ERROR( "bad controller reference: ctrlr=0x%p\n", ctrlr );
20350 + down_write( &ctrlr->update_sem );
20351 + if ( ctrlr->stack.ncards > 0 ) {
20352 + tmp = ctrlr->stack.first;
20355 + if ( tmp == card ) {
20363 + if ( tmp->usage > 0 ) {
20365 + MMC_DEBUG( MMC_DEBUG_LEVEL2, "usage=%d"
20366 + "owner=0x%p\n", tmp->usage,
20367 + ctrlr->tmpl->owner );
20368 + if ( !tmp->usage && (ctrlr->usage > 0)
20369 + && ctrlr->tmpl->owner ) {
20371 + MMC_DEBUG( MMC_DEBUG_LEVEL2,
20372 + "'%s' use count "
20373 + "decreased (%d)\n",
20374 + ctrlr->tmpl->name,
20376 + __MOD_DEC_USE_COUNT(
20377 + ctrlr->tmpl->owner );
20381 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "bad card reference\n" );
20384 + up_write( &ctrlr->update_sem );
20386 + up_read( &mmc_controller_sem );
20388 + __LEAVE( "found=%d", found );
20391 +EXPORT_SYMBOL( mmc_put_card );
20393 +static inline void *mmc_register_user( mmc_notifier_t notifier )
20395 + mmc_notifier_t ret = NULL, last = mmc_notifier;
20397 + MOD_INC_USE_COUNT;
20398 + if ( notifier ) {
20399 + down_write( &mmc_notifier_sem );
20401 + notifier->next = NULL;
20403 + mmc_notifier = notifier;
20406 + while ( last->next ) {
20407 + if ( last == notifier ) {
20408 + MOD_DEC_USE_COUNT;
20411 + last = last->next;
20413 + if ( last != notifier ) {
20414 + last->next = notifier;
20418 + up_write( &mmc_notifier_sem );
20420 +/* notify new user about the cards present in the system */
20421 + if ( ret && ret->add ) {
20424 + down_read( &mmc_controller_sem );
20425 + for ( i = 0; i < mmc_ncontrollers; i++ ) {
20426 + mmc_controller_t ctrlr = mmc_controller[i];
20428 + down_read( &ctrlr->update_sem ); /* FIXME */
20429 + __mmc_card_stack_foreach( &ctrlr->stack,
20430 + ret->add, FALSE );
20431 + up_read( &ctrlr->update_sem ); /* FIXME */
20433 + up_read( &mmc_controller_sem );
20436 + __LEAVE( "mmc_notifier=0x%p, mmc_notifier->next=0x%p",
20437 + mmc_notifier, mmc_notifier ? mmc_notifier->next : NULL );
20441 +static inline mmc_controller_t mmc_register_controller( mmc_controller_tmpl_t tmpl, size_t extra )
20443 + mmc_controller_t ret = NULL;
20447 + MOD_INC_USE_COUNT;
20449 + down_write( &mmc_controller_sem );
20451 + if ( mmc_ncontrollers >= MMC_CONTROLLERS_MAX ) {
20452 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "there're too many controllers\n" );
20457 + for ( i = 0; i < MMC_CONTROLLERS_MAX; i++ )
20458 + if ( !mmc_controller[i] ) {
20464 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "there're no empty slots\n" );
20468 + if ( !tmpl->init ) {
20469 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "host template lacks 'init()'\n" );
20473 + if ( !tmpl->probe ) {
20474 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "host template lacks 'probe()'\n" );
20478 + if ( !tmpl->init_card_stack ) {
20479 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "host template lacks 'init_card_stack()'\n" );
20483 + if ( !tmpl->update_acq ) {
20484 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "host template lacks 'update_acq()'\n" );
20488 + if ( !tmpl->check_card_stack ) {
20489 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "host template lacks 'check_card_stack()'\n" );
20493 + if ( !tmpl->setup_card ) {
20494 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "host template lacks 'setup_card()'\n" );
20498 + ret = kmalloc( sizeof( mmc_controller_rec_t ) + extra, GFP_ATOMIC ); /* FIXME: ISA + GFP_DMA */
20500 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "out of memory\n" );
20504 + memset( ret, 0, sizeof( mmc_controller_rec_t ) + extra );
20506 + if ( (tmpl->probe( ret ) != 1) ) {
20507 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "controller probe failed\n" );
20511 + if ( tmpl->init( ret ) ) {
20512 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "controller initialization failure\n" );
20516 + ret->state = MMC_CONTROLLER_FOUND;
20518 + ret->tmpl = tmpl;
20519 + init_MUTEX( &ret->io_sem );
20520 + init_rwsem( &ret->update_sem );
20521 +#ifdef CONFIG_PROC_FS
20522 + if ( mmc_proc_dir ) {
20523 + snprintf( ret->proc_name, sizeof( ret->proc_name ),
20524 + "host%d", ret->slot );
20525 + ret->proc = proc_mkdir( ret->proc_name, mmc_proc_dir );
20529 +/* initialize card stack */
20530 + if ( ret->tmpl->init_card_stack( ret ) ) {
20531 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "card stack initialization failure\n" );
20532 + if ( ret->tmpl->remove )
20533 + ret->tmpl->remove( ret ); /* FIXME */
20537 + mmc_controller[ret->slot] = ret;
20538 + ++mmc_ncontrollers;
20540 +/* notify users */
20541 + if ( ret->stack.ncards > 0 ) {
20542 + down_read( &mmc_notifier_sem );
20543 + if ( (i = __mmc_card_stack_foreach( &ret->stack, mmc_notify_add, FALSE ) ) < 0 )
20544 + MMC_ERROR( "device add notification failed at slot %d\n", -i );
20545 + up_read( &mmc_notifier_sem );
20550 +#ifdef CONFIG_PROC_FS
20552 + remove_proc_entry( ret->proc_name, mmc_proc_dir );
20557 + MOD_DEC_USE_COUNT;
20559 + up_write( &mmc_controller_sem );
20563 +static inline mmc_card_t mmc_register_card( mmc_card_t card )
20565 + mmc_card_t ret = NULL;
20566 + mmc_controller_t ctrlr;
20568 + if ( !card || !card->ctrlr )
20571 + ctrlr = card->ctrlr;
20572 +#ifdef CONFIG_PROC_FS
20573 + if ( ctrlr->proc ) {
20574 + snprintf( card->proc_name, sizeof( card->proc_name ),
20575 + "card%d", card->slot );
20576 + card->proc = create_proc_read_entry( card->proc_name,
20577 + 0444, ctrlr->proc,
20578 + mmc_proc_read_card_info, card );
20581 + mmc_notify_add( card );
20586 +void *mmc_register( mmc_reg_type_t reg_type, void *tmpl, size_t extra )
20588 + void *ret = NULL;
20590 + switch ( reg_type ) {
20591 + case MMC_REG_TYPE_CARD:
20592 + ret = mmc_register_card( (mmc_card_t)tmpl );
20595 + case MMC_REG_TYPE_USER:
20596 + ret = mmc_register_user( (mmc_notifier_t)tmpl );
20599 + case MMC_REG_TYPE_HOST:
20600 + ret = mmc_register_controller( (mmc_controller_tmpl_t)tmpl, extra );
20604 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "register request for unknown type\n" );
20609 +EXPORT_SYMBOL( mmc_register );
20611 +static inline void mmc_unregister_user( mmc_notifier_t notifier )
20613 + mmc_notifier_t prev = mmc_notifier;
20614 + int found = FALSE;
20616 + if ( notifier ) {
20617 + down_write( &mmc_notifier_sem );
20619 + if ( mmc_notifier == notifier) {
20620 + mmc_notifier = prev->next;
20623 + } else if ( mmc_notifier ) {
20625 + if ( prev->next == notifier ) {
20627 + prev->next = prev->next->next;
20630 + prev = prev->next;
20635 + if ( notifier->remove ) {
20638 + down_read( &mmc_controller_sem );
20639 + for ( i = 0; i < mmc_ncontrollers; i++ ) {
20640 + mmc_controller_t ctrlr =
20641 + mmc_controller[i];
20643 + down_read( &ctrlr->update_sem );
20644 + __mmc_card_stack_foreach( &ctrlr->stack, notifier->remove, FALSE );
20645 + up_read( &ctrlr->update_sem );
20647 + up_read( &mmc_controller_sem );
20651 + up_write( &mmc_notifier_sem );
20654 + MOD_DEC_USE_COUNT;
20657 +static inline void mmc_unregister_controller( mmc_controller_t ctrlr )
20659 + if ( !ctrlr || (mmc_controller[ctrlr->slot] != ctrlr ) ) {
20660 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "bad unregister request\n" );
20664 + down_write( &mmc_controller_sem );
20666 +/* notify users */
20667 + if ( ctrlr->stack.ncards > 0 ) {
20670 + down_read( &mmc_notifier_sem );
20671 + if ( (slot = __mmc_card_stack_foreach( &ctrlr->stack, mmc_notify_remove, FALSE ) ) )
20672 + MMC_ERROR( "device remove notification failed at slot %d\n", -slot );
20673 + up_read( &mmc_notifier_sem );
20676 +#ifdef CONFIG_PROC_FS
20677 + if ( ctrlr->proc )
20678 + remove_proc_entry( ctrlr->proc_name, mmc_proc_dir );
20681 + if ( ctrlr->tmpl && ctrlr->tmpl->remove )
20682 + ctrlr->tmpl->remove( ctrlr );
20684 + mmc_controller[ctrlr->slot] = NULL;
20685 + --mmc_ncontrollers;
20687 + __mmc_free_controller( ctrlr );
20689 + up_write( &mmc_controller_sem );
20690 + MOD_DEC_USE_COUNT;
20695 +void mmc_unregister( mmc_reg_type_t reg_type, void *tmpl )
20697 + switch ( reg_type ) {
20698 + case MMC_REG_TYPE_USER:
20699 + mmc_unregister_user( (mmc_notifier_t)tmpl );
20702 + case MMC_REG_TYPE_HOST:
20703 + mmc_unregister_controller( (mmc_controller_t)tmpl );
20707 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "unregister request for unknown type\n" );
20710 +EXPORT_SYMBOL( mmc_unregister );
20713 +/* power management support */
20714 +static int mmc_pm_callback( struct pm_dev *pmdev, pm_request_t pmreq, void *pmdata )
20716 + int ret = -EINVAL;
20717 + mmc_controller_t ctrlr;
20720 + __ENTER( "pmreq=%d", pmreq );
20722 + down_read( &mmc_controller_sem );
20724 + switch ( pmreq ) {
20726 + for ( ret = 0, i = 0; !ret && (i < mmc_ncontrollers); i++ ) {
20727 + ctrlr = mmc_controller[i];
20728 + if ( ctrlr->tmpl->suspend )
20729 + ret = ctrlr->tmpl->suspend( ctrlr );
20735 + for ( i = mmc_ncontrollers - 1; i >= 0; i-- ) {
20736 + ctrlr = mmc_controller[i];
20737 + if ( ctrlr->tmpl->resume )
20738 + ctrlr->tmpl->resume( ctrlr );
20744 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "unsupported PM request %d\n",
20748 + up_read( &mmc_controller_sem );
20750 + __LEAVE( "ret=%d", ret );
20755 +/* kernel module stuff */
20756 +static int __init mmc_core_module_init( void )
20758 + int ret = -ENODEV;
20760 + memset( &mmc_controller, 0, sizeof( mmc_controller ) );
20762 + init_rwsem( &mmc_controller_sem );
20763 + init_rwsem( &mmc_notifier_sem );
20765 + if ( !(mmc_pm_dev = pm_register( PM_UNKNOWN_DEV, 0, mmc_pm_callback )) ) MMC_DEBUG( MMC_DEBUG_LEVEL0, "failed to register PM callback\n" );
20767 +#ifdef CONFIG_PROC_FS
20768 + mmc_proc_dir = proc_mkdir( "mmc", NULL );
20775 +static void __exit mmc_core_module_cleanup( void )
20777 +#ifdef CONFIG_PROC_FS
20778 + if ( mmc_proc_dir )
20779 + remove_proc_entry( "mmc", NULL );
20782 + pm_unregister( mmc_pm_dev );
20786 +module_init( mmc_core_module_init );
20787 +module_exit( mmc_core_module_cleanup );
20789 +MODULE_LICENSE( "GPL" );
20792 +++ linux-2.4.27/drivers/mmc/mmc_pxa.c
20795 + * linux/drivers/mmc/mmc_pxa.c
20796 + * driver for Cotulla MMC controller
20798 + * Authors: Vladimir Shebordaev, Igor Oblakov
20799 + * Copyright: MontaVista Software Inc.
20801 + * $Id: mmc_pxa.c,v 0.3.1.12 2002/09/25 19:25:48 ted Exp ted $
20803 + * This program is free software; you can redistribute it and/or modify
20804 + * it under the terms of the GNU General Public License version 2 as
20805 + * published by the Free Software Foundation.
20807 +#include <linux/version.h>
20808 +#include <linux/config.h>
20809 +#include <linux/kernel.h>
20810 +#include <linux/init.h>
20811 +#include <linux/module.h>
20812 +#include <linux/errno.h>
20814 +#include <linux/slab.h>
20815 +#include <linux/sched.h>
20816 +#include <linux/delay.h>
20818 +#include <asm/hardware.h>
20819 +#include <asm/io.h>
20820 +#include <asm/irq.h>
20821 +#include <asm/dma.h>
20823 +#include <asm/uaccess.h>
20824 +#include <asm/semaphore.h>
20826 +#include <mmc/types.h>
20827 +#include <mmc/mmc.h>
20828 +#include <mmc/ioctl.h>
20830 +#include "types.h"
20832 +#include "mmc_pxa.h"
20834 +static mmc_controller_t host = NULL;
20836 +/* service routines */
20837 +static inline int pxa_mmc_check_state( mmc_controller_t ctrlr, pxa_mmc_state_t state )
20840 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
20842 + if ( hostdata->state != state ) {
20843 + //MMC_DEBUG( MMC_DEBUG_LEVEL3, "state (%s vs %s)\n", PXA_MMC_STATE_LABEL( hostdata->state ), PXA_MMC_STATE_LABEL( state ) );
20851 +static inline void pxa_mmc_set_state( mmc_controller_t ctrlr, pxa_mmc_state_t state )
20853 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
20855 + hostdata->state = state;
20858 +static inline int pxa_mmc_init_completion( mmc_controller_t ctrlr, u32 mask )
20861 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
20863 + if ( xchg( &hostdata->busy, 1 ) ) {
20864 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "another interrupt "
20865 + "is already been expected\n" );
20869 +#if CONFIG_MMC_DEBUG_IRQ
20870 + hostdata->irqcnt = 1000;
20872 + init_completion( &hostdata->completion );
20874 + MMC_I_MASK = MMC_I_MASK_ALL & ~mask;
20880 +#if CONFIG_MMC_DEBUG_IRQ
20881 +static struct timer_list timer;
20882 +static void wait_timeo( unsigned long arg ) {
20883 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)arg;
20884 + hostdata->timeo = 1;
20885 + complete( &hostdata->completion );
20890 +static inline int pxa_mmc_wait_for_completion( mmc_controller_t ctrlr, u32 mask )
20893 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
20895 + if ( !xchg( &hostdata->busy, 1 ) ) {
20896 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "there were no "
20897 + "interrupt awaited for\n" );
20901 +#if CONFIG_MMC_DEBUG_IRQ
20902 + hostdata->timeo = 0;
20903 + del_timer( &timer );
20904 + timer.function = wait_timeo;
20905 + timer.expires = jiffies + 1UL*HZ;
20906 + timer.data = (unsigned long)hostdata;
20907 + add_timer( &timer );
20909 + wait_for_completion( &hostdata->completion );
20910 +#if CONFIG_MMC_DEBUG_IRQ
20911 + del_timer( &timer );
20912 + if ( hostdata->timeo ) {
20913 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "irq timed out: " "mask=%x stat=%x\n", mask, MMC_STAT );
20917 + /* verify interrupt */
20918 + if ( (mask == ~0UL) || !( hostdata->mmc_i_reg & ~mask ) )
20922 + xchg( &hostdata->busy, 0 );
20926 +static inline int pxa_mmc_stop_bus_clock( mmc_controller_t ctrlr )
20930 + if ( !pxa_mmc_check_state( ctrlr, PXA_MMC_FSM_CLK_OFF ) )
20933 + if ( !pxa_mmc_check_state( ctrlr, PXA_MMC_FSM_BUFFER_IN_TRANSIT ) ) {
20934 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "BUFFER_IN_TRANSIT\n" );
20938 + if ( pxa_mmc_init_completion( ctrlr, MMC_I_MASK_CLK_IS_OFF ) )
20941 + MMC_STRPCL = MMC_STRPCL_STOP_CLK;
20943 + if ( pxa_mmc_wait_for_completion( ctrlr, MMC_I_REG_CLK_IS_OFF ) )
20946 + //MMC_DEBUG( MMC_DEBUG_LEVEL3, "clock is off\n" );
20947 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_CLK_OFF );
20954 +static inline int pxa_mmc_start_bus_clock( mmc_controller_t ctrlr )
20957 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
20959 + if ( (hostdata->state != PXA_MMC_FSM_CLK_OFF)
20960 + && (hostdata->state != PXA_MMC_FSM_END_IO) ) {
20961 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "illegal state %s\n", PXA_MMC_STATE_LABEL( hostdata->state ) );
20965 + MMC_STRPCL = MMC_STRPCL_START_CLK;
20967 + //MMC_DEBUG( MMC_DEBUG_LEVEL3, "clock is on\n" );
20974 +int pxa_mmc_complete_cmd( mmc_controller_t ctrlr, mmc_response_fmt_t response )
20976 +Effects: initializes completion to wait for END_CMD_RES intr,
20977 + waits for intr to occur, checks controller and card status
20978 +Requiers: controller is in CLK_OFF state
20979 +Modifies: moves controller to the END_CMD state
20982 +static mmc_error_t pxa_mmc_complete_cmd( mmc_controller_t ctrlr, mmc_response_fmt_t format, int send_abort )
20984 + mmc_error_t ret = MMC_ERROR_GENERIC;
20985 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
20986 + int mask, nwords;
20989 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD%d(0x%04x%04x)\n", MMC_CMD & 0x3f, MMC_ARGH, MMC_ARGL);
20991 +/* FIXME: check arguments */
20993 + if ( (hostdata->state != PXA_MMC_FSM_CLK_OFF)
20994 + && (hostdata->state != PXA_MMC_FSM_END_IO) ) {
20995 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "illegal state %s\n",
20996 + PXA_MMC_STATE_LABEL( hostdata->state ) );
21000 + mask = MMC_I_MASK_END_CMD_RES;
21001 + if ( pxa_mmc_init_completion( ctrlr, mask ) )
21004 + MMC_PRTBUF = MMC_PRTBUF_BUF_FULL;
21005 +/* start the clock */
21006 + if ( pxa_mmc_start_bus_clock( ctrlr ) )
21009 +/* wait for END_CMD_RES intr */
21010 + if ( pxa_mmc_wait_for_completion( ctrlr, MMC_I_REG_END_CMD_RES ) )
21013 +/* check status */
21014 + if ( hostdata->mmc_stat & MMC_STAT_TIME_OUT_RESPONSE ) {
21015 + // MMC_DEBUG(MMC_DEBUG_LEVEL3, "response timeout\n");
21016 + ret = MMC_ERROR_TIME_OUT_RESPONSE;
21019 + } else if ( hostdata->mmc_stat & MMC_STAT_READ_TIME_OUT ) {
21020 + // MMC_DEBUG(MMC_DEBUG_LEVEL3, "read timeout\n");
21021 + ret = MMC_ERROR_READ_TIME_OUT;
21024 + } else if ( hostdata->mmc_stat & MMC_STAT_RES_CRC_ERROR ) {
21025 + // MMC_DEBUG(MMC_DEBUG_LEVEL3, "response crc err\n");
21026 + ret = MMC_ERROR_RES_CRC_ERROR;
21029 + } else if ( hostdata->mmc_stat & MMC_STAT_CRC_READ_ERROR ) {
21030 + // MMC_DEBUG(MMC_DEBUG_LEVEL3, "read crc err\n");
21031 + ret = MMC_ERROR_CRC_READ_ERROR;
21034 + } else if ( hostdata->mmc_stat & MMC_STAT_CRC_WRITE_ERROR ) {
21035 + // MMC_DEBUG(MMC_DEBUG_LEVEL3, "write crc err\n");
21036 + ret = MMC_ERROR_CRC_WRITE_ERROR;
21040 + nwords = (format == MMC_NORESPONSE) ? 0 :
21041 + (format == MMC_R1) ? 3 :
21042 + (format == MMC_R2) ? 8 :
21043 + (format == MMC_R3) ? 3 :
21046 + if ( nwords > 0 ) {
21049 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "nwords=%d\n", nwords );
21050 + for ( i = nwords - 1; i >= 0 ; i-- ) {
21051 + u32 res = MMC_RES;
21052 + int ibase = i<<1;
21054 + hostdata->mmc_res[ibase] = ((u8 *)&res)[0];
21055 + hostdata->mmc_res[ibase + 1] = ((u8 *)&res)[1];
21058 +#ifdef CONFIG_MMC_DEBUG
21059 + switch ( format ) {
21061 + MMC_DUMP_R1( ctrlr );
21064 + MMC_DUMP_R2( ctrlr );
21067 + MMC_DUMP_R3( ctrlr );
21070 + MMC_DEBUG( MMC_DEBUG_LEVEL3,
21071 + "unknown response format\n" );
21072 + ret = MMC_ERROR_GENERIC;
21077 +/* check card status for R1(b) commands */
21078 + if ( format == MMC_R1 ) {
21081 + ((u8 *)&status)[0] = hostdata->mmc_res[1];
21082 + ((u8 *)&status)[1] = hostdata->mmc_res[2];
21083 + ((u8 *)&status)[2] = hostdata->mmc_res[3];
21084 + ((u8 *)&status)[3] = hostdata->mmc_res[4];
21085 + cmd = PXA_MMC_RESPONSE( ctrlr, 5 )&0x3f;
21086 + MMC_DEBUG( MMC_DEBUG_LEVEL3,
21087 + //printk( KERN_INFO __FUNCTION__"(): "
21088 + "cmd=%u status: 0x%08x\n",
21095 + if ( !(status & 0x00000100) ) /* FIXME */
21100 + if ( status & MMC_CARD_STATUS_OUT_OF_RANGE ) {
21101 + ret = MMC_ERROR_OUT_OF_RANGE;
21103 + } else if ( status & MMC_CARD_STATUS_ADDRESS_ERROR ) {
21104 + ret = MMC_ERROR_ADDRESS_ERROR;
21106 + } else if ( status & MMC_CARD_STATUS_BLOCK_LEN_ERROR ) {
21107 + ret = MMC_ERROR_ADDRESS_ERROR;
21109 + } else if ( status & MMC_CARD_STATUS_ERASE_SEQ_ERROR ) {
21110 + ret = MMC_ERROR_ERASE_SEQ_ERROR;
21112 + } else if ( status & MMC_CARD_STATUS_ERASE_PARAM ) {
21113 + ret = MMC_ERROR_ERASE_PARAM;
21115 + } else if ( status & MMC_CARD_STATUS_WP_VIOLATION ) {
21116 + ret = MMC_ERROR_WP_VIOLATION;
21118 + } else if ( status & MMC_CARD_STATUS_CARD_IS_LOCKED ) {
21119 + ret = MMC_ERROR_CARD_IS_LOCKED;
21121 + } else if ( status & MMC_CARD_STATUS_LOCK_UNLOCK_FAILED ) {
21122 + ret = MMC_ERROR_LOCK_UNLOCK_FAILED;
21124 + } else if ( status & MMC_CARD_STATUS_COM_CRC_ERROR ) {
21125 + ret = MMC_ERROR_COM_CRC_ERROR;
21127 + } else if ( status & MMC_CARD_STATUS_ILLEGAL_COMMAND ) {
21128 + ret = MMC_ERROR_ILLEGAL_COMMAND;
21130 + } else if ( status & MMC_CARD_STATUS_CARD_ECC_FAILED ) {
21131 + ret = MMC_ERROR_CARD_ECC_FAILED;
21133 + } else if ( status & MMC_CARD_STATUS_CC_ERROR ) {
21134 + ret = MMC_ERROR_CC_ERROR;
21136 + } else if ( status & MMC_CARD_STATUS_ERROR ) {
21137 + ret = MMC_ERROR_ERROR;
21139 + } else if ( status & MMC_CARD_STATUS_UNDERRUN ) {
21140 + ret = MMC_ERROR_UNDERRUN;
21142 + } else if ( status & MMC_CARD_STATUS_OVERRUN ) {
21143 + ret = MMC_ERROR_OVERRUN;
21145 + } else if ( status & MMC_CARD_STATUS_CID_CSD_OVERWRITE ) {
21146 + ret = MMC_ERROR_CID_CSD_OVERWRITE;
21148 + } else if ( status & MMC_CARD_STATUS_ERASE_RESET ) {
21149 + ret = MMC_ERROR_ERASE_RESET;
21156 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_END_CMD );
21160 + if ( send_abort ) {
21161 + /* send CMD12 to abort failed transfer */
21162 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21165 + MMC_CMD = CMD(12); /* STOP_TRANSMISSION */
21166 + MMC_CMDAT = MMC_CMDAT_R1;
21168 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE )) )
21176 + /* move controller to the IDLE state */
21177 + pxa_mmc_stop_bus_clock( ctrlr );
21178 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_IDLE );
21184 +int pxa_mmc_complete_io( mmc_controller_t ctrlr, mmc_dir_t cmd, mmc_dir_t dir, mmc_transfer_mode_t mode )
21186 +Effects: finilizes data transfer request
21187 +Reqires: controller is in the END_BUFFER state
21188 +Modifies: moves controller to the IDLE state
21189 +Returns: zero upon success or error condition code otherwise
21191 +static mmc_error_t pxa_mmc_complete_io( mmc_controller_t ctrlr, mmc_dir_t dir, mmc_transfer_mode_t mode )
21193 + int ret = MMC_ERROR_GENERIC;
21195 + if ( pxa_mmc_check_state( ctrlr, PXA_MMC_FSM_END_IO ) )
21198 + switch ( mode ) {
21199 + case MMC_TRANSFER_MODE_STREAM: /* FIXME */
21200 + if ( dir == MMC_WRITE ) {
21201 + /* 1. wait for STOP_CMD intr */
21202 + if ( (ret = pxa_mmc_init_completion( ctrlr,
21203 + MMC_I_MASK_STOP_CMD )) )
21205 + if ( (ret = pxa_mmc_wait_for_completion( ctrlr,
21206 + MMC_I_REG_STOP_CMD )) )
21209 + /* 2. send CMD12 */
21210 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21213 + MMC_CMD = CMD(12); /* STOP_TRANSMISSION */
21214 + MMC_CMDAT = MMC_CMDAT_R1;
21215 + if ( dir == MMC_WRITE )
21216 + MMC_CMDAT |= MMC_CMDAT_BUSY;
21218 + /* 3. wait for CMD12 to complete */
21219 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "ready for CMD12\n" );
21220 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE )) )
21223 + /* 4. wait for DATA_TRAN_DONE intr */
21224 + if ( (ret = pxa_mmc_init_completion( ctrlr,
21225 + MMC_I_MASK_DATA_TRAN_DONE )) )
21227 + if ( (ret = pxa_mmc_wait_for_completion( ctrlr,
21228 + MMC_I_REG_DATA_TRAN_DONE )) )
21231 + if ( dir == MMC_WRITE ) {
21232 + /* 5. wait for PRG_DONE intr */
21233 + if ( (ret = pxa_mmc_init_completion( ctrlr,
21234 + MMC_I_MASK_PRG_DONE )) )
21236 + if ( (ret = pxa_mmc_wait_for_completion( ctrlr,
21237 + MMC_I_REG_PRG_DONE )) )
21241 + case MMC_TRANSFER_MODE_BLOCK_MULTIPLE:
21242 + /* 1. wait for DATA_TRAN done intr */
21243 + if ( (ret = pxa_mmc_init_completion( ctrlr,
21244 + MMC_I_MASK_DATA_TRAN_DONE )) )
21246 + if ( (ret = pxa_mmc_wait_for_completion( ctrlr,
21247 + MMC_I_REG_DATA_TRAN_DONE )) )
21250 + /* 2. send CMD12 */
21251 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21254 + MMC_CMD = CMD(12); /* STOP_TRANSMISSION */
21255 + MMC_CMDAT = MMC_CMDAT_R1;
21256 + if ( dir == MMC_WRITE )
21257 + MMC_CMDAT |= MMC_CMDAT_BUSY;
21259 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD12\n" );
21260 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE )) )
21263 + if ( dir == MMC_WRITE ) {
21264 + /* 3. wait for PRG_DONE intr */
21265 + if ( (ret = pxa_mmc_init_completion( ctrlr,
21266 + MMC_I_MASK_PRG_DONE )) )
21268 + if ( (ret = pxa_mmc_wait_for_completion( ctrlr,
21269 + MMC_I_REG_PRG_DONE )) )
21273 + case MMC_TRANSFER_MODE_BLOCK_SINGLE:
21274 + /* 1. wait for DATA_TRAN_DONE intr */
21275 + if ( (ret = pxa_mmc_init_completion( ctrlr,
21276 + MMC_I_MASK_DATA_TRAN_DONE )) )
21278 + if ( (ret = pxa_mmc_wait_for_completion( ctrlr,
21279 + MMC_I_REG_DATA_TRAN_DONE )) )
21282 + if ( dir == MMC_WRITE ) {
21283 + /* 2. wait for PRG_DONE intr */
21284 + if ( (ret = pxa_mmc_init_completion( ctrlr,
21285 + MMC_I_MASK_PRG_DONE )) )
21287 + if ( (ret = pxa_mmc_wait_for_completion( ctrlr,
21288 + MMC_I_REG_PRG_DONE )) )
21293 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "unknown transfer mode\n" );
21296 +/* move the controller to the IDLE state */
21297 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21300 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_IDLE );
21307 +static inline int pxa_mmc_update_acq( mmc_controller_t ctrlr )
21309 + int ret = -EINVAL;
21310 + pxa_mmc_hostdata_t hostdata = NULL;
21311 + mmc_card_t card = NULL;
21312 + mmc_card_stack_rec_t fake;
21313 + mmc_card_stack_t stack = &fake;
21314 + u16 argl = 0U, argh = 0U;
21320 + hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
21322 + __mmc_card_stack_init( stack );
21324 + /* max open-drain mode frequency is 400kHZ */
21325 + MMC_CLKRT = MMC_CLKRT_0_3125MHZ;
21326 + MMC_RESTO = MMC_RES_TO_MAX; /* set response timeout */
21328 + /* discover and add cards to the stack */
21329 + /* I. bus operation condition setup */
21330 + /* 1) send CMD1 */
21331 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21337 + MMC_CMD = CMD(1);
21341 + MMC_CMDAT = MMC_CMDAT_BUSY|MMC_CMDAT_R3;
21343 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD1(0x%04x%04x)\n", argh, argl );
21344 + ret = pxa_mmc_complete_cmd( ctrlr, MMC_R3, FALSE );
21346 + argh = (PXA_MMC_RESPONSE( ctrlr, 4 ) << 8)
21347 + | PXA_MMC_RESPONSE( ctrlr, 3 );
21348 + argl = (PXA_MMC_RESPONSE( ctrlr, 2 ) << 8)
21349 + | PXA_MMC_RESPONSE( ctrlr, 1 );
21351 + } else if ( ret != MMC_ERROR_TIME_OUT_RESPONSE )
21354 + if ( !argh && !argl ) {
21355 + MMC_DEBUG( MMC_DEBUG_LEVEL3,
21356 + "assuming full voltage range support\n" );
21361 + /* 2) continuously send CMD1 'till there're busy cards */
21363 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21366 + MMC_CMD = CMD(1);
21370 + MMC_CMDAT = MMC_CMDAT_BUSY|MMC_CMDAT_R3;
21372 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD1(0x%04x%04x)\n", argh, argl );
21373 + ret = pxa_mmc_complete_cmd( ctrlr, MMC_R3, FALSE );
21374 + if ( ret == MMC_ERROR_TIME_OUT_RESPONSE )
21377 + else if ( !ret ) {
21378 + /* busy state reported by LOW signal level
21379 + * (MMC v3.2, p.58)
21381 + * Thanks to Alexander Samoutin :)
21383 + if ( !(PXA_MMC_RESPONSE( ctrlr, 4 ) & 0x80) ) {
21384 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "busy state reported\n");
21393 +/* II. card identification: the cards in Ready state
21394 + * are the only expected to respond
21400 + /* 1) send CMD2 */
21401 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21404 + MMC_CMD = CMD(2);
21405 + MMC_ARGH = 0x0003;
21406 + MMC_ARGL = 0xf300;
21407 + MMC_CMDAT = MMC_CMDAT_R2;
21409 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD2(0x%04x%04x)\n", argh, argl );
21410 + ret = pxa_mmc_complete_cmd( ctrlr, MMC_R2, FALSE );
21411 + if ( ret == MMC_ERROR_TIME_OUT_RESPONSE )
21414 + else if ( ret ) /* bus error */
21417 + /* TODO: store CID for the card */
21419 + /* 2) assign RCA */
21420 + if ( !++ctrlr->rca_next ) /* overflow */
21421 + ++ctrlr->rca_next;
21422 + argh = ctrlr->rca_next;
21424 + /* 3) send it to the card last responded (CMD3) */
21425 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21428 + MMC_CMD = CMD(3);
21431 + MMC_CMDAT = MMC_CMDAT_R1;
21433 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD3(0x%04x%04x)\n", argh, argl );
21434 + ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE );
21435 + if ( ret ) /* CMD3 failed */
21438 + card = __mmc_card_alloc( sizeof( pxa_mmc_card_data_rec_t ) );
21440 + MMC_ERROR( "out of memory\n" );
21444 + card->info.rca = argh;
21445 + card->slot = ctrlr->slot_next++; /* FIXME: minor encoding */
21446 + card->ctrlr = ctrlr;
21448 + if ( !__mmc_card_stack_add( stack, card ) )
21451 + MMC_DEBUG( MMC_DEBUG_LEVEL2, "added card: "
21452 + "slot %d, RCA=0x%04x\n", card->slot, argh );
21457 +/* III. read CSD registers of all cards; DSR support also reported there */
21458 + for ( card = stack->first; card; card = card->next ) {
21459 + pxa_mmc_card_data_t card_data =
21460 + (pxa_mmc_card_data_t)card->card_data;
21462 + /* 1) send CMD9 */
21463 + argh = card->info.rca;
21466 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21469 + MMC_CMD = CMD(9);
21472 + MMC_CMDAT = MMC_CMDAT_R2;
21474 + MMC_DEBUG( MMC_DEBUG_LEVEL3,
21475 + "CMD9(0x%04x%04x)\n", argh, argl );
21476 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R2, FALSE )) )
21479 + memcpy( &card->info.csd, hostdata->mmc_res, 15 );
21480 + MMC_DUMP_CSD( card );
21482 + card->info.read_bl_len = (1<<card->info.csd.read_bl_len);
21483 + card->info.write_bl_len = (1<<card->info.csd.write_bl_len);
21484 + card->info.capacity = (card->info.csd.c_size + 1)
21485 + * (1<<(card->info.csd.c_size_mult + 2))
21486 + * card->info.read_bl_len;
21487 + MMC_DEBUG( MMC_DEBUG_LEVEL2, "card capacity=%dMb\n",
21488 + card->info.capacity>>20 );
21489 + card->info.tran_speed = 20*1024; /* FIXME */
21490 + card->info.transfer_mode = MMC_TRANSFER_MODE_BLOCK_SINGLE;
21491 + /* 2) set bus operation freq */
21492 + card_data->clkrt = pxa_mmc_clkrt( card->info.tran_speed );
21493 + /* 3) register card with MMC core */
21494 + mmc_register( MMC_REG_TYPE_CARD, card, 0 );
21496 +/* IV. set DSR registers of the cards */
21498 + if ( card->info.csd.dsr_imp ) {
21500 + /* calculate DSR */
21509 +/* merge list of the newly inserted cards into controller card stack */
21510 + if ( !ctrlr->stack.ncards ) {
21511 + ctrlr->stack.first = stack->first;
21512 + ctrlr->stack.last = stack->last;
21514 + ctrlr->stack.last->next = stack->first;
21516 + ctrlr->stack.ncards += stack->ncards;
21521 + __mmc_card_stack_free( stack );
21527 +/* MMC protocol macros: v3.4, p.120 */
21528 +static int pxa_mmc_init_card_stack( mmc_controller_t ctrlr )
21531 + u16 argl = 0U, argh = 0U;
21533 + if ( !ctrlr || ctrlr->stack.ncards ) {
21538 + /* initialize stack */
21539 + /* 1) send CMD0 */
21540 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21543 + /* max open-drain mode frequency is 400kHZ */
21544 + MMC_CLKRT = MMC_CLKRT_0_3125MHZ;
21545 + MMC_RESTO = MMC_RES_TO_MAX; /* set response timeout */
21546 + MMC_SPI = MMC_SPI_DISABLE;
21548 + MMC_CMD = CMD(0); /* CMD0 with zero argument */
21551 + MMC_CMDAT = MMC_CMDAT_INIT;
21553 + //MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD0(0x%04x%04x)\n", argh, argl );
21554 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_NORESPONSE, FALSE )) )
21557 + /* update card stack */
21558 + if ( (ret = pxa_mmc_update_acq( ctrlr )) )
21561 + /* move the controller to the IDLE state */
21562 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21565 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_IDLE );
21568 + MMC_DEBUG( MMC_DEBUG_LEVEL2, "ncards=%d\n", ctrlr->stack.ncards );
21572 + __mmc_card_stack_free( &ctrlr->stack );
21578 +static int pxa_mmc_check_card_stack( mmc_controller_t ctrlr )
21586 + if ( ctrlr->stack.ncards > 0 ) {
21587 +/* for each card in the stack: */
21588 + for( card = ctrlr->stack.first; card; card = card->next ) {
21589 + u16 argh = card->info.rca;
21592 +/* 1) send CMD9( card->rca ) */
21593 + if ( pxa_mmc_stop_bus_clock( ctrlr ) )
21596 + /* SanDisk's cards do not respond to CMD9 */
21597 + MMC_CMD = CMD(13);
21600 + MMC_CMDAT = MMC_CMDAT_R1;
21602 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD13(0x%04x%04x)\n",
21604 + ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE );
21605 +/* 2) if card responded, it is still there */
21607 + card->state = MMC_CARD_STATE_UNPLUGGED;
21615 +/* This procedure links the bus master with a single card
21616 + * 1) cross checks with the internal stack management data if a card still
21617 + * exists in the slot
21618 + * 2) send CMD7( card->public.rca )
21619 + * 3) setup data path and controller options
21621 +static int pxa_mmc_setup_card( mmc_controller_t ctrlr, mmc_card_t card )
21623 + int ret = -ENODEV;
21624 + pxa_mmc_hostdata_t hostdata;
21625 + pxa_mmc_card_data_t card_data;
21627 +#ifdef CONFIG_MMC_DEBUG
21631 + if ( !ctrlr || !card ) {
21636 + if ( card->ctrlr != ctrlr ) {
21637 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "card is on another bus\n" );
21641 + hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
21642 + card_data = (pxa_mmc_card_data_t)card->card_data;
21644 + argh = card->info.rca;
21646 +/* select requested card */
21647 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21650 + MMC_CMD = CMD(7);
21652 + MMC_CMDAT = MMC_CMDAT_R1;
21654 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD7(0x%04x%04x)\n", argh, argl );
21655 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE )) )
21658 +/* set controller options */
21659 +#ifndef CONFIG_MMC_DEBUG
21660 + MMC_CLKRT = card_data->clkrt;
21662 +/* move the controller to the IDLE state */
21663 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21666 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_IDLE );
21673 +static inline int pxa_mmc_iobuf_init( mmc_controller_t ctrlr, ssize_t cnt )
21676 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
21681 + hostdata->iobuf.buf.pos = hostdata->iobuf.iodata;
21682 + hostdata->iobuf.buf.cnt = cnt;
21686 +/* TODO: ssize_t pxa_mmc_read_buffer( mmc_controller_t ctrlr, ssize_t cnt )
21687 +effects: reads at most cnt bytes from the card to the controller I/O buffer;
21688 + takes care of partial data transfers
21690 +modifies: ctrlr->iobuf
21691 +returns: number of bytes actually transferred or negative error code if there were any errors
21693 +ssize_t pxa_mmc_read_buffer( mmc_controller_t ctrlr, ssize_t cnt )
21695 + ssize_t ret = -EIO;
21696 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
21698 + register int ndesc;
21699 + int chan = hostdata->iobuf.buf.chan;
21700 + pxa_dma_desc *desc;
21703 + if ( (hostdata->state != PXA_MMC_FSM_END_CMD) && (hostdata->state != PXA_MMC_FSM_END_BUFFER) ) {
21707 + if ( cnt > hostdata->iobuf.bufsz )
21708 + cnt = hostdata->iobuf.bufsz;
21710 + if ( (ret = pxa_mmc_iobuf_init( ctrlr, cnt )) )
21713 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_BUFFER_IN_TRANSIT );
21715 + if ( pxa_mmc_init_completion( ctrlr, ~MMC_I_MASK_ALL ) ) /* FIXME */
21718 + if ( (desc = hostdata->iobuf.buf.last_read_desc) ) {
21719 + desc->ddadr &= ~DDADR_STOP;
21720 + desc->dcmd &= ~(DCMD_ENDIRQEN|DCMD_LENGTH);
21721 + desc->dcmd |= (1<<5);
21723 +/* 1) setup descriptors for DMA transfer from the device */
21724 + ndesc = (cnt>>5) - 1; /* FIXME: partial read */
21725 + desc = &hostdata->iobuf.buf.read_desc[ndesc];
21726 + hostdata->iobuf.buf.last_read_desc = desc;
21727 + /* TODO: partial read */
21728 + desc->ddadr |= DDADR_STOP;
21729 + desc->dcmd |= DCMD_ENDIRQEN;
21730 +/* 2) start DMA channel */
21731 + DDADR( chan ) = hostdata->iobuf.buf.read_desc_phys_addr;
21732 + DCSR( chan ) |= DCSR_RUN;
21734 + if ( pxa_mmc_init_completion( ctrlr, MMC_I_MASK_RXFIFO_RD_REQ ) )
21738 + if ( pxa_mmc_wait_for_completion( ctrlr, ~0UL ) )
21741 + if ( pxa_mmc_check_state( ctrlr, PXA_MMC_FSM_END_BUFFER ) )
21744 + if ( !(hostdata->mmc_stat & MMC_STAT_ERRORS) ) /* FIXME */
21750 +ssize_t pxa_mmc_write_buffer( mmc_controller_t ctrlr, ssize_t cnt )
21752 + ssize_t ret = -EIO;
21753 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
21755 + register int ndesc;
21756 + int chan = hostdata->iobuf.buf.chan;
21757 + pxa_dma_desc *desc;
21760 + if ( (hostdata->state != PXA_MMC_FSM_END_CMD)
21761 + && (hostdata->state != PXA_MMC_FSM_END_BUFFER) ) {
21762 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "unexpected state (%s)\n",
21763 + PXA_MMC_STATE_LABEL( hostdata->state ) );
21767 + if ( cnt > hostdata->iobuf.bufsz )
21768 + cnt = hostdata->iobuf.bufsz;
21770 + if ( (ret = pxa_mmc_iobuf_init( ctrlr, cnt )) )
21773 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_BUFFER_IN_TRANSIT );
21775 + if ( pxa_mmc_init_completion( ctrlr, ~MMC_I_MASK_ALL ) ) /* FIXME */
21777 + if ( (desc = hostdata->iobuf.buf.last_write_desc) ) {
21778 + desc->ddadr &= ~DDADR_STOP;
21779 + desc->dcmd &= ~(DCMD_ENDIRQEN|DCMD_LENGTH);
21780 + desc->dcmd |= (1<<5);
21782 +/* 1) setup descriptors for DMA transfer to the device */
21783 + ndesc = (cnt>>5) - 1; /* FIXME: partial write */
21784 + desc = &hostdata->iobuf.buf.write_desc[ndesc];
21785 + /* TODO: partial write */
21786 + hostdata->iobuf.buf.last_write_desc = desc;
21787 + desc->ddadr |= DDADR_STOP;
21788 + desc->dcmd |= DCMD_ENDIRQEN;
21789 +/* 2) start DMA channel */
21790 + DDADR( chan ) = hostdata->iobuf.buf.write_desc_phys_addr;
21791 + DCSR( chan ) |= DCSR_RUN;
21793 + if ( pxa_mmc_init_completion( ctrlr, MMC_I_MASK_TXFIFO_WR_REQ ) )
21796 + if ( pxa_mmc_wait_for_completion( ctrlr, ~0UL ) )
21799 + if ( pxa_mmc_check_state( ctrlr, PXA_MMC_FSM_END_BUFFER ) )
21802 + if ( !(hostdata->mmc_stat & MMC_STAT_ERRORS) ) /* FIXME */
21808 +/* TODO: ssize_t pxa_mmc_copy_from_buffer( ctrlr, mmc_buftype_t to, char *buf, ssize_t cnt )
21809 +effects: copies at most cnt bytes from the controller I/O buffer to the user or kernel buffer
21813 +returns: number of bytes actually transferred or negative error code if there were any errors
21815 +ssize_t pxa_mmc_copy_from_buffer( mmc_controller_t ctrlr, mmc_buftype_t to, char *buf, ssize_t cnt )
21817 + ssize_t ret = -EIO;
21818 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
21821 +/* TODO: check that DMA channel is not running */
21825 + if ( copy_to_user( buf, hostdata->iobuf.iodata, cnt ) ) {
21831 + memcpy( buf, hostdata->iobuf.iodata, cnt );
21834 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "unknown buffer type\n" );
21842 +ssize_t pxa_mmc_copy_to_buffer( mmc_controller_t ctrlr, mmc_buftype_t to, char *buf, ssize_t cnt )
21844 + ssize_t ret = -EIO;
21845 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
21847 +/* check that DMA channel is not running */
21851 + if ( copy_from_user( hostdata->iobuf.iodata, buf, cnt ) ) {
21857 + memcpy( hostdata->iobuf.iodata, buf, cnt );
21860 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "unknown buffer type\n" );
21868 +/* This procedure sequentally passes the data from the user buffer to the card */
21869 +static int pxa_mmc_stream_read( mmc_controller_t ctrlr, mmc_data_transfer_req_t transfer )
21872 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
21873 + u16 argh = 0UL, argl = 0UL;
21874 + ssize_t size = 0;
21876 + while ( transfer->cnt > 0 ) {
21877 + size = (transfer->cnt < hostdata->iobuf.blksz) ?
21878 + transfer->cnt : hostdata->iobuf.blksz;
21879 + /* 1. send CMD11 */
21880 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21883 + argh = transfer->addr >> 16;
21884 + argl = transfer->addr;
21885 + /* 2. setup controller registers to start stream data transfer */
21886 + MMC_CMD = CMD(11); /* READ_DAT_UNTIL_STOP */
21889 + MMC_NOB = 0xffff;
21890 + MMC_BLKLEN = size;
21891 + MMC_CMDAT = MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_STREAM|MMC_CMDAT_DATA_EN;
21893 + MMC_CMDAT |= MMC_CMDAT_MMC_DMA_EN;
21895 + /* 3. wait for cmd to complete */
21896 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD11(0x%04x%04x)\n", argh, argl );
21897 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, TRUE )) )
21900 + /* 4. transfer the data to the caller supplied buffer */
21901 + if ( (ret = pxa_mmc_read_buffer( ctrlr, size )) < 0 )
21904 + if ( (ret = pxa_mmc_copy_from_buffer( ctrlr, transfer->type, transfer->buf, ret )) < 0 )
21907 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_END_IO );
21909 + if ( (ret = pxa_mmc_complete_io( ctrlr, transfer->cmd, transfer->mode )) )
21912 + transfer->buf += ret;
21913 + transfer->addr += ret;
21914 + transfer->cnt -= ret;
21921 +/* This procedure reads a data block from a card at a given kernel address */
21922 +static int pxa_mmc_read_block( mmc_controller_t ctrlr, mmc_data_transfer_req_t transfer )
21924 + int ret = -ENODEV;
21925 + u16 argh = 0UL, argl = 0UL;
21927 +/* send CMD16 (SET_BLOCK_LEN) when requested block size is not the default
21928 + * for the current card */
21929 + if ( transfer->blksz != ctrlr->stack.selected->info.read_bl_len ) {
21930 + argh = transfer->blksz >> 16;
21931 + argl = transfer->blksz;
21932 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21935 + MMC_CMD = CMD(16); /* SET_BLOCK_LEN */
21938 + MMC_CMDAT = MMC_CMDAT_R1;
21940 + MMC_DEBUG( MMC_DEBUG_LEVEL3,
21941 + "CMD16(0x%04x%04x)\n", argh, argl );
21942 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE )) )
21946 +/* CMD17 (READ_SINGLE_BLOCK) */
21947 + argh = transfer->addr >> 16;
21948 + argl = transfer->addr;
21949 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
21952 + MMC_CMD = CMD(17); /* READ_SINGLE_BLOCK */
21955 + MMC_CMDAT = MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN;
21957 + MMC_BLKLEN = transfer->blksz;
21959 + MMC_CMDAT |= MMC_CMDAT_MMC_DMA_EN;
21962 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD17(0x%04x%04x)\n", argh, argl );
21963 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE )) )
21966 +/* transfer the data to the caller supplied buffer */
21967 + if ( (ret = pxa_mmc_read_buffer( ctrlr, transfer->blksz )) < 0 )
21970 + if ( (ret = pxa_mmc_copy_from_buffer( ctrlr, transfer->type, transfer->buf, ret )) < 0 )
21973 + transfer->buf += ret;
21974 + transfer->cnt -= ret;
21975 + transfer->nob -= 1;
21977 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_END_IO );
21979 + if ( (ret = pxa_mmc_complete_io( ctrlr, transfer->cmd, transfer->mode )) )
21987 +/* This procedure sequentally reads data blocks from
21988 + * a card to the user buffer. Controller options and block size
21989 + * are already set by setup_card(). Data alignment and partial
21990 + * data accessibility assumed to be checked by mmc_core */
21991 +static int pxa_mmc_read_mblock( mmc_controller_t ctrlr, mmc_data_transfer_req_t transfer )
21994 + u16 argh = 0UL, argl = 0UL;
21996 +/* send CMD16 (SET_BLOCK_LEN) when requested block size is not the default
21997 + * for the current card */
21998 + if ( transfer->blksz != ctrlr->stack.selected->info.read_bl_len ) {
21999 + argh = transfer->blksz >> 16;
22000 + argl = transfer->blksz;
22001 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
22004 + MMC_CMD = CMD(16); /* SET_BLOCK_LEN */
22007 + MMC_CMDAT = MMC_CMDAT_R1;
22009 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD16(0x%04x%04x)\n", argh, argl );
22010 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE )) )
22014 + argh = transfer->addr >> 16;
22015 + argl = transfer->addr;
22016 +/* 1. stop bus clock */
22017 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
22020 +/* 2. setup controller registers to start multiple block transfer */
22021 + MMC_CMD = CMD(18); /* READ_MULTIPLE_BLOCK */
22024 + MMC_NOB = transfer->nob;
22025 + MMC_BLKLEN = transfer->blksz;
22026 + MMC_CMDAT = MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN;
22028 + MMC_CMDAT |= MMC_CMDAT_MMC_DMA_EN;
22031 +/* 3. start clock */
22032 + if ( (ret = pxa_mmc_start_bus_clock( ctrlr )) )
22035 +/* 4. wait for cmd to complete */
22036 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD18(0x%04x%04x)\n", argh, argl );
22037 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, TRUE )) )
22040 +/* 6. transfer the data to the caller supplied buffer */
22041 + while ( transfer->cnt > 0 ) {
22042 + if ( (ret = pxa_mmc_read_buffer( ctrlr, transfer->cnt )) < 0 )
22045 + if ( (ret = pxa_mmc_copy_from_buffer( ctrlr, transfer->type, transfer->buf, ret )) < 0 )
22048 + transfer->buf += ret;
22049 + transfer->cnt -= ret;
22052 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_END_IO );
22054 + if ( (ret = pxa_mmc_complete_io( ctrlr, transfer->cmd, transfer->mode )) )
22062 +/* Sequentally writes the data from a user buffer to the card */
22063 +static int pxa_mmc_stream_write( mmc_controller_t ctrlr, mmc_data_transfer_req_t transfer )
22066 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
22067 + u16 argh = 0UL, argl = 0UL;
22068 + ssize_t size = 0;
22070 + __ENTER( "transfer: cmd=%d mode=%d type=%d blksz=%d "
22071 + "nob=%d buf=%p cnt=%d addr=%Lx", transfer->cmd,
22072 + transfer->mode, transfer->type, transfer->blksz,
22073 + transfer->nob, transfer->buf, transfer->cnt, transfer->addr );
22075 + argh = transfer->addr >> 16;
22076 + argl = transfer->addr;
22077 +/* 1. stop bus clock */
22078 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
22081 +/* 2. setup controller registers to start stream data transfer */
22082 + MMC_CMD = CMD(20); /* WRITE_DAT_UNTIL_STOP */
22085 + MMC_NOB = 0xffff;
22086 + MMC_BLKLEN = hostdata->iobuf.blksz;
22087 + MMC_CMDAT = MMC_CMDAT_R1|MMC_CMDAT_WRITE|MMC_CMDAT_STREAM|MMC_CMDAT_DATA_EN;
22089 + MMC_CMDAT |= MMC_CMDAT_MMC_DMA_EN;
22092 +/* 3. wait for cmd to complete */
22093 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD20(0x%04x%04x)\n", argh, argl );
22094 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, TRUE )) )
22097 +/* 4. transfer the data to the caller supplied buffer */
22098 + while ( transfer->cnt > 0 ) {
22099 + size = (transfer->cnt < hostdata->iobuf.blksz) ?
22100 + transfer->cnt : hostdata->iobuf.blksz;
22101 + if ( (ret = pxa_mmc_copy_to_buffer( ctrlr,
22102 + transfer->type, transfer->buf, size )) < 0 )
22105 + if ( (ret = pxa_mmc_write_buffer( ctrlr, ret )) < 0 )
22108 + transfer->buf += ret;
22109 + transfer->cnt -= ret;
22112 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_END_IO );
22114 + if ( (ret = pxa_mmc_complete_io( ctrlr, transfer->cmd, transfer->mode )) )
22122 +/* This procedure writes a data block to a card at a given address */
22123 +static int pxa_mmc_write_block( mmc_controller_t ctrlr, mmc_data_transfer_req_t transfer )
22125 + int ret = -ENODEV;
22126 + u16 argh = 0UL, argl = 0UL;
22128 +/* send CMD16 (SET_BLOCK_LEN) when requested block size is not the default
22129 + * for the current card */
22130 + if ( transfer->blksz != ctrlr->stack.selected->info.read_bl_len ) {
22131 + argh = transfer->blksz >> 16;
22132 + argl = transfer->blksz;
22133 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
22136 + MMC_CMD = CMD(16); /* SET_BLOCK_LEN */
22139 + MMC_CMDAT = MMC_CMDAT_R1;
22141 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD16(0x%04x%04x)\n", argh, argl );
22142 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE )) )
22146 +/* CMD17 (READ_SINGLE_BLOCK) */
22147 + argh = transfer->addr >> 16;
22148 + argl = transfer->addr;
22149 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
22152 + MMC_CMD = CMD(24); /* WRITE_BLOCK */
22155 + MMC_CMDAT = MMC_CMDAT_R1|MMC_CMDAT_WRITE|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN;
22157 + MMC_CMDAT |= MMC_CMDAT_MMC_DMA_EN;
22160 + MMC_BLKLEN = transfer->blksz;
22162 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD24(0x%04x%04x)\n", argh, argl );
22163 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE )) )
22166 +/* transfer the data to the caller supplied buffer */
22167 + if ( (ret = pxa_mmc_copy_to_buffer( ctrlr, transfer->type, transfer->buf, transfer->cnt )) < 0 )
22170 + if ( (ret = pxa_mmc_write_buffer( ctrlr, ret )) < 0 )
22173 + transfer->buf += ret;
22174 + transfer->cnt -= ret;
22175 + transfer->nob -= 1;
22177 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_END_IO );
22179 + if ( (ret = pxa_mmc_complete_io( ctrlr, transfer->cmd, transfer->mode )) )
22187 +/* This procedure sequentally writes data blocks to a card at a given address */
22188 +static ssize_t pxa_mmc_write_mblock( mmc_controller_t ctrlr, mmc_data_transfer_req_t transfer )
22191 + u16 argh = 0UL, argl = 0UL;
22193 +/* send CMD16 (SET_BLOCK_LEN) when requested block size is not the default
22194 + * for the current card */
22195 + if ( transfer->blksz != ctrlr->stack.selected->info.write_bl_len ) {
22196 + argh = transfer->blksz >> 16;
22197 + argl = transfer->blksz;
22198 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
22201 + MMC_CMD = CMD(16); /* SET_BLOCK_LEN */
22204 + MMC_CMDAT = MMC_CMDAT_R1;
22206 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD16(0x%04x%04x)\n", argh, argl );
22207 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE )) )
22211 + argh = transfer->addr >> 16;
22212 + argl = transfer->addr;
22213 +/* 1. stop bus clock */
22214 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
22217 +/* 2. setup controller registers to start multiple block transfer */
22218 + MMC_CMD = CMD(25); /* WRITE_MULTIPLE_BLOCK */
22221 + MMC_NOB = transfer->nob;
22222 + MMC_BLKLEN = transfer->blksz;
22223 + MMC_CMDAT = MMC_CMDAT_R1|MMC_CMDAT_WRITE|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN;
22225 + MMC_CMDAT |= MMC_CMDAT_MMC_DMA_EN;
22228 +/* 3. start clock */
22229 + if ( (ret = pxa_mmc_start_bus_clock( ctrlr )) )
22232 +/* 4. wait for cmd to complete */
22233 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD25(0x%04x%04x)\n", argh, argl );
22234 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, TRUE )) )
22237 +/* 6. transfer the data to the caller supplied buffer */
22238 + while ( transfer->cnt > 0 ) {
22239 + if ( (ret = pxa_mmc_copy_to_buffer( ctrlr, transfer->type,
22240 + transfer->buf, transfer->cnt )) < 0 )
22243 + if ( (ret = pxa_mmc_write_buffer( ctrlr, ret )) < 0 )
22246 + transfer->buf += ret;
22247 + transfer->cnt -= ret;
22250 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_END_IO );
22252 + if ( (ret = pxa_mmc_complete_io( ctrlr, transfer->cmd, transfer->mode )) )
22260 +static void pxa_mmc_irq( int irq, void *dev_id, struct pt_regs *regs )
22262 + mmc_controller_t ctrlr = (mmc_controller_t)dev_id;
22263 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
22265 + register int i, cnt;
22266 + register char *buf;
22269 + hostdata->mmc_i_reg = MMC_I_REG;
22270 + hostdata->mmc_stat = MMC_STAT;
22271 + hostdata->mmc_cmdat = MMC_CMDAT;
22273 + if (hostdata->mmc_i_reg != 0x0010) {
22274 + printk("IREG %08x", hostdata->mmc_i_reg);
22275 + if (hostdata->mmc_i_reg & 0x0001) printk(" DATA_TRAN_DONE");
22276 + if (hostdata->mmc_i_reg & 0x0002) printk(" PRG_DONE");
22277 + if (hostdata->mmc_i_reg & 0x0004) printk(" END_CMD");
22278 + if (hostdata->mmc_i_reg & 0x0008) printk(" STOP_CMD");
22279 + if (hostdata->mmc_i_reg & 0x0010) printk(" CLK_OFF");
22280 + if (hostdata->mmc_i_reg & 0x0020) printk(" RX_FIFO");
22281 + if (hostdata->mmc_i_reg & 0x0040) printk(" TX_FIFO");
22282 + printk("\nSTAT %08x", hostdata->mmc_stat);
22283 + if (hostdata->mmc_stat & 0x0001) printk(" READ_TO");
22284 + if (hostdata->mmc_stat & 0x0002) printk(" RESP_TO");
22285 + if (hostdata->mmc_stat & 0x0004) printk(" WR_CRC");
22286 + if (hostdata->mmc_stat & 0x0008) printk(" READ_CRC");
22287 + if (hostdata->mmc_stat & 0x0010) printk(" SPI_RD_TKN");
22288 + if (hostdata->mmc_stat & 0x0020) printk(" RESP_CRC");
22289 + if (hostdata->mmc_stat & 0x0040) printk(" TX_FIFO");
22290 + if (hostdata->mmc_stat & 0x0080) printk(" RX_FIFO");
22291 + if (hostdata->mmc_stat & 0x0100) printk(" CLK");
22292 + if (hostdata->mmc_stat & 0x0800) printk(" DATA_TRAN_DONE");
22293 + if (hostdata->mmc_stat & 0x1000) printk(" PRG_DONE");
22294 + if (hostdata->mmc_stat & 0x2000) printk(" END_CMD");
22299 +#if CONFIG_MMC_DEBUG_IRQ
22300 + if ( --hostdata->irqcnt <= 0 ) {
22301 + printk( KERN_INFO __FUNCTION__"(): irqcnt exceeded\n" );
22305 + switch ( hostdata->state ) {
22306 + case PXA_MMC_FSM_IDLE:
22307 + case PXA_MMC_FSM_CLK_OFF:
22308 + case PXA_MMC_FSM_END_IO:
22309 + case PXA_MMC_FSM_END_BUFFER:
22310 + case PXA_MMC_FSM_END_CMD:
22313 + case PXA_MMC_FSM_BUFFER_IN_TRANSIT:
22314 + if ( hostdata->mmc_stat & MMC_STAT_ERRORS )
22317 + buf = hostdata->iobuf.buf.pos;
22318 + cnt = (hostdata->iobuf.buf.cnt < 32) ?
22319 + hostdata->iobuf.buf.cnt : 32;
22320 + if ( hostdata->mmc_cmdat & MMC_CMDAT_WRITE ) {
22321 + if ( !(hostdata->mmc_stat & MMC_STAT_XMIT_FIFO_EMPTY) )
22323 + for ( i = 0; i < cnt; i++ )
22324 + MMC_TXFIFO = *buf++;
22326 + MMC_PRTBUF = MMC_PRTBUF_BUF_PART_FULL;
22327 + } else { /* i.e. MMC_CMDAT_READ */
22328 + if( !(hostdata->mmc_stat & MMC_STAT_RECV_FIFO_FULL) )
22330 + for( i = 0; i < cnt; i++ )
22331 + *buf++ = MMC_RXFIFO;
22334 + hostdata->iobuf.buf.pos = buf;
22335 + hostdata->iobuf.buf.cnt -= i;
22336 + if ( hostdata->iobuf.buf.cnt <= 0 ) {
22337 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_END_BUFFER );
22338 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "buffer transferred\n" );
22344 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "unexpected state %d\n",
22345 + hostdata->state );
22350 + MMC_I_MASK = MMC_I_MASK_ALL;
22351 + complete( &hostdata->completion );
22356 +static void pxa_mmc_dma_irq( int irq, void *dev_id, struct pt_regs *regs )
22358 + mmc_controller_t ctrlr = (mmc_controller_t)dev_id;
22359 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
22362 + int chan = hostdata->iobuf.buf.chan;
22364 + ddadr = DDADR( chan );
22365 + dcsr = DCSR( chan );
22366 + DCSR( chan ) = dcsr & ~DCSR_STOPIRQEN;
22368 + MMC_DEBUG( MMC_DEBUG_LEVEL3,
22369 + "MMC DMA interrupt: chan=%d ddadr=0x%08x "
22370 + "dcmd=0x%08x dcsr=0x%08x\n",
22371 + chan, ddadr, DCMD( chan ), dcsr );
22373 + if ( dcsr & DCSR_BUSERR ) {
22374 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "bus error on DMA channel %d\n",
22376 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_ERROR );
22379 +/* data transfer completed */
22380 + if ( dcsr & DCSR_ENDINTR ) {
22381 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "buffer transferred\n" );
22382 + pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_END_BUFFER );
22387 + complete( &hostdata->completion );
22393 +static int pxa_mmc_init( mmc_controller_t ctrlr )
22395 + int ret = -ENODEV;
22396 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
22399 + register pxa_dma_desc *desc;
22402 +/* hardware initialization */
22403 +/* I. prepare to transfer data */
22404 +/* 1. allocate buffer */
22406 + hostdata->iobuf.buf.read_desc = consistent_alloc( GFP_KERNEL,
22407 + (PXA_MMC_IODATA_SIZE>>5)
22408 + * sizeof( pxa_dma_desc ),
22409 + &hostdata->iobuf.buf.read_desc_phys_addr, 0 );
22410 + if ( !hostdata->iobuf.buf.read_desc ) {
22414 + hostdata->iobuf.buf.write_desc = consistent_alloc( GFP_KERNEL,
22415 + (PXA_MMC_IODATA_SIZE>>5)
22416 + * sizeof( pxa_dma_desc ),
22417 + &hostdata->iobuf.buf.write_desc_phys_addr, 0 );
22418 + if ( !hostdata->iobuf.buf.write_desc ) {
22422 + hostdata->iobuf.iodata = consistent_alloc( GFP_ATOMIC,
22423 + PXA_MMC_IODATA_SIZE,
22424 + &hostdata->iobuf.buf.phys_addr, 0 );
22426 + hostdata->iobuf.iodata = kmalloc( PXA_MMC_IODATA_SIZE, GFP_ATOMIC );
22428 + if ( !hostdata->iobuf.iodata ) {
22432 +/* 2. initialize iobuf */
22433 + hostdata->iobuf.blksz = PXA_MMC_BLKSZ_MAX;
22434 + hostdata->iobuf.bufsz = PXA_MMC_IODATA_SIZE;
22435 + hostdata->iobuf.nob = PXA_MMC_BLOCKS_PER_BUFFER;
22437 + /* request DMA channel */
22438 + if ( (hostdata->iobuf.buf.chan = pxa_request_dma( "MMC", DMA_PRIO_LOW,
22439 + pxa_mmc_dma_irq, ctrlr )) < 0 ) {
22440 + MMC_ERROR( "failed to request DMA channel\n" );
22444 + DRCMRRXMMC = hostdata->iobuf.buf.chan | DRCMR_MAPVLD;
22445 + DRCMRTXMMC = hostdata->iobuf.buf.chan | DRCMR_MAPVLD;
22447 + for ( i = 0; i < ((PXA_MMC_IODATA_SIZE>>5) - 1); i++ ) {
22448 + desc = &hostdata->iobuf.buf.read_desc[i];
22449 + desc->ddadr = hostdata->iobuf.buf.read_desc_phys_addr
22450 + + ((i + 1) * sizeof( pxa_dma_desc ));
22451 + desc->dsadr = MMC_RXFIFO_PHYS_ADDR;
22452 + desc->dtadr = hostdata->iobuf.buf.phys_addr + (i<<5);
22453 + desc->dcmd = DCMD_FLOWSRC|DCMD_INCTRGADDR
22454 + |DCMD_WIDTH1|DCMD_BURST32|(1<<5);
22456 + desc = &hostdata->iobuf.buf.write_desc[i];
22457 + desc->ddadr = hostdata->iobuf.buf.write_desc_phys_addr
22458 + + ((i + 1) * sizeof( pxa_dma_desc ));
22459 + desc->dsadr = hostdata->iobuf.buf.phys_addr + (i<<5);
22460 + desc->dtadr = MMC_TXFIFO_PHYS_ADDR;
22461 + desc->dcmd = DCMD_FLOWTRG|DCMD_INCSRCADDR
22462 + |DCMD_WIDTH1|DCMD_BURST32|(1<<5);
22464 + desc = &hostdata->iobuf.buf.read_desc[i];
22465 + desc->ddadr = (hostdata->iobuf.buf.read_desc_phys_addr +
22466 + (i + 1) * sizeof( pxa_dma_desc))|DDADR_STOP;
22467 + desc->dsadr = MMC_RXFIFO_PHYS_ADDR;
22468 + desc->dtadr = hostdata->iobuf.buf.phys_addr + (i<<5);
22469 + desc->dcmd = DCMD_FLOWSRC|DCMD_INCTRGADDR
22470 + |DCMD_WIDTH1|DCMD_BURST32|(1<<5);
22472 + desc = &hostdata->iobuf.buf.write_desc[i];
22473 + desc->ddadr = (hostdata->iobuf.buf.write_desc_phys_addr +
22474 + (i + 1) * sizeof( pxa_dma_desc))|DDADR_STOP;
22475 + desc->dsadr = hostdata->iobuf.buf.phys_addr + (i<<5);
22476 + desc->dtadr = MMC_TXFIFO_PHYS_ADDR;
22477 + desc->dcmd = DCMD_FLOWTRG|DCMD_INCSRCADDR
22478 + |DCMD_WIDTH1|DCMD_BURST32|(1<<5);
22481 +/* 1) request irq */
22482 + if ( request_irq( IRQ_MMC, pxa_mmc_irq, 0, "MMC", ctrlr ) ) {
22483 + MMC_ERROR( "failed to request IRQ_MMC\n" );
22487 +/* 2) initialize h/w and ctrlr */
22488 + set_GPIO_mode( GPIO6_MMCCLK_MD );
22489 + CKEN |= CKEN12_MMC; /* enable MMC unit clock */
22495 +/* free DMA resources */
22496 + if ( hostdata->iobuf.buf.chan >= 0 ) {
22499 + pxa_free_dma( hostdata->iobuf.buf.chan );
22501 + if ( hostdata->iobuf.iodata )
22502 + consistent_free( hostdata->iobuf.iodata,
22503 + PXA_MMC_IODATA_SIZE,
22504 + hostdata->iobuf.buf.phys_addr );
22505 + if ( hostdata->iobuf.buf.read_desc )
22506 + consistent_free( hostdata->iobuf.buf.read_desc,
22507 + (PXA_MMC_IODATA_SIZE>>5)
22508 + * sizeof( pxa_dma_desc ),
22509 + hostdata->iobuf.buf.read_desc_phys_addr );
22510 + if ( hostdata->iobuf.buf.write_desc )
22511 + consistent_free( hostdata->iobuf.buf.write_desc,
22512 + (PXA_MMC_IODATA_SIZE>>5)
22513 + * sizeof( pxa_dma_desc ),
22514 + hostdata->iobuf.buf.write_desc_phys_addr );
22516 + kfree( hostdata->iobuf.iodata );
22522 +static void pxa_mmc_remove( mmc_controller_t ctrlr )
22524 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
22526 +/* 1) free buffer(s) */
22528 + consistent_free( hostdata->iobuf.iodata, PXA_MMC_IODATA_SIZE,
22529 + hostdata->iobuf.buf.phys_addr );
22530 + consistent_free( hostdata->iobuf.buf.read_desc,
22531 + (PXA_MMC_IODATA_SIZE>>5)
22532 + * sizeof( pxa_dma_desc ),
22533 + hostdata->iobuf.buf.read_desc_phys_addr );
22534 + consistent_free( hostdata->iobuf.buf.write_desc,
22535 + (PXA_MMC_IODATA_SIZE>>5)
22536 + * sizeof( pxa_dma_desc ),
22537 + hostdata->iobuf.buf.write_desc_phys_addr );
22538 +/* 2) release DMA channel */
22539 + if ( hostdata->iobuf.buf.chan >= 0 ) {
22542 + pxa_free_dma( hostdata->iobuf.buf.chan );
22545 + kfree( hostdata->iobuf.iodata );
22548 +/* 1) release irq */
22549 + free_irq( IRQ_MMC, ctrlr );
22550 + CKEN &= ~CKEN12_MMC; /* disable MMC unit clock */
22553 +static int pxa_mmc_probe( mmc_controller_t ctrlr )
22559 +static int pxa_mmc_suspend( mmc_controller_t ctrlr )
22561 + int ret = -EBUSY;
22562 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
22564 + MMC_DEBUG( MMC_DEBUG_LEVEL2, "state=%s\n",
22565 + PXA_MMC_STATE_LABEL( hostdata->state ) );
22567 + if ( hostdata->state == PXA_MMC_FSM_IDLE ) {
22568 + /* save registers */
22569 + SAVED_MMC_CLKRT = MMC_CLKRT;
22570 + SAVED_MMC_RESTO = MMC_RESTO;
22571 + SAVED_MMC_SPI = MMC_SPI;
22572 + SAVED_DRCMRRXMMC = DRCMRRXMMC;
22573 + SAVED_DRCMRTXMMC = DRCMRTXMMC;
22577 + if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )
22580 + MMC_CMD = CMD(0); /* CMD0 with zero argument */
22585 + MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD0(0x%04x%04x)\n", 0UL, 0UL );
22586 + if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_NORESPONSE,
22594 + set_GPIO_mode( GPIO6_MMCCLK );
22595 + CKEN &= ~CKEN12_MMC; /* disable MMC unit clock */
22597 + hostdata->suspended = TRUE;
22604 +static void pxa_mmc_resume( mmc_controller_t ctrlr )
22606 + pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;
22608 + if ( hostdata->suspended == TRUE ) {
22609 + set_GPIO_mode( GPIO6_MMCCLK_MD );
22610 + CKEN |= CKEN12_MMC; /* enable MMC unit clock */
22612 + /* restore registers */
22613 + MMC_CLKRT = SAVED_MMC_CLKRT;
22614 + MMC_RESTO = SAVED_MMC_RESTO;
22615 + MMC_SPI = SAVED_MMC_SPI;
22616 + DRCMRRXMMC = SAVED_DRCMRRXMMC;
22617 + DRCMRTXMMC = SAVED_DRCMRTXMMC;
22619 + hostdata->suspended = FALSE;
22621 + mmc_update_card_stack( ctrlr->slot ); /* FIXME */
22628 +static mmc_controller_tmpl_rec_t pxa_mmc_controller_tmpl_rec = {
22629 + owner: THIS_MODULE,
22631 + block_size_max: PXA_MMC_BLKSZ_MAX,
22632 + nob_max: PXA_MMC_NOB_MAX,
22633 + probe: pxa_mmc_probe,
22634 + init: pxa_mmc_init,
22635 + remove: __devexit_p( pxa_mmc_remove ),
22637 + suspend: pxa_mmc_suspend,
22638 + resume: pxa_mmc_resume,
22639 +#endif /* CONFIG_PM */
22640 + update_acq: pxa_mmc_update_acq,
22641 +// single_card_acq: pxa_mmc_single_card_acq,
22642 + init_card_stack: pxa_mmc_init_card_stack,
22643 + check_card_stack: pxa_mmc_check_card_stack,
22644 + setup_card: pxa_mmc_setup_card,
22645 + stream_read: pxa_mmc_stream_read,
22646 + read_block: pxa_mmc_read_block,
22647 + read_mblock: pxa_mmc_read_mblock,
22648 + stream_write: pxa_mmc_stream_write,
22649 + write_block: pxa_mmc_write_block,
22650 + write_mblock: pxa_mmc_write_mblock
22652 + sg_io: pxa_mmc_sg_io
22656 + * write protection,
22657 + * lock/password management methods
22661 +static int __devinit mmc_pxa_module_init( void )
22663 + int ret = -ENODEV;
22664 +#ifdef CONFIG_ARCH_RAMSES
22669 + host = mmc_register( MMC_REG_TYPE_HOST, &pxa_mmc_controller_tmpl_rec,
22670 + sizeof( pxa_mmc_hostdata_rec_t ) );
22672 + MMC_DEBUG( MMC_DEBUG_LEVEL0,
22673 + "failed to register with MMC core\n" );
22682 +static void __devexit mmc_pxa_module_cleanup( void )
22684 + mmc_unregister( MMC_REG_TYPE_HOST, host );
22685 +#ifdef CONFIG_ARCH_RAMSES
22686 + RAMSES_MMC_OFF();
22690 +EXPORT_NO_SYMBOLS;
22692 +MODULE_LICENSE( "GPL" );
22694 +module_init( mmc_pxa_module_init );
22695 +module_exit( mmc_pxa_module_cleanup );
22697 +++ linux-2.4.27/drivers/mmc/mmc_pxa.h
22700 + * linux/drivers/mmc/mmc_pxa.h
22702 + * Author: Vladimir Shebordaev, Igor Oblakov
22703 + * Copyright: MontaVista Software Inc.
22705 + * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $
22707 + * This program is free software; you can redistribute it and/or modify
22708 + * it under the terms of the GNU General Public License version 2 as
22709 + * published by the Free Software Foundation.
22711 +#ifndef __MMC_PXA_P_H__
22712 +#define __MMC_PXA_P_H__
22714 +#include <linux/completion.h>
22718 +/* PXA-250 MMC controller registers */
22721 +#define MMC_STRPCL_STOP_CLK (0x0001UL)
22722 +#define MMC_STRPCL_START_CLK (0x0002UL)
22725 +#define MMC_STAT_END_CMD_RES (0x0001UL << 13)
22726 +#define MMC_STAT_PRG_DONE (0x0001UL << 12)
22727 +#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11)
22728 +#define MMC_STAT_CLK_EN (0x0001UL << 8)
22729 +#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7)
22730 +#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6)
22731 +#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5)
22732 +#define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4)
22733 +#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3)
22734 +#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2)
22735 +#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1)
22736 +#define MMC_STAT_READ_TIME_OUT (0x0001UL)
22738 +#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
22739 + |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
22740 + |MMC_STAT_READ_TIME_OUT)
22743 +#define MMC_CLKRT_20MHZ (0x0000UL)
22744 +#define MMC_CLKRT_10MHZ (0x0001UL)
22745 +#define MMC_CLKRT_5MHZ (0x0002UL)
22746 +#define MMC_CLKRT_2_5MHZ (0x0003UL)
22747 +#define MMC_CLKRT_1_25MHZ (0x0004UL)
22748 +#define MMC_CLKRT_0_625MHZ (0x0005UL)
22749 +#define MMC_CLKRT_0_3125MHZ (0x0006UL)
22752 +#define MMC_SPI_DISABLE (0x00UL)
22753 +#define MMC_SPI_EN (0x01UL)
22754 +#define MMC_SPI_CS_EN (0x01UL << 2)
22755 +#define MMC_SPI_CS_ADDRESS (0x01UL << 3)
22756 +#define MMC_SPI_CRC_ON (0x01UL << 1)
22759 +#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7)
22760 +#define MMC_CMDAT_INIT (0x0001UL << 6)
22761 +#define MMC_CMDAT_BUSY (0x0001UL << 5)
22762 +#define MMC_CMDAT_STREAM (0x0001UL << 4)
22763 +#define MMC_CMDAT_BLOCK (0x0000UL << 4)
22764 +#define MMC_CMDAT_WRITE (0x0001UL << 3)
22765 +#define MMC_CMDAT_READ (0x0000UL << 3)
22766 +#define MMC_CMDAT_DATA_EN (0x0001UL << 2)
22767 +#define MMC_CMDAT_R1 (0x0001UL)
22768 +#define MMC_CMDAT_R2 (0x0002UL)
22769 +#define MMC_CMDAT_R3 (0x0003UL)
22772 +#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */
22775 +#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */
22778 +#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */
22781 +#define MMC_PRTBUF_BUF_PART_FULL (0x01UL)
22782 +#define MMC_PRTBUF_BUF_FULL (0x00UL )
22785 +#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6)
22786 +#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5)
22787 +#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4)
22788 +#define MMC_I_MASK_STOP_CMD (0x01UL << 3)
22789 +#define MMC_I_MASK_END_CMD_RES (0x01UL << 2)
22790 +#define MMC_I_MASK_PRG_DONE (0x01UL << 1)
22791 +#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL)
22792 +#define MMC_I_MASK_ALL (0x07fUL)
22796 +#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6)
22797 +#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5)
22798 +#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4)
22799 +#define MMC_I_REG_STOP_CMD (0x01UL << 3)
22800 +#define MMC_I_REG_END_CMD_RES (0x01UL << 2)
22801 +#define MMC_I_REG_PRG_DONE (0x01UL << 1)
22802 +#define MMC_I_REG_DATA_TRAN_DONE (0x01UL)
22803 +#define MMC_I_REG_ALL (0x007fUL)
22806 +#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */
22807 +#define CMD(x) (x)
22813 +#define MMC_RXFIFO_PHYS_ADDR 0x41100040 //MMC_RXFIFO physical address
22815 +#define MMC_TXFIFO_PHYS_ADDR 0x41100044 //MMC_TXFIFO physical address
22817 +/* implementation specific declarations */
22818 +#define PXA_MMC_BLKSZ_MAX (1<<9) /* actually 1023 */
22819 +#define PXA_MMC_NOB_MAX ((1<<16)-2)
22820 +#define PXA_MMC_BLOCKS_PER_BUFFER (2)
22822 +#define PXA_MMC_IODATA_SIZE (PXA_MMC_BLOCKS_PER_BUFFER*PXA_MMC_BLKSZ_MAX) /* 1K */
22824 +typedef enum _pxa_mmc_fsm { /* command processing FSM */
22825 + PXA_MMC_FSM_IDLE = 1,
22826 + PXA_MMC_FSM_CLK_OFF,
22827 + PXA_MMC_FSM_END_CMD,
22828 + PXA_MMC_FSM_BUFFER_IN_TRANSIT,
22829 + PXA_MMC_FSM_END_BUFFER,
22830 + PXA_MMC_FSM_END_IO,
22831 + PXA_MMC_FSM_END_PRG,
22832 + PXA_MMC_FSM_ERROR
22833 +} pxa_mmc_state_t;
22835 +#define PXA_MMC_STATE_LABEL( state ) (\
22836 + (state == PXA_MMC_FSM_IDLE) ? "IDLE" :\
22837 + (state == PXA_MMC_FSM_CLK_OFF) ? "CLK_OFF" :\
22838 + (state == PXA_MMC_FSM_END_CMD) ? "END_CMD" :\
22839 + (state == PXA_MMC_FSM_BUFFER_IN_TRANSIT) ? "IN_TRANSIT" :\
22840 + (state == PXA_MMC_FSM_END_BUFFER) ? "END_BUFFER" :\
22841 + (state == PXA_MMC_FSM_END_IO) ? "END_IO" :\
22842 + (state == PXA_MMC_FSM_END_PRG) ? "END_PRG" : "UNKNOWN" )
22844 +typedef enum _pxa_mmc_result {
22845 + PXA_MMC_NORMAL = 0,
22846 + PXA_MMC_INVALID_STATE = -1,
22847 + PXA_MMC_TIMEOUT = -2,
22848 + PXA_MMC_ERROR = -3
22849 +} pxa_mmc_result_t;
22851 +typedef u32 pxa_mmc_clkrt_t;
22853 +typedef char *pxa_mmc_iodata_t;
22855 +typedef struct _pxa_mmc_piobuf_rec {
22856 + char *pos; /* current buffer position */
22857 + int cnt; /* byte counter */
22858 +} pxa_mmc_piobuf_rec_t, *pxa_mmc_piobuf_t;
22859 +#else /* i.e. DMA */
22860 +typedef struct _pxa_mmc_dmabuf_rec { /* TODO: buffer ring, DMA irq completion */
22861 + int chan; /* dma channel no */
22862 + dma_addr_t phys_addr; /* iodata physical address */
22863 + pxa_dma_desc *read_desc; /* input descriptor array virtual address */
22864 + pxa_dma_desc *write_desc; /* output descriptor array virtual address */
22865 + dma_addr_t read_desc_phys_addr; /* descriptor array physical address */
22866 + dma_addr_t write_desc_phys_addr; /* descriptor array physical address */
22867 + pxa_dma_desc *last_read_desc; /* last input descriptor
22868 + * used by the previous transfer
22870 + pxa_dma_desc *last_write_desc; /* last output descriptor
22871 + * used by the previous transfer
22873 +} pxa_mmc_dmabuf_rec_t, *pxa_mmc_dmabuf_t;
22876 +typedef struct _pxa_mmc_iobuf_rec {
22877 + ssize_t blksz; /* current block size in bytes */
22878 + ssize_t bufsz; /* buffer size for each transfer */
22879 + ssize_t nob; /* number of blocks pers buffer */
22881 + pxa_mmc_dmabuf_rec_t buf; /* i.e. DMA buffer ring on the iodata */
22882 +#else /* i.e. DMA */
22883 + pxa_mmc_piobuf_rec_t buf; /* PIO buffer accounting */
22885 + pxa_mmc_iodata_t iodata; /* I/O data buffer */
22886 +} pxa_mmc_iobuf_rec_t, *pxa_mmc_iobuf_t;
22888 +typedef struct _pxa_mmc_hostdata_rec {
22889 + pxa_mmc_state_t state; /* FSM */
22893 + pxa_mmc_iobuf_rec_t iobuf; /* data transfer state */
22895 + int busy; /* atomic busy flag */
22896 + struct completion completion; /* completion */
22897 +#if CONFIG_MMC_DEBUG_IRQ
22902 +/* cached controller state */
22903 + u32 mmc_i_reg; /* interrupt last requested */
22904 + u32 mmc_i_mask; /* mask to be set by intr handler */
22905 + u32 mmc_stat; /* status register at the last intr */
22906 + u32 mmc_cmdat; /* MMC_CMDAT at the last inr */
22907 + u8 mmc_res[16]; /* response to the last command in host order */
22908 + u32 saved_mmc_clkrt;
22909 + u32 saved_mmc_resto;
22910 + u32 saved_mmc_spi;
22911 + u32 saved_drcmrrxmmc;
22912 + u32 saved_drcmrtxmmc;
22914 +/* controller options */
22915 + pxa_mmc_clkrt_t clkrt; /* current bus clock rate */
22916 +} pxa_mmc_hostdata_rec_t, *pxa_mmc_hostdata_t;
22918 +#define PXA_MMC_STATUS( ctrlr ) (((pxa_mmc_hostdata_t)ctrlr->host_data)->mmc_stat)
22919 +#define PXA_MMC_RESPONSE( ctrlr, idx ) ((((pxa_mmc_hostdata_t)ctrlr->host_data)->mmc_res)[idx])
22920 +#define PXA_MMC_CLKRT( ctrlr ) (((pxa_mmc_hostdata_t)ctrlr->host_data)->clkrt)
22922 +#define SAVED_MMC_CLKRT (hostdata->saved_mmc_clkrt)
22923 +#define SAVED_MMC_RESTO (hostdata->saved_mmc_resto)
22924 +#define SAVED_MMC_SPI (hostdata->saved_mmc_spi)
22925 +#define SAVED_DRCMRRXMMC (hostdata->saved_drcmrrxmmc )
22926 +#define SAVED_DRCMRTXMMC (hostdata->saved_drcmrtxmmc )
22928 +static inline int pxa_mmc_clkrt( int speed )
22930 + return MMC_CLKRT_20MHZ; /* TODO */
22933 +/* PXA MMC controller specific card data */
22934 +typedef struct _pxa_mmc_card_data_rec {
22935 + pxa_mmc_clkrt_t clkrt; /* clock rate to be set for the card */
22936 +} pxa_mmc_card_data_rec_t, *pxa_mmc_card_data_t;
22938 +#ifdef CONFIG_MMC_DEBUG
22939 +#undef MMC_DUMP_R1
22940 +#undef MMC_DUMP_R2
22941 +#undef MMC_DUMP_R3
22942 +#define MMC_DUMP_R2( ctrlr ) MMC_DEBUG( MMC_DEBUG_LEVEL3, \
22943 +"R2 response: %02x %02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n", \
22944 +PXA_MMC_RESPONSE( ctrlr, 15 ), \
22945 +PXA_MMC_RESPONSE( ctrlr, 14 ), \
22946 +PXA_MMC_RESPONSE( ctrlr, 13 ), \
22947 +PXA_MMC_RESPONSE( ctrlr, 12 ), \
22948 +PXA_MMC_RESPONSE( ctrlr, 11 ), \
22949 +PXA_MMC_RESPONSE( ctrlr, 10 ), \
22950 +PXA_MMC_RESPONSE( ctrlr, 9 ), \
22951 +PXA_MMC_RESPONSE( ctrlr, 8 ), \
22952 +PXA_MMC_RESPONSE( ctrlr, 7 ), \
22953 +PXA_MMC_RESPONSE( ctrlr, 6 ), \
22954 +PXA_MMC_RESPONSE( ctrlr, 5 ), \
22955 +PXA_MMC_RESPONSE( ctrlr, 4 ), \
22956 +PXA_MMC_RESPONSE( ctrlr, 3 ), \
22957 +PXA_MMC_RESPONSE( ctrlr, 2 ), \
22958 +PXA_MMC_RESPONSE( ctrlr, 1 ), \
22959 +PXA_MMC_RESPONSE( ctrlr, 0 ) );
22960 +#define MMC_DUMP_R1( ctrlr ) MMC_DEBUG( MMC_DEBUG_LEVEL3, \
22961 +"R1(b) response: %02x %02x%02x%02x%02x\n", \
22962 +PXA_MMC_RESPONSE( ctrlr, 5 ), \
22963 +PXA_MMC_RESPONSE( ctrlr, 4 ), \
22964 +PXA_MMC_RESPONSE( ctrlr, 3 ), \
22965 +PXA_MMC_RESPONSE( ctrlr, 2 ), \
22966 +PXA_MMC_RESPONSE( ctrlr, 1 ) );
22967 +#define MMC_DUMP_R3( ctrlr ) MMC_DEBUG( MMC_DEBUG_LEVEL3, \
22968 +"R3 response: %02x %02x%02x%02x%02x\n", \
22969 +PXA_MMC_RESPONSE( ctrlr, 5 ), \
22970 +PXA_MMC_RESPONSE( ctrlr, 4 ), \
22971 +PXA_MMC_RESPONSE( ctrlr, 3 ), \
22972 +PXA_MMC_RESPONSE( ctrlr, 2 ), \
22973 +PXA_MMC_RESPONSE( ctrlr, 1 ) );
22976 +#endif /* __MMC_PXA_P_H__ */
22978 +++ linux-2.4.27/drivers/mmc/mmc_test.c
22981 + * linux/drivers/mmc/mmc_test.c
22983 + * Author: Vladimir Shebordaev
22984 + * Copyright: MontaVista Software Inc.
22986 + * $Id: mmc_test.c,v 0.4 2002/08/01 12:26:40 ted Exp ted $
22988 + * This program is free software; you can redistribute it and/or modify
22989 + * it under the terms of the GNU General Public License version 2 as
22990 + * published by the Free Software Foundation.
22992 +#include <linux/version.h>
22993 +#include <linux/config.h>
22994 +#include <linux/types.h>
22995 +#include <linux/init.h>
22996 +#include <linux/module.h>
22997 +#include <linux/errno.h>
22999 +#include <linux/fs.h>
23000 +#ifdef CONFIG_DEVFS_FS
23001 +#include <linux/devfs_fs_kernel.h>
23004 +#include <asm/uaccess.h>
23006 +#include <mmc/types.h>
23007 +#include <mmc/mmc.h>
23008 +#include <mmc/ioctl.h>
23010 +#include "types.h"
23013 +typedef struct _mmc_test_device_rec mmc_test_device_rec_t;
23014 +typedef struct _mmc_test_device_rec *mmc_test_device_t;
23016 +struct _mmc_test_device_rec {
23018 + mmc_transfer_mode_t transfer_mode;
23020 +#ifdef CONFIG_DEVFS_FS
23021 + devfs_handle_t devfs_handle;
23025 +/* MMC device table */
23026 +static mmc_test_device_rec_t mmc_test_device[MMC_CONTROLLERS_MAX][MMC_CARDS_MAX];
23027 +static DECLARE_MUTEX(mmc_test_device_mutex);
23029 +static inline mmc_test_device_t __mmc_test_get_device( kdev_t rdev )
23031 + mmc_test_device_t ret = NULL;
23032 + u8 minor = MINOR( rdev );
23033 + int host_no, card_no;
23035 + host_no = minor >> MMC_MINOR_HOST_SHIFT;
23036 + if ( host_no >= MMC_CONTROLLERS_MAX )
23039 + card_no = minor & MMC_MINOR_CARD_MASK;
23040 + if ( card_no >= MMC_CARDS_MAX )
23043 + ret = &mmc_test_device[host_no][card_no];
23044 + if ( !ret->card ) {
23045 + ret->card = mmc_get_card( host_no, card_no );
23046 + if ( !ret->card ) {
23047 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "failed to get card: host=%d, card=%d\n", host_no, card_no );
23059 +static inline void __mmc_test_put_device( mmc_test_device_t dev )
23061 + mmc_put_card( dev->card );
23065 +static inline mmc_test_device_t mmc_test_get_device( kdev_t kdev )
23067 + mmc_test_device_t ret = NULL;
23069 + down( &mmc_test_device_mutex );
23070 + ret = __mmc_test_get_device( kdev );
23071 + up( &mmc_test_device_mutex );
23076 +static inline void mmc_test_put_device( mmc_test_device_t dev )
23079 + down( &mmc_test_device_mutex );
23080 + __mmc_test_put_device( dev );
23081 + if ( !dev->usage ) {
23082 + if ( dev->card ) {
23083 + if ( dev->card->usage ) {
23084 + MMC_DEBUG( MMC_DEBUG_LEVEL0,
23085 + "broken card reference\n" );
23087 + memset( dev, 0, sizeof( mmc_test_device_rec_t ) );
23090 + up( &mmc_test_device_mutex );
23094 +static inline int mmc_test_set_transfer_mode( mmc_test_device_t dev, mmc_transfer_mode_t mode )
23099 + down( &mmc_test_device_mutex );
23100 + dev->transfer_mode = mode;
23102 + up( &mmc_test_device_mutex );
23107 +static inline mmc_transfer_mode_t mmc_test_get_transfer_mode( mmc_test_device_t dev )
23109 + mmc_transfer_mode_t ret = MMC_TRANSFER_MODE_UNDEFINED;
23112 + down( &mmc_test_device_mutex );
23113 + ret = dev->transfer_mode;
23114 + up( &mmc_test_device_mutex );
23119 +static int mmc_test_open( struct inode *inode, struct file *file )
23121 + int ret = -ENODEV;
23122 + mmc_test_device_t dev = NULL;
23124 + MOD_INC_USE_COUNT;
23127 + dev = mmc_test_get_device( inode->i_rdev );
23128 + if ( !dev || !dev->card ) {
23129 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "failed to acquire device\n" );
23133 + if ( dev->card->usage > 1 ) {
23138 + dev->transfer_mode = MMC_TEST_TRANSFER_MODE_DEFAULT; /* FIXME: should check card CCC */
23139 + file->private_data = dev;
23144 + MOD_DEC_USE_COUNT;
23145 + mmc_test_put_device( dev );
23146 + __LEAVE( "ret=%d", ret );
23150 +static int mmc_test_release( struct inode *inode, struct file *file )
23152 + int ret = -ENODEV;
23153 + mmc_test_device_t dev = (mmc_test_device_t)file->private_data;
23156 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "file->private_data == NULL\n" );
23160 + __ENTER( "host=%d, card=%d", dev->card->ctrlr->slot, dev->card->slot );
23162 + file->private_data = NULL;
23164 + mmc_test_put_device( dev );
23165 + MOD_DEC_USE_COUNT;
23169 + __LEAVE( "ret=%d", ret );
23173 +static ssize_t mmc_test_read( struct file *file, char *buf, size_t size, loff_t *ppos )
23175 + ssize_t ret = -ENODEV;
23176 + ssize_t retsize = 0;
23177 + mmc_test_device_t dev = (mmc_test_device_t)file->private_data;
23179 + __ENTER( "host=%d, card=%d, size=%d", dev->card->ctrlr->slot, dev->card->slot, size );
23182 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "file->private_data == NULL\n" );
23186 + switch ( dev->transfer_mode ) {
23189 + case MMC_TRANSFER_MODE_BLOCK_SINGLE:
23190 + mbuf = kmalloc( 512, GFP_ATOMIC ); /* FIXME: actual read_bl_len or ctrlr->block_size_max whichever is less ), GFP_KERNEL */
23196 + while( size > 0 ) {
23197 + int lsize = (size > 512) ? 512 : size;
23199 + MMC_DEBUG( MMC_DEBUG_LEVEL4,
23200 + "before mmc_read mbuf=0x%x "
23201 + "lsize=%d ppos=0x%x *ppos=%d\n",
23202 + mbuf, lsize, ppos, *ppos );
23203 + ret = mmc_read( dev->card,
23204 + MMC_TRANSFER_MODE_BLOCK_SINGLE,
23205 + mbuf, lsize, ppos );
23209 + /* Copy to user */
23210 + if ( copy_to_user( buf, mbuf, ret ) ) {
23219 + if ( retsize > 0 )
23224 + case MMC_TRANSFER_MODE_BLOCK_MULTIPLE:
23225 + mbuf = kmalloc( 1024, GFP_ATOMIC ); /* FIXME */
23231 + while( size > 0 ) {
23232 + int lsize = (size > 1024) ? 1024 : size;
23234 + MMC_DEBUG( MMC_DEBUG_LEVEL4,
23235 + "before mmc_read mbuf=0x%x "
23236 + "lsize=%d ppos=0x%x *ppos=%d\n",
23237 + mbuf, lsize, ppos, *ppos );
23238 + ret = mmc_read( dev->card,
23239 + MMC_TRANSFER_MODE_BLOCK_MULTIPLE,
23240 + mbuf, lsize, ppos );
23244 + /* Copy to user */
23245 + if ( copy_to_user( buf, mbuf, ret ) ) {
23254 + if ( retsize > 0 )
23259 + case MMC_TRANSFER_MODE_STREAM:
23260 + ret = mmc_read( dev->card, dev->transfer_mode,
23261 + buf, size, ppos );
23265 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "invalid transfer mode\n" );
23268 + __LEAVE( "ret=%d", ret );
23272 +static ssize_t mmc_test_write( struct file *file, const char *buf, size_t size, loff_t *ppos )
23274 + ssize_t ret = -ENODEV;
23275 + mmc_test_device_t dev = (mmc_test_device_t)file->private_data;
23278 + __ENTER( "host=%d, card=%d, size=%d", dev->card->ctrlr->slot, dev->card->slot, size );
23281 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "file->private_data == NULL\n" );
23285 + switch ( dev->transfer_mode ) {
23288 + case MMC_TRANSFER_MODE_BLOCK_SINGLE:
23289 + mbuf = kmalloc( 512, GFP_ATOMIC ); /* FIXME: actual write_bl_len or ctrlr->block_size_max whichever is less, GFP_KERNEL */
23295 + while ( size > 0 ) {
23296 + int lsize = ( size > 512 ) ? 512 : size;
23298 + /* Copy from user */
23299 + if ( copy_from_user( mbuf, buf, lsize ) ) {
23304 + ret = mmc_write( dev->card,
23305 + MMC_TRANSFER_MODE_BLOCK_SINGLE,
23306 + mbuf, lsize, ppos );
23315 + if ( retsize > 0 )
23321 + case MMC_TRANSFER_MODE_BLOCK_MULTIPLE:
23322 + mbuf = kmalloc( 1024, GFP_ATOMIC ); /* FIXME */
23328 + while( size > 0 ) {
23329 + int lsize = (size > 1024) ? 1024 : size;
23331 + MMC_DEBUG( MMC_DEBUG_LEVEL4,
23332 + "before mmc_read mbuf=0x%x "
23333 + "lsize=%d ppos=0x%x *ppos=%d\n",
23334 + mbuf, lsize, ppos, *ppos );
23335 + ret = mmc_write( dev->card,
23336 + MMC_TRANSFER_MODE_BLOCK_MULTIPLE,
23337 + mbuf, lsize, ppos );
23341 + /* Copy to user */
23342 + if ( copy_to_user( (char *)buf, mbuf, ret ) ) {
23351 + if ( retsize > 0 )
23355 + case MMC_TRANSFER_MODE_STREAM:
23356 + ret = mmc_write( dev->card, dev->transfer_mode,
23357 + buf, size, ppos );
23361 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "invalid transfer mode\n" );
23364 + __LEAVE( "ret=%d", ret );
23368 +static loff_t mmc_test_llseek( struct file *file, loff_t offset, int origin )
23370 + loff_t ret = -ESPIPE;
23371 + mmc_test_device_t dev = (mmc_test_device_t)file->private_data;
23375 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "file->private_data == NULL\n" );
23380 + __ENTER( "host=%d, card=%d, off=%ld, orig=%d", dev->card->ctrlr->slot, dev->card->slot, (long)offset, origin );
23382 + card = dev->card;
23384 + switch ( origin ) {
23386 + file->f_pos += offset;
23390 + file->f_pos = card->info.capacity + offset;
23394 + file->f_pos = offset;
23402 + ret = file->f_pos;
23404 + __LEAVE( "ret=%ld", (long)ret );
23408 +static int mmc_test_ioctl( struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg )
23410 + int ret = -ENODEV;
23411 + mmc_test_device_t dev = (mmc_test_device_t)file->private_data;
23414 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "file->private_data == NULL\n" );
23419 + case IOCMMCSTRNSMODE:
23420 + if ( get_user( ret, (int *)arg ) ) {
23424 + ret = mmc_test_set_transfer_mode( dev, ret );
23427 + case IOCMMCGTRNSMODE:
23428 + ret = mmc_test_get_transfer_mode( dev );
23429 + if ( put_user( ret, (int *)arg ) )
23434 + ret = mmc_ioctl( dev->card, cmd, arg );
23441 +struct file_operations mmc_test_fops = {
23442 + owner: THIS_MODULE,
23443 + open: mmc_test_open,
23444 + release: mmc_test_release,
23445 + read: mmc_test_read,
23446 + write: mmc_test_write,
23447 + ioctl: mmc_test_ioctl,
23448 + llseek: mmc_test_llseek
23451 +#ifdef CONFIG_DEVFS_FS
23452 +static int mmc_test_add_card( mmc_card_t card ) /* TODO */
23455 + __ENTER( "host=%d, card=%d", card->ctrlr->slot, card->slot );
23456 +/* TODO: make kdev; register with devfs */
23461 +static int mmc_test_remove_card( mmc_card_t card ) /* TODO */
23464 + __ENTER( "host=%d, card=%d", card->ctrlr->slot, card->slot );
23465 +/* TODO: make kdev; unregister with devfs */
23470 +static mmc_notifier_rec_t mmc_test_notifier = {
23471 + add: mmc_test_add_card,
23472 + remove: mmc_test_remove_card
23474 +#endif /* CONFIG_DEVFS_FS */
23476 +static int __init mmc_test_module_init( void )
23478 + int ret = -ENODEV;
23480 +#ifdef CONFIG_DEVFS_FS
23481 + if ( !mmc_register( MMC_REG_TYPE_USER, &mmc_test_notifier, 0 ) ) {
23482 + MMC_DEBUG( MMC_DEBUG_LEVEL0, "failed to register with MMC core\n" );
23486 + mmc_register( MMC_REG_TYPE_USER, NULL, 0 );
23487 + if ( register_chrdev( MMC_TEST_MAJOR, "mmc_test", &mmc_test_fops ) ) {
23488 + MMC_DEBUG( MMC_DEBUG_LEVEL0,
23489 + "failed to request device major number\n" );
23490 + mmc_unregister( MMC_REG_TYPE_USER, NULL );
23495 + memset( mmc_test_device, 0, sizeof( mmc_test_device ) );
23502 +static void __exit mmc_test_module_cleanup( void )
23504 +#ifdef CONFIG_DEVFS_FS
23505 + mmc_unregister( MMC_REG_TYPE_USER, &mmc_test_notifier );
23507 + mmc_unregister( MMC_REG_TYPE_USER, NULL );
23508 + unregister_chrdev( MMC_TEST_MAJOR, "mmc_test" );
23512 +EXPORT_NO_SYMBOLS;
23514 +module_init( mmc_test_module_init );
23515 +module_exit( mmc_test_module_cleanup );
23517 +MODULE_LICENSE("GPL");
23519 +++ linux-2.4.27/drivers/mmc/pm_test.c
23521 +/* Power Managment Test Module. RTSoft Co. 2002 */
23523 +/* The necessary header files */
23525 +/* Standard in kernel modules */
23526 +#include <linux/kernel.h> /* We're doing kernel work */
23527 +#include <linux/module.h> /* Specifically, a module */
23529 +#include <linux/pm.h>
23532 +static int pmdata = -1;
23534 +/* Initialize the module - register the proc file */
23538 + pm_send_all(PM_SUSPEND,&pmdata);
23543 +/* Cleanup - unregister our file from /proc */
23544 +void cleanup_module()
23546 + pm_send_all(PM_RESUME,NULL);
23549 +MODULE_LICENSE( "GPL" );
23551 +++ linux-2.4.27/drivers/mmc/types.h
23554 + * linux/drivers/mmc/types.h
23556 + * Author: Vladimir Shebordaev
23557 + * Copyright: MontaVista Software Inc.
23559 + * $Id: types.h,v 0.5 2002/08/13 17:34:02 ted Exp ted $
23561 + * This program is free software; you can redistribute it and/or modify
23562 + * it under the terms of the GNU General Public License version 2 as
23563 + * published by the Free Software Foundation.
23565 +#ifndef __MMC_TYPES_P_H__
23566 +#define __MMC_TYPES_P_H__
23569 +#include <linux/kdev_t.h>
23571 +typedef enum _mmc_reg_type mmc_reg_type_t;
23572 +typedef enum _mmc_response mmc_response_fmt_t;
23574 +/* MMC card private description */
23575 +typedef struct _mmc_card_rec mmc_card_rec_t;
23576 +typedef struct _mmc_card_rec *mmc_card_t;
23577 +typedef enum _mmc_dir mmc_dir_t;
23578 +typedef enum _mmc_buftype mmc_buftype_t;
23580 +/* notifier declarations */
23581 +typedef struct _mmc_notifier_rec mmc_notifier_rec_t;
23582 +typedef struct _mmc_notifier_rec *mmc_notifier_t;
23584 +typedef int (*mmc_notifier_fn_t) ( mmc_card_t );
23586 +/* MMC card stack */
23587 +typedef struct _mmc_card_stack_rec mmc_card_stack_rec_t;
23588 +typedef struct _mmc_card_stack_rec *mmc_card_stack_t;
23590 +typedef struct _mmc_data_transfer_req_rec mmc_data_transfer_req_rec_t;
23591 +typedef struct _mmc_data_transfer_req_rec *mmc_data_transfer_req_t;
23593 +/* MMC controller */
23594 +typedef struct _mmc_controller_tmpl_rec mmc_controller_tmpl_rec_t;
23595 +typedef struct _mmc_controller_tmpl_rec *mmc_controller_tmpl_t;
23597 +typedef enum _mmc_controller_state mmc_controller_state_t;
23598 +typedef struct _mmc_controller_rec mmc_controller_rec_t;
23599 +typedef struct _mmc_controller_rec *mmc_controller_t;
23601 +/* various kernel types */
23602 +typedef struct semaphore semaphore_t;
23603 +typedef struct rw_semaphore rwsemaphore_t;
23604 +typedef struct proc_dir_entry proc_dir_entry_rec_t;
23605 +typedef struct proc_dir_entry *proc_dir_entry_t;
23606 +typedef struct gendisk gendisk_rec_t;
23607 +typedef struct gendisk *gendisk_t;
23608 +#endif /* __KERNEL__ */
23610 +#endif /* __MMC_TYPES_P_H__ */
23612 --- linux-2.4.27/drivers/mtd/maps/Config.in~2.4.27-vrs1-pxa1
23613 +++ linux-2.4.27/drivers/mtd/maps/Config.in
23617 if [ "$CONFIG_ARM" = "y" ]; then
23618 + dep_tristate ' CFI Flash device mapped on Lubbock board' CONFIG_MTD_LUBBOCK $CONFIG_MTD_CFI $CONFIG_ARCH_LUBBOCK $CONFIG_MTD_PARTITIONS
23619 dep_tristate ' CFI Flash device mapped on Nora' CONFIG_MTD_NORA $CONFIG_MTD_CFI
23620 dep_tristate ' CFI Flash device mapped on ARM Integrator/P720T' CONFIG_MTD_ARM_INTEGRATOR $CONFIG_MTD_CFI
23621 dep_tristate ' Cirrus CDB89712 evaluation board mappings' CONFIG_MTD_CDB89712 $CONFIG_MTD_CFI $CONFIG_ARCH_CDB89712
23622 --- linux-2.4.27/drivers/mtd/maps/Makefile~2.4.27-vrs1-pxa1
23623 +++ linux-2.4.27/drivers/mtd/maps/Makefile
23625 obj-$(CONFIG_MTD_ELAN_104NC) += elan-104nc.o
23626 obj-$(CONFIG_MTD_EPXA) += epxa-flash.o
23627 obj-$(CONFIG_MTD_IQ80310) += iq80310.o
23628 +obj-$(CONFIG_MTD_LUBBOCK) += lubbock.o
23629 +obj-$(CONFIG_MTD_PXA_CERF) += pxa_cerf.o
23630 +obj-$(CONFIG_MTD_TRIZEPS2) += trizeps2.o
23631 obj-$(CONFIG_MTD_L440GX) += l440gx.o
23632 obj-$(CONFIG_MTD_AMD76XROM) += amd76xrom.o
23633 obj-$(CONFIG_MTD_ICH2ROM) += ich2rom.o
23635 +++ linux-2.4.27/drivers/mtd/maps/lubbock.c
23640 + * Map driver for the Lubbock developer platform.
23642 + * Author: Nicolas Pitre
23643 + * Copyright: (C) 2001 MontaVista Software Inc.
23645 + * This program is free software; you can redistribute it and/or modify
23646 + * it under the terms of the GNU General Public License version 2 as
23647 + * published by the Free Software Foundation.
23650 +#include <linux/module.h>
23651 +#include <linux/types.h>
23652 +#include <linux/kernel.h>
23653 +#include <asm/io.h>
23654 +#include <linux/mtd/mtd.h>
23655 +#include <linux/mtd/map.h>
23656 +#include <linux/mtd/partitions.h>
23659 +#define WINDOW_ADDR 0
23660 +//#define WINDOW_ADDR 0x04000000
23661 +#define WINDOW_SIZE 64*1024*1024
23663 +static __u8 lubbock_read8(struct map_info *map, unsigned long ofs)
23665 + return *(__u8 *)(map->map_priv_1 + ofs);
23668 +static __u16 lubbock_read16(struct map_info *map, unsigned long ofs)
23670 + return *(__u16 *)(map->map_priv_1 + ofs);
23673 +static __u32 lubbock_read32(struct map_info *map, unsigned long ofs)
23675 + return *(__u32 *)(map->map_priv_1 + ofs);
23678 +static void lubbock_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
23680 + memcpy(to, (void *)(map->map_priv_1 + from), len);
23683 +static void lubbock_write8(struct map_info *map, __u8 d, unsigned long adr)
23685 + *(__u8 *)(map->map_priv_1 + adr) = d;
23688 +static void lubbock_write16(struct map_info *map, __u16 d, unsigned long adr)
23690 + *(__u16 *)(map->map_priv_1 + adr) = d;
23693 +static void lubbock_write32(struct map_info *map, __u32 d, unsigned long adr)
23695 + *(__u32 *)(map->map_priv_1 + adr) = d;
23698 +static void lubbock_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
23700 + memcpy((void *)(map->map_priv_1 + to), from, len);
23703 +static struct map_info lubbock_map = {
23704 + name: "Lubbock flash",
23705 + size: WINDOW_SIZE,
23706 + read8: lubbock_read8,
23707 + read16: lubbock_read16,
23708 + read32: lubbock_read32,
23709 + copy_from: lubbock_copy_from,
23710 + write8: lubbock_write8,
23711 + write16: lubbock_write16,
23712 + write32: lubbock_write32,
23713 + copy_to: lubbock_copy_to
23716 +static struct mtd_partition lubbock_partitions[] = {
23718 + name: "Bootloader",
23719 + size: 0x00040000,
23721 + mask_flags: MTD_WRITEABLE /* force read-only */
23724 + size: 0x00100000,
23725 + offset: 0x00040000,
23727 + name: "Filesystem",
23728 + size: MTDPART_SIZ_FULL,
23729 + offset: 0x00140000
23733 +#define NB_OF(x) (sizeof(x)/sizeof(x[0]))
23735 +static struct mtd_info *mymtd;
23736 +static struct mtd_partition *parsed_parts;
23738 +extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
23740 +static int __init init_lubbock(void)
23742 + struct mtd_partition *parts;
23743 + int nb_parts = 0;
23744 + int parsed_nr_parts = 0;
23745 + char *part_type = "static";
23747 + lubbock_map.buswidth = (BOOT_DEF & 1) ? 2 : 4;
23748 + printk( "Probing Lubbock flash at physical address 0x%08x (%d-bit buswidth)\n",
23749 + WINDOW_ADDR, lubbock_map.buswidth * 8 );
23750 + lubbock_map.map_priv_1 = (unsigned long)__ioremap(WINDOW_ADDR, WINDOW_SIZE, 0);
23751 + if (!lubbock_map.map_priv_1) {
23752 + printk("Failed to ioremap\n");
23755 + mymtd = do_map_probe("cfi_probe", &lubbock_map);
23757 + iounmap((void *)lubbock_map.map_priv_1);
23760 + mymtd->module = THIS_MODULE;
23762 +#ifdef CONFIG_MTD_REDBOOT_PARTS
23763 + if (parsed_nr_parts == 0) {
23764 + int ret = parse_redboot_partitions(mymtd, &parsed_parts);
23767 + part_type = "RedBoot";
23768 + parsed_nr_parts = ret;
23773 + if (parsed_nr_parts > 0) {
23774 + parts = parsed_parts;
23775 + nb_parts = parsed_nr_parts;
23777 + parts = lubbock_partitions;
23778 + nb_parts = NB_OF(lubbock_partitions);
23781 + printk(KERN_NOTICE "Using %s partition definition\n", part_type);
23782 + add_mtd_partitions(mymtd, parts, nb_parts);
23784 + add_mtd_device(mymtd);
23789 +static void __exit cleanup_lubbock(void)
23792 + del_mtd_partitions(mymtd);
23793 + map_destroy(mymtd);
23794 + if (parsed_parts)
23795 + kfree(parsed_parts);
23797 + if (lubbock_map.map_priv_1)
23798 + iounmap((void *)lubbock_map.map_priv_1);
23802 +module_init(init_lubbock);
23803 +module_exit(cleanup_lubbock);
23806 +++ linux-2.4.27/drivers/mtd/maps/pxa_cerf.c
23809 + * Map driver for the PXA Cerf.
23811 + * This program is free software; you can redistribute it and/or modify
23812 + * it under the terms of the GNU General Public License version 2 as
23813 + * published by the Free Software Foundation.
23816 +#include <linux/module.h>
23817 +#include <linux/types.h>
23818 +#include <linux/kernel.h>
23819 +#include <asm/io.h>
23820 +#include <linux/mtd/mtd.h>
23821 +#include <linux/mtd/map.h>
23822 +#include <linux/mtd/partitions.h>
23825 +#define WINDOW_ADDR 0
23826 +#if defined (CONFIG_PXA_CERF_FLASH_64MB)
23827 +#define WINDOW_SIZE 64*1024*1024
23828 +#elif defined (CONFIG_PXA_CERF_FLASH_32MB)
23829 +#define WINDOW_SIZE 32*1024*1024
23830 +#elif defined (CONFIG_PXA_CERF_FLASH_16MB)
23831 +#define WINDOW_SIZE 16*1024*1024
23833 +#define BUSWIDTH 4
23835 +static __u8 pxa_cerf_read8(struct map_info *map, unsigned long ofs)
23837 + return *(__u8 *)(map->map_priv_1 + ofs);
23840 +static __u16 pxa_cerf_read16(struct map_info *map, unsigned long ofs)
23842 + return *(__u16 *)(map->map_priv_1 + ofs);
23845 +static __u32 pxa_cerf_read32(struct map_info *map, unsigned long ofs)
23847 + return *(__u32 *)(map->map_priv_1 + ofs);
23850 +static void pxa_cerf_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
23852 + memcpy(to, (void *)(map->map_priv_1 + from), len);
23855 +static void pxa_cerf_write8(struct map_info *map, __u8 d, unsigned long adr)
23857 + *(__u8 *)(map->map_priv_1 + adr) = d;
23860 +static void pxa_cerf_write16(struct map_info *map, __u16 d, unsigned long adr)
23862 + *(__u16 *)(map->map_priv_1 + adr) = d;
23865 +static void pxa_cerf_write32(struct map_info *map, __u32 d, unsigned long adr)
23867 + *(__u32 *)(map->map_priv_1 + adr) = d;
23870 +static void pxa_cerf_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
23872 + memcpy((void *)(map->map_priv_1 + to), from, len);
23875 +static struct map_info pxa_cerf_map = {
23876 + name: "PXA Cerf Flash",
23877 + size: WINDOW_SIZE,
23878 + buswidth: BUSWIDTH,
23879 + read8: pxa_cerf_read8,
23880 + read16: pxa_cerf_read16,
23881 + read32: pxa_cerf_read32,
23882 + copy_from: pxa_cerf_copy_from,
23883 + write8: pxa_cerf_write8,
23884 + write16: pxa_cerf_write16,
23885 + write32: pxa_cerf_write32,
23886 + copy_to: pxa_cerf_copy_to
23889 +static struct mtd_partition pxa_cerf_partitions[] = {
23891 + name: "Bootloader",
23892 + size: 0x00040000,
23894 + mask_flags: MTD_WRITEABLE /* force read-only */
23896 + name: "Partition Tables",
23897 + size: 0x00080000,
23898 + offset: 0x00040000,
23901 + size: 0x00100000,
23902 + offset: 0x000C0000,
23904 + name: "Filesystem",
23905 + size: WINDOW_SIZE-0x001C0000, //MTDPART_SIZ_FULL,
23906 + offset: 0x001C0000
23910 +#define NB_OF(x) (sizeof(x)/sizeof(x[0]))
23912 +static struct mtd_info *mymtd;
23913 +static struct mtd_partition *parsed_parts;
23915 +extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
23917 +static int __init init_pxa_cerf(void)
23919 + struct mtd_partition *parts;
23920 + int nb_parts = 0;
23921 + int parsed_nr_parts = 0;
23922 + char *part_type = "static";
23924 + printk("Probing PXA Cerf flash at physical address 0x%08x\n", WINDOW_ADDR);
23925 + pxa_cerf_map.map_priv_1 = (unsigned long)__ioremap(WINDOW_ADDR, WINDOW_SIZE, 0);
23926 + if (!pxa_cerf_map.map_priv_1) {
23927 + printk("Failed to ioremap\n");
23930 + mymtd = do_map_probe("cfi_probe", &pxa_cerf_map);
23932 + iounmap((void *)pxa_cerf_map.map_priv_1);
23935 + mymtd->module = THIS_MODULE;
23937 +#ifdef CONFIG_MTD_REDBOOT_PARTS
23938 + if (parsed_nr_parts == 0) {
23939 + int ret = parse_redboot_partitions(mymtd, &parsed_parts);
23942 + part_type = "RedBoot";
23943 + parsed_nr_parts = ret;
23948 + if (parsed_nr_parts > 0) {
23949 + parts = parsed_parts;
23950 + nb_parts = parsed_nr_parts;
23952 + parts = pxa_cerf_partitions;
23953 + nb_parts = NB_OF(pxa_cerf_partitions);
23956 + printk(KERN_NOTICE "Using %s partition definition\n", part_type);
23957 + add_mtd_partitions(mymtd, parts, nb_parts);
23959 + add_mtd_device(mymtd);
23964 +static void __exit cleanup_pxa_cerf(void)
23967 + del_mtd_partitions(mymtd);
23968 + map_destroy(mymtd);
23969 + if (parsed_parts)
23970 + kfree(parsed_parts);
23972 + if (pxa_cerf_map.map_priv_1)
23973 + iounmap((void *)pxa_cerf_map.map_priv_1);
23977 +module_init(init_pxa_cerf);
23978 +module_exit(cleanup_pxa_cerf);
23981 +++ linux-2.4.27/drivers/mtd/maps/trizeps2.c
23986 + * Map driver for the Trizeps-2 module.
23988 + * Author: Luc De Cock
23989 + * Copyright: (C) 2003 Teradyne DS, Ltd.
23991 + * This program is free software; you can redistribute it and/or modify
23992 + * it under the terms of the GNU General Public License version 2 as
23993 + * published by the Free Software Foundation.
23996 +#include <linux/module.h>
23997 +#include <linux/types.h>
23998 +#include <linux/kernel.h>
23999 +#include <asm/io.h>
24000 +#include <linux/mtd/mtd.h>
24001 +#include <linux/mtd/map.h>
24002 +#include <linux/mtd/partitions.h>
24005 +#define WINDOW_ADDR 0
24006 +#define WINDOW_SIZE 16*1024*1024
24008 +static __u8 trizeps2_read8(struct map_info *map, unsigned long ofs)
24010 + return *(__u8 *)(map->map_priv_1 + ofs);
24013 +static __u16 trizeps2_read16(struct map_info *map, unsigned long ofs)
24015 + return *(__u16 *)(map->map_priv_1 + ofs);
24018 +static __u32 trizeps2_read32(struct map_info *map, unsigned long ofs)
24020 + return *(__u32 *)(map->map_priv_1 + ofs);
24023 +static void trizeps2_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
24025 + memcpy(to, (void *)(map->map_priv_1 + from), len);
24028 +static void trizeps2_write8(struct map_info *map, __u8 d, unsigned long adr)
24030 + *(__u8 *)(map->map_priv_1 + adr) = d;
24033 +static void trizeps2_write16(struct map_info *map, __u16 d, unsigned long adr)
24035 + *(__u16 *)(map->map_priv_1 + adr) = d;
24038 +static void trizeps2_write32(struct map_info *map, __u32 d, unsigned long adr)
24040 + *(__u32 *)(map->map_priv_1 + adr) = d;
24043 +static void trizeps2_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
24045 + memcpy((void *)(map->map_priv_1 + to), from, len);
24048 +static struct map_info trizeps2_map = {
24049 + name: "Trizeps-2 flash",
24050 + size: WINDOW_SIZE,
24051 + read8: trizeps2_read8,
24052 + read16: trizeps2_read16,
24053 + read32: trizeps2_read32,
24054 + copy_from: trizeps2_copy_from,
24055 + write8: trizeps2_write8,
24056 + write16: trizeps2_write16,
24057 + write32: trizeps2_write32,
24058 + copy_to: trizeps2_copy_to
24061 +static struct mtd_partition trizeps2_partitions[] = {
24063 + name: "Bootloader",
24064 + size: 0x00040000,
24066 + mask_flags: MTD_WRITEABLE /* force read-only */
24068 + name: "Bootloader (backup)",
24069 + size: 0x00040000,
24070 + offset: 0x00040000,
24071 + mask_flags: MTD_WRITEABLE /* force read-only */
24074 + size: 0x000C0000,
24075 + offset: 0x00080000,
24077 + name: "Filesystem",
24078 + size: MTDPART_SIZ_FULL,
24079 + offset: 0x00140000
24083 +#define NB_OF(x) (sizeof(x)/sizeof(x[0]))
24085 +static struct mtd_info *mymtd;
24086 +static struct mtd_partition *parsed_parts;
24088 +extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
24090 +static int __init init_trizeps2(void)
24092 + struct mtd_partition *parts;
24093 + int nb_parts = 0;
24094 + int parsed_nr_parts = 0;
24095 + char *part_type = "static";
24097 + trizeps2_map.buswidth = (BOOT_DEF & 1) ? 2 : 4;
24098 + printk( "Probing Trizeps-2 flash at physical address 0x%08x (%d-bit buswidth)\n",
24099 + WINDOW_ADDR, trizeps2_map.buswidth * 8 );
24100 + trizeps2_map.map_priv_1 = (unsigned long)__ioremap(WINDOW_ADDR, WINDOW_SIZE, 0);
24101 + if (!trizeps2_map.map_priv_1) {
24102 + printk("Failed to ioremap\n");
24105 + mymtd = do_map_probe("cfi_probe", &trizeps2_map);
24107 + iounmap((void *)trizeps2_map.map_priv_1);
24110 + mymtd->module = THIS_MODULE;
24112 +#ifdef CONFIG_MTD_REDBOOT_PARTS
24113 + if (parsed_nr_parts == 0) {
24114 + int ret = parse_redboot_partitions(mymtd, &parsed_parts);
24117 + part_type = "RedBoot";
24118 + parsed_nr_parts = ret;
24123 + if (parsed_nr_parts > 0) {
24124 + parts = parsed_parts;
24125 + nb_parts = parsed_nr_parts;
24127 + parts = trizeps2_partitions;
24128 + nb_parts = NB_OF(trizeps2_partitions);
24131 + printk(KERN_NOTICE "Using %s partition definition\n", part_type);
24132 + add_mtd_partitions(mymtd, parts, nb_parts);
24134 + add_mtd_device(mymtd);
24139 +static void __exit cleanup_trizeps2(void)
24142 + del_mtd_partitions(mymtd);
24143 + map_destroy(mymtd);
24144 + if (parsed_parts)
24145 + kfree(parsed_parts);
24147 + if (trizeps2_map.map_priv_1)
24148 + iounmap((void *)trizeps2_map.map_priv_1);
24152 +module_init(init_trizeps2);
24153 +module_exit(cleanup_trizeps2);
24155 --- linux-2.4.27/drivers/net/Config.in~2.4.27-vrs1-pxa1
24156 +++ linux-2.4.27/drivers/net/Config.in
24157 @@ -125,6 +125,7 @@
24158 dep_tristate ' SMC Ultra support' CONFIG_ULTRA $CONFIG_ISA
24159 dep_tristate ' SMC Ultra32 EISA support' CONFIG_ULTRA32 $CONFIG_EISA
24160 dep_tristate ' SMC 9194 support' CONFIG_SMC9194 $CONFIG_ISA
24161 + tristate ' SMC 91C9x/91C1xx support' CONFIG_SMC91X
24163 bool ' Racal-Interlan (Micom) NI cards' CONFIG_NET_VENDOR_RACAL
24164 if [ "$CONFIG_NET_VENDOR_RACAL" = "y" ]; then
24165 --- linux-2.4.27/drivers/net/Makefile~2.4.27-vrs1-pxa1
24166 +++ linux-2.4.27/drivers/net/Makefile
24167 @@ -137,6 +137,7 @@
24168 obj-$(CONFIG_SK_G16) += sk_g16.o
24169 obj-$(CONFIG_HP100) += hp100.o
24170 obj-$(CONFIG_SMC9194) += smc9194.o
24171 +obj-$(CONFIG_SMC91X) += smc91x.o
24172 obj-$(CONFIG_ARM_AM79C961A) += am79c961a.o
24173 obj-$(CONFIG_ARM_ETHERH) += 8390.o
24174 obj-$(CONFIG_WD80x3) += wd.o 8390.o
24175 --- linux-2.4.27/drivers/net/cirrus.c~2.4.27-vrs1-pxa1
24176 +++ linux-2.4.27/drivers/net/cirrus.c
24178 #elif CONFIG_ARCH_CDB89712
24179 # define CIRRUS_DEFAULT_IO ETHER_BASE + 0x300
24180 # define CIRRUS_DEFAULT_IRQ IRQ_EINT3
24181 +#elif CONFIG_ARCH_CSB226
24182 +# define CIRRUS_DEFAULT_IO 0xF8000000
24183 +# define CIRRUS_DEFAULT_IRQ IRQ_GPIO(14)
24185 # define CIRRUS_DEFAULT_IO 0
24186 # define CIRRUS_DEFAULT_IRQ 0
24187 --- linux-2.4.27/drivers/net/irda/Config.in~2.4.27-vrs1-pxa1
24188 +++ linux-2.4.27/drivers/net/irda/Config.in
24190 if [ "$CONFIG_ARCH_SA1100" = "y" ]; then
24191 dep_tristate 'SA1100 Internal IR' CONFIG_SA1100_FIR $CONFIG_IRDA $CONFIG_EXPERIMENTAL
24194 +if [ "$CONFIG_ARCH_PXA" = "y" ]; then
24195 + dep_tristate 'Intel PXA2xx Internal IR' CONFIG_PXA_FIR $CONFIG_IRDA $CONFIG_EXPERIMENTAL
24198 --- linux-2.4.27/drivers/net/irda/Makefile~2.4.27-vrs1-pxa1
24199 +++ linux-2.4.27/drivers/net/irda/Makefile
24201 obj-$(CONFIG_USB_IRDA) += irda-usb.o
24202 obj-$(CONFIG_NSC_FIR) += nsc-ircc.o
24203 obj-$(CONFIG_WINBOND_FIR) += w83977af_ir.o
24204 +obj-$(CONFIG_PXA_FIR) += pxa_ir.o
24205 obj-$(CONFIG_SA1100_FIR) += sa1100_ir.o
24206 obj-$(CONFIG_TOSHIBA_OLD) += toshoboe.o
24207 obj-$(CONFIG_TOSHIBA_FIR) += donauboe.o
24209 +++ linux-2.4.27/drivers/net/irda/pxa_ir.c
24212 + * linux/drivers/net/irda/pxa_ir.c
24215 + * Alexey Lugovskoy RTSoft.
24216 + * lugovskoy@rtsoft.msk.ru
24218 + * Dmitrij Frasenyak RTSoft.
24221 + * This program is free software; you can redistribute it and/or modify
24222 + * it under the terms of the GNU General Public License version 2 as
24223 + * published by the Free Software Foundation.
24225 + * Infra-red SIR and FIR driver for the PXA 210/250 embedded microprocessors
24226 + * Based on linux/drivers/net/irda/sa1100_ir.c
24231 +#include <linux/config.h>
24232 +#include <linux/module.h>
24233 +#include <linux/types.h>
24234 +#include <linux/init.h>
24235 +#include <linux/errno.h>
24236 +#include <linux/netdevice.h>
24237 +#include <linux/slab.h>
24238 +#include <linux/rtnetlink.h>
24239 +#include <linux/interrupt.h>
24240 +#include <linux/delay.h>
24241 +#include <linux/ioport.h>
24242 +#include <linux/delay.h>
24244 +#include <linux/pm.h>
24246 +#include <net/irda/irda.h>
24247 +#include <net/irda/irmod.h>
24248 +#include <net/irda/wrapper.h>
24249 +#include <net/irda/irda_device.h>
24251 +#include <asm/irq.h>
24252 +#include <asm/dma.h>
24253 +#include <asm/hardware.h>
24254 +#include <asm/mach-types.h>
24255 +#include <asm/arch/lubbock.h>
24258 +static int rx_count = 0;
24259 +static int tx_count = 0;
24262 + * Our netdevice. There is only ever one of these.
24265 +static struct net_device *netdev;
24267 +struct pxa250_irda {
24269 + unsigned char open;
24274 + struct sk_buff *txskb;
24275 + struct sk_buff *rxskb;
24279 + unsigned int fir_irq;
24282 + dma_addr_t txbuf_dma;
24283 + dma_addr_t rxbuf_dma;
24284 + void* txbuf_dma_virt;
24285 + void* rxbuf_dma_virt;
24287 + struct net_device_stats stats;
24288 + struct irlap_cb *irlap;
24289 + struct pm_dev *pmdev;
24290 + struct qos_info qos;
24293 + iobuff_t tx_buff;
24294 + iobuff_t rx_buff;
24298 +#define IS_FIR(si) ((si)->speed >= 4000000)
24300 +#define HPSIR_MAX_RXLEN 2050
24301 +#define HPSIR_MAX_TXLEN 2050
24302 +#define TXBUFF_MAX_SIZE HPSIR_MAX_TXLEN
24303 +#define SET_SIR_MODE STISR = STISR_RCVEIR | STISR_XMITIR | STISR_XMODE
24306 + * If you want to disable debug information
24307 + * please uncomment line bellow
24310 +#define PXA_FIR_DUMP_ENABLE
24311 +#undef PXA_FIR_DUMP_ENABLE
24314 +#define PXA_FIR_DEBUG_ENABLE
24315 +#undef PXA_FIR_DEBUG_ENABLE
24317 +#define PXA_FIR_IRQ_DEBUG_ENABLE
24318 +#undef PXA_FIR_IRQ_DEBUG_ENABLE
24320 +#ifdef PXA_FIR_DEBUG_ENABLE
24321 +#define __ECHO_IN printk(KERN_ERR "%s: enter\n",__FUNCTION__);
24322 +#define __ECHO_OUT printk(KERN_ERR "%s: exit\n",__FUNCTION__);
24323 +#define DBG(args...) printk(KERN_ERR __FUNCTION__"():"args);
24326 +#define __ECHO_OUT
24327 +#define DBG(args...)
24330 +#ifdef PXA_FIR_IRQ_DEBUG_ENABLE
24331 +#define DBG_IRQ(args...) printk(KERN_ERR __FUNCTION__"():"args);
24333 +#define DBG_IRQ(args...)
24337 +static int pxa250_irda_set_speed(struct net_device *dev,int speed);
24338 +static void pxa250_start_rx_dma(struct net_device *dev);
24342 +/**************************************************************************
24343 + * Misc FIR/SIR functions *
24344 + **************************************************************************/
24346 + * Allocate the receive buffer, unless it is already allocated.
24349 +static int pxa250_irda_rx_alloc(struct pxa250_irda *si)
24356 + si->rxskb = alloc_skb(HPSIR_MAX_RXLEN + 1, GFP_ATOMIC);
24358 + if (!si->rxskb) {
24359 + printk(KERN_ERR "pxa250_ir: out of memory for RX SKB\n");
24364 + * Align any IP headers that may be contained
24365 + * within the frame.
24367 + skb_reserve(si->rxskb, 1);
24376 +/**************************************************************************
24378 + **************************************************************************/
24383 +static inline void pxa250_dma_stop(int ch)
24387 + DCSR(ch) &= ~DCSR_RUN;
24394 +static void pxa250_ficp_rx_start(void)
24397 + ICCR2 = 1 << 2 | 0 << 3 ;
24398 + ICCR0 = ICCR0_ITR ;
24399 + ICCR0 |= ICCR0_RIE | ICCR0_RXE ;
24403 + * Change Alternative Function encoding
24404 + * Enable ICP unit
24405 + * Disabe STUART unit
24406 + * Enable IRQ unit clock;
24407 + * Configure direction of GPIO used by ICP
24411 +static void pxa250_do_fir_GPIO_config(void)
24414 + * Modify GPIO 46 and 47 Alternate Function
24420 + set_GPIO_mode (GPIO46_ICPRXD_MD);
24421 + set_GPIO_mode (GPIO47_ICPTXD_MD);
24423 + if (machine_is_lubbock())
24424 + LUB_MISC_WR |= 1 << 4;
24427 + CKEN |= CKEN13_FICP;
24433 + * Low level hardware configuration and startup.
24436 +static int pxa250_fir_irda_startup(struct pxa250_irda *si)
24445 + STIER &= ~IER_UUE;
24447 + /*Disable STUART FIFO */
24451 + * Do low level configuration for HW AF and clock
24453 + pxa250_do_fir_GPIO_config();
24461 + * Aieeeeee .. we should never get here :(
24463 +static void pxa250_irda_rxdma_irq(int ch,void *id, struct pt_regs *regs)
24465 + struct net_device *dev=id;
24466 + struct pxa250_irda *si=dev->priv;
24473 + * Make sure that irq is our.
24476 + if ( ch != si->rxdma_ch )
24484 + DBG("DCSR=%x\n",dcsr);
24486 + if (dcsr & DCSR_STOPSTATE )
24488 + DBG_IRQ("Chanel %d in stop state\n",ch);
24491 + if (dcsr & DCSR_BUSERR )
24494 + * BUS Error we must restart reception
24497 + DBG("PXA IrDA: bus error interrupt on channel %d\n", ch);
24498 + DCSR(ch) |= DCSR_BUSERR;
24501 + if (dcsr & DCSR_ENDINTR )
24503 + DBG("PXA IrDA: Normal end of dma channel %d - packet to big\n", ch);
24504 + DCSR(ch) |= DCSR_ENDINTR;
24507 + /* no mater what restart rx*/
24508 + pxa250_start_rx_dma(dev);
24515 +static void pxa250_irda_txdma_irq(int ch, void *id , struct pt_regs *regs)
24517 + struct net_device *dev=id;
24518 + struct pxa250_irda *si=dev->priv;
24519 + struct sk_buff *skb = si->txskb;
24524 + DBG_IRQ("transmit\n");
24528 + * Make sure that irq is our.
24531 + if ( ch != si->txdma_ch )
24540 + DBG("DCSR=%x",dcsr);
24542 + if (dcsr & DCSR_STOPSTATE )
24544 + DBG("Chanel %d in stop state\n",ch);
24547 + if (dcsr & DCSR_BUSERR )
24549 + DBG("PXA IrDA: bus error interrupt on channel %d\n", ch);
24550 + DCSR(ch) |= DCSR_BUSERR;
24551 + si->txskb = NULL;
24554 + if (dcsr & DCSR_ENDINTR )
24556 + DBG("PXA IrDA: Normal end of dma channel %d\n", ch);
24557 + DCSR(ch) |= DCSR_ENDINTR;
24558 + si->txskb = NULL;
24562 + * Account and free the packet.
24566 + si->stats.tx_packets ++;
24567 + si->stats.tx_bytes += skb->len;
24568 + dev_kfree_skb_irq(skb);
24571 + /*Disable transceiver and enable receiver*/
24573 + if (si->newspeed) {
24574 + pxa250_irda_set_speed(dev, si->newspeed);
24575 + si->newspeed = 0;
24578 + while (ICSR1 & ICSR1_TBY)
24581 + ICCR0 &= ~ICCR0_TXE;
24584 + enable_irq(si->fir_irq);
24586 + ICCR0 |= ICCR0_RXE;
24589 + * Make sure that the TX queue is available for sending
24590 + * (for retries). TX has priority over RX at all times.
24592 + netif_wake_queue(dev);
24598 +static void pxa250_start_rx_dma(struct net_device *dev)
24600 + struct pxa250_irda *si = dev->priv;
24601 + int ch=si->rxdma_ch;
24603 + if (!si->rxskb) {
24604 + DBG("rx buffer went missing\n");
24609 + DCSR(ch)=DCSR_NODESC;
24610 + DSADR(ch) = __PREG(ICDR);
24611 + DTADR(ch) = si->rxbuf_dma; /* phisical address */;
24613 + /* We should never do END_IRQ. !!!*/
24614 + DCMD(ch) = DCMD_ENDIRQEN| DCMD_INCTRGADDR | DCMD_FLOWSRC | DCMD_BURST8 | DCMD_WIDTH1 | HPSIR_MAX_RXLEN;
24617 + * All right information will be available as soon as we set RXE flag
24620 + DCSR(ch) = DCSR_ENDINTR | DCSR_BUSERR;
24621 + DCSR(ch) = DCSR_RUN | DCSR_NODESC ;
24628 +static int pxa250_get_rx_len(struct pxa250_irda *si)
24631 + * DMA have to be stoped here
24634 + if ( ! (DCSR(si->rxdma_ch) & DCSR_STOPSTATE) )
24635 + printk("warning dma have to be stoped befor counting len\n");
24637 + return ( HPSIR_MAX_RXLEN - ( DCMD(si->rxdma_ch) & DCMD_LENGTH ) );
24641 +static void pxa250_irda_fir_error(struct net_device *dev)
24643 + struct pxa250_irda *si = dev->priv;
24644 + struct sk_buff *skb = si->rxskb;
24652 + printk("pxa250 fir_error: SKB is NULL!\n");
24657 + * Get the current data position.
24660 + len=pxa250_get_rx_len(si);
24661 + DBG("RXLEN=%d\n",len);
24662 + memcpy(skb->data, si->rxbuf_dma_virt, len);
24666 + * Read Status, and then Data.
24671 + if (stat & (ICSR1_CRE | ICSR1_ROR)) {
24672 + si->stats.rx_errors++;
24673 + if (stat & ICSR1_CRE)
24674 + si->stats.rx_crc_errors++;
24675 + if (stat & ICSR1_ROR)
24676 + si->stats.rx_frame_errors++;
24678 + skb->data[len++] = data;
24681 + * If we hit the end of frame, there's
24682 + * no point in continuing.
24684 + if (stat & ICSR1_EOF)
24686 + } while (ICSR0 & ICSR0_EIF);
24688 + if (stat & ICSR1_EOF) {
24689 + si->rxskb = NULL;
24691 + skb_put(skb, len);
24693 + skb->mac.raw = skb->data;
24694 + skb->protocol = htons(ETH_P_IRDA);
24695 + si->stats.rx_packets++;
24696 + si->stats.rx_bytes += len;
24699 + * Before we pass the buffer up, allocate a new one.
24702 + si->rxskb = alloc_skb(HPSIR_MAX_RXLEN + 1, GFP_ATOMIC);
24704 + if (!si->rxskb) {
24705 + printk(KERN_ERR "pxa250_ir: out of memory for RX SKB\n");
24710 + * Align any IP headers that may be contained
24711 + * within the frame.
24713 + skb_reserve(si->rxskb, 1);
24720 + * FIR format interrupt service routine. We only have to
24721 + * handle RX events; transmit events go via the TX DMA irq handler.
24723 + * No matter what, we disable RX, process, and then restart RX.
24726 +static void pxa250_irda_fir_irq(int irq, void *dev_id, struct pt_regs *regs)
24728 + struct net_device *dev = dev_id;
24729 + struct pxa250_irda *si = dev->priv;
24738 + pxa250_dma_stop(si->rxdma_ch);
24742 + * Framing error - we throw away the packet completely.
24743 + * Clearing RXE flushes the error conditions and data
24748 + if (status & (ICSR0_FRE | ICSR0_RAB)) {
24749 + DBG_IRQ("Framing error or RAB\n");
24751 + si->stats.rx_errors++;
24753 + if (ICSR0 & ICSR0_FRE)
24754 + si->stats.rx_frame_errors++;
24757 + * DMA will be cleared when we restart RX
24758 + * Should we check RNE after that?
24761 + ICCR0 &= ~ICCR0_RXE;
24764 + * Clear selected status bits now, so we
24765 + * don't miss them next time around.
24767 + ICSR0 = status & (ICSR0_FRE | ICSR0_RAB);
24772 + * Deal with any receive errors. The any of the lowest
24773 + * 8 bytes in the FIFO may contain an error. We must read
24774 + * them one by one. The "error" could even be the end of
24777 + if (ICSR0 & ICSR0_EIF)
24778 + pxa250_irda_fir_error(dev);
24781 + * No matter what happens, we must restart reception.
24785 + pxa250_start_rx_dma(dev);
24786 + pxa250_ficp_rx_start();
24794 +/**************************************************************************
24796 + **************************************************************************/
24798 + * HP-SIR format interrupt service routines.
24800 +static void pxa250_sir_transmit(struct net_device *dev)
24802 + struct pxa250_irda *si = dev->priv;
24804 + if (si->tx_buff.len)
24806 + /* Disable receiver and enable transmiter*/
24810 + STISR &= ~STISR_RCVEIR;
24811 +// STISR |= STISR_XMITIR;
24815 + disable_irq(dev->irq);
24820 + if (STLSR & LSR_TDRQ)
24822 + STTHR = *si->tx_buff.data++;
24823 + si->tx_buff.len -= 1;
24829 + } while (si->tx_buff.len);
24832 + if (si->tx_buff.len == 0)
24836 + si->stats.tx_packets++;
24837 + si->stats.tx_bytes += si->tx_buff.data -
24838 + si->tx_buff.head;
24841 + * We need to ensure that the transmitter has
24850 + while ( ! (STLSR & LSR_TEMT) );
24855 + * Ok, we've finished transmitting. Now enable
24856 + * the receiver. Sometimes we get a receive IRQ
24857 + * immediately after a transmit...
24860 + if (si->newspeed)
24862 + pxa250_irda_set_speed(dev, si->newspeed);
24863 + si->newspeed = 0;
24866 + /* I'm hungry! */
24867 + netif_wake_queue(dev);
24870 + enable_irq (dev->irq);
24871 + STIER = (IER_RAVIE | IER_UUE | IER_RTIOE);
24873 + STISR |= STISR_RCVEIR;
24874 +// STISR &= ~STISR_XMITIR;
24878 +static void pxa250_irda_hpsir_irq(struct net_device *dev)
24880 + struct pxa250_irda *si = dev->priv;
24883 + * Deal with any receive errors first. The bytes in error may be
24884 + * the only bytes in the receive FIFO, so we do this first.
24888 + while (STLSR & LSR_FIFOE)
24896 + if (stat & (LSR_FE | LSR_OE | LSR_PE))
24899 + si->stats.rx_errors++;
24900 + if (stat & LSR_FE)
24901 + si->stats.rx_frame_errors++;
24902 + if (stat & LSR_OE)
24903 + si->stats.rx_fifo_errors++;
24908 + async_unwrap_char(dev, &si->stats, &si->rx_buff, data);
24914 + * We must clear certain bits.
24917 + if (STLSR & (LSR_DR))
24920 + * Fifo contains at least 1 character.
24928 + async_unwrap_char(dev, &si->stats, &si->rx_buff,
24929 + data); /* was Ser2UTDR); Clo */
24932 + } while (STLSR & LSR_DR);
24934 + dev->last_rx = jiffies;
24940 +static void pxa250_sir_irda_shutdown(struct pxa250_irda *si)
24946 + CKEN &= ~CKEN5_STUART;
24950 +/************************************************************************************/
24952 +/*Low level init/uninstall function PM control and IrDA protocol stack registration */
24955 + * Set the IrDA communications speed.
24956 + * Interrupt have to be disabled here.
24959 +static int pxa250_irda_startup(struct net_device *dev)
24966 + * Ensure that the ports for this device are setup correctly.
24970 + set_GPIO_mode (GPIO46_STRXD_MD);
24971 + set_GPIO_mode (GPIO47_STTXD_MD);
24973 + STMCR = MCR_OUT2;
24974 + STLCR = LCR_WLS1 | LCR_WLS0;
24977 + CKEN |= CKEN5_STUART;
24978 + /* enable irq from stuart */
24979 + ICMR |= ( 1 << 20 );
24983 +/* STFCR = FCR_TRFIFOE | FCR_RESETTF | FCR_RESETRF;// | FCR_ITL_16;
24985 + STIER = IER_UUE | IER_RAVIE | IER_RTOIE;
24996 + * Suspend the IrDA interface.
24999 +static int pxa250_irda_shutdown(struct pxa250_irda *si)
25002 + pxa250_sir_irda_shutdown(si);
25008 +static int pxa250_irda_suspend(struct net_device *dev, int state)
25010 + struct pxa250_irda *si = dev->priv;
25012 + if (si && si->open) {
25014 + * Stop the transmit queue
25019 + netif_stop_queue(dev);
25020 + disable_irq(dev->irq);
25021 + disable_irq(si->fir_irq);
25022 + pxa250_sir_irda_shutdown(si);
25029 + * Resume the IrDA interface.
25032 +static int pxa250_irda_resume(struct net_device *dev)
25034 + struct pxa250_irda *si = dev->priv;
25038 + if (si && si->open) {
25040 + * If we missed a speed change, initialise at the new speed
25041 + * directly. It is debatable whether this is actually
25042 + * required, but in the interests of continuing from where
25043 + * we left off it is desireable. The converse argument is
25044 + * that we should re-negotiate at 9600 baud again.
25046 + if (si->newspeed) {
25047 + si->speed = si->newspeed;
25048 + si->newspeed = 0;
25051 + pxa250_irda_startup(dev);
25052 + enable_irq(dev->irq);
25055 + * This automatically wakes up the queue
25057 + netif_wake_queue(dev);
25058 + pxa250_irda_set_speed(dev,si->speed = 9600);
25066 +static int pxa250_irda_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data)
25077 + ret = pxa250_irda_suspend((struct net_device *)dev->data,
25082 + ret = pxa250_irda_resume((struct net_device *)dev->data);
25098 +static void pxa250_irda_irq(int irq, void *dev_id, struct pt_regs *regs)
25100 + struct net_device *dev = dev_id;
25102 + pxa250_irda_hpsir_irq(dev);
25107 +static int pxa250_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
25109 + struct pxa250_irda *si = dev->priv;
25110 + int speed = irda_get_next_speed(skb);
25116 + * Does this packet contain a request to change the interface
25117 + * speed? If so, remember it until we complete the transmission
25120 + if (speed != si->speed && speed != -1)
25121 + si->newspeed = speed;
25124 + * If this is an empty frame, we can bypass a lot.
25126 + if (skb->len == 0) {
25127 + if (si->newspeed) {
25128 + si->newspeed = 0;
25129 + pxa250_irda_set_speed(dev, speed);
25131 + dev_kfree_skb(skb);
25136 + DBG("stop queue\n");
25137 + netif_stop_queue(dev);
25142 + si->tx_buff.data = si->tx_buff.head;
25143 + si->tx_buff.len = async_wrap_skb(skb, si->tx_buff.data,
25144 + si->tx_buff.truesize);
25147 + pxa250_sir_transmit(dev);
25151 + dev_kfree_skb(skb);
25153 + dev->trans_start = jiffies;
25159 + DBG("Enter FIR transmit\n");
25161 + * We must not be transmitting...
25166 + disable_irq(si->fir_irq);
25168 + netif_stop_queue(dev);
25169 + DBG("queue stoped\n");
25172 + /* we could not just map so we'll need some triks */
25173 + /* skb->data may be not DMA capable -Sed- */
25176 + if (skb->len > TXBUFF_MAX_SIZE)
25178 + printk (KERN_ERR "skb data too large\n");
25179 + printk (KERN_ERR "len=%d",skb->len);
25184 + DBG("gonna copy %d bytes to txbuf\n",skb->len);
25186 + memcpy (si->txbuf_dma_virt, skb->data , skb->len);
25188 + /* Actual sending ;must not be receiving !!! */
25189 + /* Write data and source address */
25191 + DBG("ICSR1 & RNE =%d\n",(ICSR1 & ICSR1_RNE) ? 1 : 0 );
25193 + /*Disable receiver and enable transifer */
25194 + ICCR0 &= ~ICCR0_RXE;
25196 + if (ICSR1 & ICSR1_TBY)
25199 + ICCR0 |= ICCR0_TXE;
25201 + DBG("FICP status %x\n",ICSR0);
25206 + DBG("sending packet\n");
25207 + for (i=0;i<skb->len;i++)
25208 + (i % 64) ? printk ("%2x ",skb->data[i]) : printk ("%2x \n",skb->data[i]) ;
25213 + * If we have a mean turn-around time, impose the specified
25214 + * specified delay. We could shorten this by timing from
25215 + * the point we received the packet.
25218 + mtt = irda_get_mtt(skb);
25222 + DCSR(si->txdma_ch)=0;
25223 + DCSR(si->txdma_ch)=DCSR_NODESC;
25224 + DSADR(si->txdma_ch) = si->txbuf_dma; /* phisic address */
25225 + DTADR(si->txdma_ch) = __PREG(ICDR);
25227 + DCMD(si->txdma_ch) = DCMD_ENDIRQEN| DCMD_INCSRCADDR | DCMD_FLOWTRG | DCMD_BURST8 | DCMD_WIDTH1 | skb->len;
25229 + DCSR(si->txdma_ch) = DCSR_ENDINTR | DCSR_BUSERR;
25230 + DCSR(si->txdma_ch) = DCSR_RUN | DCSR_NODESC ;
25232 + DBG("FICP status %x\n",ICSR0);
25240 +pxa250_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
25242 + struct if_irda_req *rq = (struct if_irda_req *)ifreq;
25243 + struct pxa250_irda *si = dev->priv;
25244 + int ret = -EOPNOTSUPP;
25249 + case SIOCSBANDWIDTH:
25250 + if (capable(CAP_NET_ADMIN)) {
25252 + * We are unable to set the speed if the
25253 + * device is not running.
25256 + ret = pxa250_irda_set_speed(dev,
25257 + rq->ifr_baudrate);
25259 + printk("pxa250_irda_ioctl: SIOCSBANDWIDTH: !netif_running\n");
25265 + case SIOCSMEDIABUSY:
25267 + if (capable(CAP_NET_ADMIN)) {
25268 + irda_device_set_media_busy(dev, TRUE);
25273 + case SIOCGRECEIVING:
25274 + rq->ifr_receiving = IS_FIR(si) ? 0
25275 + : si->rx_buff.state != OUTSIDE_FRAME;
25287 +static struct net_device_stats *pxa250_irda_stats(struct net_device *dev)
25289 + struct pxa250_irda *si = dev->priv;
25290 + return &si->stats;
25293 +static int pxa250_irda_start(struct net_device *dev)
25295 + struct pxa250_irda *si = dev->priv;
25297 + unsigned int flags;
25300 + MOD_INC_USE_COUNT;
25303 + si->speed = 9600;
25305 + local_irq_save(flags);
25307 + err = request_irq(si->fir_irq, pxa250_irda_fir_irq, 0, dev->name, dev);
25309 + goto err_fir_irq;
25311 + err = request_irq(dev->irq, pxa250_irda_irq, 0, dev->name, dev);
25316 + * The interrupt must remain disabled for now.
25319 + disable_irq(dev->irq);
25320 + disable_irq(si->fir_irq);
25322 + local_irq_restore(flags);
25325 + /* Allocate DMA channel for receiver (not used) */
25326 + err = pxa_request_dma("IrDA receive", DMA_PRIO_LOW, pxa250_irda_rxdma_irq, dev);
25329 + si->rxdma_ch=err;
25331 + DRCMRRXICDR = DRCMR_MAPVLD | si->rxdma_ch;
25334 + /* Allocate DMA channel for transmit */
25335 + err = pxa_request_dma("IrDA transmit", DMA_PRIO_LOW, pxa250_irda_txdma_irq , dev);
25339 + si->txdma_ch=err;
25342 + * Make sure that ICP will be able
25343 + * to assert the transmit dma request bit
25344 + * through the peripherals request bus (PREQ)
25347 + DRCMRTXICDR = DRCMR_MAPVLD | si->txdma_ch;
25349 + DBG("rx(not used) channel=%d tx channel=%d\n",si->rxdma_ch,si->txdma_ch);
25351 + /* allocate consistent buffers for dma access
25352 + * buffers have to be aligned and situated in dma capable memory region;
25354 + si->rxbuf_dma_virt = consistent_alloc(GFP_KERNEL | GFP_DMA ,HPSIR_MAX_RXLEN , &si->rxbuf_dma);
25355 + if (! si->rxbuf_dma_virt )
25356 + goto err_rxbuf_dma;
25358 + si->txbuf_dma_virt = consistent_alloc(GFP_KERNEL | GFP_DMA, HPSIR_MAX_TXLEN, &si->txbuf_dma);
25359 + if (! si->txbuf_dma_virt )
25360 + goto err_txbuf_dma;
25362 + /* Alocate skb for receiver */
25363 + err=pxa250_irda_rx_alloc(si);
25365 + goto err_rx_alloc;
25368 + * Setup the serial port for the specified config.
25370 + err = pxa250_irda_startup(dev);
25372 + goto err_startup;
25374 + pxa250_irda_set_speed(dev,si->speed = 9600);
25378 + * Open a new IrLAP layer instance.
25380 + si->irlap = irlap_open(dev, &si->qos, "pxa250");
25386 + * Now enable the interrupt and start the queue
25389 + enable_irq(dev->irq);
25390 + netif_start_queue(dev);
25395 + pxa250_sir_irda_shutdown(si);
25397 + dev_kfree_skb(si->rxskb);
25399 + consistent_free (si->txbuf_dma_virt,HPSIR_MAX_TXLEN,si->txbuf_dma);
25401 + consistent_free (si->rxbuf_dma_virt,HPSIR_MAX_RXLEN,si->rxbuf_dma);
25403 + pxa_free_dma(si->txdma_ch);
25405 + pxa_free_dma(si->rxdma_ch);
25407 + free_irq(dev->irq, dev);
25409 + free_irq(si->fir_irq, dev);
25411 + MOD_DEC_USE_COUNT;
25415 +static int pxa250_irda_stop(struct net_device *dev)
25417 + struct pxa250_irda *si = dev->priv;
25419 + printk(KERN_ERR "Irda stop... RX = %d TX = %d\n",rx_count,tx_count);
25421 + disable_irq(dev->irq);
25422 + disable_irq(si->fir_irq);
25423 +/* pxa250_irda_shutdown(si); */
25426 + * If we have been doing DMA receive, make sure we
25427 + * tidy that up cleanly.
25430 + dev_kfree_skb(si->rxskb);
25431 + si->rxskb = NULL;
25436 + irlap_close(si->irlap);
25437 + si->irlap = NULL;
25440 + consistent_free (si->txbuf_dma_virt,HPSIR_MAX_TXLEN,si->txbuf_dma);
25441 + consistent_free (si->rxbuf_dma_virt,HPSIR_MAX_RXLEN,si->rxbuf_dma);
25442 + pxa_free_dma(si->txdma_ch);
25443 + pxa_free_dma(si->rxdma_ch);
25445 + netif_stop_queue(dev);
25451 + free_irq(dev->irq, dev);
25452 + free_irq(si->fir_irq, dev);
25455 + MOD_DEC_USE_COUNT;
25460 +static int pxa250_irda_init_iobuf(iobuff_t *io, int size)
25462 + io->head = kmalloc(size, GFP_KERNEL | GFP_DMA);
25463 + if (io->head != NULL) {
25464 + io->truesize = size;
25465 + io->in_frame = FALSE;
25466 + io->state = OUTSIDE_FRAME;
25467 + io->data = io->head;
25469 + return io->head ? 0 : -ENOMEM;
25475 +static int pxa250_stop_fir(struct net_device *dev)
25477 + struct pxa250_irda *si = dev->priv;
25478 + unsigned int flag;
25480 + save_flags(flag);
25483 + pxa250_dma_stop(si->txdma_ch);
25484 + pxa250_dma_stop(si->rxdma_ch);
25487 + dev_kfree_skb_irq(si->txskb);
25489 + ICCR0 &= ~(ICCR0_RXE | ICCR0_TXE );
25490 + disable_irq(si->fir_irq);
25491 + CKEN &= ~CKEN13_FICP;
25493 + restore_flags(flag);
25500 +static int pxa250_irda_set_speed(struct net_device *dev, int speed)
25502 + struct pxa250_irda *si = dev->priv;
25503 + int brd, ret = -EINVAL;
25504 + static int last_fir_speed=0;
25511 + case 9600: case 19200: case 38400:
25512 + case 57600: case 115200:
25514 + /* Baud rate fixed - Clo */
25519 + if (last_fir_speed)
25522 + pxa250_stop_fir(dev);
25523 + set_GPIO_mode (GPIO46_STRXD_MD);
25524 + set_GPIO_mode (GPIO47_STTXD_MD);
25526 + enable_irq(dev->irq);
25527 + netif_wake_queue(dev);
25528 + last_fir_speed=0;
25532 + LUB_MISC_WR &= ~(1 << 4);
25534 + brd = 14745600 / (16 * speed);
25536 + STLCR |= LCR_DLAB;
25538 + STDLH = brd >> 8; /* Clo: set Divisor Latch High */
25539 + STDLL = brd & 0xFF; /* Clo: set Devisor Latch Low */
25541 + STLCR &= ~LCR_DLAB; /* Clo: clear DLAB bit */
25543 + STMCR = MCR_OUT2;
25545 + CKEN |= CKEN5_STUART;
25547 + ICMR |= ( 1 << 20 );
25549 + STLCR = LCR_WLS1 | LCR_WLS0;
25553 + STFCR = FCR_TRFIFOE | FCR_RESETTF | FCR_RESETRF | FCR_ITL_1 ;// | FCR_ITL_16;
25555 + STIER = IER_UUE | IER_RAVIE | IER_RTIOE;
25557 + si->speed = speed;
25564 + if (last_fir_speed)
25567 + disable_irq(dev->irq);
25569 + pxa250_sir_irda_shutdown(si);
25570 + pxa250_fir_irda_startup(si);
25571 + pxa250_irda_rx_alloc(si);
25573 + pxa250_start_rx_dma(dev);
25574 + pxa250_ficp_rx_start();
25576 + enable_irq(si->fir_irq);
25577 + DBG("enable FIR \n");
25578 + si->speed = speed;
25580 + netif_wake_queue(dev);
25581 + last_fir_speed=1;
25597 +static int pxa250_irda_net_init(struct net_device *dev)
25599 + struct pxa250_irda *si = dev->priv;
25600 + unsigned int baudrate_mask;
25601 + int err = -ENOMEM;
25603 + si = kmalloc(sizeof(struct pxa250_irda), GFP_KERNEL);
25607 + memset(si, 0, sizeof(*si));
25610 + * Initialise the HP-SIR buffers
25613 + err = pxa250_irda_init_iobuf(&si->rx_buff, 14384);
25616 + err = pxa250_irda_init_iobuf(&si->tx_buff, 4000);
25618 + goto out_free_rx;
25620 + si->fir_irq = IRQ_ICP;
25622 + dev->hard_start_xmit = pxa250_irda_hard_xmit;
25623 + dev->open = pxa250_irda_start;
25624 + dev->stop = pxa250_irda_stop;
25625 + dev->do_ioctl = pxa250_irda_ioctl;
25626 + dev->get_stats = pxa250_irda_stats;
25628 + irda_device_setup(dev);
25629 + irda_init_max_qos_capabilies(&si->qos);
25632 + * We support original IRDA up to 115k2. (we don't currently
25633 + * support 4Mbps). Min Turn Time set to 1ms or greater.
25635 + baudrate_mask = IR_9600|IR_19200|IR_38400|IR_57600|IR_115200;
25636 + baudrate_mask |= IR_4000000 << 8;
25637 + si->qos.baud_rate.bits &= baudrate_mask;
25638 + si->qos.min_turn_time.bits = 7;
25640 + irda_qos_bits_to_value(&si->qos);
25644 + * Power-Management is optional.
25646 + si->pmdev = pm_register(PM_SYS_DEV, PM_SYS_IRDA, pxa250_irda_pmproc);
25648 + si->pmdev->data = dev;
25653 + kfree(si->tx_buff.head);
25655 + kfree(si->rx_buff.head);
25663 + * Remove all traces of this driver module from the kernel, so we can't be
25664 + * called. Note that the device has already been stopped, so we don't have
25665 + * to worry about interrupts or dma.
25667 +static void pxa250_irda_net_uninit(struct net_device *dev)
25669 + struct pxa250_irda *si = dev->priv;
25671 + dev->hard_start_xmit = NULL;
25672 + dev->open = NULL;
25673 + dev->stop = NULL;
25674 + dev->do_ioctl = NULL;
25675 + dev->get_stats = NULL;
25676 + dev->priv = NULL;
25678 + pm_unregister(si->pmdev);
25680 + kfree(si->tx_buff.head);
25681 + kfree(si->rx_buff.head);
25685 +static int __init pxa250_irda_init(void)
25687 + struct net_device *dev;
25691 + err = request_mem_region(__PREG(STRBR), 0x24, "IrDA") ? 0 : -EBUSY;
25696 + err = request_mem_region(__PREG(ICCR0), 0x1c, "IrDA") ? 0 : -EBUSY;
25702 + dev = dev_alloc("irda%d", &err);
25704 + dev->irq = IRQ_STUART;
25705 + dev->init = pxa250_irda_net_init;
25706 + dev->uninit = pxa250_irda_net_uninit;
25708 + err = register_netdevice(dev);
25718 + release_mem_region(__PREG(ICCR0), 0x1c);
25720 + release_mem_region(__PREG(STRBR), 0x24);
25726 +static void __exit pxa250_irda_exit(void)
25728 + struct net_device *dev = netdev;
25733 + unregister_netdevice(dev);
25737 + release_mem_region(__PREG(ICCR0), 0x1c);
25739 + release_mem_region(__PREG(STRBR), 0x24);
25742 + * We now know that the netdevice is no longer in use, and all
25743 + * references to our driver have been removed. The only structure
25744 + * which may still be present is the netdevice, which will get
25745 + * cleaned up by net/core/dev.c
25749 +module_init(pxa250_irda_init);
25750 +module_exit(pxa250_irda_exit);
25752 +MODULE_AUTHOR("Alexey Lugovskoy Frasenyak Dmitrij");
25753 +MODULE_DESCRIPTION("PXA250 SIR/FIR");
25754 +MODULE_LICENSE("GPL");
25755 +EXPORT_NO_SYMBOLS;
25757 +++ linux-2.4.27/drivers/net/smc91x.c
25759 +/*------------------------------------------------------------------------
25761 + . This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices.
25763 + . Copyright (C) 1996 by Erik Stahlman
25764 + . Copyright (C) 2001 Standard Microsystems Corporation
25765 + . Developed by Simple Network Magic Corporation
25766 + . Copyright (C) 2003 Monta Vista Software, Inc.
25767 + . Unified SMC91x driver by Nicolas Pitre
25769 + . This program is free software; you can redistribute it and/or modify
25770 + . it under the terms of the GNU General Public License as published by
25771 + . the Free Software Foundation; either version 2 of the License, or
25772 + . (at your option) any later version.
25774 + . This program is distributed in the hope that it will be useful,
25775 + . but WITHOUT ANY WARRANTY; without even the implied warranty of
25776 + . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25777 + . GNU General Public License for more details.
25779 + . You should have received a copy of the GNU General Public License
25780 + . along with this program; if not, write to the Free Software
25781 + . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25784 + . io = for the base address
25785 + . irq = for the IRQ
25786 + . nowait = 0 for normal wait states, 1 eliminates additional wait states
25788 + . original author:
25789 + . Erik Stahlman <erik@vt.edu>
25791 + . hardware multicast code:
25792 + . Peter Cammaert <pc@denkart.be>
25795 + . Daris A Nevil <dnevil@snmc.com>
25796 + . Nicolas Pitre <nico@cam.org>
25799 + . 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet
25800 + . 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ"
25801 + . 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111
25802 + . 08/22/01 Scott Anderson merge changes from smc9194 to smc91111
25803 + . 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111
25804 + . 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support
25805 + . 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races,
25806 + . more bus abstraction, big cleanup, etc.
25807 + ----------------------------------------------------------------------------*/
25809 +static const char version[] =
25810 + "smc91x.c: v1.0, mar 07 2003 by Nicolas Pitre <nico@cam.org>\n";
25812 +/* Debugging level */
25814 +#define SMC_DEBUG 0
25818 +#include <linux/config.h>
25819 +#include <linux/init.h>
25820 +#include <linux/module.h>
25821 +#include <linux/kernel.h>
25822 +#include <linux/sched.h>
25823 +#include <linux/slab.h>
25824 +#include <linux/delay.h>
25825 +#include <linux/timer.h>
25826 +#include <linux/errno.h>
25827 +#include <linux/ioport.h>
25829 +#include <linux/netdevice.h>
25830 +#include <linux/etherdevice.h>
25831 +#include <linux/skbuff.h>
25833 +#include <linux/pm.h>
25836 +#include <asm/io.h>
25837 +#include <asm/hardware.h>
25838 +#include <asm/irq.h>
25840 +#include "smc91x.h"
25845 + . the LAN91C111 can be at any of the following port addresses. To change,
25846 + . for a slightly different card, you can add it to the array. Keep in
25847 + . mind that the array must end in zero.
25849 +static unsigned int smc_portlist[] __initdata = {
25850 + 0x200, 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x2E0,
25851 + 0x300, 0x320, 0x340, 0x360, 0x380, 0x3A0, 0x3C0, 0x3E0, 0
25853 +#endif /* CONFIG_ISA */
25855 +#ifndef SMC_IOADDR
25856 +# define SMC_IOADDR -1
25858 +static int io = SMC_IOADDR;
25861 +# define SMC_IRQ -1
25863 +static int irq = SMC_IRQ;
25865 +#ifndef SMC_NOWAIT
25866 +# define SMC_NOWAIT 0
25868 +static int nowait = SMC_NOWAIT;
25870 +MODULE_PARM(io, "i");
25871 +MODULE_PARM(irq, "i");
25872 +MODULE_PARM(nowait, "i");
25873 +MODULE_PARM_DESC(io, "I/O base address");
25874 +MODULE_PARM_DESC(irq, "IRQ number");
25875 +MODULE_PARM_DESC(nowait, "set to 1 for no wait state");
25878 +/*------------------------------------------------------------------------
25880 + . The internal workings of the driver. If you are changing anything
25881 + . here with the SMC stuff, you should have the datasheet and know
25882 + . what you are doing.
25884 + -------------------------------------------------------------------------*/
25885 +#define CARDNAME "LAN91x"
25887 +// Use power-down feature of the chip
25888 +#define POWER_DOWN 1
25891 + . Wait time for memory to be free. This probably shouldn't be
25892 + . tuned that much, as waiting for this means nothing else happens
25895 +#define MEMORY_WAIT_TIME 16
25898 + . This selects whether TX packets are sent one by one to the SMC91x internal
25899 + . memory ans throttled until transmission completes. This may prevent
25900 + . RX overruns a litle by keeping much of the memory free for RX packets
25901 + . but to the expense of reduced TX throughput and increased IRQ overhead.
25902 + . Note this is not a cure for a too slow data bus or too high IRQ latency.
25904 +#define THROTTLE_TX_PKTS 0
25907 +/* store this information for the driver.. */
25908 +struct smc_local {
25910 + // If I have to wait until memory is available to send
25911 + // a packet, I will store the skbuff here, until I get the
25912 + // desired memory. Then, I'll send it out and free it.
25913 + struct sk_buff *saved_skb;
25915 + // these are things that the kernel wants me to keep, so users
25916 + // can find out semi-useless statistics of how well the card is
25918 + struct net_device_stats stats;
25920 + // version/revision of the SMC91x chip
25923 + // Set to true during the auto-negotiation sequence
25924 + int autoneg_active;
25926 + // Address of our PHY port
25932 + // Last contents of PHY Register 18
25935 + // Contains the current active transmission mode
25936 + int tcr_cur_mode;
25938 + // Contains the current active receive mode
25939 + int rcr_cur_mode;
25941 + // Contains the current active receive/phy mode
25942 + int rpc_cur_mode;
25948 + struct pm_dev* pm;
25955 +#define PRINTK3(args...) printk(args)
25957 +#define PRINTK3(args...) do { } while(0)
25961 +#define PRINTK2(args...) printk(args)
25963 +#define PRINTK2(args...) do { } while(0)
25967 +#define PRINTK1(args...) printk(args)
25968 +#define PRINTK(args...) printk(args)
25970 +#define PRINTK1(args...) do { } while(0)
25971 +#define PRINTK(args...) printk(KERN_DEBUG args)
25975 +static void PRINT_PKT(u_char *buf, int length)
25981 + lines = length / 16;
25982 + remainder = length % 16;
25984 + for (i = 0; i < lines ; i ++) {
25986 + for (cur = 0; cur < 8; cur++) {
25990 + printk("%02x%02x ", a, b);
25994 + for (i = 0; i < remainder/2 ; i++) {
25998 + printk("%02x%02x ", a, b );
26003 +#define PRINT_PKT(x...) do { } while(0)
26007 +/* this enables an interrupt in the interrupt mask register */
26008 +#define SMC_ENABLE_INT(x) do { \
26009 + unsigned long flags; \
26010 + unsigned char mask; \
26011 + local_irq_save(flags); \
26012 + mask = SMC_GET_INT_MASK(); \
26014 + SMC_SET_INT_MASK(mask); \
26015 + local_irq_restore(flags); \
26018 +/* this disables an interrupt from the interrupt mask register */
26019 +#define SMC_DISABLE_INT(x) do { \
26020 + unsigned long flags; \
26021 + unsigned char mask; \
26022 + local_irq_save(flags); \
26023 + mask = SMC_GET_INT_MASK(); \
26025 + SMC_SET_INT_MASK(mask); \
26026 + local_irq_restore(flags); \
26029 +/* wait while MMU is busy */
26030 +#define SMC_WAIT_MMU_BUSY() do { \
26031 + if (unlikely(SMC_GET_MMU_CMD() & MC_BUSY)) { \
26032 + unsigned long timeout = jiffies + 2; \
26033 + while (SMC_GET_MMU_CMD() & MC_BUSY) { \
26034 + if (time_after(jiffies, timeout)) { \
26035 + printk("%s: timeout %s line %d\n", \
26036 + dev->name, __FILE__, __LINE__); \
26044 +/* this does a soft reset on the device */
26046 +smc_reset(struct net_device *dev)
26048 + unsigned long ioaddr = dev->base_addr;
26049 + struct smc_local *lp = (struct smc_local *)dev->priv;
26050 + int phyaddr = lp->phyaddr;
26052 + PRINTK2("%s: %s\n", dev->name, __FUNCTION__);
26054 + /* This resets the registers mostly to defaults, but doesn't
26055 + affect EEPROM. That seems unnecessary */
26056 + SMC_SELECT_BANK( 0 );
26057 + SMC_SET_RCR( RCR_SOFTRST );
26059 + /* Setup the Configuration Register */
26060 + /* This is necessary because the CONFIG_REG is not affected */
26061 + /* by a soft reset */
26062 + SMC_SELECT_BANK( 1 );
26063 + SMC_SET_CONFIG( CONFIG_DEFAULT );
26065 + /* Setup for fast accesses if requested */
26066 + /* If the card/system can't handle it then there will */
26067 + /* be no recovery except for a hard reset or power cycle */
26069 + SMC_SET_CONFIG( SMC_GET_CONFIG() | CONFIG_NO_WAIT );
26072 + /* Release from possible power-down state */
26073 + /* Configuration register is not affected by Soft Reset */
26074 + SMC_SELECT_BANK( 1 );
26075 + SMC_SET_CONFIG( SMC_GET_CONFIG() | CONFIG_EPH_POWER_EN );
26076 + status = smc_read_phy_register(ioaddr, phyaddr, PHY_CNTL_REG);
26077 + status &= ~PHY_CNTL_PDN;
26078 + smc_write_phy_register(ioaddr, phyaddr, PHY_CNTL_REG);
26081 + /* this should pause enough for the chip to be happy */
26084 + /* Disable transmit and receive functionality */
26085 + SMC_SELECT_BANK( 0 );
26086 + SMC_SET_RCR( RCR_CLEAR );
26087 + SMC_SET_TCR( TCR_CLEAR );
26089 + /* set the control register to automatically
26090 + release successfully transmitted packets, to make the best
26091 + use out of our limited memory */
26092 + SMC_SELECT_BANK( 1 );
26093 +#if ! THROTTLE_TX_PKTS
26094 + SMC_SET_CTL( SMC_GET_CTL() | CTL_AUTO_RELEASE );
26096 + SMC_SET_CTL( SMC_GET_CTL() & ~CTL_AUTO_RELEASE );
26099 + /* Disable all interrupts */
26100 + SMC_SELECT_BANK( 2 );
26101 + SMC_SET_INT_MASK( 0 );
26103 + /* Reset the MMU */
26104 + SMC_SET_MMU_CMD( MC_RESET );
26105 + SMC_WAIT_MMU_BUSY();
26108 +/* Enable Interrupts, Receive, and Transmit */
26110 +smc_enable(struct net_device *dev)
26112 + unsigned long ioaddr = dev->base_addr;
26113 + struct smc_local *lp = (struct smc_local *)dev->priv;
26116 + PRINTK2("%s: %s\n", dev->name, __FUNCTION__);
26118 + /* see the header file for options in TCR/RCR DEFAULT*/
26119 + SMC_SELECT_BANK( 0 );
26120 + SMC_SET_TCR( lp->tcr_cur_mode );
26121 + SMC_SET_RCR( lp->rcr_cur_mode );
26123 + /* now, enable interrupts */
26124 + mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT;
26125 + if (lp->version >= 0x70)
26126 + mask |= IM_MDINT;
26127 + SMC_SELECT_BANK( 2 );
26128 + SMC_SET_INT_MASK( mask );
26131 +/* this puts the device in an inactive state */
26133 +smc_shutdown(struct net_device *dev)
26135 + int ioaddr = dev->base_addr;
26136 + struct smc_local *lp = (struct smc_local *)dev->priv;
26137 + int phyaddr = lp->phyaddr;
26140 + PRINTK2("%s: %s\n", CARDNAME, __FUNCTION__);
26142 + /* no more interrupts for me */
26143 + SMC_SELECT_BANK( 2 );
26144 + SMC_SET_INT_MASK( 0 );
26146 + /* and tell the card to stay away from that nasty outside world */
26147 + SMC_SELECT_BANK( 0 );
26148 + SMC_SET_RCR( RCR_CLEAR );
26149 + SMC_SET_TCR( TCR_CLEAR );
26152 + status = smc_read_phy_register(ioaddr, phyaddr, PHY_CNTL_REG);
26153 + status |= PHY_CNTL_PDN;
26154 + smc_write_phy_register(ioaddr, phyaddr, PHY_CNTL_REG);
26156 + /* finally, shut the chip down */
26157 + SMC_SELECT_BANK( 1 );
26158 + SMC_SET_CONFIG( SMC_GET_CONFIG() & ~CONFIG_EPH_POWER_EN );
26162 +/* This is the procedure to handle the receipt of a packet. */
26163 +static inline void
26164 +smc_rcv(struct net_device *dev)
26166 + struct smc_local *lp = (struct smc_local *)dev->priv;
26167 + unsigned long ioaddr = dev->base_addr;
26168 + unsigned int packet_number, status, packet_len;
26170 + PRINTK3("%s: %s\n", dev->name, __FUNCTION__);
26172 + packet_number = SMC_GET_RXFIFO();
26173 + if (unlikely(packet_number & RXFIFO_REMPTY)) {
26174 + PRINTK("%s: smc_rcv with nothing on FIFO.\n", dev->name);
26178 + /* read from start of packet */
26179 + SMC_SET_PTR( PTR_READ | PTR_RCV | PTR_AUTOINC );
26181 + /* First two words are status and packet length */
26182 + SMC_GET_PKT_HDR(status, packet_len);
26183 + packet_len &= 0x07ff; /* mask off top bits */
26184 + PRINTK2("%s: RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n",
26185 + dev->name, packet_number, status,
26186 + packet_len, packet_len);
26188 + if (unlikely(status & RS_ERRORS)) {
26189 + lp->stats.rx_errors++;
26190 + if (status & RS_ALGNERR)
26191 + lp->stats.rx_frame_errors++;
26192 + if (status & (RS_TOOSHORT | RS_TOOLONG))
26193 + lp->stats.rx_length_errors++;
26194 + if (status & RS_BADCRC)
26195 + lp->stats.rx_crc_errors++;
26197 + struct sk_buff *skb;
26198 + unsigned char *data;
26199 + unsigned int data_len;
26201 + /* set multicast stats */
26202 + if (status & RS_MULTICAST)
26203 + lp->stats.multicast++;
26206 + * Actual payload is packet_len - 4 (or 3 if odd byte).
26207 + * We want skb_reserve(2) and the final ctrl word
26208 + * (2 bytes, possibly containing the payload odd byte).
26209 + * Ence packet_len - 4 + 2 + 2.
26211 + skb = dev_alloc_skb(packet_len);
26212 + if (unlikely(skb == NULL)) {
26213 + printk(KERN_NOTICE "%s: Low memory, packet dropped.\n",
26215 + lp->stats.rx_dropped++;
26219 + /* Align IP header to 32 bits */
26220 + skb_reserve(skb, 2);
26222 + /* BUG: the LAN91C111 rev A never sets this bit. Force it. */
26223 + if (lp->version == 0x90)
26224 + status |= RS_ODDFRAME;
26227 + * If odd length: packet_len - 3,
26228 + * otherwise packet_len - 4.
26230 + data_len = packet_len - ((status & RS_ODDFRAME) ? 3 : 4);
26231 + data = skb_put(skb, data_len);
26232 + SMC_PULL_DATA(data, packet_len - 2);
26234 + PRINT_PKT(data, packet_len - 2);
26236 + dev->last_rx = jiffies;
26238 + skb->protocol = eth_type_trans(skb, dev);
26240 + lp->stats.rx_packets++;
26241 + lp->stats.rx_bytes += data_len;
26245 + SMC_WAIT_MMU_BUSY();
26246 + SMC_SET_MMU_CMD( MC_RELEASE );
26250 + * This is called to actually send a packet to the chip.
26251 + * Returns non-zero when successful.
26254 +smc_hardware_send_packet(struct net_device *dev)
26256 + struct smc_local *lp = (struct smc_local *)dev->priv;
26257 + unsigned long ioaddr = dev->base_addr;
26258 + struct sk_buff *skb = lp->saved_skb;
26259 + unsigned int packet_no, len;
26260 + unsigned char *buf;
26262 + PRINTK3("%s: %s\n", dev->name, __FUNCTION__);
26264 + if (unlikely(!skb)) {
26265 + printk ("%s: In XMIT with no packet to send\n", dev->name);
26269 + packet_no = SMC_GET_AR();
26270 + if (unlikely(packet_no & AR_FAILED)) {
26271 + printk("%s: Memory allocation failed.\n", dev->name);
26272 + lp->saved_skb = NULL;
26273 + lp->stats.tx_errors++;
26274 + lp->stats.tx_fifo_errors++;
26275 + dev_kfree_skb_any(skb);
26279 + /* point to the beginning of the packet */
26280 + SMC_SET_PN( packet_no );
26281 + SMC_SET_PTR( PTR_AUTOINC );
26285 + PRINTK2("%s: TX PNR 0x%x lENGTH 0x%04x (%d) BUF 9x%p\n",
26286 + dev->name, packet_no, len, len, buf);
26287 + PRINT_PKT(buf, len);
26290 + * Send the packet length ( +6 for status words, length, and ctl.
26291 + * The card will pad to 64 bytes with zeroes if packet is too small.
26293 + SMC_PUT_PKT_HDR(0, len + 6);
26295 + /* send the actual data */
26296 + SMC_PUSH_DATA(buf, len & ~1);
26298 + /* Send final ctl word with the last byte if there is one */
26299 + SMC_outw( ((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG );
26301 + /* and let the chipset deal with it */
26302 + SMC_SET_MMU_CMD( MC_ENQUEUE );
26303 + SMC_ACK_INT( IM_TX_EMPTY_INT );
26305 + dev->trans_start = jiffies;
26306 + dev_kfree_skb_any(skb);
26307 + lp->saved_skb = NULL;
26308 + lp->stats.tx_packets++;
26309 + lp->stats.tx_bytes += len;
26313 + . Since I am not sure if I will have enough room in the chip's ram
26314 + . to store the packet, I call this routine which either sends it
26315 + . now, or set the card to generates an interrupt when ready
26316 + . for the packet.
26319 +smc_hard_start_xmit( struct sk_buff * skb, struct net_device * dev )
26321 + struct smc_local *lp = (struct smc_local *)dev->priv;
26322 + unsigned long ioaddr = dev->base_addr;
26323 + unsigned int numPages, poll_count, status, saved_bank;
26325 + PRINTK3("%s: %s\n", dev->name, __FUNCTION__);
26327 + if (unlikely(lp->saved_skb != NULL)) {
26328 + /* THIS SHOULD NEVER HAPPEN. */
26329 + printk( KERN_CRIT
26330 + "%s: Bad Craziness - sent packet while busy.\n",
26332 + lp->stats.tx_errors++;
26333 + lp->stats.tx_aborted_errors++;
26336 + lp->saved_skb = skb;
26339 + ** The MMU wants the number of pages to be the number of 256 bytes
26340 + ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
26342 + ** The 91C111 ignores the size bits, but the code is left intact
26343 + ** for backwards and future compatibility.
26345 + ** Pkt size for allocating is data length +6 (for additional status
26346 + ** words, length and ctl!)
26348 + ** If odd size then last byte is included in ctl word.
26350 + numPages = ((skb->len & ~1) + (6 - 1)) >> 8;
26351 + if (unlikely(numPages > 7)) {
26352 + printk("%s: Far too big packet error.\n", dev->name);
26353 + lp->saved_skb = NULL;
26354 + lp->stats.tx_errors++;
26355 + lp->stats.tx_dropped++;
26356 + dev_kfree_skb(skb);
26360 + /* now, try to allocate the memory */
26361 + saved_bank = SMC_CURRENT_BANK();
26362 + SMC_SELECT_BANK( 2 );
26363 + SMC_SET_MMU_CMD( MC_ALLOC | numPages );
26366 + * Poll the chip for a short amount of time in case the
26367 + * allocation succeeds quickly.
26369 + poll_count = MEMORY_WAIT_TIME;
26371 + status = SMC_GET_INT();
26372 + if (status & IM_ALLOC_INT) {
26373 + SMC_ACK_INT( IM_ALLOC_INT );
26376 + } while (--poll_count);
26378 + if (!poll_count) {
26379 + /* oh well, wait until the chip finds memory later */
26380 + netif_stop_queue(dev);
26381 + PRINTK2("%s: TX memory allocation deferred.\n", dev->name);
26382 + SMC_ENABLE_INT( IM_ALLOC_INT );
26384 + /* Send current packet immediately.. */
26385 +#if THROTTLE_TX_PKTS
26386 + netif_stop_queue(dev);
26388 + smc_hardware_send_packet(dev);
26389 + SMC_ENABLE_INT( IM_TX_INT | IM_TX_EMPTY_INT );
26392 + SMC_SELECT_BANK( saved_bank );
26397 + . This handles a TX interrupt, which is only called when an error
26398 + . relating to a packet is sent or CTL_AUTO_RELEASE is not set.
26401 +smc_tx(struct net_device *dev)
26403 + unsigned long ioaddr = dev->base_addr;
26404 + struct smc_local *lp = (struct smc_local *)dev->priv;
26405 + unsigned int saved_packet, packet_no, tx_status, pkt_len;
26407 + PRINTK3("%s: %s\n", dev->name, __FUNCTION__);
26409 + /* If the TX FIFO is empty then nothing to do */
26410 + packet_no = SMC_GET_TXFIFO();
26411 + if (unlikely(packet_no & TXFIFO_TEMPTY)) {
26412 + PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name);
26416 + /* select packet to read from */
26417 + saved_packet = SMC_GET_PN();
26418 + SMC_SET_PN( packet_no );
26420 + /* read the first word (status word) from this packet */
26421 + SMC_SET_PTR( PTR_AUTOINC | PTR_READ );
26422 + SMC_GET_PKT_HDR(tx_status, pkt_len);
26423 + PRINTK2("%s: TX STATUS 0x%04x PNR 0x%02x\n",
26424 + dev->name, tx_status, packet_no);
26426 + if (!(tx_status & TS_SUCCESS))
26427 + lp->stats.tx_errors++;
26428 + if (tx_status & TS_LOSTCAR)
26429 + lp->stats.tx_carrier_errors++;
26430 + if (tx_status & TS_LATCOL) {
26431 + printk( KERN_DEBUG
26432 + "%s: Late collision occurred on last xmit.\n",
26434 + lp->stats.tx_window_errors++;
26437 + /* kill the packet */
26438 + SMC_WAIT_MMU_BUSY();
26439 + SMC_SET_MMU_CMD( MC_FREEPKT );
26441 + /* Don't restore Packet Number Reg until busy bit is cleared */
26442 + SMC_WAIT_MMU_BUSY();
26443 + SMC_SET_PN( saved_packet );
26445 + /* re-enable transmit */
26446 + SMC_SELECT_BANK( 0 );
26447 + SMC_SET_TCR( lp->tcr_cur_mode );
26448 + SMC_SELECT_BANK( 2 );
26452 +//---PHY CONTROL AND CONFIGURATION-----------------------------------------
26454 +/*------------------------------------------------------------
26455 + . Debugging function for viewing MII Management serial bitstream
26456 + .-------------------------------------------------------------*/
26459 +PRINT_MII_STREAM(u_char *bits, int size)
26464 + for (i = 0; i < size; ++i)
26465 + printk("%d", i%10);
26467 + printk("\nMDOE:");
26468 + for (i = 0; i < size; ++i) {
26469 + if (bits[i] & MII_MDOE)
26475 + printk("\nMDO :");
26476 + for (i = 0; i < size; ++i) {
26477 + if (bits[i] & MII_MDO)
26483 + printk("\nMDI :");
26484 + for (i = 0; i < size; ++i) {
26485 + if (bits[i] & MII_MDI)
26494 +#define PRINT_MII_STREAM(x...)
26497 +/*------------------------------------------------------------
26498 + . Reads a register from the MII Management serial interface
26499 + .-------------------------------------------------------------*/
26501 +smc_read_phy_register(unsigned long ioaddr, int phyaddr, int phyreg)
26504 + int i, mask, mii_reg;
26506 + int input_idx, phydata;
26509 + // 32 consecutive ones on MDO to establish sync
26510 + for (i = 0; i < 32; ++i)
26511 + bits[clk_idx++] = MII_MDOE | MII_MDO;
26513 + // Start code <01>
26514 + bits[clk_idx++] = MII_MDOE;
26515 + bits[clk_idx++] = MII_MDOE | MII_MDO;
26517 + // Read command <10>
26518 + bits[clk_idx++] = MII_MDOE | MII_MDO;
26519 + bits[clk_idx++] = MII_MDOE;
26521 + // Output the PHY address, msb first
26523 + for (i = 0; i < 5; ++i) {
26524 + if (phyaddr & mask)
26525 + bits[clk_idx++] = MII_MDOE | MII_MDO;
26527 + bits[clk_idx++] = MII_MDOE;
26529 + // Shift to next lowest bit
26533 + // Output the phy register number, msb first
26535 + for (i = 0; i < 5; ++i) {
26536 + if (phyreg & mask)
26537 + bits[clk_idx++] = MII_MDOE | MII_MDO;
26539 + bits[clk_idx++] = MII_MDOE;
26541 + // Shift to next lowest bit
26545 + // Tristate and turnaround (2 bit times)
26546 + bits[clk_idx++] = 0;
26547 + //bits[clk_idx++] = 0;
26549 + // Input starts at this bit time
26550 + input_idx = clk_idx;
26552 + // Will input 16 bits
26553 + for (i = 0; i < 16; ++i)
26554 + bits[clk_idx++] = 0;
26556 + // Final clock bit
26557 + bits[clk_idx++] = 0;
26559 + // Save the current bank
26560 + oldBank = SMC_CURRENT_BANK();
26563 + SMC_SELECT_BANK( 3 );
26565 + // Get the current MII register value
26566 + mii_reg = SMC_GET_MII();
26568 + // Turn off all MII Interface bits
26569 + mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
26571 + // Clock all 64 cycles
26572 + for (i = 0; i < sizeof bits; ++i) {
26573 + // Clock Low - output data
26574 + SMC_SET_MII( mii_reg | bits[i] );
26577 + // Clock Hi - input data
26578 + SMC_SET_MII( mii_reg | bits[i] | MII_MCLK );
26580 + bits[i] |= SMC_GET_MII() & MII_MDI;
26583 + // Return to idle state
26584 + // Set clock to low, data to low, and output tristated
26585 + SMC_SET_MII( mii_reg );
26588 + // Restore original bank select
26589 + SMC_SELECT_BANK( oldBank );
26591 + // Recover input data
26593 + for (i = 0; i < 16; ++i) {
26596 + if (bits[input_idx++] & MII_MDI)
26597 + phydata |= 0x0001;
26600 + PRINTK3("%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
26601 + __FUNCTION__, phyaddr, phyreg, phydata);
26602 + PRINT_MII_STREAM(bits, sizeof(bits));
26607 +/*------------------------------------------------------------
26608 + . Writes a register to the MII Management serial interface
26609 + .-------------------------------------------------------------*/
26611 +smc_write_phy_register( unsigned long ioaddr, int phyaddr,
26612 + int phyreg, int phydata )
26615 + int i, mask, mii_reg;
26619 + // 32 consecutive ones on MDO to establish sync
26620 + for (i = 0; i < 32; ++i)
26621 + bits[clk_idx++] = MII_MDOE | MII_MDO;
26623 + // Start code <01>
26624 + bits[clk_idx++] = MII_MDOE;
26625 + bits[clk_idx++] = MII_MDOE | MII_MDO;
26627 + // Write command <01>
26628 + bits[clk_idx++] = MII_MDOE;
26629 + bits[clk_idx++] = MII_MDOE | MII_MDO;
26631 + // Output the PHY address, msb first
26633 + for (i = 0; i < 5; ++i) {
26634 + if (phyaddr & mask)
26635 + bits[clk_idx++] = MII_MDOE | MII_MDO;
26637 + bits[clk_idx++] = MII_MDOE;
26639 + // Shift to next lowest bit
26643 + // Output the phy register number, msb first
26645 + for (i = 0; i < 5; ++i) {
26646 + if (phyreg & mask)
26647 + bits[clk_idx++] = MII_MDOE | MII_MDO;
26649 + bits[clk_idx++] = MII_MDOE;
26651 + // Shift to next lowest bit
26655 + // Tristate and turnaround (2 bit times)
26656 + bits[clk_idx++] = 0;
26657 + bits[clk_idx++] = 0;
26659 + // Write out 16 bits of data, msb first
26661 + for (i = 0; i < 16; ++i) {
26662 + if (phydata & mask)
26663 + bits[clk_idx++] = MII_MDOE | MII_MDO;
26665 + bits[clk_idx++] = MII_MDOE;
26667 + // Shift to next lowest bit
26671 + // Final clock bit (tristate)
26672 + bits[clk_idx++] = 0;
26674 + // Save the current bank
26675 + oldBank = SMC_CURRENT_BANK();
26678 + SMC_SELECT_BANK( 3 );
26680 + // Get the current MII register value
26681 + mii_reg = SMC_GET_MII();
26683 + // Turn off all MII Interface bits
26684 + mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
26686 + // Clock all cycles
26687 + for (i = 0; i < sizeof bits; ++i) {
26688 + // Clock Low - output data
26689 + SMC_SET_MII( mii_reg | bits[i] );
26692 + // Clock Hi - input data
26693 + SMC_SET_MII( mii_reg | bits[i] | MII_MCLK );
26695 + bits[i] |= SMC_GET_MII() & MII_MDI;
26698 + // Return to idle state
26699 + // Set clock to low, data to low, and output tristated
26700 + SMC_SET_MII( mii_reg );
26703 + // Restore original bank select
26704 + SMC_SELECT_BANK( oldBank );
26706 + PRINTK3("%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
26707 + __FUNCTION__, phyaddr, phyreg, phydata);
26708 + PRINT_MII_STREAM(bits, sizeof(bits));
26712 +/*------------------------------------------------------------
26713 + . Finds and reports the PHY address
26714 + .-------------------------------------------------------------*/
26715 +static int smc_detect_phy(struct net_device* dev)
26717 + struct smc_local *lp = (struct smc_local *)dev->priv;
26718 + unsigned long ioaddr = dev->base_addr;
26719 + int phy_id1, phy_id2;
26723 + PRINTK2("%s: %s\n", dev->name, __FUNCTION__);
26725 + // Scan all 32 PHY addresses if necessary
26726 + for (phyaddr = 0; phyaddr < 32; ++phyaddr) {
26727 + // Read the PHY identifiers
26728 + phy_id1 = smc_read_phy_register(ioaddr, phyaddr, PHY_ID1_REG);
26729 + phy_id2 = smc_read_phy_register(ioaddr, phyaddr, PHY_ID2_REG);
26731 + PRINTK3("%s: phy_id1=0x%x, phy_id2=0x%x\n",
26732 + dev->name, phy_id1, phy_id2);
26734 + // Make sure it is a valid identifier
26735 + if ((phy_id2 > 0x0000) && (phy_id2 < 0xffff) &&
26736 + (phy_id1 > 0x0000) && (phy_id1 < 0xffff)) {
26737 + if ((phy_id1 != 0x8000) && (phy_id2 != 0x8000)) {
26738 + // Save the PHY's address
26739 + lp->phyaddr = phyaddr;
26747 + PRINTK("%s: No PHY found\n", dev->name);
26751 + // Set the PHY type
26752 + if ( (phy_id1 == 0x0016) && ((phy_id2 & 0xFFF0) == 0xF840 ) ) {
26753 + lp->phytype = PHY_LAN83C183;
26754 + PRINTK("%s: PHY=LAN83C183 (LAN91C111 Internal)\n", dev->name);
26757 + if ( (phy_id1 == 0x0282) && ((phy_id2 & 0xFFF0) == 0x1C50) ) {
26758 + lp->phytype = PHY_LAN83C180;
26759 + PRINTK("%s: PHY=LAN83C180\n", dev->name);
26765 +/*------------------------------------------------------------
26766 + . Waits the specified number of milliseconds - kernel friendly
26767 + .-------------------------------------------------------------*/
26769 +smc_wait_ms(unsigned int ms)
26771 + if (!in_interrupt()) {
26772 + set_current_state(TASK_UNINTERRUPTIBLE);
26773 + schedule_timeout(1 + ms * HZ / 1000);
26775 + /* if this happens it must be fixed */
26776 + printk( KERN_WARNING "%s: busy wait while in interrupt!\n",
26782 +/*------------------------------------------------------------
26783 + . Sets the PHY to a configuration as determined by the user
26784 + .-------------------------------------------------------------*/
26786 +smc_phy_fixed(struct net_device *dev)
26788 + unsigned long ioaddr = dev->base_addr;
26789 + struct smc_local *lp = (struct smc_local *)dev->priv;
26790 + int phyaddr = lp->phyaddr;
26791 + int my_fixed_caps, cfg1;
26793 + PRINTK3("%s: %s\n", dev->name, __FUNCTION__);
26795 + // Enter Link Disable state
26796 + cfg1 = smc_read_phy_register(ioaddr, phyaddr, PHY_CFG1_REG);
26797 + cfg1 |= PHY_CFG1_LNKDIS;
26798 + smc_write_phy_register(ioaddr, phyaddr, PHY_CFG1_REG, cfg1);
26800 + // Set our fixed capabilities
26801 + // Disable auto-negotiation
26802 + my_fixed_caps = 0;
26804 + if (lp->ctl_rfduplx)
26805 + my_fixed_caps |= PHY_CNTL_DPLX;
26807 + if (lp->ctl_rspeed == 100)
26808 + my_fixed_caps |= PHY_CNTL_SPEED;
26810 + // Write our capabilities to the phy control register
26811 + smc_write_phy_register(ioaddr, phyaddr, PHY_CNTL_REG, my_fixed_caps);
26813 + // Re-Configure the Receive/Phy Control register
26814 + SMC_SET_RPC( lp->rpc_cur_mode );
26820 +/*------------------------------------------------------------
26821 + . Configures the specified PHY through the MII management interface
26822 + . using Autonegotiation.
26823 + . Calls smc_phy_fixed() if the user has requested a certain config.
26824 + .-------------------------------------------------------------*/
26826 +smc_phy_configure(struct net_device* dev)
26828 + unsigned long ioaddr = dev->base_addr;
26829 + struct smc_local *lp = (struct smc_local *)dev->priv;
26832 + int my_phy_caps; // My PHY capabilities
26833 + int my_ad_caps; // My Advertised capabilities
26836 + PRINTK3("%s:smc_program_phy()\n", dev->name);
26838 + // Set the blocking flag
26839 + lp->autoneg_active = 1;
26841 + // Find the address and type of our phy
26842 + if (!smc_detect_phy(dev))
26843 + goto smc_phy_configure_exit;
26845 + // Get the detected phy address
26846 + phyaddr = lp->phyaddr;
26848 + // Reset the PHY, setting all other bits to zero
26849 + smc_write_phy_register(ioaddr, phyaddr, PHY_CNTL_REG, PHY_CNTL_RST);
26851 + // Wait for the reset to complete, or time out
26852 + timeout = 6; // Wait up to 3 seconds
26853 + while (timeout--) {
26854 + if (!(smc_read_phy_register(ioaddr, phyaddr, PHY_CNTL_REG)
26856 + // reset complete
26858 + smc_wait_ms(500); // wait 500 millisecs
26859 + if (signal_pending(current)) { // Exit anyway if signaled
26860 + PRINTK("%s: PHY reset interrupted by signal\n",
26867 + if (timeout < 1) {
26868 + printk("%s: PHY reset timed out\n", dev->name);
26869 + goto smc_phy_configure_exit;
26872 + // Read PHY Register 18, Status Output
26873 + lp->lastPhy18 = smc_read_phy_register(ioaddr, phyaddr, PHY_INT_REG);
26875 + // Enable PHY Interrupts (for register 18)
26876 + // Interrupts listed here are disabled
26877 + smc_write_phy_register(ioaddr, phyaddr, PHY_MASK_REG,
26878 + PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
26879 + PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
26880 + PHY_INT_SPDDET | PHY_INT_DPLXDET);
26882 + /* Configure the Receive/Phy Control register */
26883 + SMC_SELECT_BANK( 0 );
26884 + SMC_SET_RPC( lp->rpc_cur_mode );
26886 + // Copy our capabilities from PHY_STAT_REG to PHY_AD_REG
26887 + my_phy_caps = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG);
26889 + // If the user requested no auto neg, then go set his request
26890 + if (!(lp->ctl_autoneg)) {
26891 + smc_phy_fixed(dev);
26892 + goto smc_phy_configure_exit;
26895 + if( !( my_phy_caps & PHY_STAT_CAP_ANEG))
26897 + printk(KERN_INFO "Auto negotiation NOT supported\n");
26898 + smc_phy_fixed(dev);
26899 + goto smc_phy_configure_exit;
26902 + my_ad_caps = PHY_AD_CSMA; // I am CSMA capable
26904 + if (my_phy_caps & PHY_STAT_CAP_T4)
26905 + my_ad_caps |= PHY_AD_T4;
26907 + if (my_phy_caps & PHY_STAT_CAP_TXF)
26908 + my_ad_caps |= PHY_AD_TX_FDX;
26910 + if (my_phy_caps & PHY_STAT_CAP_TXH)
26911 + my_ad_caps |= PHY_AD_TX_HDX;
26913 + if (my_phy_caps & PHY_STAT_CAP_TF)
26914 + my_ad_caps |= PHY_AD_10_FDX;
26916 + if (my_phy_caps & PHY_STAT_CAP_TH)
26917 + my_ad_caps |= PHY_AD_10_HDX;
26919 + // Disable capabilities not selected by our user
26920 + if (lp->ctl_rspeed != 100)
26921 + my_ad_caps &= ~(PHY_AD_T4|PHY_AD_TX_FDX|PHY_AD_TX_HDX);
26923 + if (!lp->ctl_rfduplx)
26924 + my_ad_caps &= ~(PHY_AD_TX_FDX|PHY_AD_10_FDX);
26926 + // Update our Auto-Neg Advertisement Register
26927 + smc_write_phy_register(ioaddr, phyaddr, PHY_AD_REG, my_ad_caps);
26929 + // Read the register back. Without this, it appears that when
26930 + // auto-negotiation is restarted, sometimes it isn't ready and
26931 + // the link does not come up.
26932 + status = smc_read_phy_register(ioaddr, phyaddr, PHY_AD_REG);
26934 + PRINTK2("%s: phy caps=%x\n", dev->name, my_phy_caps);
26935 + PRINTK2("%s: phy advertised caps=%x\n", dev->name, my_ad_caps);
26937 + // Restart auto-negotiation process in order to advertise my caps
26938 + smc_write_phy_register( ioaddr, phyaddr, PHY_CNTL_REG,
26939 + PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST );
26941 + // Wait for the auto-negotiation to complete. This may take from
26942 + // 2 to 3 seconds.
26943 + // Wait for the reset to complete, or time out
26944 + timeout = 20; // Wait up to 10 seconds
26945 + while (timeout--) {
26946 + status = smc_read_phy_register(ioaddr, phyaddr, PHY_RMT_REG);
26947 + if (status & PHY_AD_ACK)
26948 + // auto-negotiate complete
26951 + smc_wait_ms(500); // wait 500 millisecs
26952 + if (signal_pending(current)) { // Exit anyway if signaled
26953 + printk(KERN_DEBUG
26954 + "%s: PHY auto-negotiate interrupted by signal\n",
26960 + status = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG);
26962 + if (timeout < 1) {
26963 + PRINTK("%s: PHY auto-negotiate timed out\n", dev->name);
26966 + // Fail if we detected an auto-negotiate remote fault
26967 + if (status & PHY_STAT_REM_FLT) {
26968 + PRINTK("%s: PHY remote fault detected\n", dev->name);
26971 + // Wait for link. Once the link is up, phy18 should be up to date
26976 + status = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG);
26977 + } while ( ((status & PHY_STAT_LINK)==0) && --timeout);
26979 + if (status & PHY_STAT_LINK)
26981 + PRINTK("%s: Ethernet Link Detected\n", dev->name);
26984 + // The smc_phy_interrupt() routine will be called to update lastPhy18
26986 + // Set our sysctl parameters to match auto-negotiation results
26987 + if ( lp->lastPhy18 & PHY_INT_SPDDET ) {
26988 + PRINTK("%s: PHY 100BaseT\n", dev->name);
26989 + lp->rpc_cur_mode |= RPC_SPEED;
26991 + PRINTK("%s: PHY 10BaseT\n", dev->name);
26992 + lp->rpc_cur_mode &= ~RPC_SPEED;
26995 + if ( lp->lastPhy18 & PHY_INT_DPLXDET ) {
26996 + PRINTK("%s: PHY Full Duplex\n", dev->name);
26997 + lp->rpc_cur_mode |= RPC_DPLX;
26998 + lp->tcr_cur_mode |= TCR_SWFDUP;
27000 + PRINTK("%s: PHY Half Duplex\n", dev->name);
27001 + lp->rpc_cur_mode &= ~RPC_DPLX;
27002 + lp->tcr_cur_mode &= ~TCR_SWFDUP;
27005 + // Re-Configure the Receive/Phy Control register and TCR
27006 + SMC_SET_RPC( lp->rpc_cur_mode );
27007 + SMC_SET_TCR( lp->tcr_cur_mode );
27009 +smc_phy_configure_exit:
27010 + // Exit auto-negotiation
27011 + lp->autoneg_active = 0;
27014 +/*************************************************************************
27015 + . smc_phy_interrupt
27017 + . Purpose: Handle interrupts relating to PHY register 18. This is
27018 + . called from the "hard" interrupt handler.
27020 + ************************************************************************/
27022 +smc_phy_interrupt(struct net_device* dev)
27024 + unsigned long ioaddr = dev->base_addr;
27025 + struct smc_local *lp = (struct smc_local *)dev->priv;
27026 + int phyaddr = lp->phyaddr;
27029 + PRINTK2("%s: %s\n", dev->name, __FUNCTION__);
27032 + // Read PHY Register 18, Status Output
27033 + phy18 = smc_read_phy_register(ioaddr, phyaddr, PHY_INT_REG);
27035 + // Exit if not more changes
27036 + if (phy18 == lp->lastPhy18)
27040 + PRINTK2("%s: phy18=0x%04x\n", dev->name, phy18);
27041 + PRINTK2("%s: lastPhy18=0x%04x\n", dev->name, lp->lastPhy18);
27044 + if ((phy18 & PHY_INT_LNKFAIL) !=
27045 + (lp->lastPhy18 & PHY_INT_LNKFAIL))
27046 + PRINTK2("%s: PHY Link Fail=%x\n", dev->name,
27047 + phy18 & PHY_INT_LNKFAIL);
27049 + if ((phy18 & PHY_INT_LOSSSYNC) !=
27050 + (lp->lastPhy18 & PHY_INT_LOSSSYNC))
27051 + PRINTK2("%s: PHY LOSS SYNC=%x\n", dev->name,
27052 + phy18 & PHY_INT_LOSSSYNC);
27054 + if ((phy18 & PHY_INT_CWRD) != (lp->lastPhy18 & PHY_INT_CWRD))
27055 + PRINTK2("%s: PHY INVALID 4B5B code=%x\n", dev->name,
27056 + phy18 & PHY_INT_CWRD);
27058 + if ((phy18 & PHY_INT_SSD) != (lp->lastPhy18 & PHY_INT_SSD))
27059 + PRINTK2("%s: PHY No Start Of Stream=%x\n", dev->name,
27060 + phy18 & PHY_INT_SSD);
27062 + if ((phy18 & PHY_INT_ESD) != (lp->lastPhy18 & PHY_INT_ESD))
27064 + PRINTK2("%s: PHY No End Of Stream=%x\n", dev->name,
27065 + phy18 & PHY_INT_ESD);
27067 + if ((phy18 & PHY_INT_RPOL) != (lp->lastPhy18 & PHY_INT_RPOL))
27068 + PRINTK2("%s: PHY Reverse Polarity Detected=%x\n",
27069 + dev->name, phy18 & PHY_INT_RPOL);
27071 + if ((phy18 & PHY_INT_JAB) != (lp->lastPhy18 & PHY_INT_JAB))
27072 + PRINTK2("%s: PHY Jabber Detected=%x\n", dev->name,
27073 + phy18 & PHY_INT_JAB);
27075 + if ((phy18 & PHY_INT_SPDDET) !=
27076 + (lp->lastPhy18 & PHY_INT_SPDDET))
27077 + PRINTK2("%s: PHY Speed Detect=%x\n", dev->name,
27078 + phy18 & PHY_INT_SPDDET);
27080 + if ((phy18 & PHY_INT_DPLXDET) !=
27081 + (lp->lastPhy18 & PHY_INT_DPLXDET))
27082 + PRINTK2("%s: PHY Duplex Detect=%x\n", dev->name,
27083 + phy18 & PHY_INT_DPLXDET);
27085 + // Update the last phy 18 variable
27086 + lp->lastPhy18 = phy18;
27090 +//--- END PHY CONTROL AND CONFIGURATION-------------------------------------
27094 + * This is the main routine of the driver, to handle the device when
27095 + * it needs some attention.
27098 +smc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
27100 + struct net_device *dev = dev_id;
27101 + unsigned long ioaddr = dev->base_addr;
27102 + struct smc_local *lp = (struct smc_local *)dev->priv;
27103 + int status, mask, timeout, card_stats;
27104 + int saved_bank, saved_pointer;
27106 + PRINTK3("%s: %s\n", dev->name, __FUNCTION__);
27108 + saved_bank = SMC_CURRENT_BANK();
27109 + SMC_SELECT_BANK(2);
27110 + saved_pointer = SMC_GET_PTR();
27111 + mask = SMC_GET_INT_MASK();
27112 + SMC_SET_INT_MASK( 0 );
27114 + /* set a timeout value, so I don't stay here forever */
27118 + status = SMC_GET_INT();
27120 + PRINTK2("%s: IRQ 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n",
27121 + dev->name, status, mask,
27122 + ({ int meminfo; SMC_SELECT_BANK(0);
27123 + meminfo = SMC_GET_MIR();
27124 + SMC_SELECT_BANK(2); meminfo; }),
27131 + if (status & IM_RCV_INT) {
27132 + PRINTK3("%s: RX irq\n", dev->name);
27134 + } else if (status & IM_TX_INT) {
27135 + PRINTK3("%s: TX int\n", dev->name);
27137 + SMC_ACK_INT( IM_TX_INT );
27138 +#if THROTTLE_TX_PKTS
27139 + netif_wake_queue(dev);
27141 + } else if (status & IM_ALLOC_INT) {
27142 + PRINTK3("%s: Allocation irq\n", dev->name);
27143 + smc_hardware_send_packet(dev);
27144 + mask |= (IM_TX_INT | IM_TX_EMPTY_INT);
27145 + mask &= ~IM_ALLOC_INT;
27146 +#if ! THROTTLE_TX_PKTS
27147 + netif_wake_queue(dev);
27149 + } else if (status & IM_TX_EMPTY_INT) {
27150 + PRINTK3("%s: TX empty\n", dev->name);
27151 + mask &= ~IM_TX_EMPTY_INT;
27153 + /* update stats */
27154 + SMC_SELECT_BANK( 0 );
27155 + card_stats = SMC_GET_COUNTER();
27156 + SMC_SELECT_BANK( 2 );
27158 + /* single collisions */
27159 + lp->stats.collisions += card_stats & 0xF;
27160 + card_stats >>= 4;
27162 + /* multiple collisions */
27163 + lp->stats.collisions += card_stats & 0xF;
27164 + } else if (status & IM_RX_OVRN_INT) {
27165 + PRINTK1( "%s: RX overrun\n", dev->name);
27166 + SMC_ACK_INT( IM_RX_OVRN_INT );
27167 + lp->stats.rx_errors++;
27168 + lp->stats.rx_fifo_errors++;
27169 + } else if (status & IM_EPH_INT) {
27170 + PRINTK("%s: UNSUPPORTED: EPH INTERRUPT\n", dev->name);
27171 + } else if (status & IM_MDINT) {
27172 + SMC_ACK_INT( IM_MDINT );
27173 + smc_phy_interrupt(dev);
27174 + } else if (status & IM_ERCV_INT ) {
27175 + SMC_ACK_INT( IM_ERCV_INT );
27176 + PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT \n", dev->name);
27178 + } while (--timeout);
27180 + /* restore register states */
27181 + SMC_SET_INT_MASK( mask );
27182 + SMC_SET_PTR( saved_pointer );
27183 + SMC_SELECT_BANK( saved_bank );
27185 + PRINTK3("%s: Interrupt done\n", dev->name);
27188 +/* Our watchdog timed out. Called by the networking layer */
27190 +smc_timeout(struct net_device *dev)
27192 + struct smc_local *lp = (struct smc_local *)dev->priv;
27194 + PRINTK2("%s: %s\n", dev->name, __FUNCTION__);
27200 + /* Reconfiguring the PHY doesn't seem like a bad idea here, but
27201 + * it introduced a problem. Now that this is a timeout routine,
27202 + * we are getting called from within an interrupt context.
27203 + * smc_phy_configure() calls smc_wait_ms() which calls
27204 + * schedule_timeout() which calls schedule(). When schedule()
27205 + * is called from an interrupt context, it prints out
27206 + * "Scheduling in interrupt" and then calls BUG(). This is
27207 + * obviously not desirable. This was worked around by removing
27208 + * the call to smc_phy_configure() here because it didn't seem
27209 + * absolutely necessary. Ultimately, if smc_wait_ms() is
27210 + * supposed to be usable from an interrupt context (which it
27211 + * looks like it thinks it should handle), it should be fixed.
27213 + /* Reconfigure the PHY */
27214 + smc_phy_configure(dev);
27217 + /* clear anything saved */
27218 + if (lp->saved_skb != NULL) {
27219 + dev_kfree_skb (lp->saved_skb);
27220 + lp->saved_skb = NULL;
27221 + lp->stats.tx_errors++;
27222 + lp->stats.tx_aborted_errors++;
27224 + dev->trans_start = jiffies;
27225 + netif_wake_queue(dev);
27229 + * Finds the CRC32 of a set of bytes.
27230 + * (from Peter Cammaert's code)
27233 +crc32(char *s, int length)
27238 + /* crc polynomial for Ethernet */
27239 + const unsigned long poly = 0xedb88320;
27240 + /* crc value - preinitialized to all 1's */
27241 + unsigned long crc_value = 0xffffffff;
27243 + for ( perByte = 0; perByte < length; perByte ++ ) {
27247 + for ( perBit = 0; perBit < 8; perBit++ ) {
27248 + crc_value = (crc_value>>1)^
27249 + (((crc_value^c)&0x01)?poly:0);
27253 + return crc_value;
27257 + . This sets the internal hardware table to filter out unwanted multicast
27258 + . packets before they take up memory.
27260 + . The SMC chip uses a hash table where the high 6 bits of the CRC of
27261 + . address are the offset into the table. If that bit is 1, then the
27262 + . multicast packet is accepted. Otherwise, it's dropped silently.
27264 + . To use the 6 bits as an offset into the table, the high 3 bits are the
27265 + . number of the 8 bit register, while the low 3 bits are the bit within
27268 + . This routine is based very heavily on the one provided by Peter Cammaert.
27271 +smc_setmulticast(unsigned long ioaddr, int count, struct dev_mc_list *addrs)
27274 + unsigned char multicast_table[ 8 ];
27275 + struct dev_mc_list *cur_addr;
27277 + /* table for flipping the order of 3 bits */
27278 + static unsigned char invert3[] = { 0, 4, 2, 6, 1, 5, 3, 7 };
27280 + /* start with a table of all zeros: reject all */
27281 + memset( multicast_table, 0, sizeof( multicast_table ) );
27283 + cur_addr = addrs;
27284 + for ( i = 0; i < count ; i ++, cur_addr = cur_addr->next ) {
27287 + /* do we have a pointer here? */
27290 + /* make sure this is a multicast address - shouldn't this
27291 + be a given if we have it here ? */
27292 + if ( !( *cur_addr->dmi_addr & 1 ) )
27295 + /* only use the low order bits */
27296 + position = crc32( cur_addr->dmi_addr, 6 ) & 0x3f;
27298 + /* do some messy swapping to put the bit in the right spot */
27299 + multicast_table[invert3[position&7]] |=
27300 + (1<<invert3[(position>>3)&7]);
27303 + /* now, the table can be loaded into the chipset */
27304 + SMC_SELECT_BANK( 3 );
27305 + SMC_SET_MCAST( multicast_table );
27309 + . This routine will, depending on the values passed to it,
27310 + . either make it accept multicast packets, go into
27311 + . promiscuous mode ( for TCPDUMP and cousins ) or accept
27312 + . a select set of multicast packets
27314 +static void smc_set_multicast_list(struct net_device *dev)
27316 + struct smc_local *lp = (struct smc_local *)dev->priv;
27317 + unsigned long ioaddr = dev->base_addr;
27319 + PRINTK2("%s: %s\n", dev->name, __FUNCTION__);
27321 + SMC_SELECT_BANK(0);
27322 + if ( dev->flags & IFF_PROMISC ) {
27323 + PRINTK2("%s: RCR_PRMS\n", dev->name);
27324 + lp->rcr_cur_mode |= RCR_PRMS;
27325 + SMC_SET_RCR( lp->rcr_cur_mode );
27328 +/* BUG? I never disable promiscuous mode if multicasting was turned on.
27329 + Now, I turn off promiscuous mode, but I don't do anything to multicasting
27330 + when promiscuous mode is turned on.
27333 + /* Here, I am setting this to accept all multicast packets.
27334 + I don't need to zero the multicast table, because the flag is
27335 + checked before the table is
27337 + else if (dev->flags & IFF_ALLMULTI) {
27338 + lp->rcr_cur_mode |= RCR_ALMUL;
27339 + SMC_SET_RCR( lp->rcr_cur_mode );
27340 + PRINTK2("%s: RCR_ALMUL\n", dev->name);
27343 + /* We just get all multicast packets even if we only want them
27344 + . from one source. This will be changed at some future
27346 + else if (dev->mc_count ) {
27347 + /* support hardware multicasting */
27349 + /* be sure I get rid of flags I might have set */
27350 + lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
27351 + SMC_SET_RCR( lp->rcr_cur_mode );
27352 + /* NOTE: this has to set the bank, so make sure it is the
27353 + last thing called. The bank is set to zero at the top */
27354 + smc_setmulticast( ioaddr, dev->mc_count, dev->mc_list );
27356 + PRINTK2("%s: ~(RCR_PRMS|RCR_ALMUL)\n", dev->name);
27357 + lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
27358 + SMC_SET_RCR( lp->rcr_cur_mode );
27361 + since I'm disabling all multicast entirely, I need to
27362 + clear the multicast list
27364 + SMC_SELECT_BANK( 3 );
27365 + SMC_CLEAR_MCAST();
27371 + * Open and Initialize the board
27373 + * Set up everything, reset the card, etc ..
27376 +smc_open(struct net_device *dev)
27378 + struct smc_local *lp = (struct smc_local *)dev->priv;
27379 + unsigned long ioaddr = dev->base_addr;
27381 + PRINTK2("%s: %s\n", dev->name, __FUNCTION__);
27383 + /* clear out all the junk that was put here before... */
27384 + memset(dev->priv, 0, sizeof(struct smc_local));
27386 + // Setup the default Register Modes
27387 + lp->tcr_cur_mode = TCR_DEFAULT;
27388 + lp->rcr_cur_mode = RCR_DEFAULT;
27389 + lp->rpc_cur_mode = RPC_DEFAULT;
27391 + /* Set default parameters */
27392 +#ifdef CONFIG_ARCH_RAMSES
27393 + lp->ctl_autoneg = 0;
27394 + lp->ctl_rfduplx = 0;
27395 + lp->ctl_rspeed = 10;
27397 + lp->ctl_autoneg = 1;
27398 + lp->ctl_rfduplx = 1;
27399 + lp->ctl_rspeed = 100;
27402 + SMC_SELECT_BANK(3);
27403 + lp->version = SMC_GET_REV() & 0xff;
27405 + /* reset the hardware */
27409 + SMC_SELECT_BANK( 1 );
27410 + SMC_SET_MAC_ADDR(dev->dev_addr);
27412 + /* Configure the PHY */
27413 + if (lp->version >= 0x70)
27414 + smc_phy_configure(dev);
27416 + netif_start_queue(dev);
27420 +/*----------------------------------------------------
27423 + . this makes the board clean up everything that it can
27424 + . and not talk to the outside world. Caused by
27425 + . an 'ifconfig ethX down'
27427 + -----------------------------------------------------*/
27429 +smc_close(struct net_device *dev)
27431 + PRINTK2("%s: %s\n", dev->name, __FUNCTION__);
27433 + netif_stop_queue(dev);
27435 + /* clear everything */
27436 + smc_shutdown(dev);
27441 +/*------------------------------------------------------------
27442 + . Get the current statistics.
27443 + . This may be called with the card open or closed.
27444 + .-------------------------------------------------------------*/
27445 +static struct net_device_stats *
27446 +smc_query_statistics(struct net_device *dev)
27448 + struct smc_local *lp = (struct smc_local *)dev->priv;
27450 + PRINTK2("%s: %s\n", dev->name, __FUNCTION__);
27452 + return &lp->stats;
27455 +/*----------------------------------------------------------------------
27458 + . This routine has a simple purpose -- make the SMC chip generate an
27459 + . interrupt, so an auto-detect routine can detect it, and find the IRQ,
27460 + ------------------------------------------------------------------------
27463 +smc_findirq( unsigned long ioaddr )
27465 + int timeout = 20;
27466 + unsigned long cookie;
27468 + PRINTK2("%s: %s\n", CARDNAME, __FUNCTION__);
27470 + cookie = probe_irq_on();
27473 + * What I try to do here is trigger an ALLOC_INT. This is done
27474 + * by allocating a small chunk of memory, which will give an interrupt
27478 + /* enable ALLOCation interrupts ONLY */
27479 + SMC_SELECT_BANK(2);
27480 + SMC_SET_INT_MASK( IM_ALLOC_INT );
27483 + . Allocate 512 bytes of memory. Note that the chip was just
27484 + . reset so all the memory is available
27486 + SMC_SET_MMU_CMD( MC_ALLOC | 1 );
27489 + . Wait until positive that the interrupt has been generated
27494 + int_status = SMC_GET_INT();
27495 + if (int_status & IM_ALLOC_INT)
27496 + break; /* got the interrupt */
27497 + } while (--timeout);
27499 + /* there is really nothing that I can do here if timeout fails,
27500 + as autoirq_report will return a 0 anyway, which is what I
27501 + want in this case. Plus, the clean up is needed in both
27504 + /* and disable all interrupts again */
27505 + SMC_SET_INT_MASK( 0 );
27507 + /* and return what I found */
27508 + return probe_irq_off(cookie);
27511 +/*----------------------------------------------------------------------
27512 + . Function: smc_probe( unsigned long ioaddr )
27515 + . Tests to see if a given ioaddr points to an SMC91x chip.
27516 + . Returns a 0 on success
27519 + . (1) see if the high byte of BANK_SELECT is 0x33
27520 + . (2) compare the ioaddr with the base register's address
27521 + . (3) see if I recognize the chip ID in the appropriate register
27523 + .---------------------------------------------------------------------
27525 +/*---------------------------------------------------------------
27526 + . Here I do typical initialization tasks.
27528 + . o Initialize the structure if needed
27529 + . o print out my vanity message if not done so already
27530 + . o print out what type of hardware is detected
27531 + . o print out the ethernet address
27533 + . o set up my private data
27534 + . o configure the dev structure with my subroutines
27535 + . o actually GRAB the irq.
27536 + . o GRAB the region
27537 + .-----------------------------------------------------------------
27540 +smc_probe(struct net_device *dev, unsigned long ioaddr)
27542 + struct smc_local *lp = (struct smc_local *)dev->priv;
27543 + static int version_printed = 0;
27545 + unsigned int val, revision_register;
27546 + const char *version_string;
27548 + PRINTK2("%s: %s\n", CARDNAME, __FUNCTION__);
27550 + /* Grab the region so that no one else tries to probe our ioports. */
27551 + if (!request_region(ioaddr, SMC_IO_EXTENT, dev->name))
27554 + /* First, see if the high byte is 0x33 */
27555 + val = SMC_CURRENT_BANK();
27556 + PRINTK2("%s: bank signature probe returned 0x%04x\n", CARDNAME, val);
27557 + if ( (val & 0xFF00) != 0x3300 ) {
27558 + if ( (val & 0xFF) == 0x33 ) {
27559 + printk( KERN_WARNING
27560 + "%s: Detected possible byte-swapped interface"
27561 + " at IOADDR 0x%lx\n", CARDNAME, ioaddr);
27563 + retval = -ENODEV;
27567 + /* The above MIGHT indicate a device, but I need to write to further
27569 + SMC_SELECT_BANK(0);
27570 + val = SMC_CURRENT_BANK();
27571 + if ( (val & 0xFF00 ) != 0x3300 ) {
27572 + retval = -ENODEV;
27576 + /* well, we've already written once, so hopefully another time won't
27577 + hurt. This time, I need to switch the bank register to bank 1,
27578 + so I can access the base address register */
27579 + SMC_SELECT_BANK(1);
27580 + val = SMC_GET_BASE();
27581 + val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT;
27582 + if ( (ioaddr & ((PAGE_SIZE-1)<<SMC_IO_SHIFT)) != val ) {
27583 + printk( "%s: IOADDR %lx doesn't match configuration (%x).\n",
27584 + CARDNAME, ioaddr, val );
27587 + /* check if the revision register is something that I recognize.
27588 + These might need to be added to later, as future revisions
27589 + could be added. */
27590 + SMC_SELECT_BANK(3);
27591 + revision_register = SMC_GET_REV();
27592 + PRINTK2("%s: revision = 0x%04x\n", CARDNAME, revision_register);
27593 + version_string = chip_ids[ (revision_register >> 4) & 0xF];
27594 + if (!version_string || (revision_register & 0xff00) != 0x3300) {
27595 + /* I don't recognize this chip, so... */
27596 + printk( "%s: IO 0x%lx: Unrecognized revision register 0x%04x"
27597 + ", Contact author.\n", CARDNAME,
27598 + ioaddr, revision_register);
27600 + retval = -ENODEV;
27604 + /* At this point I'll assume that the chip is an SMC91x. */
27605 + if (version_printed++ == 0)
27606 + printk("%s", version);
27608 + /* set the private data to zero by default */
27609 + memset(lp, 0, sizeof(struct smc_local));
27611 + /* fill in some of the fields */
27612 + dev->base_addr = ioaddr;
27613 + lp->version = revision_register & 0xff;
27615 + /* Get the MAC address */
27616 + SMC_SELECT_BANK( 1 );
27617 + SMC_GET_MAC_ADDR(dev->dev_addr);
27619 + /* now, reset the chip, and put it into a known state */
27620 + smc_reset( dev );
27623 + . If dev->irq is 0, then the device has to be banged on to see
27624 + . what the IRQ is.
27626 + . This banging doesn't always detect the IRQ, for unknown reasons.
27627 + . a workaround is to reset the chip and try again.
27629 + . Interestingly, the DOS packet driver *SETS* the IRQ on the card to
27630 + . be what is requested on the command line. I don't do that, mostly
27631 + . because the card that I have uses a non-standard method of accessing
27632 + . the IRQs, and because this _should_ work in most configurations.
27634 + . Specifying an IRQ is done with the assumption that the user knows
27635 + . what (s)he is doing. No checking is done!!!!
27638 + if ( dev->irq < 1 ) {
27642 + while ( trials-- ) {
27643 + dev->irq = smc_findirq( ioaddr );
27646 + /* kick the card and try again */
27647 + smc_reset( dev );
27650 + if (dev->irq == 0 ) {
27651 + printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n",
27653 + retval = -ENODEV;
27656 + dev->irq = irq_cannonicalize(dev->irq);
27658 + /* now, print out the card info, in a short format.. */
27659 + printk( "%s: %s (rev %d) at %#lx IRQ %d%s%s\n",
27660 + dev->name, version_string, revision_register & 0x0f,
27661 + ioaddr, dev->irq, nowait ? " [nowait]" : "",
27662 + THROTTLE_TX_PKTS ? " [throttle_tx]" : "" );
27664 + /* Print the Ethernet address */
27665 + printk("%s: Ethernet addr: ", dev->name);
27666 + for (i = 0; i < 5; i++)
27667 + printk("%2.2x:", dev->dev_addr[i] );
27668 + printk("%2.2x\n", dev->dev_addr[5] );
27670 + /* Fill in the fields of the device structure with ethernet values. */
27671 + ether_setup(dev);
27673 + /* Grab the IRQ */
27674 + retval = request_irq(dev->irq, &smc_interrupt, 0, dev->name, dev);
27679 + dev->open = smc_open;
27680 + dev->stop = smc_close;
27681 + dev->hard_start_xmit = smc_hard_start_xmit;
27682 + dev->tx_timeout = smc_timeout;
27683 + dev->watchdog_timeo = HZ/10;
27684 + dev->get_stats = smc_query_statistics;
27685 + dev->set_multicast_list = smc_set_multicast_list;
27690 + release_region(ioaddr, SMC_IO_EXTENT);
27694 +/*-------------------------------------------------------------------------
27696 + | smc_init( void )
27697 + | Input parameters:
27698 + | dev->base_addr == 0, try to find all possible locations
27699 + | dev->base_addr > 0x1ff, this is the address to check
27700 + | dev->base_addr == <anything else>, return failure code
27703 + | 0 --> there is a device
27704 + | anything else, error
27706 + ---------------------------------------------------------------------------
27708 +static struct net_device *global_dev = NULL; /* needs to be fixed */
27712 +static int smc_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *data)
27714 + unsigned long ioaddr = global_dev->base_addr;
27715 + struct smc_local *lp = (struct smc_local *)global_dev->priv;
27719 + smc_shutdown(global_dev);
27722 + smc_reset(global_dev);
27723 + smc_enable(global_dev);
27724 + SMC_SELECT_BANK( 1 );
27725 + SMC_SET_MAC_ADDR(global_dev->dev_addr);
27726 + if (lp->version >= 0x70)
27727 + smc_phy_configure(global_dev);
27740 + PRINTK2("%s: %s\n", CARDNAME, __FUNCTION__);
27744 + printk( KERN_WARNING
27745 + "%s: You shouldn't use auto-probing with insmod!\n",
27749 + if (global_dev) {
27750 + printk("%s: already initialized.\n", CARDNAME);
27754 + global_dev = init_etherdev(0, sizeof(struct smc_local));
27755 + if (!global_dev) {
27756 + printk("%s: could not allocate device.\n", CARDNAME);
27759 + SET_MODULE_OWNER(global_dev);
27761 + /* copy the parameters from insmod into the device structure */
27763 + global_dev->base_addr = io;
27765 + global_dev->irq = irq;
27768 + /* try a specific location */
27769 + if (global_dev->base_addr > 0x1ff)
27770 + ret = smc_probe(global_dev, global_dev->base_addr);
27771 + else if (global_dev->base_addr != 0)
27776 + /* check every ethernet address */
27777 + for (i = 0; smc_portlist[i]; i++) {
27778 + ret = smc_probe(global_dev, smc_portlist[i]);
27783 +#elif defined(CONFIG_ARCH_LUBBOCK)
27785 + int ioaddr = LUBBOCK_ETH_VIRT + (0x300 << 2);
27786 + volatile int *attaddr = (int *)(LUBBOCK_ETH_VIRT + 0x100000);
27787 + unsigned long flags;
27789 + /* first reset, then enable the device. Sequence is critical */
27790 + local_irq_save(flags);
27791 + attaddr[ECOR] |= ECOR_RESET;
27793 + attaddr[ECOR] &= ~ECOR_RESET;
27794 + attaddr[ECOR] |= ECOR_ENABLE;
27796 + /* force 16-bit mode */
27797 + attaddr[ECSR] &= ~ECSR_IOIS8;
27799 + local_irq_restore(flags);
27801 + global_dev->irq = LUBBOCK_ETH_IRQ;
27802 + ret = smc_probe(global_dev, ioaddr);
27804 +#elif defined(CONFIG_ARCH_PXA_IDP)
27806 + int ioaddr = IDP_ETH_BASE + 0x300;
27807 + global_dev->irq = SMC_IRQ;
27808 + ret = smc_probe(global_dev, ioaddr);
27810 +#elif defined(CONFIG_ARCH_RAMSES)
27812 + int ioaddr = RAMSES_ETH_BASE + 0x300;
27813 + global_dev->irq = SMC_IRQ;
27814 + ret = smc_probe(global_dev, ioaddr);
27817 + if (global_dev->base_addr == -1) {
27818 + printk(KERN_WARNING"%s: SMC91X_BASE_ADDR not set!\n", CARDNAME);
27821 + void *ioaddr = ioremap(global_dev->base_addr, SMC_IO_EXTENT);
27822 + ret = smc_probe(global_dev, (unsigned long)ioaddr);
27828 +#ifdef SMC_USE_PXA_DMA
27830 + int dma = pxa_request_dma(global_dev->name, DMA_PRIO_LOW,
27831 + smc_pxa_dma_irq, NULL);
27833 + global_dev->dma = dma;
27834 + PRINTK("%s: using DMA channel %d\n", global_dev->name, dma);
27836 + global_dev->dma = -1;
27843 + struct smc_local *lp = (struct smc_local *)global_dev->priv;
27844 + lp->pm = pm_register(PM_SYS_UNKNOWN, 0x73393178, smc_pm_callback);
27849 + printk("%s: not found.\n", CARDNAME);
27850 + kfree(global_dev->priv);
27851 + unregister_netdev(global_dev);
27852 + kfree(global_dev);
27858 +static void __exit
27861 + unregister_netdev(global_dev);
27864 + struct smc_local *lp = (struct smc_local *)global_dev->priv;
27865 + pm_unregister(lp->pm);
27868 + free_irq(global_dev->irq, global_dev);
27869 + release_region(global_dev->base_addr, SMC_IO_EXTENT);
27871 +#ifndef CONFIG_ISA
27872 + iounmap((void *)global_dev->base_addr);
27875 + kfree(global_dev);
27876 + global_dev = NULL;
27879 +module_init(smc_init);
27880 +module_exit(smc_cleanup);
27883 +++ linux-2.4.27/drivers/net/smc91x.h
27885 +/*------------------------------------------------------------------------
27886 + . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
27888 + . Copyright (C) 1996 by Erik Stahlman
27889 + . Copyright (C) 2001 Standard Microsystems Corporation
27890 + . Developed by Simple Network Magic Corporation
27891 + . Copyright (C) 2003 Monta Vista Software, Inc.
27892 + . Unified SMC91x driver by Nicolas Pitre
27894 + . This program is free software; you can redistribute it and/or modify
27895 + . it under the terms of the GNU General Public License as published by
27896 + . the Free Software Foundation; either version 2 of the License, or
27897 + . (at your option) any later version.
27899 + . This program is distributed in the hope that it will be useful,
27900 + . but WITHOUT ANY WARRANTY; without even the implied warranty of
27901 + . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27902 + . GNU General Public License for more details.
27904 + . You should have received a copy of the GNU General Public License
27905 + . along with this program; if not, write to the Free Software
27906 + . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27908 + . Information contained in this file was obtained from the LAN91C111
27909 + . manual from SMC. To get a copy, if you really want one, you can find
27910 + . information under www.smsc.com.
27913 + . Erik Stahlman <erik@vt.edu>
27914 + . Daris A Nevil <dnevil@snmc.com>
27915 + . Nicolas Pitre <nico@cam.org>
27917 + ---------------------------------------------------------------------------*/
27918 +#ifndef _SMC91X_H_
27919 +#define _SMC91X_H_
27923 + * Define your architecture specific configuration parameters here.
27926 +#if defined(CONFIG_SA1100_GRAPHICSCLIENT) || \
27927 + defined(CONFIG_SA1100_PFS168) || \
27928 + defined(CONFIG_SA1100_FLEXANET) || \
27929 + defined(CONFIG_SA1100_GRAPHICSMASTER) || \
27930 + defined(CONFIG_ARCH_LUBBOCK)
27932 +/* We can only do 16-bit reads and writes in the static memory space. */
27933 +#define SMC_CAN_USE_8BIT 0
27934 +#define SMC_CAN_USE_16BIT 1
27935 +#define SMC_CAN_USE_32BIT 0
27936 +#define SMC_NOWAIT 1
27938 +/* The first two address lines aren't connected... */
27939 +#define SMC_IO_SHIFT 2
27941 +#define SMC_inw(a, r) readw((a) + (r))
27942 +#define SMC_outw(v, a, r) writew(v, (a) + (r))
27943 +#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
27944 +#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
27946 +#ifdef CONFIG_ARCH_LUBBOCK
27947 +#define SMC_IOADDR LUBBOCK_ETH_PHYS
27950 +#elif defined(CONFIG_ARCH_MAINSTONE) || defined(CONFIG_ARCH_PXA_IDP) || defined(CONFIG_ARCH_RAMSES)
27952 +#ifdef CONFIG_ARCH_MAINSTONE
27953 +#include <asm/arch/mainstone.h>
27954 +#define SMC_IOADDR (MST_ETH_PHYS + 0x300)
27955 +#define SMC_IRQ MAINSTONE_IRQ(3)
27957 +#elif CONFIG_ARCH_PXA_IDP
27958 +#include <asm/arch/idp.h>
27959 +#define SMC_IOADDR (IDP_ETH_PHYS + 0x300)
27960 +#define SMC_IRQ ETHERNET_IRQ
27962 +#elif CONFIG_ARCH_RAMSES
27963 +#include <asm/arch/ramses.h>
27964 +#define SMC_IOADDR (RAMSES_ETH_PHYS + 0x300)
27965 +#define SMC_IRQ ETHERNET_IRQ
27968 +#define SMC_CAN_USE_8BIT 1
27969 +#define SMC_CAN_USE_16BIT 1
27970 +#define SMC_CAN_USE_32BIT 1
27971 +#define SMC_IO_SHIFT 0
27972 +#define SMC_NOWAIT 1
27973 +#define SMC_USE_PXA_DMA 1
27975 +#define SMC_inb(a, r) readb((a) + (r))
27976 +#define SMC_inw(a, r) readw((a) + (r))
27977 +#define SMC_inl(a, r) readl((a) + (r))
27978 +#define SMC_outb(v, a, r) writeb(v, (a) + (r))
27979 +#define SMC_outl(v, a, r) writel(v, (a) + (r))
27980 +#define SMC_insl(a, r, p, l) insl((a) + (r), p, l)
27981 +#define SMC_outsl(a, r, p, l) outsl((a) + (r), p, l)
27983 +/* We actually can't write halfwords properly if not word aligned */
27984 +static inline void
27985 +SMC_outw(u16 val, unsigned long ioaddr, int reg)
27988 + unsigned int v = val << 16;
27989 + v |= readl(ioaddr + (reg & ~2)) & 0xffff;
27990 + writel(v, ioaddr + (reg & ~2));
27992 + writew(val, ioaddr + reg);
27996 +#elif defined(CONFIG_ISA)
27998 +#define SMC_CAN_USE_8BIT 1
27999 +#define SMC_CAN_USE_16BIT 1
28000 +#define SMC_CAN_USE_32BIT 0
28002 +#define SMC_inb(a, r) inb((a) + (r))
28003 +#define SMC_inw(a, r) inw((a) + (r))
28004 +#define SMC_outb(v, a, r) outb(v, (a) + (r))
28005 +#define SMC_outw(v, a, r) outw(v, (a) + (r))
28006 +#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
28007 +#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
28012 +#ifdef SMC_USE_PXA_DMA
28014 + * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
28015 + * always happening in irq context so no need to worry about races. TX is
28016 + * different and probably not worth it for that reason, and not as critical
28017 + * as RX which can overrun memory and lose packets.
28019 +#include <linux/pci.h>
28020 +#include <asm/dma.h>
28024 +#define SMC_insl(a, r, p, l) smc_pxa_dma_insl(a, r, dev->dma, p, l)
28025 +static inline void
28026 +smc_pxa_dma_insl(u_long ioaddr, int reg, int dma, u_char *buf, int len)
28028 + dma_addr_t dmabuf;
28030 + /* fallback if no DMA available */
28032 + insl(ioaddr + reg, buf, len);
28036 + /* 64 bit alignment is required for memory to memory DMA */
28037 + if ((long)buf & 4) {
28038 + *((u32 *)buf)++ = SMC_inl(ioaddr, reg);
28043 + dmabuf = pci_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE);
28044 + DCSR(dma) = DCSR_NODESC;
28045 + DTADR(dma) = dmabuf;
28046 + DSADR(dma) = SMC_IOADDR + reg;
28047 + DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
28048 + DCMD_WIDTH4 | (DCMD_LENGTH & len));
28049 + DCSR(dma) = DCSR_NODESC | DCSR_RUN;
28050 + while (!(DCSR(dma) & DCSR_STOPSTATE));
28052 + pci_unmap_single(NULL, dmabuf,len, PCI_DMA_FROMDEVICE);
28058 +#define SMC_insw(a, r, p, l) smc_pxa_dma_insw(a, r, dev->dma, p, l)
28059 +static inline void
28060 +smc_pxa_dma_insw(u_long ioaddr, int reg, int dma, u_char *buf, int len)
28062 + dma_addr_t dmabuf;
28064 + /* fallback if no DMA available */
28066 + insw(ioaddr + reg, buf, len);
28070 + /* 64 bit alignment is required for memory to memory DMA */
28071 + while ((long)buf & 6) {
28072 + *((u16 *)buf)++ = SMC_inw(ioaddr, reg);
28077 + dmabuf = pci_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE);
28078 + DCSR(dma) = DCSR_NODESC;
28079 + DTADR(dma) = dmabuf;
28080 + DSADR(dma) = SMC_IOADDR + reg;
28081 + DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
28082 + DCMD_WIDTH2 | (DCMD_LENGTH & len));
28083 + DCSR(dma) = DCSR_NODESC | DCSR_RUN;
28084 + while (!(DCSR(dma) & DCSR_STOPSTATE));
28086 + pci_unmap_single(NULL, dmabuf,len, PCI_DMA_FROMDEVICE);
28091 +smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs)
28095 +#endif /* SMC_USE_PXA_DMA */
28098 +/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
28099 +#ifndef SMC_IO_SHIFT
28100 +#define SMC_IO_SHIFT 0
28102 +#define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
28106 + . Bank Select Register:
28108 + . yyyy yyyy 0000 00xx
28109 + . xx = bank number
28110 + . yyyy yyyy = 0x33, for identification purposes.
28112 +#define BANK_SELECT (14 << SMC_IO_SHIFT)
28115 +// Transmit Control Register
28117 +#define TCR_REG SMC_REG(0x0000, 0)
28118 +#define TCR_ENABLE 0x0001 // When 1 we can transmit
28119 +#define TCR_LOOP 0x0002 // Controls output pin LBK
28120 +#define TCR_FORCOL 0x0004 // When 1 will force a collision
28121 +#define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
28122 +#define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
28123 +#define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
28124 +#define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
28125 +#define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
28126 +#define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
28127 +#define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
28129 +#define TCR_CLEAR 0 /* do NOTHING */
28130 +/* the default settings for the TCR register : */
28131 +#define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
28134 +// EPH Status Register
28136 +#define EPH_STATUS_REG SMC_REG(0x0002, 0)
28137 +#define ES_TX_SUC 0x0001 // Last TX was successful
28138 +#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
28139 +#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
28140 +#define ES_LTX_MULT 0x0008 // Last tx was a multicast
28141 +#define ES_16COL 0x0010 // 16 Collisions Reached
28142 +#define ES_SQET 0x0020 // Signal Quality Error Test
28143 +#define ES_LTXBRD 0x0040 // Last tx was a broadcast
28144 +#define ES_TXDEFR 0x0080 // Transmit Deferred
28145 +#define ES_LATCOL 0x0200 // Late collision detected on last tx
28146 +#define ES_LOSTCARR 0x0400 // Lost Carrier Sense
28147 +#define ES_EXC_DEF 0x0800 // Excessive Deferral
28148 +#define ES_CTR_ROL 0x1000 // Counter Roll Over indication
28149 +#define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
28150 +#define ES_TXUNRN 0x8000 // Tx Underrun
28153 +// Receive Control Register
28155 +#define RCR_REG SMC_REG(0x0004, 0)
28156 +#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
28157 +#define RCR_PRMS 0x0002 // Enable promiscuous mode
28158 +#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
28159 +#define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
28160 +#define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
28161 +#define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
28162 +#define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
28163 +#define RCR_SOFTRST 0x8000 // resets the chip
28165 +/* the normal settings for the RCR register : */
28166 +#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
28167 +#define RCR_CLEAR 0x0 // set it to a base state
28170 +// Counter Register
28172 +#define COUNTER_REG SMC_REG(0x0006, 0)
28175 +// Memory Information Register
28177 +#define MIR_REG SMC_REG(0x0008, 0)
28180 +// Receive/Phy Control Register
28182 +#define RPC_REG SMC_REG(0x000A, 0)
28183 +#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
28184 +#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
28185 +#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
28186 +#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
28187 +#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
28188 +#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
28189 +#define RPC_LED_RES (0x01) // LED = Reserved
28190 +#define RPC_LED_10 (0x02) // LED = 10Mbps link detect
28191 +#define RPC_LED_FD (0x03) // LED = Full Duplex Mode
28192 +#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
28193 +#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
28194 +#define RPC_LED_TX (0x06) // LED = TX packet occurred
28195 +#define RPC_LED_RX (0x07) // LED = RX packet occurred
28196 +#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
28199 +/* Bank 0 0x0C is reserved */
28201 +// Bank Select Register
28203 +#define BSR_REG 0x000E
28206 +// Configuration Reg
28208 +#define CONFIG_REG SMC_REG(0x0000, 1)
28209 +#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
28210 +#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
28211 +#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
28212 +#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
28214 +// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
28215 +#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
28218 +// Base Address Register
28220 +#define BASE_REG SMC_REG(0x0002, 1)
28223 +// Individual Address Registers
28225 +#define ADDR0_REG SMC_REG(0x0004, 1)
28226 +#define ADDR1_REG SMC_REG(0x0006, 1)
28227 +#define ADDR2_REG SMC_REG(0x0008, 1)
28230 +// General Purpose Register
28232 +#define GP_REG SMC_REG(0x000A, 1)
28235 +// Control Register
28237 +#define CTL_REG SMC_REG(0x000C, 1)
28238 +#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
28239 +#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
28240 +#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
28241 +#define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
28242 +#define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
28243 +#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
28244 +#define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
28245 +#define CTL_STORE 0x0001 // When set stores registers into EEPROM
28248 +// MMU Command Register
28250 +#define MMU_CMD_REG SMC_REG(0x0000, 2)
28251 +#define MC_BUSY 1 // When 1 the last release has not completed
28252 +#define MC_NOP (0<<5) // No Op
28253 +#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
28254 +#define MC_RESET (2<<5) // Reset MMU to initial state
28255 +#define MC_REMOVE (3<<5) // Remove the current rx packet
28256 +#define MC_RELEASE (4<<5) // Remove and release the current rx packet
28257 +#define MC_FREEPKT (5<<5) // Release packet in PNR register
28258 +#define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
28259 +#define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
28262 +// Packet Number Register
28264 +#define PN_REG SMC_REG(0x0002, 2)
28267 +// Allocation Result Register
28269 +#define AR_REG SMC_REG(0x0003, 2)
28270 +#define AR_FAILED 0x80 // Alocation Failed
28273 +// TX FIFO Ports Register
28275 +#define TXFIFO_REG SMC_REG(0x0004, 2)
28276 +#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
28278 +// RX FIFO Ports Register
28280 +#define RXFIFO_REG SMC_REG(0x0005, 2)
28281 +#define RXFIFO_REMPTY 0x80 // RX FIFO Empty
28283 +#define FIFO_REG SMC_REG(0x0004, 2)
28285 +// Pointer Register
28287 +#define PTR_REG SMC_REG(0x0006, 2)
28288 +#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
28289 +#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
28290 +#define PTR_READ 0x2000 // When 1 the operation is a read
28295 +#define DATA_REG SMC_REG(0x0008, 2)
28298 +// Interrupt Status/Acknowledge Register
28300 +#define INT_REG SMC_REG(0x000C, 2)
28303 +// Interrupt Mask Register
28305 +#define IM_REG SMC_REG(0x000D, 2)
28306 +#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
28307 +#define IM_ERCV_INT 0x40 // Early Receive Interrupt
28308 +#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
28309 +#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
28310 +#define IM_ALLOC_INT 0x08 // Set when allocation request is completed
28311 +#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
28312 +#define IM_TX_INT 0x02 // Transmit Interrupt
28313 +#define IM_RCV_INT 0x01 // Receive Interrupt
28316 +// Multicast Table Registers
28318 +#define MCAST_REG1 SMC_REG(0x0000, 3)
28319 +#define MCAST_REG2 SMC_REG(0x0002, 3)
28320 +#define MCAST_REG3 SMC_REG(0x0004, 3)
28321 +#define MCAST_REG4 SMC_REG(0x0006, 3)
28324 +// Management Interface Register (MII)
28326 +#define MII_REG SMC_REG(0x0008, 3)
28327 +#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
28328 +#define MII_MDOE 0x0008 // MII Output Enable
28329 +#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
28330 +#define MII_MDI 0x0002 // MII Input, pin MDI
28331 +#define MII_MDO 0x0001 // MII Output, pin MDO
28334 +// Revision Register
28336 +/* ( hi: chip id low: rev # ) */
28337 +#define REV_REG SMC_REG(0x000A, 3)
28340 +// Early RCV Register
28342 +/* this is NOT on SMC9192 */
28343 +#define ERCV_REG SMC_REG(0x000C, 3)
28344 +#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
28345 +#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
28348 +// External Register
28350 +#define EXT_REG SMC_REG(0x0000, 7)
28353 +#define CHIP_9192 3
28354 +#define CHIP_9194 4
28355 +#define CHIP_9195 5
28356 +#define CHIP_9196 6
28357 +#define CHIP_91100 7
28358 +#define CHIP_91100FD 8
28359 +#define CHIP_91111FD 9
28361 +static const char * chip_ids[ 16 ] = {
28362 + NULL, NULL, NULL,
28363 + /* 3 */ "SMC91C90/91C92",
28364 + /* 4 */ "SMC91C94",
28365 + /* 5 */ "SMC91C95",
28366 + /* 6 */ "SMC91C96",
28367 + /* 7 */ "SMC91C100",
28368 + /* 8 */ "SMC91C100FD",
28369 + /* 9 */ "SMC91C11xFD",
28370 + NULL, NULL, NULL,
28371 + NULL, NULL, NULL};
28375 + . Transmit status bits
28377 +#define TS_SUCCESS 0x0001
28378 +#define TS_LOSTCAR 0x0400
28379 +#define TS_LATCOL 0x0200
28380 +#define TS_16COL 0x0010
28383 + . Receive status bits
28385 +#define RS_ALGNERR 0x8000
28386 +#define RS_BRODCAST 0x4000
28387 +#define RS_BADCRC 0x2000
28388 +#define RS_ODDFRAME 0x1000
28389 +#define RS_TOOLONG 0x0800
28390 +#define RS_TOOSHORT 0x0400
28391 +#define RS_MULTICAST 0x0001
28392 +#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
28397 + PHY_LAN83C183 = 1, // LAN91C111 Internal PHY
28402 +// PHY Register Addresses (LAN91C111 Internal PHY)
28404 +// PHY Control Register
28405 +#define PHY_CNTL_REG 0x00
28406 +#define PHY_CNTL_RST 0x8000 // 1=PHY Reset
28407 +#define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback
28408 +#define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs
28409 +#define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation
28410 +#define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode
28411 +#define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled
28412 +#define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate
28413 +#define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex
28414 +#define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test
28416 +// PHY Status Register
28417 +#define PHY_STAT_REG 0x01
28418 +#define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable
28419 +#define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable
28420 +#define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable
28421 +#define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable
28422 +#define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable
28423 +#define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble
28424 +#define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed
28425 +#define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected
28426 +#define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable
28427 +#define PHY_STAT_LINK 0x0004 // 1=valid link
28428 +#define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition
28429 +#define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented
28431 +// PHY Identifier Registers
28432 +#define PHY_ID1_REG 0x02 // PHY Identifier 1
28433 +#define PHY_ID2_REG 0x03 // PHY Identifier 2
28435 +// PHY Auto-Negotiation Advertisement Register
28436 +#define PHY_AD_REG 0x04
28437 +#define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page
28438 +#define PHY_AD_ACK 0x4000 // 1=got link code word from remote
28439 +#define PHY_AD_RF 0x2000 // 1=advertise remote fault
28440 +#define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4
28441 +#define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX
28442 +#define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX
28443 +#define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX
28444 +#define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX
28445 +#define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA
28447 +// PHY Auto-negotiation Remote End Capability Register
28448 +#define PHY_RMT_REG 0x05
28449 +// Uses same bit definitions as PHY_AD_REG
28451 +// PHY Configuration Register 1
28452 +#define PHY_CFG1_REG 0x10
28453 +#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
28454 +#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
28455 +#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
28456 +#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
28457 +#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
28458 +#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
28459 +#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
28460 +#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
28461 +#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
28462 +#define PHY_CFG1_TLVL_MASK 0x003C
28463 +#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
28466 +// PHY Configuration Register 2
28467 +#define PHY_CFG2_REG 0x11
28468 +#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
28469 +#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
28470 +#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
28471 +#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
28473 +// PHY Status Output (and Interrupt status) Register
28474 +#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
28475 +#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
28476 +#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
28477 +#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
28478 +#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
28479 +#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
28480 +#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
28481 +#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
28482 +#define PHY_INT_JAB 0x0100 // 1=Jabber detected
28483 +#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
28484 +#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
28486 +// PHY Interrupt/Status Mask Register
28487 +#define PHY_MASK_REG 0x13 // Interrupt Mask
28488 +// Uses the same bit definitions as PHY_INT_REG
28492 + * SMC91C96 ethernet config and status registers.
28493 + * These are in the "attribute" space.
28495 +#define ECOR 0x8000
28496 +#define ECOR_RESET 0x80
28497 +#define ECOR_LEVEL_IRQ 0x40
28498 +#define ECOR_WR_ATTRIB 0x04
28499 +#define ECOR_ENABLE 0x01
28501 +#define ECSR 0x8002
28502 +#define ECSR_IOIS8 0x20
28503 +#define ECSR_PWRDWN 0x04
28504 +#define ECSR_INT 0x02
28508 + * Macros to abstract register access according to the data bus
28509 + * capabilities. Please try to use those and not the in/out primitives.
28510 + * Note: the following macros do *not* select the bank -- this must
28511 + * be done separately as needed in the main code. The SMC_REG() macro
28512 + * only uses the bank argument for debugging purposes.
28516 +#define SMC_REG(reg, bank) \
28518 + int __b = SMC_CURRENT_BANK(); \
28519 + if ((__b & ~0xf0) != (0x3300 | bank)) { \
28520 + printk( "%s: bank reg screwed (0x%04x)\n", \
28521 + CARDNAME, __b ); \
28524 + reg<<SMC_IO_SHIFT; \
28527 +#define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
28530 +#if SMC_CAN_USE_8BIT
28531 +#define SMC_GET_PN() SMC_inb( ioaddr, PN_REG )
28532 +#define SMC_SET_PN(x) SMC_outb( x, ioaddr, PN_REG )
28533 +#define SMC_GET_AR() SMC_inb( ioaddr, AR_REG )
28534 +#define SMC_GET_TXFIFO() SMC_inb( ioaddr, TXFIFO_REG )
28535 +#define SMC_GET_RXFIFO() SMC_inb( ioaddr, RXFIFO_REG )
28536 +#define SMC_GET_INT() SMC_inb( ioaddr, INT_REG )
28537 +#define SMC_ACK_INT(x) SMC_outb( x, ioaddr, INT_REG )
28538 +#define SMC_GET_INT_MASK() SMC_inb( ioaddr, IM_REG )
28539 +#define SMC_SET_INT_MASK(x) SMC_outb( x, ioaddr, IM_REG )
28541 +#define SMC_GET_PN() (SMC_inw( ioaddr, PN_REG ) & 0xFF)
28542 +#define SMC_SET_PN(x) SMC_outw( x, ioaddr, PN_REG )
28543 +#define SMC_GET_AR() (SMC_inw( ioaddr, PN_REG ) >> 8)
28544 +#define SMC_GET_TXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) & 0xFF)
28545 +#define SMC_GET_RXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) >> 8)
28546 +#define SMC_GET_INT() (SMC_inw( ioaddr, INT_REG ) & 0xFF)
28547 +#define SMC_ACK_INT(x) \
28549 + unsigned long __flags; \
28551 + local_irq_save(__flags); \
28552 + __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
28553 + SMC_outw( __mask | (x), ioaddr, INT_REG ); \
28554 + local_irq_restore(__flags); \
28556 +#define SMC_GET_INT_MASK() (SMC_inw( ioaddr, INT_REG ) >> 8)
28557 +#define SMC_SET_INT_MASK(x) SMC_outw( (x) << 8, ioaddr, INT_REG )
28560 +#define SMC_CURRENT_BANK() SMC_inw( ioaddr, BANK_SELECT )
28561 +#define SMC_SELECT_BANK(x) SMC_outw( x, ioaddr, BANK_SELECT )
28562 +#define SMC_GET_BASE() SMC_inw( ioaddr, BASE_REG )
28563 +#define SMC_SET_BASE(x) SMC_outw( x, ioaddr, BASE_REG )
28564 +#define SMC_GET_CONFIG() SMC_inw( ioaddr, CONFIG_REG )
28565 +#define SMC_SET_CONFIG(x) SMC_outw( x, ioaddr, CONFIG_REG )
28566 +#define SMC_GET_COUNTER() SMC_inw( ioaddr, COUNTER_REG )
28567 +#define SMC_GET_CTL() SMC_inw( ioaddr, CTL_REG )
28568 +#define SMC_SET_CTL(x) SMC_outw( x, ioaddr, CTL_REG )
28569 +#define SMC_GET_MII() SMC_inw( ioaddr, MII_REG )
28570 +#define SMC_SET_MII(x) SMC_outw( x, ioaddr, MII_REG )
28571 +#define SMC_GET_MIR() SMC_inw( ioaddr, MIR_REG )
28572 +#define SMC_SET_MIR(x) SMC_outw( x, ioaddr, MIR_REG )
28573 +#define SMC_GET_MMU_CMD() SMC_inw( ioaddr, MMU_CMD_REG )
28574 +#define SMC_SET_MMU_CMD(x) SMC_outw( x, ioaddr, MMU_CMD_REG )
28575 +#define SMC_GET_FIFO() SMC_inw( ioaddr, FIFO_REG )
28576 +#define SMC_GET_PTR() SMC_inw( ioaddr, PTR_REG )
28577 +#define SMC_SET_PTR(x) SMC_outw( x, ioaddr, PTR_REG )
28578 +#define SMC_GET_RCR() SMC_inw( ioaddr, RCR_REG )
28579 +#define SMC_SET_RCR(x) SMC_outw( x, ioaddr, RCR_REG )
28580 +#define SMC_GET_REV() SMC_inw( ioaddr, REV_REG )
28581 +#define SMC_GET_RPC() SMC_inw( ioaddr, RPC_REG )
28582 +#define SMC_SET_RPC(x) SMC_outw( x, ioaddr, RPC_REG )
28583 +#define SMC_GET_TCR() SMC_inw( ioaddr, TCR_REG )
28584 +#define SMC_SET_TCR(x) SMC_outw( x, ioaddr, TCR_REG )
28586 +#ifndef SMC_GET_MAC_ADDR
28587 +#define SMC_GET_MAC_ADDR(addr) \
28589 + unsigned int __v; \
28590 + __v = SMC_inw( ioaddr, ADDR0_REG ); \
28591 + addr[0] = __v; addr[1] = __v >> 8; \
28592 + __v = SMC_inw( ioaddr, ADDR1_REG ); \
28593 + addr[2] = __v; addr[3] = __v >> 8; \
28594 + __v = SMC_inw( ioaddr, ADDR2_REG ); \
28595 + addr[4] = __v; addr[5] = __v >> 8; \
28599 +#define SMC_SET_MAC_ADDR(addr) \
28601 + SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
28602 + SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
28603 + SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
28606 +#define SMC_CLEAR_MCAST() \
28608 + SMC_outw( 0, ioaddr, MCAST_REG1 ); \
28609 + SMC_outw( 0, ioaddr, MCAST_REG2 ); \
28610 + SMC_outw( 0, ioaddr, MCAST_REG3 ); \
28611 + SMC_outw( 0, ioaddr, MCAST_REG4 ); \
28613 +#define SMC_SET_MCAST(x) \
28615 + unsigned char *mt = (x); \
28616 + SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
28617 + SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
28618 + SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
28619 + SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
28622 +#if SMC_CAN_USE_32BIT
28624 + * Some setups just can't write 8 or 16 bits reliably when not aligned
28625 + * to a 32 bit boundary. I tell you that exists!
28626 + * We do the ones that can have their low parts written to 0 here.
28628 +#undef SMC_SELECT_BANK
28629 +#define SMC_SELECT_BANK(x) SMC_outl( (x)<<16, ioaddr, 12<<SMC_IO_SHIFT )
28630 +#undef SMC_SET_RPC
28631 +#define SMC_SET_RPC(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(8, 0) )
28633 +#define SMC_SET_PN(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(0, 2) )
28634 +#undef SMC_SET_PTR
28635 +#define SMC_SET_PTR(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(4, 2) )
28638 +#if SMC_CAN_USE_32BIT
28639 +#define SMC_PUT_PKT_HDR(status, length) \
28640 + SMC_outl( (status) | (length) << 16, ioaddr, DATA_REG )
28641 +#define SMC_GET_PKT_HDR(status, length) \
28643 + unsigned int __val = SMC_inl( ioaddr, DATA_REG ); \
28644 + (status) = __val & 0xffff; \
28645 + (length) = __val >> 16; \
28648 +#define SMC_PUT_PKT_HDR(status, length) \
28650 + SMC_outw( status, ioaddr, DATA_REG ); \
28651 + SMC_outw( length, ioaddr, DATA_REG ); \
28653 +#define SMC_GET_PKT_HDR(status, length) \
28655 + (status) = SMC_inw( ioaddr, DATA_REG ); \
28656 + (length) = SMC_inw( ioaddr, DATA_REG ); \
28660 +#if SMC_CAN_USE_32BIT
28661 +#define SMC_PUSH_DATA(p, l) \
28663 + char *__ptr = (p); \
28664 + int __len = (l); \
28665 + if (__len >= 2 && (long)__ptr & 2) { \
28667 + SMC_outw( *((u16 *)__ptr)++, ioaddr, DATA_REG );\
28669 + SMC_outsl( ioaddr, DATA_REG, __ptr, __len >> 2); \
28670 + if (__len & 2) { \
28671 + __ptr += (__len & ~3); \
28672 + SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \
28675 +#define SMC_PULL_DATA(p, l) \
28677 + char *__ptr = (p); \
28678 + int __len = (l); \
28679 + if ((long)__ptr & 2) { \
28681 + * We want 32bit alignment here. \
28682 + * Since some buses perform a full 32bit \
28683 + * fetch even for 16bit data we can't use \
28684 + * SMC_inw() here. Back both source (on chip \
28685 + * and destination) pointers of 2 bytes. \
28687 + (long)__ptr &= ~2; \
28689 + SMC_SET_PTR( 2|PTR_READ|PTR_RCV|PTR_AUTOINC ); \
28692 + SMC_insl( ioaddr, DATA_REG, __ptr, __len >> 2); \
28694 +#elif SMC_CAN_USE_16BIT
28695 +#define SMC_PUSH_DATA(p, l) SMC_outsw( ioaddr, DATA_REG, p, (l) >> 1 )
28696 +#define SMC_PULL_DATA(p, l) SMC_insw ( ioaddr, DATA_REG, p, (l) >> 1 )
28697 +#elif SMC_CAN_USE_8BIT
28698 +#define SMC_PUSH_DATA(p, l) SMC_outsb( ioaddr, DATA_REG, p, l )
28699 +#define SMC_PULL_DATA(p, l) SMC_insb ( ioaddr, DATA_REG, p, l )
28702 +#if ! SMC_CAN_USE_16BIT
28703 +#define SMC_outw(x, ioaddr, reg) \
28705 + unsigned int __val16 = (x); \
28706 + SMC_outb( __val16, ioaddr, reg ); \
28707 + SMC_outb( __val16 >> 8, ioaddr, reg + 1 ); \
28709 +#define SMC_inw(ioaddr, reg) \
28711 + unsigned int __val16; \
28712 + __val16 = SMC_inb( ioaddr, reg ); \
28713 + __val16 |= SMC_inb( ioaddr, reg + 1 ) << 8; \
28719 +#endif /* _SMC91X_H_ */
28720 --- linux-2.4.27/drivers/pcmcia/Config.in~2.4.27-vrs1-pxa1
28721 +++ linux-2.4.27/drivers/pcmcia/Config.in
28723 if [ "$CONFIG_ARM" = "y" ]; then
28724 dep_tristate ' CLPS6700 support' CONFIG_PCMCIA_CLPS6700 $CONFIG_ARCH_CLPS711X $CONFIG_PCMCIA
28725 dep_tristate ' SA1100 support' CONFIG_PCMCIA_SA1100 $CONFIG_ARCH_SA1100 $CONFIG_PCMCIA
28726 + dep_tristate ' PXA250/210 support' CONFIG_PCMCIA_PXA $CONFIG_ARCH_PXA $CONFIG_PCMCIA
28730 --- linux-2.4.27/drivers/pcmcia/Makefile~2.4.27-vrs1-pxa1
28731 +++ linux-2.4.27/drivers/pcmcia/Makefile
28734 obj-$(CONFIG_PCMCIA_VRC4173) += vrc4173_cardu.o
28736 +subdir-$(CONFIG_PCMCIA_PXA) += pxa
28737 +ifeq ($(CONFIG_PCMCIA_PXA),y)
28738 + obj-y += pxa/pxa_cs.o
28741 include $(TOPDIR)/Rules.make
28743 pcmcia_core.o: $(pcmcia_core-objs)
28745 +++ linux-2.4.27/drivers/pcmcia/pxa/Makefile
28748 +# Makefile for the Intel PXA250/210 PCMCIA driver
28750 +# Note! Dependencies are done automagically by 'make dep', which also
28751 +# removes any old dependencies. DON'T put your own dependencies here
28752 +# unless it's something special (ie not a .c file).
28754 +O_TARGET := pxa_cs.o
28757 +obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
28758 +obj-$(CONFIG_ARCH_PXA_IDP) += pxa_idp.o
28759 +obj-$(CONFIG_ARCH_TRIZEPS2) += trizeps2.o
28760 +obj-$(CONFIG_ARCH_PXA_CERF) += ../sa1100_cerf.o
28762 +obj-m := $(O_TARGET)
28764 +include $(TOPDIR)/Rules.make
28766 +++ linux-2.4.27/drivers/pcmcia/pxa/lubbock.c
28769 + * linux/drivers/pcmcia/pxa/lubbock.c
28771 + * Author: George Davis
28772 + * Created: Jan 10, 2002
28773 + * Copyright: MontaVista Software Inc.
28775 + * This program is free software; you can redistribute it and/or modify
28776 + * it under the terms of the GNU General Public License version 2 as
28777 + * published by the Free Software Foundation.
28779 + * Originally based upon linux/drivers/pcmcia/sa1100_neponset.c
28781 + * Lubbock PCMCIA specific routines.
28785 +#include <linux/kernel.h>
28786 +#include <linux/sched.h>
28788 +#include <pcmcia/ss.h>
28790 +#include <asm/delay.h>
28791 +#include <asm/hardware.h>
28792 +#include <asm/irq.h>
28793 +#include <asm/arch/pcmcia.h>
28794 +#include <asm/hardware/sa1111.h>
28797 + * I'd really like to move the INTPOL stuff to arch/arm/mach-sa1100/sa1111.c
28798 + * ... and maybe even arch/arm/mach-pxa/sa1111.c now too! : )
28800 +#define SA1111_IRQMASK_LO(x) (1 << (x - IRQ_SA1111_START))
28801 +#define SA1111_IRQMASK_HI(x) (1 << (x - IRQ_SA1111_START - 32))
28803 +static int lubbock_pcmcia_init(struct pcmcia_init *init){
28804 + int return_val=0;
28806 + /* Set PCMCIA Socket 0 power to standby mode.
28808 + PA_DWR &= ~(GPIO_bit(0) | GPIO_bit(1) | GPIO_bit(2) | GPIO_bit(3));
28810 + /* Set GPIO_A<3:0> to be outputs for PCMCIA (socket 0) power controller.
28811 + * Note that this is done only after first initializing GPIO_A<3:0>
28812 + * output state above to be certain that we drive signals to the same
28813 + * state as the pull-downs connected to these lines. The pull-downs are
28814 + * req'd to make sure PCMCIA power is OFF until we can get around to
28815 + * setting up the GPIO_A<3:0> state and direction.
28817 + PA_DDR &= ~(GPIO_bit(0) | GPIO_bit(1) | GPIO_bit(2) | GPIO_bit(3));
28819 + /* Set CF Socket 1 power to standby mode. */
28820 + LUB_MISC_WR &= ~(GPIO_bit(15) | GPIO_bit(14));
28822 + INTPOL1 |= SA1111_IRQMASK_HI(S0_READY_NINT) |
28823 + SA1111_IRQMASK_HI(S1_READY_NINT) |
28824 + SA1111_IRQMASK_HI(S0_CD_VALID) |
28825 + SA1111_IRQMASK_HI(S1_CD_VALID) |
28826 + SA1111_IRQMASK_HI(S0_BVD1_STSCHG) |
28827 + SA1111_IRQMASK_HI(S1_BVD1_STSCHG);
28829 +#warning what if a request_irq fails?
28830 + return_val+=request_irq(S0_CD_VALID, init->handler, SA_INTERRUPT,
28831 + "Lubbock PCMCIA (0) CD", NULL);
28832 + return_val+=request_irq(S1_CD_VALID, init->handler, SA_INTERRUPT,
28833 + "Lubbock CF (1) CD", NULL);
28834 + return_val+=request_irq(S0_BVD1_STSCHG, init->handler, SA_INTERRUPT,
28835 + "Lubbock PCMCIA (0) BVD1", NULL);
28836 + return_val+=request_irq(S1_BVD1_STSCHG, init->handler, SA_INTERRUPT,
28837 + "Lubbock CF (1) BVD1", NULL);
28839 + return (return_val<0) ? -1 : 2;
28842 +static int lubbock_pcmcia_shutdown(void){
28844 + free_irq(S0_CD_VALID, NULL);
28845 + free_irq(S1_CD_VALID, NULL);
28846 + free_irq(S0_BVD1_STSCHG, NULL);
28847 + free_irq(S1_BVD1_STSCHG, NULL);
28849 + INTPOL1 &= ~(SA1111_IRQMASK_HI(S0_CD_VALID) |
28850 + SA1111_IRQMASK_HI(S1_CD_VALID) |
28851 + SA1111_IRQMASK_HI(S0_BVD1_STSCHG) |
28852 + SA1111_IRQMASK_HI(S1_BVD1_STSCHG));
28857 +static int lubbock_pcmcia_socket_state(struct pcmcia_state_array
28859 + unsigned long status;
28860 + int return_val=1;
28862 + if(state_array->size<2) return -1;
28864 + memset(state_array->state, 0,
28865 + (state_array->size)*sizeof(struct pcmcia_state));
28869 + state_array->state[0].detect=((status & PCSR_S0_DETECT)==0)?1:0;
28871 + state_array->state[0].ready=((status & PCSR_S0_READY)==0)?0:1;
28873 + state_array->state[0].bvd1=((status & PCSR_S0_BVD1)==0)?0:1;
28875 + state_array->state[0].bvd2=((status & PCSR_S0_BVD2)==0)?0:1;
28877 + state_array->state[0].wrprot=((status & PCSR_S0_WP)==0)?0:1;
28879 + state_array->state[0].vs_3v=((status & PCSR_S0_VS1)==0)?1:0;
28881 + state_array->state[0].vs_Xv=((status & PCSR_S0_VS2)==0)?1:0;
28883 + state_array->state[1].detect=((status & PCSR_S1_DETECT)==0)?1:0;
28885 + state_array->state[1].ready=((status & PCSR_S1_READY)==0)?0:1;
28887 + state_array->state[1].bvd1=((status & PCSR_S1_BVD1)==0)?0:1;
28889 + state_array->state[1].bvd2=((status & PCSR_S1_BVD2)==0)?0:1;
28891 + state_array->state[1].wrprot=((status & PCSR_S1_WP)==0)?0:1;
28893 + state_array->state[1].vs_3v=((status & PCSR_S1_VS1)==0)?1:0;
28895 + state_array->state[1].vs_Xv=((status & PCSR_S1_VS2)==0)?1:0;
28897 + return return_val;
28900 +static int lubbock_pcmcia_get_irq_info(struct pcmcia_irq_info *info){
28902 + switch(info->sock){
28904 + info->irq=S0_READY_NINT;
28908 + info->irq=S1_READY_NINT;
28919 +lubbock_pcmcia_configure_socket(unsigned int sock, socket_state_t *state)
28921 + unsigned long flags, pccr, gpio, misc_wr, status;
28924 + local_irq_save(flags);
28928 + misc_wr = LUB_MISC_WR;
28930 + /* Lubbock uses the Maxim MAX1602, with the following connections:
28932 + * Socket 0 (PCMCIA):
28933 + * MAX1602 Lubbock Register
28935 + * ----- ------- ----------------------
28936 + * A0VPP S0_PWR0 SA-1111 GPIO A<0>
28937 + * A1VPP S0_PWR1 SA-1111 GPIO A<1>
28938 + * A0VCC S0_PWR2 SA-1111 GPIO A<2>
28939 + * A1VCC S0_PWR3 SA-1111 GPIO A<3>
28943 + * CODE +3.3V Cirrus Code, CODE = High (VY)
28946 + * MAX1602 Lubbock Register
28948 + * ----- ------- ----------------------
28949 + * A0VPP GND VPP is not connected
28950 + * A1VPP GND VPP is not connected
28951 + * A0VCC S1_PWR0 MISC_WR<14>
28952 + * A1VCC S1_PWR0 MISC_WR<15>
28955 + * 12IN GND VPP is not connected
28956 + * CODE +3.3V Cirrus Code, CODE = High (VY)
28964 + switch(state->Vcc){
28966 + pccr = (pccr & ~PCCR_S0_FLT);
28967 + gpio &= ~(GPIO_bit(2) | GPIO_bit(3));
28971 + pccr = (pccr & ~PCCR_S0_PSE) | PCCR_S0_FLT | PCCR_S0_PWAITEN;
28972 + gpio = (gpio & ~(GPIO_bit(2) | GPIO_bit(3))) | GPIO_bit(3);
28976 + pccr = (pccr | PCCR_S0_PSE | PCCR_S0_FLT | PCCR_S0_PWAITEN);
28977 + gpio = (gpio & ~(GPIO_bit(2) | GPIO_bit(3))) | GPIO_bit(2);
28981 + printk(KERN_ERR "%s(): unrecognized Vcc %u\n", __FUNCTION__, state->Vcc);
28986 + switch(state->Vpp){
28988 + gpio &= ~(GPIO_bit(0) | GPIO_bit(1));
28992 + gpio = (gpio & ~(GPIO_bit(0) | GPIO_bit(1))) | GPIO_bit(1);
28996 + /* REVISIT: I'm not sure about this? Is this correct?
28997 + Is it always safe or do we have potential problems
28998 + with bogus combinations of Vcc and Vpp settings? */
28999 + if(state->Vpp == state->Vcc)
29000 + gpio = (gpio & ~(GPIO_bit(0) | GPIO_bit(1))) | GPIO_bit(0);
29002 + printk(KERN_ERR "%s(): unrecognized Vpp %u\n", __FUNCTION__, state->Vpp);
29008 + pccr = (state->flags&SS_RESET) ? (pccr|PCCR_S0_RST) : (pccr&~PCCR_S0_RST);
29013 + switch(state->Vcc){
29015 + pccr = (pccr & ~PCCR_S1_FLT);
29016 + misc_wr &= ~((1 << 15) | (1 << 14));
29020 + pccr = (pccr & ~PCCR_S1_PSE) | PCCR_S1_FLT | PCCR_S1_PWAITEN;
29021 + misc_wr = (misc_wr & ~(1 << 15)) | (1 << 14);
29022 + gpio = (gpio & ~(GPIO_bit(2) | GPIO_bit(3))) | GPIO_bit(2);
29026 + pccr = (pccr | PCCR_S1_PSE | PCCR_S1_FLT | PCCR_S1_PWAITEN);
29027 + misc_wr = (misc_wr & ~(1 << 15)) | (1 << 14);
29031 + printk(KERN_ERR "%s(): unrecognized Vcc %u\n", __FUNCTION__, state->Vcc);
29036 + if(state->Vpp!=state->Vcc && state->Vpp!=0){
29037 + printk(KERN_ERR "%s(): CF slot cannot support Vpp %u\n", __FUNCTION__, state->Vpp);
29042 + pccr = (state->flags&SS_RESET) ? (pccr|PCCR_S1_RST) : (pccr&~PCCR_S1_RST);
29052 + LUB_MISC_WR = misc_wr;
29060 + * We can't sense the voltage properly on Lubbock before actually
29061 + * applying some power to the socket (catch 22).
29062 + * Resense the socket Voltage Sense pins after applying socket power.
29065 + status = PCSR & (PCSR_S0_VS1 | PCSR_S0_VS2);
29067 + status = PCSR & (PCSR_S1_VS1 | PCSR_S1_VS2);
29069 + if ((status == (PCSR_S0_VS1 | PCSR_S0_VS2)) && (state->Vcc == 33)) {
29070 + /* Switch to 5V, Configure socket 0 with 5V voltage */
29071 + PA_DWR &= ~(GPIO_bit(0) | GPIO_bit(1) | GPIO_bit(2) | GPIO_bit(3));
29072 + PA_DDR &= ~(GPIO_bit(0) | GPIO_bit(1) | GPIO_bit(2) | GPIO_bit(3));
29077 + if ((status == (PCSR_S1_VS1 | PCSR_S1_VS2)) && (state->Vcc == 33)) {
29078 + /* Switch to 5V, Configure socket 1 with 5V voltage */
29079 + LUB_MISC_WR &= ~((1 << 15) | (1 << 14));
29086 + local_irq_restore(flags);
29090 +struct pcmcia_low_level lubbock_pcmcia_ops = {
29091 + lubbock_pcmcia_init,
29092 + lubbock_pcmcia_shutdown,
29093 + lubbock_pcmcia_socket_state,
29094 + lubbock_pcmcia_get_irq_info,
29095 + lubbock_pcmcia_configure_socket
29098 +++ linux-2.4.27/drivers/pcmcia/pxa/pxa.c
29101 + * linux/drivers/pcmcia/pxa/pxa.c
29103 + * Author: George Davis
29104 + * Created: Jan 10, 2002
29105 + * Copyright: MontaVista Software Inc.
29107 + * This program is free software; you can redistribute it and/or modify
29108 + * it under the terms of the GNU General Public License version 2 as
29109 + * published by the Free Software Foundation.
29111 + * Originally based upon linux/drivers/pcmcia/sa1100_generic.c
29115 +/*======================================================================
29117 + Device driver for the PCMCIA control functionality of Intel
29118 + PXA250/210 microprocessors.
29120 + The contents of this file are subject to the Mozilla Public
29121 + License Version 1.1 (the "License"); you may not use this file
29122 + except in compliance with the License. You may obtain a copy of
29123 + the License at http://www.mozilla.org/MPL/
29125 + Software distributed under the License is distributed on an "AS
29126 + IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
29127 + implied. See the License for the specific language governing
29128 + rights and limitations under the License.
29130 + The initial developer of the original code is John G. Dorsey
29131 + <john+@cs.cmu.edu>. Portions created by John G. Dorsey are
29132 + Copyright (C) 1999 John G. Dorsey. All Rights Reserved.
29134 + Alternatively, the contents of this file may be used under the
29135 + terms of the GNU Public License version 2 (the "GPL"), in which
29136 + case the provisions of the GPL are applicable instead of the
29137 + above. If you wish to allow the use of your version of this file
29138 + only under the terms of the GPL and not to allow others to use
29139 + your version of this file under the MPL, indicate your decision
29140 + by deleting the provisions above and replace them with the notice
29141 + and other provisions required by the GPL. If you do not delete
29142 + the provisions above, a recipient may use your version of this
29143 + file under either the MPL or the GPL.
29145 +======================================================================*/
29147 +#include <linux/module.h>
29148 +#include <linux/init.h>
29149 +#include <linux/config.h>
29150 +#include <linux/cpufreq.h>
29151 +#include <linux/delay.h>
29152 +#include <linux/ioport.h>
29153 +#include <linux/kernel.h>
29154 +#include <linux/tqueue.h>
29155 +#include <linux/timer.h>
29156 +#include <linux/mm.h>
29157 +#include <linux/notifier.h>
29158 +#include <linux/proc_fs.h>
29159 +#include <linux/version.h>
29160 +#include <linux/cpufreq.h>
29162 +#include <pcmcia/version.h>
29163 +#include <pcmcia/cs_types.h>
29164 +#include <pcmcia/cs.h>
29165 +#include <pcmcia/ss.h>
29166 +#include <pcmcia/bus_ops.h>
29168 +#include <asm/hardware.h>
29169 +#include <asm/io.h>
29170 +#include <asm/irq.h>
29171 +#include <asm/system.h>
29172 +#include <asm/arch/lubbock.h>
29176 +#ifdef PCMCIA_DEBUG
29177 +static int pc_debug;
29180 +MODULE_AUTHOR("George Davis <davis_g@mvista.com>");
29181 +MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA250/210 Socket Controller");
29183 +/* This structure maintains housekeeping state for each socket, such
29184 + * as the last known values of the card detect pins, or the Card Services
29185 + * callback value associated with the socket:
29187 +static struct pxa_pcmcia_socket
29188 +pxa_pcmcia_socket[PXA_PCMCIA_MAX_SOCK];
29190 +static int pxa_pcmcia_socket_count;
29193 +/* Returned by the low-level PCMCIA interface: */
29194 +static struct pcmcia_low_level *pcmcia_low_level;
29196 +/* Event poll timer structure */
29197 +static struct timer_list poll_timer;
29200 +/* Prototypes for routines which are used internally: */
29202 +static int pxa_pcmcia_driver_init(void);
29203 +static void pxa_pcmcia_driver_shutdown(void);
29204 +static void pxa_pcmcia_task_handler(void *data);
29205 +static void pxa_pcmcia_poll_event(unsigned long data);
29206 +static void pxa_pcmcia_interrupt(int irq, void *dev,
29207 + struct pt_regs *regs);
29208 +static struct tq_struct pxa_pcmcia_task;
29210 +#ifdef CONFIG_PROC_FS
29211 +static int pxa_pcmcia_proc_status(char *buf, char **start, off_t pos,
29212 + int count, int *eof, void *data);
29216 +/* Prototypes for operations which are exported to the
29217 + * new-and-impr^H^H^H^H^H^H^H^H^H^H in-kernel PCMCIA core:
29220 +static int pxa_pcmcia_init(unsigned int sock);
29221 +static int pxa_pcmcia_suspend(unsigned int sock);
29222 +static int pxa_pcmcia_register_callback(unsigned int sock,
29223 + void (*handler)(void *,
29226 +static int pxa_pcmcia_inquire_socket(unsigned int sock,
29227 + socket_cap_t *cap);
29228 +static int pxa_pcmcia_get_status(unsigned int sock, u_int *value);
29229 +static int pxa_pcmcia_get_socket(unsigned int sock,
29230 + socket_state_t *state);
29231 +static int pxa_pcmcia_set_socket(unsigned int sock,
29232 + socket_state_t *state);
29233 +static int pxa_pcmcia_get_io_map(unsigned int sock,
29234 + struct pccard_io_map *io);
29235 +static int pxa_pcmcia_set_io_map(unsigned int sock,
29236 + struct pccard_io_map *io);
29237 +static int pxa_pcmcia_get_mem_map(unsigned int sock,
29238 + struct pccard_mem_map *mem);
29239 +static int pxa_pcmcia_set_mem_map(unsigned int sock,
29240 + struct pccard_mem_map *mem);
29241 +#ifdef CONFIG_PROC_FS
29242 +static void pxa_pcmcia_proc_setup(unsigned int sock,
29243 + struct proc_dir_entry *base);
29246 +static struct pccard_operations pxa_pcmcia_operations = {
29248 + pxa_pcmcia_suspend,
29249 + pxa_pcmcia_register_callback,
29250 + pxa_pcmcia_inquire_socket,
29251 + pxa_pcmcia_get_status,
29252 + pxa_pcmcia_get_socket,
29253 + pxa_pcmcia_set_socket,
29254 + pxa_pcmcia_get_io_map,
29255 + pxa_pcmcia_set_io_map,
29256 + pxa_pcmcia_get_mem_map,
29257 + pxa_pcmcia_set_mem_map,
29258 +#ifdef CONFIG_PROC_FS
29259 + pxa_pcmcia_proc_setup
29263 +#ifdef CONFIG_CPU_FREQ
29264 +/* forward declaration */
29265 +static struct notifier_block pxa_pcmcia_notifier_block;
29269 +/* pxa_pcmcia_driver_init()
29270 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^
29272 + * This routine performs a basic sanity check to ensure that this
29273 + * kernel has been built with the appropriate board-specific low-level
29274 + * PCMCIA support, performs low-level PCMCIA initialization, registers
29275 + * this socket driver with Card Services, and then spawns the daemon
29276 + * thread which is the real workhorse of the socket driver.
29278 + * Please see linux/Documentation/arm/SA1100/PCMCIA for more information
29279 + * on the low-level kernel interface.
29281 + * Returns: 0 on success, -1 on error
29283 +static int __init pxa_pcmcia_driver_init(void){
29285 + struct pcmcia_init pcmcia_init;
29286 + struct pcmcia_state state[PXA_PCMCIA_MAX_SOCK];
29287 + struct pcmcia_state_array state_array;
29288 + unsigned int i, clock;
29289 + unsigned long mecr;
29291 + printk(KERN_INFO "Intel PXA250/210 PCMCIA (CS release %s)\n", CS_RELEASE);
29293 + CardServices(GetCardServicesInfo, &info);
29295 + if(info.Revision!=CS_RELEASE_CODE){
29296 + printk(KERN_ERR "Card Services release codes do not match\n");
29300 + /* Setup GPIOs for PCMCIA/CF alternate function mode.
29302 + * It would be nice if set_GPIO_mode included support
29303 + * for driving GPIO outputs to default high/low state
29304 + * before programming GPIOs as outputs. Setting GPIO
29305 + * outputs to default high/low state via GPSR/GPCR
29306 + * before defining them as outputs should reduce
29307 + * the possibility of glitching outputs during GPIO
29308 + * setup. This of course assumes external terminators
29309 + * are present to hold GPIOs in a defined state.
29311 + * In the meantime, setup default state of GPIO
29312 + * outputs before we enable them as outputs.
29315 + GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
29316 + GPIO_bit(GPIO49_nPWE) |
29317 + GPIO_bit(GPIO50_nPIOR) |
29318 + GPIO_bit(GPIO51_nPIOW) |
29319 + GPIO_bit(GPIO52_nPCE_1) |
29320 + GPIO_bit(GPIO53_nPCE_2);
29322 + set_GPIO_mode(GPIO48_nPOE_MD);
29323 + set_GPIO_mode(GPIO49_nPWE_MD);
29324 + set_GPIO_mode(GPIO50_nPIOR_MD);
29325 + set_GPIO_mode(GPIO51_nPIOW_MD);
29326 + set_GPIO_mode(GPIO52_nPCE_1_MD);
29327 + set_GPIO_mode(GPIO53_nPCE_2_MD);
29328 + set_GPIO_mode(GPIO54_pSKTSEL_MD); /* REVISIT: s/b dependent on num sockets */
29329 + set_GPIO_mode(GPIO55_nPREG_MD);
29330 + set_GPIO_mode(GPIO56_nPWAIT_MD);
29331 + set_GPIO_mode(GPIO57_nIOIS16_MD);
29334 + if(machine_is_lubbock()){
29335 +#if defined(CONFIG_ARCH_LUBBOCK) || defined(CONFIG_ARCH_CSB226)
29336 + pcmcia_low_level=&lubbock_pcmcia_ops;
29338 + } else if (machine_is_pxa_idp()) {
29339 + pcmcia_low_level=&pxa_idp_pcmcia_ops;
29340 + } else if( machine_is_pxa_cerf()){
29341 + pcmcia_low_level=&cerf_pcmcia_ops;
29342 + } else if (machine_is_trizeps2()){
29343 +#ifdef CONFIG_ARCH_TRIZEPS2
29344 + pcmcia_low_level=&trizeps2_pcmcia_ops;
29348 + if (!pcmcia_low_level) {
29349 + printk(KERN_ERR "This hardware is not supported by the PXA250/210 Card Service driver\n");
29353 + pcmcia_init.handler=pxa_pcmcia_interrupt;
29355 + if((pxa_pcmcia_socket_count=pcmcia_low_level->init(&pcmcia_init))<0){
29356 + printk(KERN_ERR "Unable to initialize kernel PCMCIA service.\n");
29360 + state_array.size=pxa_pcmcia_socket_count;
29361 + state_array.state=state;
29363 + /* Configure MECR based on the number of sockets present. */
29364 + if (pxa_pcmcia_socket_count == 2) {
29365 + MECR |= GPIO_bit(0);
29367 + MECR &= ~GPIO_bit(0);
29370 + if(pcmcia_low_level->socket_state(&state_array)<0){
29371 + printk(KERN_ERR "Unable to get PCMCIA status from kernel.\n");
29375 + /* Well, it looks good to go. So we can now enable the PCMCIA
29378 + MECR |= GPIO_bit(1);
29380 + /* We need to initialize the MCXX registers to default values
29381 + * here because we're not guaranteed to see a SetIOMap operation
29385 + clock = get_lclk_frequency_10khz();
29387 + for(i=0; i<pxa_pcmcia_socket_count; ++i){
29388 + pxa_pcmcia_socket[i].k_state=state[i];
29390 + /* This is an interim fix. Apparently, SetSocket is no longer
29391 + * called to initialize each socket (prior to the first detect
29392 + * event). For now, we'll just manually set up the mask.
29394 + pxa_pcmcia_socket[i].cs_state.csc_mask=SS_DETECT;
29396 + pxa_pcmcia_socket[i].virt_io=(i==0)?PCMCIA_IO_0_BASE:PCMCIA_IO_1_BASE;
29397 + pxa_pcmcia_socket[i].phys_attr=_PCMCIAAttr(i);
29398 + pxa_pcmcia_socket[i].phys_mem=_PCMCIAMem(i);
29400 + /* REVISIT: cleanup these macros */
29401 + //MCIO_SET(i, PXA_PCMCIA_IO_ACCESS, clock);
29402 + //MCATTR_SET(i, PXA_PCMCIA_5V_MEM_ACCESS, clock);
29403 + //MCMEM_SET(i, PXA_PCMCIA_5V_MEM_ACCESS, clock);
29405 + pxa_pcmcia_socket[i].speed_io=PXA_PCMCIA_IO_ACCESS;
29406 + pxa_pcmcia_socket[i].speed_attr=PXA_PCMCIA_ATTR_MEM_ACCESS;
29407 + pxa_pcmcia_socket[i].speed_mem=PXA_PCMCIA_5V_MEM_ACCESS;
29410 +/* REVISIT: cleanup these macros */
29411 +MCMEM0 = ((pxa_mcxx_setup(PXA_PCMCIA_5V_MEM_ACCESS, clock)
29412 + & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
29413 + | ((pxa_mcxx_asst(PXA_PCMCIA_5V_MEM_ACCESS, clock)
29414 + & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
29415 + | ((pxa_mcxx_hold(PXA_PCMCIA_5V_MEM_ACCESS, clock)
29416 + & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
29417 +MCMEM1 = ((pxa_mcxx_setup(PXA_PCMCIA_5V_MEM_ACCESS, clock)
29418 + & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
29419 + | ((pxa_mcxx_asst(PXA_PCMCIA_5V_MEM_ACCESS, clock)
29420 + & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
29421 + | ((pxa_mcxx_hold(PXA_PCMCIA_5V_MEM_ACCESS, clock)
29422 + & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
29423 +MCATT0 = ((pxa_mcxx_setup(PXA_PCMCIA_ATTR_MEM_ACCESS, clock)
29424 + & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
29425 + | ((pxa_mcxx_asst(PXA_PCMCIA_ATTR_MEM_ACCESS, clock)
29426 + & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
29427 + | ((pxa_mcxx_hold(PXA_PCMCIA_ATTR_MEM_ACCESS, clock)
29428 + & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
29429 +MCATT1 = ((pxa_mcxx_setup(PXA_PCMCIA_ATTR_MEM_ACCESS, clock)
29430 + & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
29431 + | ((pxa_mcxx_asst(PXA_PCMCIA_ATTR_MEM_ACCESS, clock)
29432 + & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
29433 + | ((pxa_mcxx_hold(PXA_PCMCIA_ATTR_MEM_ACCESS, clock)
29434 + & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
29435 +MCIO0 = ((pxa_mcxx_setup(PXA_PCMCIA_IO_ACCESS, clock)
29436 + & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
29437 + | ((pxa_mcxx_asst(PXA_PCMCIA_IO_ACCESS, clock)
29438 + & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
29439 + | ((pxa_mcxx_hold(PXA_PCMCIA_IO_ACCESS, clock)
29440 + & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
29441 +MCIO1 = ((pxa_mcxx_setup(PXA_PCMCIA_IO_ACCESS, clock)
29442 + & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
29443 + | ((pxa_mcxx_asst(PXA_PCMCIA_IO_ACCESS, clock)
29444 + & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
29445 + | ((pxa_mcxx_hold(PXA_PCMCIA_IO_ACCESS, clock)
29446 + & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
29448 +#ifdef CONFIG_CPU_FREQ
29449 + if(cpufreq_register_notifier(&pxa_pcmcia_notifier_block) < 0){
29450 + printk(KERN_ERR "Unable to register CPU frequency change notifier\n");
29455 + /* Only advertise as many sockets as we can detect: */
29456 + if(register_ss_entry(pxa_pcmcia_socket_count,
29457 + &pxa_pcmcia_operations)<0){
29458 + printk(KERN_ERR "Unable to register socket service routine\n");
29462 + /* Start the event poll timer. It will reschedule by itself afterwards. */
29463 + pxa_pcmcia_poll_event(0);
29465 + DEBUG(1, "pxa_cs: initialization complete\n");
29469 +} /* pxa_pcmcia_driver_init() */
29471 +module_init(pxa_pcmcia_driver_init);
29474 +/* pxa_pcmcia_driver_shutdown()
29475 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
29476 + * Invokes the low-level kernel service to free IRQs associated with this
29477 + * socket controller and reset GPIO edge detection.
29479 +static void __exit pxa_pcmcia_driver_shutdown(void){
29481 + del_timer_sync(&poll_timer);
29482 + unregister_ss_entry(&pxa_pcmcia_operations);
29483 +#ifdef CONFIG_CPU_FREQ
29484 + cpufreq_unregister_notifier(&pxa_pcmcia_notifier_block);
29486 + pcmcia_low_level->shutdown();
29487 + flush_scheduled_tasks();
29489 + DEBUG(1, "pxa_cs: shutdown complete\n");
29492 +module_exit(pxa_pcmcia_driver_shutdown);
29495 +/* pxa_pcmcia_init()
29496 + * ^^^^^^^^^^^^^^^^^^^^
29497 + * We perform all of the interesting initialization tasks in
29498 + * pxa_pcmcia_driver_init().
29502 +static int pxa_pcmcia_init(unsigned int sock){
29504 + DEBUG(2, "%s(): initializing socket %u\n", __FUNCTION__, sock);
29510 +/* pxa_pcmcia_suspend()
29511 + * ^^^^^^^^^^^^^^^^^^^^^^^
29512 + * We don't currently perform any actions on a suspend.
29516 +static int pxa_pcmcia_suspend(unsigned int sock)
29518 + socket_state_t st;
29521 + DEBUG(2, "%s(): suspending socket %u\n", __FUNCTION__, sock);
29525 + st.flags = SS_RESET;
29527 + ret = pcmcia_low_level->configure_socket(sock, &st);
29530 + pxa_pcmcia_socket[sock].cs_state = dead_socket;
29536 +/* pxa_pcmcia_events()
29537 + * ^^^^^^^^^^^^^^^^^^^^^^
29538 + * Helper routine to generate a Card Services event mask based on
29539 + * state information obtained from the kernel low-level PCMCIA layer
29540 + * in a recent (and previous) sampling. Updates `prev_state'.
29542 + * Returns: an event mask for the given socket state.
29544 +static inline unsigned pxa_pcmcia_events(struct pcmcia_state *state,
29545 + struct pcmcia_state *prev_state,
29546 + unsigned int mask,
29547 + unsigned int flags){
29548 + unsigned int events=0;
29550 + if(state->detect!=prev_state->detect){
29552 + DEBUG(2, "%s(): card detect value %u\n", __FUNCTION__, state->detect);
29554 + events|=mask&SS_DETECT;
29557 + if(state->ready!=prev_state->ready){
29559 + DEBUG(2, "%s(): card ready value %u\n", __FUNCTION__, state->ready);
29561 + events|=mask&((flags&SS_IOCARD)?0:SS_READY);
29564 + if(state->bvd1!=prev_state->bvd1){
29566 + DEBUG(2, "%s(): card BVD1 value %u\n", __FUNCTION__, state->bvd1);
29568 + events|=mask&(flags&SS_IOCARD)?SS_STSCHG:SS_BATDEAD;
29571 + if(state->bvd2!=prev_state->bvd2){
29573 + DEBUG(2, "%s(): card BVD2 value %u\n", __FUNCTION__, state->bvd2);
29575 + events|=mask&(flags&SS_IOCARD)?0:SS_BATWARN;
29578 + DEBUG(2, "events: %s%s%s%s%s%s\n",
29579 + (events==0)?"<NONE>":"",
29580 + (events&SS_DETECT)?"DETECT ":"",
29581 + (events&SS_READY)?"READY ":"",
29582 + (events&SS_BATDEAD)?"BATDEAD ":"",
29583 + (events&SS_BATWARN)?"BATWARN ":"",
29584 + (events&SS_STSCHG)?"STSCHG ":"");
29586 + *prev_state=*state;
29590 +} /* pxa_pcmcia_events() */
29593 +/* pxa_pcmcia_task_handler()
29594 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
29595 + * Processes serviceable socket events using the "eventd" thread context.
29597 + * Event processing (specifically, the invocation of the Card Services event
29598 + * callback) occurs in this thread rather than in the actual interrupt
29599 + * handler due to the use of scheduling operations in the PCMCIA core.
29601 +static void pxa_pcmcia_task_handler(void *data) {
29602 + struct pcmcia_state state[PXA_PCMCIA_MAX_SOCK];
29603 + struct pcmcia_state_array state_array;
29604 + int i, events, all_events, irq_status;
29606 + DEBUG(2, "%s(): entering PCMCIA monitoring thread\n", __FUNCTION__);
29608 + state_array.size=pxa_pcmcia_socket_count;
29609 + state_array.state=state;
29613 + DEBUG(3, "%s(): interrogating low-level PCMCIA service\n", __FUNCTION__);
29615 + if((irq_status=pcmcia_low_level->socket_state(&state_array))<0)
29616 + printk(KERN_ERR "Error in kernel low-level PCMCIA service.\n");
29620 + if(irq_status>0){
29622 + for(i=0; i<state_array.size; ++i, all_events|=events)
29624 + pxa_pcmcia_events(&state[i],
29625 + &pxa_pcmcia_socket[i].k_state,
29626 + pxa_pcmcia_socket[i].cs_state.csc_mask,
29627 + pxa_pcmcia_socket[i].cs_state.flags)))
29628 + if(pxa_pcmcia_socket[i].handler!=NULL)
29629 + pxa_pcmcia_socket[i].handler(pxa_pcmcia_socket[i].handler_info,
29633 + } while(all_events);
29634 +} /* pxa_pcmcia_task_handler() */
29636 +static struct tq_struct pxa_pcmcia_task = {
29637 + routine: pxa_pcmcia_task_handler
29641 +/* pxa_pcmcia_poll_event()
29642 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^
29643 + * Let's poll for events in addition to IRQs since IRQ only is unreliable...
29645 +static void pxa_pcmcia_poll_event(unsigned long dummy)
29647 + DEBUG(3, "%s(): polling for events\n", __FUNCTION__);
29648 + poll_timer.function = pxa_pcmcia_poll_event;
29649 + poll_timer.expires = jiffies + PXA_PCMCIA_POLL_PERIOD;
29650 + add_timer(&poll_timer);
29651 + schedule_task(&pxa_pcmcia_task);
29655 +/* pxa_pcmcia_interrupt()
29656 + * ^^^^^^^^^^^^^^^^^^^^^^^^^
29657 + * Service routine for socket driver interrupts (requested by the
29658 + * low-level PCMCIA init() operation via pxa_pcmcia_thread()).
29659 + * The actual interrupt-servicing work is performed by
29660 + * pxa_pcmcia_thread(), largely because the Card Services event-
29661 + * handling code performs scheduling operations which cannot be
29662 + * executed from within an interrupt context.
29664 +static void pxa_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs){
29665 + DEBUG(3, "%s(): servicing IRQ %d\n", __FUNCTION__, irq);
29666 + schedule_task(&pxa_pcmcia_task);
29670 +/* pxa_pcmcia_register_callback()
29671 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
29672 + * Implements the register_callback() operation for the in-kernel
29673 + * PCMCIA service (formerly SS_RegisterCallback in Card Services). If
29674 + * the function pointer `handler' is not NULL, remember the callback
29675 + * location in the state for `sock', and increment the usage counter
29676 + * for the driver module. (The callback is invoked from the interrupt
29677 + * service routine, pxa_pcmcia_interrupt(), to notify Card Services
29678 + * of interesting events.) Otherwise, clear the callback pointer in the
29679 + * socket state and decrement the module usage count.
29683 +static int pxa_pcmcia_register_callback(unsigned int sock,
29684 + void (*handler)(void *,
29687 + if(handler==NULL){
29688 + pxa_pcmcia_socket[sock].handler=NULL;
29689 + MOD_DEC_USE_COUNT;
29691 + MOD_INC_USE_COUNT;
29692 + pxa_pcmcia_socket[sock].handler=handler;
29693 + pxa_pcmcia_socket[sock].handler_info=info;
29700 +/* pxa_pcmcia_inquire_socket()
29701 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
29702 + * Implements the inquire_socket() operation for the in-kernel PCMCIA
29703 + * service (formerly SS_InquireSocket in Card Services). Of note is
29704 + * the setting of the SS_CAP_PAGE_REGS bit in the `features' field of
29705 + * `cap' to "trick" Card Services into tolerating large "I/O memory"
29706 + * addresses. Also set is SS_CAP_STATIC_MAP, which disables the memory
29707 + * resource database check. (Mapped memory is set up within the socket
29708 + * driver itself.)
29710 + * In conjunction with the STATIC_MAP capability is a new field,
29711 + * `io_offset', recommended by David Hinds. Rather than go through
29712 + * the SetIOMap interface (which is not quite suited for communicating
29713 + * window locations up from the socket driver), we just pass up
29714 + * an offset which is applied to client-requested base I/O addresses
29715 + * in alloc_io_space().
29717 + * Returns: 0 on success, -1 if no pin has been configured for `sock'
29719 +static int pxa_pcmcia_inquire_socket(unsigned int sock,
29720 + socket_cap_t *cap){
29721 + struct pcmcia_irq_info irq_info;
29723 + DEBUG(3, "%s() for sock %u\n", __FUNCTION__, sock);
29725 + if(sock>=pxa_pcmcia_socket_count){
29726 + printk(KERN_ERR "pxa_cs: socket %u not configured\n", sock);
29730 + /* SS_CAP_PAGE_REGS: used by setup_cis_mem() in cistpl.c to set the
29731 + * force_low argument to validate_mem() in rsrc_mgr.c -- since in
29732 + * general, the mapped * addresses of the PCMCIA memory regions
29733 + * will not be within 0xffff, setting force_low would be
29736 + * SS_CAP_STATIC_MAP: don't bother with the (user-configured) memory
29737 + * resource database; we instead pass up physical address ranges
29738 + * and allow other parts of Card Services to deal with remapping.
29740 + * SS_CAP_PCCARD: we can deal with 16-bit PCMCIA & CF cards, but
29741 + * not 32-bit CardBus devices.
29743 + cap->features=(SS_CAP_PAGE_REGS | SS_CAP_STATIC_MAP | SS_CAP_PCCARD);
29745 + irq_info.sock=sock;
29748 + if(pcmcia_low_level->get_irq_info(&irq_info)<0){
29749 + printk(KERN_ERR "Error obtaining IRQ info from kernel for socket %u\n",
29755 + cap->map_size=PAGE_SIZE;
29756 + cap->pci_irq=irq_info.irq;
29757 + cap->io_offset=pxa_pcmcia_socket[sock].virt_io;
29761 +} /* pxa_pcmcia_inquire_socket() */
29764 +/* pxa_pcmcia_get_status()
29765 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^
29766 + * Implements the get_status() operation for the in-kernel PCMCIA
29767 + * service (formerly SS_GetStatus in Card Services). Essentially just
29768 + * fills in bits in `status' according to internal driver state or
29769 + * the value of the voltage detect chipselect register.
29771 + * As a debugging note, during card startup, the PCMCIA core issues
29772 + * three set_socket() commands in a row the first with RESET deasserted,
29773 + * the second with RESET asserted, and the last with RESET deasserted
29774 + * again. Following the third set_socket(), a get_status() command will
29775 + * be issued. The kernel is looking for the SS_READY flag (see
29776 + * setup_socket(), reset_socket(), and unreset_socket() in cs.c).
29780 +static int pxa_pcmcia_get_status(unsigned int sock,
29781 + unsigned int *status){
29782 + struct pcmcia_state state[PXA_PCMCIA_MAX_SOCK];
29783 + struct pcmcia_state_array state_array;
29785 + DEBUG(3, "%s() for sock %u\n", __FUNCTION__, sock);
29787 + state_array.size=pxa_pcmcia_socket_count;
29788 + state_array.state=state;
29790 + if((pcmcia_low_level->socket_state(&state_array))<0){
29791 + printk(KERN_ERR "Unable to get PCMCIA status from kernel.\n");
29795 + pxa_pcmcia_socket[sock].k_state=state[sock];
29797 + *status=state[sock].detect?SS_DETECT:0;
29799 + *status|=state[sock].ready?SS_READY:0;
29801 + /* The power status of individual sockets is not available
29802 + * explicitly from the hardware, so we just remember the state
29803 + * and regurgitate it upon request:
29805 + *status|=pxa_pcmcia_socket[sock].cs_state.Vcc?SS_POWERON:0;
29807 + if(pxa_pcmcia_socket[sock].cs_state.flags&SS_IOCARD)
29808 + *status|=state[sock].bvd1?SS_STSCHG:0;
29810 + if(state[sock].bvd1==0)
29811 + *status|=SS_BATDEAD;
29812 + else if(state[sock].bvd2==0)
29813 + *status|=SS_BATWARN;
29816 + *status|=state[sock].vs_3v?SS_3VCARD:0;
29818 + *status|=state[sock].vs_Xv?SS_XVCARD:0;
29820 + DEBUG(3, "\tstatus: %s%s%s%s%s%s%s%s\n",
29821 + (*status&SS_DETECT)?"DETECT ":"",
29822 + (*status&SS_READY)?"READY ":"",
29823 + (*status&SS_BATDEAD)?"BATDEAD ":"",
29824 + (*status&SS_BATWARN)?"BATWARN ":"",
29825 + (*status&SS_POWERON)?"POWERON ":"",
29826 + (*status&SS_STSCHG)?"STSCHG ":"",
29827 + (*status&SS_3VCARD)?"3VCARD ":"",
29828 + (*status&SS_XVCARD)?"XVCARD ":"");
29832 +} /* pxa_pcmcia_get_status() */
29835 +/* pxa_pcmcia_get_socket()
29836 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^
29837 + * Implements the get_socket() operation for the in-kernel PCMCIA
29838 + * service (formerly SS_GetSocket in Card Services). Not a very
29839 + * exciting routine.
29843 +static int pxa_pcmcia_get_socket(unsigned int sock,
29844 + socket_state_t *state){
29846 + DEBUG(3, "%s() for sock %u\n", __FUNCTION__, sock);
29848 + /* This information was given to us in an earlier call to set_socket(),
29849 + * so we're just regurgitating it here:
29851 + *state=pxa_pcmcia_socket[sock].cs_state;
29857 +/* pxa_pcmcia_set_socket()
29858 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^
29859 + * Implements the set_socket() operation for the in-kernel PCMCIA
29860 + * service (formerly SS_SetSocket in Card Services). We more or
29861 + * less punt all of this work and let the kernel handle the details
29862 + * of power configuration, reset, &c. We also record the value of
29863 + * `state' in order to regurgitate it to the PCMCIA core later.
29867 +static int pxa_pcmcia_set_socket(unsigned int sock,
29868 + socket_state_t *state){
29870 + DEBUG(3, "%s() for sock %u\n", __FUNCTION__, sock);
29872 + DEBUG(3, "\tmask: %s%s%s%s%s%s\n\tflags: %s%s%s%s%s%s\n"
29873 + "\tVcc %d Vpp %d irq %d\n",
29874 + (state->csc_mask==0)?"<NONE>":"",
29875 + (state->csc_mask&SS_DETECT)?"DETECT ":"",
29876 + (state->csc_mask&SS_READY)?"READY ":"",
29877 + (state->csc_mask&SS_BATDEAD)?"BATDEAD ":"",
29878 + (state->csc_mask&SS_BATWARN)?"BATWARN ":"",
29879 + (state->csc_mask&SS_STSCHG)?"STSCHG ":"",
29880 + (state->flags==0)?"<NONE>":"",
29881 + (state->flags&SS_PWR_AUTO)?"PWR_AUTO ":"",
29882 + (state->flags&SS_IOCARD)?"IOCARD ":"",
29883 + (state->flags&SS_RESET)?"RESET ":"",
29884 + (state->flags&SS_SPKR_ENA)?"SPKR_ENA ":"",
29885 + (state->flags&SS_OUTPUT_ENA)?"OUTPUT_ENA ":"",
29886 + state->Vcc, state->Vpp, state->io_irq);
29888 + if(pcmcia_low_level->configure_socket(sock, state)<0){
29889 + printk(KERN_ERR "Unable to configure socket %u\n", sock);
29893 + pxa_pcmcia_socket[sock].cs_state=*state;
29897 +} /* pxa_pcmcia_set_socket() */
29900 +/* pxa_pcmcia_get_io_map()
29901 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^
29902 + * Implements the get_io_map() operation for the in-kernel PCMCIA
29903 + * service (formerly SS_GetIOMap in Card Services). Just returns an
29904 + * I/O map descriptor which was assigned earlier by a set_io_map().
29906 + * Returns: 0 on success, -1 if the map index was out of range
29908 +static int pxa_pcmcia_get_io_map(unsigned int sock,
29909 + struct pccard_io_map *map){
29911 + DEBUG(4, "%s() for sock %u\n", __FUNCTION__, sock);
29913 + if(map->map>=MAX_IO_WIN){
29914 + printk(KERN_ERR "%s(): map (%d) out of range\n", __FUNCTION__,
29919 + *map=pxa_pcmcia_socket[sock].io_map[map->map];
29925 +/* pxa_pcmcia_set_io_map()
29926 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^
29927 + * Implements the set_io_map() operation for the in-kernel PCMCIA
29928 + * service (formerly SS_SetIOMap in Card Services). We configure
29929 + * the map speed as requested, but override the address ranges
29930 + * supplied by Card Services.
29932 + * Returns: 0 on success, -1 on error
29934 +static int pxa_pcmcia_set_io_map(unsigned int sock,
29935 + struct pccard_io_map *map){
29936 + unsigned int clock, speed;
29937 + unsigned long mecr, start;
29939 + DEBUG(4, "%s() for sock %u\n", __FUNCTION__, sock);
29941 + DEBUG(4, "\tmap %u speed %u\n\tstart 0x%08lx stop 0x%08lx\n"
29942 + "\tflags: %s%s%s%s%s%s%s%s\n",
29943 + map->map, map->speed, map->start, map->stop,
29944 + (map->flags==0)?"<NONE>":"",
29945 + (map->flags&MAP_ACTIVE)?"ACTIVE ":"",
29946 + (map->flags&MAP_16BIT)?"16BIT ":"",
29947 + (map->flags&MAP_AUTOSZ)?"AUTOSZ ":"",
29948 + (map->flags&MAP_0WS)?"0WS ":"",
29949 + (map->flags&MAP_WRPROT)?"WRPROT ":"",
29950 + (map->flags&MAP_USE_WAIT)?"USE_WAIT ":"",
29951 + (map->flags&MAP_PREFETCH)?"PREFETCH ":"");
29953 + if(map->map>=MAX_IO_WIN){
29954 + printk(KERN_ERR "%s(): map (%d) out of range\n", __FUNCTION__,
29959 + if(map->flags&MAP_ACTIVE){
29961 + speed=(map->speed>0)?map->speed:PXA_PCMCIA_IO_ACCESS;
29963 + clock = get_lclk_frequency_10khz();
29965 + pxa_pcmcia_socket[sock].speed_io=speed;
29968 + MCIO0 = ((pxa_mcxx_setup(speed, clock)
29969 + & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
29970 + | ((pxa_mcxx_asst(speed, clock)
29971 + & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
29972 + | ((pxa_mcxx_hold(speed, clock)
29973 + & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
29975 + MCIO1 = ((pxa_mcxx_setup(speed, clock)
29976 + & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
29977 + | ((pxa_mcxx_asst(speed, clock)
29978 + & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
29979 + | ((pxa_mcxx_hold(speed, clock)
29980 + & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
29983 + DEBUG(4, "%s(): FAST%u %lx BSM%u %lx BSA%u %lx BSIO%u %lx\n",
29984 + __FUNCTION__, sock, MECR_FAST_GET(mecr, sock), sock,
29985 + MECR_BSM_GET(mecr, sock), sock, MECR_BSA_GET(mecr, sock),
29986 + sock, MECR_BSIO_GET(mecr, sock));
29990 + start=map->start;
29993 + map->stop=PAGE_SIZE-1;
29995 + map->start=pxa_pcmcia_socket[sock].virt_io;
29996 + map->stop=map->start+(map->stop-start);
29998 + pxa_pcmcia_socket[sock].io_map[map->map]=*map;
30002 +} /* pxa_pcmcia_set_io_map() */
30005 +/* pxa_pcmcia_get_mem_map()
30006 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^
30007 + * Implements the get_mem_map() operation for the in-kernel PCMCIA
30008 + * service (formerly SS_GetMemMap in Card Services). Just returns a
30009 + * memory map descriptor which was assigned earlier by a
30010 + * set_mem_map() request.
30012 + * Returns: 0 on success, -1 if the map index was out of range
30014 +static int pxa_pcmcia_get_mem_map(unsigned int sock,
30015 + struct pccard_mem_map *map){
30017 + DEBUG(4, "%s() for sock %u\n", __FUNCTION__, sock);
30019 + if(map->map>=MAX_WIN){
30020 + printk(KERN_ERR "%s(): map (%d) out of range\n", __FUNCTION__,
30025 + *map=pxa_pcmcia_socket[sock].mem_map[map->map];
30031 +/* pxa_pcmcia_set_mem_map()
30032 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^
30033 + * Implements the set_mem_map() operation for the in-kernel PCMCIA
30034 + * service (formerly SS_SetMemMap in Card Services). We configure
30035 + * the map speed as requested, but override the address ranges
30036 + * supplied by Card Services.
30038 + * Returns: 0 on success, -1 on error
30040 +static int pxa_pcmcia_set_mem_map(unsigned int sock,
30041 + struct pccard_mem_map *map){
30042 + unsigned int clock, speed;
30043 + unsigned long mecr, start;
30045 + DEBUG(4, "%s() for sock %u\n", __FUNCTION__, sock);
30047 + DEBUG(4, "\tmap %u speed %u\n\tsys_start %#lx\n"
30048 + "\tsys_stop %#lx\n\tcard_start %#x\n"
30049 + "\tflags: %s%s%s%s%s%s%s%s\n",
30050 + map->map, map->speed, map->sys_start, map->sys_stop,
30051 + map->card_start, (map->flags==0)?"<NONE>":"",
30052 + (map->flags&MAP_ACTIVE)?"ACTIVE ":"",
30053 + (map->flags&MAP_16BIT)?"16BIT ":"",
30054 + (map->flags&MAP_AUTOSZ)?"AUTOSZ ":"",
30055 + (map->flags&MAP_0WS)?"0WS ":"",
30056 + (map->flags&MAP_WRPROT)?"WRPROT ":"",
30057 + (map->flags&MAP_ATTRIB)?"ATTRIB ":"",
30058 + (map->flags&MAP_USE_WAIT)?"USE_WAIT ":"");
30060 + if(map->map>=MAX_WIN){
30061 + printk(KERN_ERR "%s(): map (%d) out of range\n", __FUNCTION__,
30066 + if(map->flags&MAP_ACTIVE){
30067 + /* When clients issue RequestMap, the access speed is not always
30068 + * properly configured:
30070 + if(map->speed > 0)
30071 + speed = map->speed;
30073 + switch(pxa_pcmcia_socket[sock].cs_state.Vcc){
30075 + speed = PXA_PCMCIA_3V_MEM_ACCESS;
30078 + speed = PXA_PCMCIA_5V_MEM_ACCESS;
30081 + clock = get_lclk_frequency_10khz();
30083 + if(map->flags&MAP_ATTRIB){
30085 + MCATT0 = ((pxa_mcxx_setup(PXA_PCMCIA_ATTR_MEM_ACCESS, clock)
30086 + & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
30087 + | ((pxa_mcxx_asst(PXA_PCMCIA_ATTR_MEM_ACCESS, clock)
30088 + & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
30089 + | ((pxa_mcxx_hold(PXA_PCMCIA_ATTR_MEM_ACCESS, clock)
30090 + & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
30092 + MCATT1 = ((pxa_mcxx_setup(PXA_PCMCIA_ATTR_MEM_ACCESS, clock)
30093 + & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
30094 + | ((pxa_mcxx_asst(PXA_PCMCIA_ATTR_MEM_ACCESS, clock)
30095 + & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
30096 + | ((pxa_mcxx_hold(PXA_PCMCIA_ATTR_MEM_ACCESS, clock)
30097 + & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
30099 + pxa_pcmcia_socket[sock].speed_attr=speed;
30102 + MCMEM0 = ((pxa_mcxx_setup(speed, clock)
30103 + & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
30104 + | ((pxa_mcxx_asst(speed, clock)
30105 + & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
30106 + | ((pxa_mcxx_hold(speed, clock)
30107 + & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
30109 + MCMEM1 = ((pxa_mcxx_setup(speed, clock)
30110 + & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
30111 + | ((pxa_mcxx_asst(speed, clock)
30112 + & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
30113 + | ((pxa_mcxx_hold(speed, clock)
30114 + & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
30116 + pxa_pcmcia_socket[sock].speed_mem=speed;
30118 + DEBUG(4, "%s(): FAST%u %lx BSM%u %lx BSA%u %lx BSIO%u %lx\n",
30119 + __FUNCTION__, sock, MECR_FAST_GET(mecr, sock), sock,
30120 + MECR_BSM_GET(mecr, sock), sock, MECR_BSA_GET(mecr, sock),
30121 + sock, MECR_BSIO_GET(mecr, sock));
30124 + start=map->sys_start;
30126 + if(map->sys_stop==0)
30127 + map->sys_stop=PAGE_SIZE-1;
30129 + map->sys_start=(map->flags & MAP_ATTRIB)?\
30130 + pxa_pcmcia_socket[sock].phys_attr:\
30131 + pxa_pcmcia_socket[sock].phys_mem;
30133 + map->sys_stop=map->sys_start+(map->sys_stop-start);
30135 + pxa_pcmcia_socket[sock].mem_map[map->map]=*map;
30139 +} /* pxa_pcmcia_set_mem_map() */
30142 +#if defined(CONFIG_PROC_FS)
30144 +/* pxa_pcmcia_proc_setup()
30145 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^
30146 + * Implements the proc_setup() operation for the in-kernel PCMCIA
30147 + * service (formerly SS_ProcSetup in Card Services).
30149 + * Returns: 0 on success, -1 on error
30151 +static void pxa_pcmcia_proc_setup(unsigned int sock,
30152 + struct proc_dir_entry *base){
30153 + struct proc_dir_entry *entry;
30155 + DEBUG(4, "%s() for sock %u\n", __FUNCTION__, sock);
30157 + if((entry=create_proc_entry("status", 0, base))==NULL){
30158 + printk(KERN_ERR "Unable to install \"status\" procfs entry\n");
30162 + entry->read_proc=pxa_pcmcia_proc_status;
30163 + entry->data=(void *)sock;
30167 +/* pxa_pcmcia_proc_status()
30168 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^
30169 + * Implements the /proc/bus/pccard/??/status file.
30171 + * Returns: the number of characters added to the buffer
30173 +static int pxa_pcmcia_proc_status(char *buf, char **start, off_t pos,
30174 + int count, int *eof, void *data){
30176 + unsigned int sock=(unsigned int)data;
30177 + unsigned int clock = get_lclk_frequency_10khz();
30178 + unsigned long mecr = MECR;
30180 + p+=sprintf(p, "k_flags : %s%s%s%s%s%s%s\n",
30181 + pxa_pcmcia_socket[sock].k_state.detect?"detect ":"",
30182 + pxa_pcmcia_socket[sock].k_state.ready?"ready ":"",
30183 + pxa_pcmcia_socket[sock].k_state.bvd1?"bvd1 ":"",
30184 + pxa_pcmcia_socket[sock].k_state.bvd2?"bvd2 ":"",
30185 + pxa_pcmcia_socket[sock].k_state.wrprot?"wrprot ":"",
30186 + pxa_pcmcia_socket[sock].k_state.vs_3v?"vs_3v ":"",
30187 + pxa_pcmcia_socket[sock].k_state.vs_Xv?"vs_Xv ":"");
30189 + p+=sprintf(p, "status : %s%s%s%s%s%s%s%s%s\n",
30190 + pxa_pcmcia_socket[sock].k_state.detect?"SS_DETECT ":"",
30191 + pxa_pcmcia_socket[sock].k_state.ready?"SS_READY ":"",
30192 + pxa_pcmcia_socket[sock].cs_state.Vcc?"SS_POWERON ":"",
30193 + pxa_pcmcia_socket[sock].cs_state.flags&SS_IOCARD?\
30195 + (pxa_pcmcia_socket[sock].cs_state.flags&SS_IOCARD &&
30196 + pxa_pcmcia_socket[sock].k_state.bvd1)?"SS_STSCHG ":"",
30197 + ((pxa_pcmcia_socket[sock].cs_state.flags&SS_IOCARD)==0 &&
30198 + (pxa_pcmcia_socket[sock].k_state.bvd1==0))?"SS_BATDEAD ":"",
30199 + ((pxa_pcmcia_socket[sock].cs_state.flags&SS_IOCARD)==0 &&
30200 + (pxa_pcmcia_socket[sock].k_state.bvd2==0))?"SS_BATWARN ":"",
30201 + pxa_pcmcia_socket[sock].k_state.vs_3v?"SS_3VCARD ":"",
30202 + pxa_pcmcia_socket[sock].k_state.vs_Xv?"SS_XVCARD ":"");
30204 + p+=sprintf(p, "mask : %s%s%s%s%s\n",
30205 + pxa_pcmcia_socket[sock].cs_state.csc_mask&SS_DETECT?\
30207 + pxa_pcmcia_socket[sock].cs_state.csc_mask&SS_READY?\
30209 + pxa_pcmcia_socket[sock].cs_state.csc_mask&SS_BATDEAD?\
30210 + "SS_BATDEAD ":"",
30211 + pxa_pcmcia_socket[sock].cs_state.csc_mask&SS_BATWARN?\
30212 + "SS_BATWARN ":"",
30213 + pxa_pcmcia_socket[sock].cs_state.csc_mask&SS_STSCHG?\
30214 + "SS_STSCHG ":"");
30216 + p+=sprintf(p, "cs_flags : %s%s%s%s%s\n",
30217 + pxa_pcmcia_socket[sock].cs_state.flags&SS_PWR_AUTO?\
30218 + "SS_PWR_AUTO ":"",
30219 + pxa_pcmcia_socket[sock].cs_state.flags&SS_IOCARD?\
30221 + pxa_pcmcia_socket[sock].cs_state.flags&SS_RESET?\
30223 + pxa_pcmcia_socket[sock].cs_state.flags&SS_SPKR_ENA?\
30224 + "SS_SPKR_ENA ":"",
30225 + pxa_pcmcia_socket[sock].cs_state.flags&SS_OUTPUT_ENA?\
30226 + "SS_OUTPUT_ENA ":"");
30228 + p+=sprintf(p, "Vcc : %d\n", pxa_pcmcia_socket[sock].cs_state.Vcc);
30230 + p+=sprintf(p, "Vpp : %d\n", pxa_pcmcia_socket[sock].cs_state.Vpp);
30232 + p+=sprintf(p, "irq : %d\n", pxa_pcmcia_socket[sock].cs_state.io_irq);
30234 + p+=sprintf(p, "I/O : %u (%u)\n", pxa_pcmcia_socket[sock].speed_io,
30236 + pxa_pcmcia_cmd_time(clock,
30237 + ((MCIO1 >> MCXX_ASST_SHIFT) & MCXX_ASST_MASK)) :
30238 + pxa_pcmcia_cmd_time(clock,
30239 + ((MCIO0 >> MCXX_ASST_SHIFT) & MCXX_ASST_MASK)));
30241 + p+=sprintf(p, "attribute: %u (%u)\n", pxa_pcmcia_socket[sock].speed_attr,
30243 + pxa_pcmcia_cmd_time(clock,
30244 + ((MCATT1 >> MCXX_ASST_SHIFT) & MCXX_ASST_MASK)) :
30245 + pxa_pcmcia_cmd_time(clock,
30246 + ((MCATT0 >> MCXX_ASST_SHIFT) & MCXX_ASST_MASK)));
30248 + p+=sprintf(p, "common : %u (%u)\n", pxa_pcmcia_socket[sock].speed_mem,
30250 + pxa_pcmcia_cmd_time(clock,
30251 + ((MCMEM1 >> MCXX_ASST_SHIFT) & MCXX_ASST_MASK)) :
30252 + pxa_pcmcia_cmd_time(clock,
30253 + ((MCMEM0 >> MCXX_ASST_SHIFT) & MCXX_ASST_MASK)));
30258 +#endif /* defined(CONFIG_PROC_FS) */
30261 +#ifdef CONFIG_CPU_FREQ
30263 +/* pxa_pcmcia_update_mecr()
30264 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^
30265 + * When pxa_pcmcia_notifier() decides that a MECR adjustment (due
30266 + * to a core clock frequency change) is needed, this routine establishes
30267 + * new BS_xx values consistent with the clock speed `clock'.
30269 +static void pxa_pcmcia_update_mecr(unsigned int clock){
30270 + unsigned int sock;
30272 + for(sock = 0; sock < PXA_PCMCIA_MAX_SOCK; ++sock){
30274 + // REVISIT: MCXX macros needed here
30275 + // MECR_BSIO_SET(mecr, sock,
30276 +// pxa_pcmcia_mecr_bs(pxa_pcmcia_socket[sock].speed_io,
30278 + // MECR_BSA_SET(mecr, sock,
30279 +// pxa_pcmcia_mecr_bs(pxa_pcmcia_socket[sock].speed_attr,
30281 + // MECR_BSM_SET(mecr, sock,
30282 +// pxa_pcmcia_mecr_bs(pxa_pcmcia_socket[sock].speed_mem,
30287 +/* pxa_pcmcia_notifier()
30288 + * ^^^^^^^^^^^^^^^^^^^^^^^^
30289 + * When changing the processor core clock frequency, it is necessary
30290 + * to adjust the MECR timings accordingly. We've recorded the timings
30291 + * requested by Card Services, so this is just a matter of finding
30292 + * out what our current speed is, and then recomputing the new MECR
30295 + * Returns: 0 on success, -1 on error
30297 +static int pxa_pcmcia_notifier(struct notifier_block *nb,
30298 + unsigned long val, void *data){
30299 + struct cpufreq_info *ci = data;
30302 + case CPUFREQ_MINMAX:
30306 + case CPUFREQ_PRECHANGE:
30308 + if(ci->new_freq > ci->old_freq){
30309 + DEBUG(2, "%s(): new frequency %u.%uMHz > %u.%uMHz, pre-updating\n",
30311 + ci->new_freq / 1000, (ci->new_freq / 100) % 10,
30312 + ci->old_freq / 1000, (ci->old_freq / 100) % 10);
30313 + pxa_pcmcia_update_mecr(ci->new_freq);
30318 + case CPUFREQ_POSTCHANGE:
30320 + if(ci->new_freq < ci->old_freq){
30321 + DEBUG(2, "%s(): new frequency %u.%uMHz < %u.%uMHz, post-updating\n",
30323 + ci->new_freq / 1000, (ci->new_freq / 100) % 10,
30324 + ci->old_freq / 1000, (ci->old_freq / 100) % 10);
30325 + pxa_pcmcia_update_mecr(ci->new_freq);
30331 + printk(KERN_ERR "%s(): unknown CPU frequency event %lx\n", __FUNCTION__,
30341 +static struct notifier_block pxa_pcmcia_notifier_block = {
30342 + notifier_call: pxa_pcmcia_notifier
30348 +++ linux-2.4.27/drivers/pcmcia/pxa/pxa.h
30351 + * linux/drivers/pcmcia/pxa/pxa.h
30353 + * Author: George Davis
30354 + * Created: Jan 10, 2002
30355 + * Copyright: MontaVista Software Inc.
30357 + * This program is free software; you can redistribute it and/or modify
30358 + * it under the terms of the GNU General Public License version 2 as
30359 + * published by the Free Software Foundation.
30361 + * Originally based upon linux/drivers/pcmcia/sa1100_generic.h
30365 +/*======================================================================
30367 + Device driver for the PCMCIA control functionality of Intel
30368 + PXA250/210 microprocessors.
30370 + The contents of this file are subject to the Mozilla Public
30371 + License Version 1.1 (the "License"); you may not use this file
30372 + except in compliance with the License. You may obtain a copy of
30373 + the License at http://www.mozilla.org/MPL/
30375 + Software distributed under the License is distributed on an "AS
30376 + IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
30377 + implied. See the License for the specific language governing
30378 + rights and limitations under the License.
30380 + The initial developer of the original code is John G. Dorsey
30381 + <john+@cs.cmu.edu>. Portions created by John G. Dorsey are
30382 + Copyright (C) 1999 John G. Dorsey. All Rights Reserved.
30384 + Alternatively, the contents of this file may be used under the
30385 + terms of the GNU Public License version 2 (the "GPL"), in which
30386 + case the provisions of the GPL are applicable instead of the
30387 + above. If you wish to allow the use of your version of this file
30388 + only under the terms of the GPL and not to allow others to use
30389 + your version of this file under the MPL, indicate your decision
30390 + by deleting the provisions above and replace them with the notice
30391 + and other provisions required by the GPL. If you do not delete
30392 + the provisions above, a recipient may use your version of this
30393 + file under either the MPL or the GPL.
30395 +======================================================================*/
30397 +#if !defined(_PCMCIA_PXA_H)
30398 +# define _PCMCIA_PXA_H
30400 +#include <pcmcia/cs_types.h>
30401 +#include <pcmcia/ss.h>
30402 +#include <pcmcia/bulkmem.h>
30403 +#include <pcmcia/cistpl.h>
30404 +#include "../cs_internal.h"
30406 +#include <asm/arch/pcmcia.h>
30409 +/* MECR: Expansion Memory Configuration Register
30410 + * (SA-1100 Developers Manual, p.10-13; SA-1110 Developers Manual, p.10-24)
30412 + * MECR layout is:
30414 + * FAST1 BSM1<4:0> BSA1<4:0> BSIO1<4:0> FAST0 BSM0<4:0> BSA0<4:0> BSIO0<4:0>
30416 + * (This layout is actually true only for the SA-1110; the FASTn bits are
30417 + * reserved on the SA-1100.)
30420 +#define MCXX_SETUP_MASK (0x7f)
30421 +#define MCXX_ASST_MASK (0x1f)
30422 +#define MCXX_HOLD_MASK (0x3f)
30423 +#define MCXX_SETUP_SHIFT (0)
30424 +#define MCXX_ASST_SHIFT (7)
30425 +#define MCXX_HOLD_SHIFT (14)
30428 +#define MECR_SET(mecr, sock, shift, mask, bs) \
30429 +((mecr)=((mecr)&~(((mask)<<(shift))<<\
30430 + ((sock)==0?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT)))|\
30431 + (((bs)<<(shift))<<((sock)==0?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT)))
30433 +#define MECR_GET(mecr, sock, shift, mask) \
30434 +((((mecr)>>(((sock)==0)?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT))>>\
30437 +#define MECR_BSIO_SET(mecr, sock, bs) \
30438 +MECR_SET((mecr), (sock), MECR_BSIO_SHIFT, MECR_BS_MASK, (bs))
30440 +#define MECR_BSIO_GET(mecr, sock) \
30441 +MECR_GET((mecr), (sock), MECR_BSIO_SHIFT, MECR_BS_MASK)
30443 +#define MECR_BSA_SET(mecr, sock, bs) \
30444 +MECR_SET((mecr), (sock), MECR_BSA_SHIFT, MECR_BS_MASK, (bs))
30446 +#define MECR_BSA_GET(mecr, sock) \
30447 +MECR_GET((mecr), (sock), MECR_BSA_SHIFT, MECR_BS_MASK)
30449 +#define MECR_BSM_SET(mecr, sock, bs) \
30450 +MECR_SET((mecr), (sock), MECR_BSM_SHIFT, MECR_BS_MASK, (bs))
30452 +#define MECR_BSM_GET(mecr, sock) \
30453 +MECR_GET((mecr), (sock), MECR_BSM_SHIFT, MECR_BS_MASK)
30455 +#define MECR_FAST_SET(mecr, sock, fast) \
30456 +MECR_SET((mecr), (sock), MECR_FAST_SHIFT, MECR_FAST_MODE_MASK, (fast))
30458 +#define MECR_FAST_GET(mecr, sock) \
30459 +MECR_GET((mecr), (sock), MECR_FAST_SHIFT, MECR_FAST_MODE_MASK)
30462 +/* This function implements the BS value calculation for setting the MECR
30463 + * using integer arithmetic:
30465 +static inline unsigned int pxa_pcmcia_mecr_bs(unsigned int pcmcia_cycle_ns,
30466 + unsigned int cpu_clock_khz){
30467 + unsigned int t = ((pcmcia_cycle_ns * cpu_clock_khz) / 6) - 1000000;
30468 + return (t / 1000000) + (((t % 1000000) == 0) ? 0 : 1);
30471 +static inline u_int pxa_mcxx_hold(u_int pcmcia_cycle_ns,
30472 + u_int mem_clk_10khz){
30473 + u_int code = pcmcia_cycle_ns * mem_clk_10khz;
30474 + return (code / 300000) + ((code % 300000) ? 1 : 0);
30477 +static inline u_int pxa_mcxx_asst(u_int pcmcia_cycle_ns,
30478 + u_int mem_clk_10khz){
30479 + u_int code = pcmcia_cycle_ns * mem_clk_10khz;
30480 + return (code / 300000) + ((code % 300000) ? 1 : 0);
30483 +static inline u_int pxa_mcxx_setup(u_int pcmcia_cycle_ns,
30484 + u_int mem_clk_10khz){
30485 + u_int code = pcmcia_cycle_ns * mem_clk_10khz;
30486 + return (code / 100000) + ((code % 100000) ? 1 : 0) + 1;
30489 +/* This function returns the (approxmiate) command assertion period, in
30490 + * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
30493 +static inline u_int pxa_pcmcia_cmd_time(u_int mem_clk_10khz,
30494 + u_int pcmcia_mcxx_asst){
30495 + return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
30499 +/* SA-1100 PCMCIA Memory and I/O timing
30500 + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
30501 + * The SA-1110 Developer's Manual, section 10.2.5, says the following:
30503 + * "To calculate the recommended BS_xx value for each address space:
30504 + * divide the command width time (the greater of twIOWR and twIORD,
30505 + * or the greater of twWE and twOE) by processor cycle time; divide
30506 + * by 2; divide again by 3 (number of BCLK's per command assertion);
30507 + * round up to the next whole number; and subtract 1."
30509 + * The PC Card Standard, Release 7, section 4.13.4, says that twIORD
30510 + * has a minimum value of 165ns. Section 4.13.5 says that twIOWR has
30511 + * a minimum value of 165ns, as well. Section 4.7.2 (describing
30512 + * common and attribute memory write timing) says that twWE has a
30513 + * minimum value of 150ns for a 250ns cycle time (for 5V operation;
30514 + * see section 4.7.4), or 300ns for a 600ns cycle time (for 3.3V
30515 + * operation, also section 4.7.4). Section 4.7.3 says that taOE
30516 + * has a maximum value of 150ns for a 300ns cycle time (for 5V
30517 + * operation), or 300ns for a 600ns cycle time (for 3.3V operation).
30519 + * When configuring memory maps, Card Services appears to adopt the policy
30520 + * that a memory access time of "0" means "use the default." The default
30521 + * PCMCIA I/O command width time is 165ns. The default PCMCIA 5V attribute
30522 + * and memory command width time is 150ns; the PCMCIA 3.3V attribute and
30523 + * memory command width time is 300ns.
30526 +/* The PXA 250 and PXA 210 Application Processors Developer's Manual
30527 + * was used to determine correct PXA_PCMCIA_IO_ACCES time
30530 +#define PXA_PCMCIA_IO_ACCESS (165)
30532 +/* Default PC Card Common Memory timings*/
30534 +#define PXA_PCMCIA_5V_MEM_ACCESS (250)
30535 +#define PXA_PCMCIA_3V_MEM_ACCESS (250)
30537 +/* Atrribute Memory timing - must be constant via PC Card standart*/
30539 +#define PXA_PCMCIA_ATTR_MEM_ACCESS (300)
30542 +/* The socket driver actually works nicely in interrupt-driven form,
30543 + * so the (relatively infrequent) polling is "just to be sure."
30545 +#define PXA_PCMCIA_POLL_PERIOD (2*HZ)
30548 +/* This structure encapsulates per-socket state which we might need to
30549 + * use when responding to a Card Services query of some kind.
30551 +struct pxa_pcmcia_socket {
30552 + socket_state_t cs_state;
30553 + struct pcmcia_state k_state;
30554 + unsigned int irq;
30555 + void (*handler)(void *, unsigned int);
30556 + void *handler_info;
30557 + pccard_io_map io_map[MAX_IO_WIN];
30558 + pccard_mem_map mem_map[MAX_WIN];
30559 + ioaddr_t virt_io, phys_attr, phys_mem;
30560 + unsigned short speed_io, speed_attr, speed_mem;
30564 +/* I/O pins replacing memory pins
30565 + * (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75)
30567 + * These signals change meaning when going from memory-only to
30568 + * memory-or-I/O interface:
30570 +#define iostschg bvd1
30571 +#define iospkr bvd2
30575 + * Declaration for all implementation specific low_level operations.
30577 +extern struct pcmcia_low_level lubbock_pcmcia_ops;
30578 +extern struct pcmcia_low_level pxa_idp_pcmcia_ops;
30579 +extern struct pcmcia_low_level cerf_pcmcia_ops;
30580 +extern struct pcmcia_low_level trizeps2_pcmcia_ops;
30582 +#endif /* !defined(_PCMCIA_PXA_H) */
30584 +++ linux-2.4.27/drivers/pcmcia/pxa/pxa_idp.c
30587 + * linux/drivers/pcmcia/pxa/pxa_idp.c
30589 + * This program is free software; you can redistribute it and/or modify
30590 + * it under the terms of the GNU General Public License version 2 as
30591 + * published by the Free Software Foundation.
30593 + * Copyright (c) 2002 Accelent Systems, Inc. All Rights Reserved
30595 + * Platform specific routines for the Accelent PXA250 IDP, based on those
30596 + * first done for the Lubbock.
30598 + * Version 1.0 2002-05-02 Jeff Sutherland <jeffs@accelent.com>
30602 +#include <linux/kernel.h>
30603 +#include <linux/sched.h>
30605 +#include <pcmcia/ss.h>
30607 +#include <asm/delay.h>
30608 +#include <asm/hardware.h>
30609 +#include <asm/irq.h>
30610 +#include <asm/arch/pcmcia.h>
30613 +pxa_idp_pcmcia_init(struct pcmcia_init *init)
30615 + int return_val = 0;
30617 + /* Set PCMCIA Socket 0 power to standby mode.
30618 + * PXA IDP has dedicated CPLD pins for all this stuff :-)
30621 + /* both slots disabled, reset NOT active */
30622 + IDP_CPLD_PCCARD_EN = PCC0_ENABLE | PCC1_ENABLE;
30624 + IDP_CPLD_PCCARD_PWR = 0; //all power to both slots off
30626 + GPDR(IRQ_TO_GPIO_2_80(PCMCIA_S0_CD_VALID)) &=
30627 + ~GPIO_bit(IRQ_TO_GPIO_2_80(PCMCIA_S0_CD_VALID));
30628 + GPDR(IRQ_TO_GPIO_2_80(PCMCIA_S1_CD_VALID)) &=
30629 + ~GPIO_bit(IRQ_TO_GPIO_2_80(PCMCIA_S1_CD_VALID));
30631 + set_GPIO_IRQ_edge(IRQ_TO_GPIO_2_80(PCMCIA_S0_CD_VALID),
30632 + GPIO_BOTH_EDGES);
30633 + set_GPIO_IRQ_edge(IRQ_TO_GPIO_2_80(PCMCIA_S1_CD_VALID),
30634 + GPIO_BOTH_EDGES);
30636 + /* irq's for slots: */
30637 + GPDR(IRQ_TO_GPIO_2_80(PCMCIA_S0_RDYINT)) &=
30638 + ~GPIO_bit(IRQ_TO_GPIO_2_80(PCMCIA_S0_RDYINT));
30639 + GPDR(IRQ_TO_GPIO_2_80(PCMCIA_S1_RDYINT)) &=
30640 + ~GPIO_bit(IRQ_TO_GPIO_2_80(PCMCIA_S1_RDYINT));
30642 + set_GPIO_IRQ_edge(IRQ_TO_GPIO_2_80(PCMCIA_S0_RDYINT),
30643 + GPIO_FALLING_EDGE);
30644 + set_GPIO_IRQ_edge(IRQ_TO_GPIO_2_80(PCMCIA_S1_RDYINT),
30645 + GPIO_FALLING_EDGE);
30648 + request_irq(PCMCIA_S0_CD_VALID, init->handler, SA_INTERRUPT,
30649 + "PXA PCMCIA CD0", NULL);
30651 + if (return_val < 0)
30655 + request_irq(PCMCIA_S1_CD_VALID, init->handler, SA_INTERRUPT,
30656 + "PXA PCMCIA CD1", NULL);
30658 + if (return_val < 0) {
30659 + free_irq(PCMCIA_S0_CD_VALID, NULL);
30667 +pxa_idp_pcmcia_shutdown(void)
30670 + free_irq(PCMCIA_S0_CD_VALID, NULL);
30671 + free_irq(PCMCIA_S1_CD_VALID, NULL);
30673 + IDP_CPLD_PCCARD_EN = 0x03; //disable slots
30675 + IDP_CPLD_PCCARD_PWR = 0; //shut off all power
30681 +pxa_idp_pcmcia_socket_state(struct pcmcia_state_array *state_array)
30683 + unsigned long status;
30684 + int return_val = 1;
30686 + volatile unsigned long *stat_regs[2] = { &IDP_CPLD_PCCARD0_STATUS,
30687 + &IDP_CPLD_PCCARD1_STATUS
30690 + if (state_array->size < 2)
30693 + memset(state_array->state, 0,
30694 + (state_array->size) * sizeof (struct pcmcia_state));
30696 + for (i = 0; i < 2; i++) {
30698 + status = *stat_regs[i];
30700 + /* this one is a gpio */
30701 + state_array->state[i].detect = (PCC_DETECT(i)) ? 0 : 1;
30703 + state_array->state[i].ready =
30704 + ((status & _PCC_IRQ) == 0) ? 0 : 1;
30705 + state_array->state[i].bvd1 = (status & PCC_BVD1) ? 0 : 1;
30706 + state_array->state[i].bvd2 = (status & PCC_BVD2) ? 0 : 1;
30707 + state_array->state[i].wrprot =
30708 + (status & _PCC_WRPROT) ? 1 : 0;
30709 + state_array->state[i].vs_3v = (status & PCC_VS1) ? 0 : 1;
30710 + state_array->state[i].vs_Xv = (status & PCC_VS2) ? 0 : 1;
30713 + return return_val;
30717 +pxa_idp_pcmcia_get_irq_info(struct pcmcia_irq_info *info)
30719 + switch (info->sock) {
30721 + info->irq = PCMCIA_S0_RDYINT;
30725 + info->irq = PCMCIA_S1_RDYINT;
30736 +pxa_idp_pcmcia_configure_socket(unsigned int sock, socket_state_t *state)
30738 + /* The PXA Idp uses the Maxim MAX1602, with the following connections:
30740 + * Socket 0 (PCMCIA):
30741 + * MAX1602 PXA_IDP Register
30742 + * Pin Signal IDP_CPLD_PCCARD_PWR:
30743 + * ----- ------- ----------------------
30744 + * A0VPP PCC0_PWR0 bit0
30745 + * A1VPP PCC0_PWR1 bit1
30746 + * A0VCC PCC0_PWR2 bit2
30747 + * A1VCC PCC0_PWR3 bit3
30751 + * CODE +3.3V Cirrus Code, CODE = High (VY)
30753 + * Socket 1 (PCMCIA):
30754 + * MAX1602 PXA_IDP Register
30755 + * Pin Signal IDP_CPLD_PCCARD_PWR:
30756 + * ----- ------- ----------------------
30757 + * A0VPP PCC1_PWR0 bit4
30758 + * A1VPP PCC1_PWR1 bit5
30759 + * A0VCC PCC1_PWR2 bit6
30760 + * A1VCC PCC1_PWR3 bit7
30764 + * CODE +3.3V Cirrus Code, CODE = High (VY)
30770 + switch (state->Vcc) {
30772 + IDP_CPLD_PCCARD_EN |= PCC0_ENABLE; // disable socket
30774 + IDP_CPLD_PCCARD_PWR &= ~(PCC0_PWR2 | PCC0_PWR3);
30778 + IDP_CPLD_PCCARD_PWR &= ~(PCC0_PWR2 | PCC0_PWR3);
30779 + IDP_CPLD_PCCARD_PWR |= PCC0_PWR3;
30780 + IDP_CPLD_PCCARD_EN &= ~PCC0_ENABLE; //turn it on
30784 + IDP_CPLD_PCCARD_PWR &= ~(PCC0_PWR2 | PCC0_PWR3);
30785 + IDP_CPLD_PCCARD_PWR |= PCC0_PWR2;
30786 + IDP_CPLD_PCCARD_EN &= ~PCC0_ENABLE;
30790 + printk(KERN_ERR "%s(): unrecognized Vcc %u\n",
30791 + __FUNCTION__, state->Vcc);
30795 + switch (state->Vpp) {
30797 + IDP_CPLD_PCCARD_PWR &= ~(PCC0_PWR0 | PCC0_PWR1);
30801 + IDP_CPLD_PCCARD_PWR &= ~(PCC0_PWR0 | PCC0_PWR1);
30802 + IDP_CPLD_PCCARD_PWR |= PCC0_PWR1;
30806 + if (state->Vpp == state->Vcc)
30807 + IDP_CPLD_PCCARD_PWR =
30808 + (IDP_CPLD_PCCARD_PWR &
30809 + ~(PCC0_PWR0 | PCC0_PWR1)) | PCC0_PWR0;
30811 + printk(KERN_ERR "%s(): unrecognized Vpp %u\n",
30812 + __FUNCTION__, state->Vpp);
30817 + IDP_CPLD_PCCARD_EN =
30818 + (state->flags & SS_RESET) ? (IDP_CPLD_PCCARD_EN | PCC0_RESET)
30819 + : (IDP_CPLD_PCCARD_EN & ~PCC0_RESET);
30823 + switch (state->Vcc) {
30825 + IDP_CPLD_PCCARD_EN |= PCC1_ENABLE; // disable socket
30827 + IDP_CPLD_PCCARD_PWR &= ~(PCC1_PWR2 | PCC1_PWR3);
30831 + IDP_CPLD_PCCARD_PWR &= ~(PCC1_PWR2 | PCC1_PWR3);
30832 + IDP_CPLD_PCCARD_PWR |= PCC1_PWR3;
30833 + IDP_CPLD_PCCARD_EN &= ~PCC1_ENABLE; //turn it on
30837 + IDP_CPLD_PCCARD_PWR &= ~(PCC1_PWR2 | PCC1_PWR3);
30838 + IDP_CPLD_PCCARD_PWR |= PCC1_PWR2;
30839 + IDP_CPLD_PCCARD_EN &= ~PCC1_ENABLE;
30843 + printk(KERN_ERR "%s(): unrecognized Vcc %u\n",
30844 + __FUNCTION__, state->Vcc);
30848 + switch (state->Vpp) {
30850 + IDP_CPLD_PCCARD_PWR &= ~(PCC1_PWR0 | PCC1_PWR1);
30854 + IDP_CPLD_PCCARD_PWR &= ~(PCC1_PWR0 | PCC1_PWR1);
30855 + IDP_CPLD_PCCARD_PWR |= PCC1_PWR1;
30859 + if (state->Vpp == state->Vcc)
30860 + IDP_CPLD_PCCARD_PWR =
30861 + (IDP_CPLD_PCCARD_PWR &
30862 + ~(PCC1_PWR0 | PCC1_PWR1)) | PCC1_PWR0;
30864 + printk(KERN_ERR "%s(): unrecognized Vpp %u\n",
30865 + __FUNCTION__, state->Vpp);
30869 + IDP_CPLD_PCCARD_EN = (state->flags & SS_RESET) ? (IDP_CPLD_PCCARD_EN | PCC1_RESET)
30870 + : (IDP_CPLD_PCCARD_EN & ~PCC1_RESET);
30876 +struct pcmcia_low_level pxa_idp_pcmcia_ops = {
30877 + pxa_idp_pcmcia_init,
30878 + pxa_idp_pcmcia_shutdown,
30879 + pxa_idp_pcmcia_socket_state,
30880 + pxa_idp_pcmcia_get_irq_info,
30881 + pxa_idp_pcmcia_configure_socket
30884 +++ linux-2.4.27/drivers/pcmcia/pxa/trizeps2.c
30887 + * linux/drivers/pcmcia/pxa/trizeps2.c
30889 + * This program is free software; you can redistribute it and/or modify
30890 + * it under the terms of the GNU General Public License version 2 as
30891 + * published by the Free Software Foundation.
30893 + * Copyright (c) 2002 Accelent Systems, Inc. All Rights Reserved
30895 + * Platform specific routines for the Keith-n-Koep Trizeps-II, based on IDP
30897 + * Copyright (c) 2003 Teradyne DS, Ltd.
30898 + * Port to Trizeps-2 MT6N board by Luc De Cock
30902 +#include <linux/kernel.h>
30903 +#include <linux/sched.h>
30905 +#include <pcmcia/ss.h>
30907 +#include <asm/delay.h>
30908 +#include <asm/hardware.h>
30909 +#include <asm/irq.h>
30910 +#include <asm/arch/pcmcia.h>
30912 +static int trizeps2_pcmcia_init(struct pcmcia_init *init)
30914 + int return_val = 0;
30915 + unsigned short *bcr = (unsigned short *) TRIZEPS2_BCR_BASE;
30916 + unsigned short val;
30918 + /* reset the PCMCIA controller */
30919 + val = trizeps2_bcr_shadow | BCR_PCMCIA_RESET;
30922 + /* un-reset it again */
30923 + trizeps2_bcr_shadow &= ~BCR_PCMCIA_RESET;
30924 + /* enable the PCMCIA buffer */
30925 + trizeps2_bcr_shadow &= ~(1 << 5);
30926 + *bcr = trizeps2_bcr_shadow;
30928 + GPDR(IRQ_TO_GPIO_2_80(PCMCIA_S_CD_VALID)) &=
30929 + ~GPIO_bit(IRQ_TO_GPIO_2_80(PCMCIA_S_CD_VALID));
30930 + set_GPIO_IRQ_edge(IRQ_TO_GPIO_2_80(PCMCIA_S_CD_VALID),
30931 + PCMCIA_S_CD_VALID_EDGE);
30932 + GPDR(IRQ_TO_GPIO(PCMCIA_S_RDYINT)) &=
30933 + ~GPIO_bit(IRQ_TO_GPIO(PCMCIA_S_RDYINT));
30934 + set_GPIO_IRQ_edge(IRQ_TO_GPIO(PCMCIA_S_RDYINT),
30935 + PCMCIA_S_RDYINT_EDGE);
30937 + return_val = request_irq(PCMCIA_S_CD_VALID, init->handler, SA_INTERRUPT,
30938 + "PXA PCMCIA CD", NULL);
30939 + if (return_val < 0) {
30942 + /* only 1 slot */
30946 +static int trizeps2_pcmcia_shutdown(void)
30948 + free_irq(PCMCIA_S_CD_VALID, NULL);
30950 + unsigned short *bcr = (unsigned short *) TRIZEPS2_BCR_BASE;
30951 + trizeps2_bcr_shadow |= (1 << 5); /* pcmcia buffer off */
30952 + *bcr = trizeps2_bcr_shadow;
30953 + trizeps2_bcr_shadow &= 0xFFF0; /* pcmcia control logic grounded */
30954 + *bcr = trizeps2_bcr_shadow;
30959 +static int trizeps2_pcmcia_socket_state(struct pcmcia_state_array *state_array)
30961 + unsigned long status;
30962 + int return_val = 1;
30963 + volatile unsigned short *stat_regs[1] = {
30964 + &TRIZEPS2_PCCARD_STATUS
30967 + if (state_array->size < 1)
30970 + memset(state_array->state, 0,
30971 + (state_array->size) * sizeof (struct pcmcia_state));
30973 + status = *stat_regs[0];
30975 + /* this one is a gpio */
30976 + state_array->state[0].detect = (PCC_DETECT) ? 0 : 1;
30977 + state_array->state[0].ready = (PCC_READY) ? 1 : 0;
30978 + state_array->state[0].bvd1 = (status & PCC_BVD1) ? 1 : 0;
30979 + state_array->state[0].bvd2 = (status & PCC_BVD2) ? 1 : 0;
30980 + state_array->state[0].wrprot = 0; /* r/w all the time */
30981 + state_array->state[0].vs_3v = (status & PCC_VS1) ? 0 : 1;
30982 + state_array->state[0].vs_Xv = (status & PCC_VS2) ? 0 : 1;
30984 + return return_val;
30987 +static int trizeps2_pcmcia_get_irq_info(struct pcmcia_irq_info *info)
30989 + switch (info->sock) {
30991 + info->irq = PCMCIA_S_RDYINT;
31001 +static int trizeps2_pcmcia_configure_socket(unsigned int sock, socket_state_t *state)
31003 + unsigned short cntr_logic = trizeps2_bcr_shadow & 0xF;
31004 + unsigned short *bcr = (unsigned short *) TRIZEPS2_BCR_BASE;
31006 + /* configure Vcc and Vpp */
31009 + switch (state->Vcc) {
31011 + cntr_logic &= ~(PCC_3V | PCC_5V);
31015 + cntr_logic &= ~(PCC_3V | PCC_5V);
31016 + cntr_logic |= PCC_3V;
31020 + cntr_logic &= ~(PCC_3V | PCC_5V);
31021 + cntr_logic |= PCC_5V;
31025 + printk(KERN_ERR "%s(): unrecognized Vcc %u\n",
31026 + __FUNCTION__, state->Vcc);
31030 + switch (state->Vpp) {
31032 + cntr_logic &= ~(PCC_EN0 | PCC_EN1);
31036 + cntr_logic &= ~(PCC_EN0 | PCC_EN1);
31037 + cntr_logic |= PCC_EN1;
31041 + if (state->Vpp == state->Vcc) {
31042 + cntr_logic &= ~(PCC_EN0 | PCC_EN1);
31043 + cntr_logic |= PCC_EN0;
31046 + printk(KERN_ERR "%s(): unrecognized Vpp %u\n",
31047 + __FUNCTION__, state->Vpp);
31051 + trizeps2_bcr_shadow &= ~(PCC_EN0 | PCC_EN1 | PCC_3V | PCC_5V |
31052 + BCR_PCMCIA_RESET);
31053 + trizeps2_bcr_shadow |= cntr_logic;
31054 + *bcr = trizeps2_bcr_shadow;
31055 + /* reset PCMCIA controller if requested */
31056 + trizeps2_bcr_shadow |=
31057 + (state->flags & SS_RESET) ? BCR_PCMCIA_RESET : 0;
31058 + *bcr = trizeps2_bcr_shadow;
31065 +struct pcmcia_low_level trizeps2_pcmcia_ops = {
31066 + trizeps2_pcmcia_init,
31067 + trizeps2_pcmcia_shutdown,
31068 + trizeps2_pcmcia_socket_state,
31069 + trizeps2_pcmcia_get_irq_info,
31070 + trizeps2_pcmcia_configure_socket
31073 --- linux-2.4.27/drivers/pcmcia/sa1100_cerf.c~2.4.27-vrs1-pxa1
31074 +++ linux-2.4.27/drivers/pcmcia/sa1100_cerf.c
31077 #include <linux/kernel.h>
31078 #include <linux/sched.h>
31079 +#include <linux/delay.h>
31081 #include <asm/hardware.h>
31082 #include <asm/irq.h>
31083 -#include "sa1100_generic.h"
31085 -#ifdef CONFIG_SA1100_CERF_CPLD
31086 -#define CERF_SOCKET 0
31087 +#include <pcmcia/ss.h>
31088 +#include <asm/arch/pcmcia.h>
31089 +#include "sa1100_cerf.h"
31092 + * Set this to zero to remove all the debug statements via
31093 + * dead code elimination
31095 +//#define DEBUGGING 1
31098 +static unsigned int pcmcia_debug = DEBUGGING;
31100 -#define CERF_SOCKET 1
31101 +#define pcmcia_debug 0 /* gcc will remove all the debug code for us */
31104 static struct irqs {
31105 @@ -23,122 +33,178 @@
31109 - { IRQ_GPIO_CF_CD, GPIO_CF_CD, "CF_CD" },
31110 - { IRQ_GPIO_CF_BVD2, GPIO_CF_BVD2, "CF_BVD2" },
31111 - { IRQ_GPIO_CF_BVD1, GPIO_CF_BVD1, "CF_BVD1" }
31112 + { PCMCIA_IRQ_CF_CD, PCMCIA_GPIO_CF_CD_EDGE, "CF_CD" },
31113 + { PCMCIA_IRQ_CF_BVD2, PCMCIA_GPIO_CF_BVD2_EDGE, "CF_BVD2" },
31114 + { PCMCIA_IRQ_CF_BVD1, PCMCIA_GPIO_CF_BVD1_EDGE, "CF_BVD1" }
31117 +static void cerf_pcmcia_reset( void)
31121 + // Make sure SKTSEL is 0 (single slot)
31122 + set_GPIO_mode(54 | GPIO_OUT);
31123 + GPCR1 = GPIO_bit(54);
31124 + set_GPIO_mode(GPIO54_pSKTSEL_MD);
31126 + PCMCIA_GPCR = PCMCIA_GPIO_CF_RESET_MASK;
31129 + PCMCIA_GPSR = PCMCIA_GPIO_CF_RESET_MASK;
31132 + PCMCIA_GPCR = PCMCIA_GPIO_CF_RESET_MASK;
31135 + for( i=0; i<10; i++)
31137 + if( cerf_pcmcia_level_ready()) break;
31142 static int cerf_pcmcia_init(struct pcmcia_init *init)
31147 - set_GPIO_IRQ_edge( GPIO_CF_IRQ, GPIO_FALLING_EDGE );
31148 + if( pcmcia_debug)
31149 + printk( KERN_INFO "cerf_pcmcia_init: enter\n");
31151 - for (i = 0; i < ARRAY_SIZE(irqs); i++) {
31152 - set_GPIO_IRQ_edge(irqs[i].gpio, GPIO_NO_EDGES);
31153 - res = request_irq(irqs[i].irq, init->handler, SA_INTERRUPT,
31154 - irqs[i].str, NULL);
31158 + cerf_pcmcia_set_gpio_direction();
31161 + set_GPIO_IRQ_edge( PCMCIA_GPIO_CF_IRQ_EDGE, GPIO_FALLING_EDGE );
31164 - printk(KERN_ERR "%s: Request for IRQ%d failed\n", __FUNCTION__, irqs[i].irq);
31165 + for (i = 0; i < ARRAY_SIZE(irqs); i++) {
31168 - free_irq(irqs[i].irq, NULL);
31169 + set_GPIO_IRQ_edge(irqs[i].gpio, GPIO_BOTH_EDGES);
31172 + res = request_irq(irqs[i].irq, init->handler, SA_INTERRUPT,
31173 + irqs[i].str, NULL);
31178 + printk( KERN_INFO "PCMCIA for Cerf: OK\n");
31180 + return CERF_SOCKET+1; /* last socket used +1 */
31183 + printk(KERN_ERR "%s: Request for IRQ%d failed\n",
31184 + __FUNCTION__, irqs[i].irq);
31187 + free_irq(irqs[i].irq, NULL);
31192 static int cerf_pcmcia_shutdown(void)
31196 + if( pcmcia_debug)
31197 + printk( KERN_INFO "cerf_pcmcia_shutdown: enter\n");
31199 - for (i = 0; i < ARRAY_SIZE(irqs); i++)
31200 - free_irq(irqs[i].irq, NULL);
31201 + for (i = 0; i < ARRAY_SIZE(irqs); i++)
31202 + free_irq(irqs[i].irq, NULL);
31208 -static int cerf_pcmcia_socket_state(struct pcmcia_state_array
31210 - unsigned long levels;
31211 - int i = CERF_SOCKET;
31212 +static int cerf_pcmcia_socket_state(struct pcmcia_state_array *state_array)
31214 + int i = CERF_SOCKET;
31216 - if(state_array->size<2) return -1;
31217 + if( pcmcia_debug > 3)
31218 + printk( KERN_INFO "cerf_pcmcia_socket_state: i=%d, size=%d\n",
31219 + i, state_array->size);
31222 + memset(state_array->state, 0,
31223 + (state_array->size)*sizeof(struct pcmcia_state));
31225 - state_array->state[i].detect=((levels & GPIO_CF_CD)==0)?1:0;
31226 - state_array->state[i].ready=(levels & GPIO_CF_IRQ)?1:0;
31227 - state_array->state[i].bvd1=(levels & GPIO_CF_BVD1)?1:0;
31228 - state_array->state[i].bvd2=(levels & GPIO_CF_BVD2)?1:0;
31229 - state_array->state[i].wrprot=0;
31230 - state_array->state[i].vs_3v=1;
31231 - state_array->state[i].vs_Xv=0;
31232 + state_array->state[i].detect = cerf_pcmcia_level_detect();
31233 + state_array->state[i].ready = cerf_pcmcia_level_ready();
31234 + state_array->state[i].bvd1 = cerf_pcmcia_level_bvd1();
31235 + state_array->state[i].bvd2 = cerf_pcmcia_level_bvd2();
31236 + state_array->state[i].wrprot=0;
31237 + state_array->state[i].vs_3v=1;
31238 + state_array->state[i].vs_Xv=0;
31241 + if( pcmcia_debug > 3)
31242 + printk( KERN_INFO "cerf_pcmcia_socket_state: "
31243 + "detect=%d ready=%d bvd1=%d bvd2=%d\n",
31244 + state_array->state[i].detect,
31245 + state_array->state[i].ready,
31246 + state_array->state[i].bvd1,
31247 + state_array->state[i].bvd2);
31252 static int cerf_pcmcia_get_irq_info(struct pcmcia_irq_info *info){
31254 - if(info->sock>1) return -1;
31255 + if( pcmcia_debug)
31256 + printk( KERN_INFO "cerf_pcmcia_get_irq_info: "
31257 + "sock=%d\n", info->sock);
31259 - if (info->sock == CERF_SOCKET)
31260 - info->irq=IRQ_GPIO_CF_IRQ;
31261 + if(info->sock>1) return -1;
31264 + if (info->sock == CERF_SOCKET)
31265 + info->irq=PCMCIA_IRQ_CF_IRQ;
31267 + if( pcmcia_debug)
31268 + printk( KERN_INFO "cerf_pcmcia_get_irq_info: irq=%d\n",info->irq);
31273 -static int cerf_pcmcia_configure_socket(const struct pcmcia_configure
31275 +static int cerf_pcmcia_configure_socket( unsigned int sock, socket_state_t *state)
31277 - if(configure->sock>1)
31279 + if( pcmcia_debug)
31280 + printk( KERN_INFO "cerf_pcmcia_configure_socket:"
31281 + "sock=%d vcc=%d flags=%x\n",
31282 + sock, state->Vcc, state->flags);
31284 - if (configure->sock != CERF_SOCKET)
31289 - switch(configure->vcc){
31292 + if (sock != CERF_SOCKET)
31297 -#ifdef CONFIG_SA1100_CERF_CPLD
31298 - GPCR = GPIO_PWR_SHUTDOWN;
31299 + switch(state->Vcc){
31305 +#if defined(CONFIG_SA1100_CERF_CPLD)
31306 + PCMCIA_GPDR |= PCMCIA_PWR_SHUTDOWN;
31307 + PCMCIA_GPCR |= PCMCIA_PWR_SHUTDOWN;
31310 + /* voltage selected automatically */
31314 - printk(KERN_ERR "%s(): unrecognized Vcc %u\n", __FUNCTION__,
31319 + printk(KERN_ERR "%s(): unrecognized Vcc %u\n",
31320 + __FUNCTION__, state->Vcc);
31324 - if(configure->reset)
31326 -#ifdef CONFIG_SA1100_CERF_CPLD
31327 - GPSR = GPIO_CF_RESET;
31332 -#ifdef CONFIG_SA1100_CERF_CPLD
31333 - GPCR = GPIO_CF_RESET;
31336 + if(state->flags&SS_RESET)
31338 + cerf_pcmcia_reset();
31345 +#ifdef CONFIG_SA1100_CERF
31346 static int cerf_pcmcia_socket_init(int sock)
31350 + if( pcmcia_debug)
31351 + printk( KERN_INFO "cerf_pcmcia_socket_init: sock=%d\n",sock);
31353 if (sock == CERF_SOCKET)
31354 for (i = 0; i < ARRAY_SIZE(irqs); i++)
31355 set_GPIO_IRQ_edge(irqs[i].gpio, GPIO_BOTH_EDGES);
31356 @@ -150,21 +216,26 @@
31360 + if( pcmcia_debug)
31361 + printk( KERN_INFO "cerf_pcmcia_socket_suspend: sock=%d\n",sock);
31363 if (sock == CERF_SOCKET)
31364 for (i = 0; i < ARRAY_SIZE(irqs); i++)
31365 set_GPIO_IRQ_edge(irqs[i].gpio, GPIO_NO_EDGES);
31371 struct pcmcia_low_level cerf_pcmcia_ops = {
31372 - init: cerf_pcmcia_init,
31373 - shutdown: cerf_pcmcia_shutdown,
31374 - socket_state: cerf_pcmcia_socket_state,
31375 - get_irq_info: cerf_pcmcia_get_irq_info,
31376 - configure_socket: cerf_pcmcia_configure_socket,
31377 +init: cerf_pcmcia_init,
31378 +shutdown: cerf_pcmcia_shutdown,
31379 +socket_state: cerf_pcmcia_socket_state,
31380 +get_irq_info: cerf_pcmcia_get_irq_info,
31381 +configure_socket: cerf_pcmcia_configure_socket,
31383 - socket_init: cerf_pcmcia_socket_init,
31384 - socket_suspend: cerf_pcmcia_socket_suspend,
31385 +#ifdef CONFIG_SA1100_CERF
31386 +socket_init: cerf_pcmcia_socket_init,
31387 +socket_suspend: cerf_pcmcia_socket_suspend,
31392 +++ linux-2.4.27/drivers/pcmcia/sa1100_cerf.h
31395 + * drivers/pcmcia/cerf.h
31397 + * PCMCIA implementation routines for CerfBoard
31398 + * Based off the Assabet.
31401 +#ifndef _LINUX_PCMCIA_CERF_H
31402 +#define _LINUX_PCMCIA_CERF_H
31404 +#include <linux/config.h>
31405 +#include <asm/hardware.h>
31406 +#include <asm/irq.h>
31407 +#include <asm/arch/pcmcia.h>
31409 +#ifdef CONFIG_PXA_CERF /* PXA */
31411 +#define PCMCIA_GPCR GPCR0
31412 +#define PCMCIA_GPSR GPSR0
31414 +#define PCMCIA_GPIO_CF_CD 14
31415 +#define PCMCIA_GPIO_CF_IRQ 13
31416 +#define PCMCIA_GPIO_CF_RESET 12
31417 +#ifdef CONFIG_PXA_CERF_PDA
31418 +# define PCMCIA_GPIO_CF_BVD1 11
31419 +# define PCMCIA_GPIO_CF_BVD2 10
31420 +#elif defined( CONFIG_PXA_CERF_BOARD)
31421 +# define PCMCIA_GPIO_CF_BVD1 32
31422 +# define PCMCIA_GPIO_CF_BVD2 10
31425 +#define PCMCIA_GPIO_CF_CD_MASK (GPIO_bit(PCMCIA_GPIO_CF_CD))
31426 +#define PCMCIA_GPIO_CF_IRQ_MASK (GPIO_bit(PCMCIA_GPIO_CF_IRQ))
31427 +#define PCMCIA_GPIO_CF_RESET_MASK (GPIO_bit(PCMCIA_GPIO_CF_RESET))
31428 +#define PCMCIA_GPIO_CF_BVD1_MASK (GPIO_bit(PCMCIA_GPIO_CF_BVD1))
31429 +#define PCMCIA_GPIO_CF_BVD2_MASK (GPIO_bit(PCMCIA_GPIO_CF_BVD2))
31431 +#define PCMCIA_GPIO_CF_CD_EDGE PCMCIA_GPIO_CF_CD
31432 +#define PCMCIA_GPIO_CF_IRQ_EDGE PCMCIA_GPIO_CF_IRQ
31433 +#define PCMCIA_GPIO_CF_RESET_EDGE PCMCIA_GPIO_CF_RESET
31434 +#define PCMCIA_GPIO_CF_BVD1_EDGE PCMCIA_GPIO_CF_BVD1
31435 +#define PCMCIA_GPIO_CF_BVD2_EDGE PCMCIA_GPIO_CF_BVD2
31437 +#define PCMCIA_IRQ_CF_CD IRQ_GPIO(PCMCIA_GPIO_CF_CD)
31438 +#define PCMCIA_IRQ_CF_IRQ IRQ_GPIO(PCMCIA_GPIO_CF_IRQ)
31439 +#define PCMCIA_IRQ_CF_BVD1 IRQ_GPIO(PCMCIA_GPIO_CF_BVD1)
31440 +#define PCMCIA_IRQ_CF_BVD2 IRQ_GPIO(PCMCIA_GPIO_CF_BVD2)
31442 +#define PCMCIA_PWR_SHUTDOWN 0 /* not needed */
31443 +#define CERF_SOCKET 0
31445 +inline void cerf_pcmcia_set_gpio_direction(void)
31447 + GPDR(PCMCIA_GPIO_CF_CD) &= ~(PCMCIA_GPIO_CF_CD_MASK);
31448 + GPDR(PCMCIA_GPIO_CF_BVD1) &= ~(PCMCIA_GPIO_CF_BVD1_MASK);
31449 + GPDR(PCMCIA_GPIO_CF_BVD2) &= ~(PCMCIA_GPIO_CF_BVD2_MASK);
31450 + GPDR(PCMCIA_GPIO_CF_IRQ) &= ~(PCMCIA_GPIO_CF_IRQ_MASK);
31451 + GPDR(PCMCIA_GPIO_CF_RESET)|= (PCMCIA_GPIO_CF_RESET_MASK);
31454 +inline int cerf_pcmcia_level_detect( void)
31456 + return ((GPLR(PCMCIA_GPIO_CF_CD)&PCMCIA_GPIO_CF_CD_MASK)==0)?1:0;
31458 +inline int cerf_pcmcia_level_ready( void)
31460 + return (GPLR(PCMCIA_GPIO_CF_IRQ)&PCMCIA_GPIO_CF_IRQ_MASK)?1:0;
31462 +inline int cerf_pcmcia_level_bvd1( void)
31464 + return (GPLR(PCMCIA_GPIO_CF_BVD1)&PCMCIA_GPIO_CF_BVD1_MASK)?1:0;
31466 +inline int cerf_pcmcia_level_bvd2( void)
31468 + return (GPLR(PCMCIA_GPIO_CF_BVD2)&PCMCIA_GPIO_CF_BVD2_MASK)?1:0;
31471 +#elif defined(CONFIG_SA1100_CERF) /* SA1100 */
31473 +#define PCMCIA_GPDR GPDR
31474 +#define PCMCIA_GPCR GPCR
31475 +#define PCMCIA_GPSR GPSR
31476 +#define PCMCIA_GPLR GPLR
31478 +#define PCMCIA_GPIO_CF_CD_MASK GPIO_CF_CD
31479 +#define PCMCIA_GPIO_CF_IRQ_MASK GPIO_CF_IRQ
31480 +#define PCMCIA_GPIO_CF_RESET_MASK GPIO_CF_RESET
31481 +#define PCMCIA_GPIO_CF_BVD1_MASK GPIO_CF_BVD1
31482 +#define PCMCIA_GPIO_CF_BVD2_MASK GPIO_CF_BVD2
31484 +#define PCMCIA_GPIO_CF_CD_EDGE PCMCIA_GPIO_CF_CD_MASK
31485 +#define PCMCIA_GPIO_CF_IRQ_EDGE PCMCIA_GPIO_CF_IRQ_MASK
31486 +#define PCMCIA_GPIO_CF_RESET_EDGE PCMCIA_GPIO_CF_RESET_MASK
31487 +#define PCMCIA_GPIO_CF_BVD1_EDGE PCMCIA_GPIO_CF_BVD1_MASK
31488 +#define PCMCIA_GPIO_CF_BVD2_EDGE PCMCIA_GPIO_CF_BVD2_MASK
31490 +#define PCMCIA_IRQ_CF_CD IRQ_GPIO_CF_CD
31491 +#define PCMCIA_IRQ_CF_IRQ IRQ_GPIO_CF_IRQ
31492 +#define PCMCIA_IRQ_CF_BVD1 IRQ_GPIO_CF_BVD1
31493 +#define PCMCIA_IRQ_CF_BVD2 IRQ_GPIO_CF_BVD2
31495 +#define PCMCIA_PWR_SHUTDOWN GPIO_PWR_SHUTDOWN
31497 +#ifdef CONFIG_SA1100_CERF_CPLD
31498 +#define CERF_SOCKET 0
31500 +#define CERF_SOCKET 1
31503 +inline void cerf_pcmcia_set_gpio_direction(void)
31505 + PCMCIA_GPDR &= ~(PCMCIA_GPIO_CF_CD_MASK |
31506 + PCMCIA_GPIO_CF_BVD1_MASK |
31507 + PCMCIA_GPIO_CF_BVD2_MASK |
31508 + PCMCIA_GPIO_CF_IRQ_MASK);
31509 + PCMCIA_GPDR |= PCMCIA_GPIO_CF_RESET_MASK;
31512 +inline int cerf_pcmcia_level_detect( void)
31514 + return ((PCMCIA_GPLR & PCMCIA_GPIO_CF_CD_MASK)==0)?1:0;
31516 +inline int cerf_pcmcia_level_ready( void)
31518 + return (PCMCIA_GPLR & PCMCIA_GPIO_CF_IRQ_MASK)?1:0;
31520 +inline int cerf_pcmcia_level_bvd1( void)
31522 + return (PCMCIA_GPLR & PCMCIA_GPIO_CF_BVD1_MASK)?1:0;
31524 +inline int cerf_pcmcia_level_bvd2( void)
31526 + return (PCMCIA_GPLR & PCMCIA_GPIO_CF_BVD2_MASK)?1:0;
31532 --- linux-2.4.27/drivers/sound/Config.in~2.4.27-vrs1-pxa1
31533 +++ linux-2.4.27/drivers/sound/Config.in
31534 @@ -239,6 +239,7 @@
31535 dep_tristate ' VIDC 16-bit sound' CONFIG_SOUND_VIDC $CONFIG_SOUND_OSS
31537 dep_tristate ' Netwinder WaveArtist' CONFIG_SOUND_WAVEARTIST $CONFIG_SOUND_OSS $CONFIG_ARCH_NETWINDER
31538 + dep_tristate ' Intel PXA250/210 AC97 audio' CONFIG_SOUND_PXA_AC97 $CONFIG_ARCH_PXA $CONFIG_SOUND
31541 dep_tristate ' TV card (bt848) mixer support' CONFIG_SOUND_TVMIXER $CONFIG_SOUND $CONFIG_I2C
31542 --- linux-2.4.27/drivers/sound/Makefile~2.4.27-vrs1-pxa1
31543 +++ linux-2.4.27/drivers/sound/Makefile
31545 msnd.o opl3.o sb_common.o sequencer_syms.o \
31546 sound_core.o sound_syms.o uart401.o \
31547 nm256_audio.o ac97.o ac97_codec.o aci.o \
31549 + sa1100-audio.o pxa-audio.o pxa-ac97.o
31551 # Each configuration option enables a list of files.
31554 obj-$(CONFIG_SOUND_SA1111_UDA1341) += sa1111-uda1341.o
31555 obj-$(CONFIG_SOUND_SA1111_AC97) += sa1111-ac97.o ac97_codec.o
31556 obj-$(CONFIG_SOUND_SA1100SSP) += sa1100ssp.o
31557 +obj-$(CONFIG_SOUND_PXA_AC97)+= pxa-ac97.o pxa-audio.o ac97_codec.o
31558 obj-$(CONFIG_SOUND_EMU10K1) += ac97_codec.o
31559 obj-$(CONFIG_SOUND_BCM_CS4297A) += swarm_cs4297a.o
31560 obj-$(CONFIG_SOUND_RME96XX) += rme96xx.o
31561 --- linux-2.4.27/drivers/sound/ac97_codec.c~2.4.27-vrs1-pxa1
31562 +++ linux-2.4.27/drivers/sound/ac97_codec.c
31563 @@ -155,6 +155,7 @@
31564 {0x45838308, "ESS Allegro ES1988", &null_ops},
31565 {0x49434511, "ICE1232", &null_ops}, /* I hope --jk */
31566 {0x4e534331, "National Semiconductor LM4549", &null_ops},
31567 + {0x50534304, "Philips UCB1400", &default_ops},
31568 {0x53494c22, "Silicon Laboratory Si3036", &null_ops},
31569 {0x53494c23, "Silicon Laboratory Si3038", &null_ops},
31570 {0x545200FF, "TriTech TR?????", &tritech_m_ops},
31572 +++ linux-2.4.27/drivers/sound/pxa-ac97.c
31575 + * linux/drivers/sound/pxa-ac97.c -- AC97 interface for the Cotula chip
31577 + * Author: Nicolas Pitre
31578 + * Created: Aug 15, 2001
31579 + * Copyright: MontaVista Software Inc.
31581 + * This program is free software; you can redistribute it and/or modify
31582 + * it under the terms of the GNU General Public License version 2 as
31583 + * published by the Free Software Foundation.
31585 + * AC97 GPIO Changes:-
31586 + * In order to read/write codec GPIO bits using AC97 link slot 12,
31587 + * all IO to AC97_GPIO_STATUS must be via the Xscale modem codec
31589 + * Liam Girdwood <liam.girdwood@wolfsonmicro.com>
31592 +#include <linux/init.h>
31593 +#include <linux/module.h>
31594 +#include <linux/kernel.h>
31595 +#include <linux/slab.h>
31596 +#include <linux/pci.h>
31597 +#include <linux/completion.h>
31598 +#include <linux/delay.h>
31599 +#include <linux/poll.h>
31600 +#include <linux/sound.h>
31601 +#include <linux/soundcard.h>
31602 +#include <linux/ac97_codec.h>
31604 +#include <asm/hardware.h>
31605 +#include <asm/irq.h>
31606 +#include <asm/uaccess.h>
31607 +#include <asm/semaphore.h>
31608 +#include <asm/dma.h>
31610 +#include "pxa-audio.h"
31612 +static struct completion CAR_completion;
31613 +static int waitingForMask;
31614 +static DECLARE_MUTEX(CAR_mutex);
31616 +static u16 pxa_ac97_read(struct ac97_codec *codec, u8 reg)
31620 + down(&CAR_mutex);
31621 + if (!(CAR & CAR_CAIP)) {
31622 + volatile u32 *reg_addr;
31624 + // if we are reading the GPIO status then this is cached
31625 + // in hardware so we don't need to read over the link.
31626 + if (reg == AC97_GPIO_STATUS) {
31627 + reg_addr = (u32 *)&PMC_REG_BASE + (reg >> 1);
31632 + reg_addr = (u32 *)&PAC_REG_BASE + (reg >> 1);
31634 + waitingForMask=GSR_SDONE;
31636 + init_completion(&CAR_completion);
31637 + (void)*reg_addr; //start read access across the ac97 link
31638 + wait_for_completion(&CAR_completion);
31640 + if (GSR & GSR_RDCS) {
31641 + GSR |= GSR_RDCS; //write a 1 to clear
31642 + printk(KERN_CRIT __FUNCTION__": read codec register timeout.\n");
31645 + init_completion(&CAR_completion);
31646 + val = *reg_addr; //valid data now but we've just started another cycle...
31647 + wait_for_completion(&CAR_completion);
31650 + printk(KERN_CRIT __FUNCTION__": CAR_CAIP already set\n");
31653 + //printk("%s(0x%02x) = 0x%04x\n", __FUNCTION__, reg, val);
31657 +static void pxa_ac97_write(struct ac97_codec *codec, u8 reg, u16 val)
31659 + down(&CAR_mutex);
31660 + if (!(CAR & CAR_CAIP)) {
31661 + volatile u32 *reg_addr;
31663 + // if we are writing to the codec GPIO using slot 12
31664 + // then we have to write to the modem register space
31665 + if (reg == AC97_GPIO_STATUS) {
31666 + reg_addr = (u32 *)&PMC_REG_BASE + (reg >> 1);
31671 + reg_addr = (u32 *)&PAC_REG_BASE + (reg >> 1);
31673 + waitingForMask=GSR_CDONE;
31674 + init_completion(&CAR_completion);
31676 + wait_for_completion(&CAR_completion);
31678 + printk(KERN_CRIT __FUNCTION__": CAR_CAIP already set\n");
31681 + //printk("%s(0x%02x, 0x%04x)\n", __FUNCTION__, reg, val);
31684 +static void pxa_ac97_irq(int irq, void *dev_id, struct pt_regs *regs)
31687 + GSR = gsr & (GSR_SDONE|GSR_CDONE); //write a 1 to clear
31688 + if (gsr & waitingForMask)
31690 + complete(&CAR_completion);
31694 +static struct ac97_codec pxa_ac97_codec = {
31695 + codec_read: pxa_ac97_read,
31696 + codec_write: pxa_ac97_write,
31699 +static DECLARE_MUTEX(pxa_ac97_mutex);
31700 +static int pxa_ac97_refcount;
31702 +int pxa_ac97_get(struct ac97_codec **codec)
31707 + down(&pxa_ac97_mutex);
31709 + if (!pxa_ac97_refcount) {
31710 + ret = request_irq(IRQ_AC97, pxa_ac97_irq, 0, "AC97", NULL);
31714 + CKEN |= CKEN2_AC97;
31715 + set_GPIO_mode(GPIO31_SYNC_AC97_MD);
31716 + set_GPIO_mode(GPIO30_SDATA_OUT_AC97_MD);
31717 + set_GPIO_mode(GPIO28_BITCLK_AC97_MD);
31718 + set_GPIO_mode(GPIO29_SDATA_IN_AC97_MD);
31722 + GCR = GCR_COLD_RST|GCR_CDONE_IE|GCR_SDONE_IE;
31723 + while (!(GSR & GSR_PCR)) {
31727 + ret = ac97_probe_codec(&pxa_ac97_codec);
31729 + free_irq(IRQ_AC97, NULL);
31730 + GCR = GCR_ACLINK_OFF;
31731 + CKEN &= ~CKEN2_AC97;
31735 + // need little hack for UCB1400 (should be moved elsewhere)
31736 + pxa_ac97_write(&pxa_ac97_codec,AC97_EXTENDED_STATUS,1);
31737 + //pxa_ac97_write(&pxa_ac97_codec, 0x6a, 0x1ff7);
31738 + pxa_ac97_write(&pxa_ac97_codec, 0x6a, 0x0050);
31739 + pxa_ac97_write(&pxa_ac97_codec, 0x6c, 0x0030);
31742 + pxa_ac97_refcount++;
31743 + up(&pxa_ac97_mutex);
31744 + *codec = &pxa_ac97_codec;
31748 +void pxa_ac97_put(void)
31750 + down(&pxa_ac97_mutex);
31751 + pxa_ac97_refcount--;
31752 + if (!pxa_ac97_refcount) {
31753 + GCR = GCR_ACLINK_OFF;
31754 + CKEN &= ~CKEN2_AC97;
31755 + free_irq(IRQ_AC97, NULL);
31757 + up(&pxa_ac97_mutex);
31760 +EXPORT_SYMBOL(pxa_ac97_get);
31761 +EXPORT_SYMBOL(pxa_ac97_put);
31765 + * Audio Mixer stuff
31768 +static audio_state_t ac97_audio_state;
31769 +static audio_stream_t ac97_audio_in;
31771 +static int mixer_ioctl( struct inode *inode, struct file *file,
31772 + unsigned int cmd, unsigned long arg)
31776 + ret = pxa_ac97_codec.mixer_ioctl(&pxa_ac97_codec, cmd, arg);
31780 + /* We must snoop for some commands to provide our own extra processing */
31782 + case SOUND_MIXER_WRITE_RECSRC:
31784 + * According to the PXA250 spec, mic-in should use different
31785 + * DRCMR and different AC97 FIFO.
31786 + * Unfortunately current UCB1400 versions (up to ver 2A) don't
31787 + * produce slot 6 for the audio input frame, therefore the PXA
31788 + * AC97 mic-in FIFO is always starved.
31791 + ret = get_user(val, (int *)arg);
31794 + pxa_audio_clear_buf(&ac97_audio_in);
31795 + *ac97_audio_in.drcmr = 0;
31796 + if (val & (1 << SOUND_MIXER_MIC)) {
31797 + ac97_audio_in.dcmd = DCMD_RXMCDR;
31798 + ac97_audio_in.drcmr = &DRCMRRXMCDR;
31799 + ac97_audio_in.dev_addr = __PREG(MCDR);
31801 + ac97_audio_in.dcmd = DCMD_RXPCDR;
31802 + ac97_audio_in.drcmr = &DRCMRRXPCDR;
31803 + ac97_audio_in.dev_addr = __PREG(PCDR);
31805 + if (ac97_audio_state.rd_ref)
31806 + *ac97_audio_in.drcmr =
31807 + ac97_audio_in.dma_ch | DRCMR_MAPVLD;
31814 +static struct file_operations mixer_fops = {
31815 + ioctl: mixer_ioctl,
31816 + llseek: no_llseek,
31817 + owner: THIS_MODULE
31821 + * AC97 codec ioctls
31824 +static int codec_adc_rate = 48000;
31825 +static int codec_dac_rate = 48000;
31827 +static int ac97_ioctl(struct inode *inode, struct file *file,
31828 + unsigned int cmd, unsigned long arg)
31834 + case SNDCTL_DSP_STEREO:
31835 + ret = get_user(val, (int *) arg);
31838 + /* FIXME: do we support mono? */
31839 + ret = (val == 0) ? -EINVAL : 1;
31840 + return put_user(ret, (int *) arg);
31842 + case SNDCTL_DSP_CHANNELS:
31843 + case SOUND_PCM_READ_CHANNELS:
31844 + /* FIXME: do we support mono? */
31845 + return put_user(2, (long *) arg);
31847 + case SNDCTL_DSP_SPEED:
31848 + ret = get_user(val, (long *) arg);
31851 + if (file->f_mode & FMODE_READ)
31852 + codec_adc_rate = ac97_set_adc_rate(&pxa_ac97_codec, val);
31853 + if (file->f_mode & FMODE_WRITE)
31854 + codec_dac_rate = ac97_set_dac_rate(&pxa_ac97_codec, val);
31855 + /* fall through */
31857 + case SOUND_PCM_READ_RATE:
31858 + if (file->f_mode & FMODE_READ)
31859 + val = codec_adc_rate;
31860 + if (file->f_mode & FMODE_WRITE)
31861 + val = codec_dac_rate;
31862 + return put_user(val, (long *) arg);
31864 + case SNDCTL_DSP_SETFMT:
31865 + case SNDCTL_DSP_GETFMTS:
31866 + /* FIXME: can we do other fmts? */
31867 + return put_user(AFMT_S16_LE, (long *) arg);
31870 + /* Maybe this is meant for the mixer (As per OSS Docs) */
31871 + return mixer_ioctl(inode, file, cmd, arg);
31881 +static audio_stream_t ac97_audio_out = {
31882 + name: "AC97 audio out",
31883 + dcmd: DCMD_TXPCDR,
31884 + drcmr: &DRCMRTXPCDR,
31885 + dev_addr: __PREG(PCDR),
31888 +static audio_stream_t ac97_audio_in = {
31889 + name: "AC97 audio in",
31890 + dcmd: DCMD_RXPCDR,
31891 + drcmr: &DRCMRRXPCDR,
31892 + dev_addr: __PREG(PCDR),
31895 +static audio_state_t ac97_audio_state = {
31896 + output_stream: &ac97_audio_out,
31897 + input_stream: &ac97_audio_in,
31898 + client_ioctl: ac97_ioctl,
31899 + sem: __MUTEX_INITIALIZER(ac97_audio_state.sem),
31902 +static int ac97_audio_open(struct inode *inode, struct file *file)
31904 + return pxa_audio_attach(inode, file, &ac97_audio_state);
31908 + * Missing fields of this structure will be patched with the call
31909 + * to pxa_audio_attach().
31912 +static struct file_operations ac97_audio_fops = {
31913 + open: ac97_audio_open,
31914 + owner: THIS_MODULE
31918 +static int __init pxa_ac97_init(void)
31921 + struct ac97_codec *dummy;
31923 + ret = pxa_ac97_get(&dummy);
31927 + ac97_audio_state.dev_dsp = register_sound_dsp(&ac97_audio_fops, -1);
31928 + pxa_ac97_codec.dev_mixer = register_sound_mixer(&mixer_fops, -1);
31933 +static void __exit pxa_ac97_exit(void)
31935 + unregister_sound_dsp(ac97_audio_state.dev_dsp);
31936 + unregister_sound_mixer(pxa_ac97_codec.dev_mixer);
31941 +module_init(pxa_ac97_init);
31942 +module_exit(pxa_ac97_exit);
31945 +++ linux-2.4.27/drivers/sound/pxa-audio.c
31948 + * linux/drivers/sound/pxa-audio.c -- audio interface for the Cotula chip
31950 + * Author: Nicolas Pitre
31951 + * Created: Aug 15, 2001
31952 + * Copyright: MontaVista Software Inc.
31954 + * This program is free software; you can redistribute it and/or modify
31955 + * it under the terms of the GNU General Public License version 2 as
31956 + * published by the Free Software Foundation.
31959 +#include <linux/init.h>
31960 +#include <linux/module.h>
31961 +#include <linux/kernel.h>
31962 +#include <linux/slab.h>
31963 +#include <linux/pci.h>
31964 +#include <linux/poll.h>
31965 +#include <linux/sound.h>
31966 +#include <linux/soundcard.h>
31968 +#include <asm/hardware.h>
31969 +#include <asm/irq.h>
31970 +#include <asm/uaccess.h>
31971 +#include <asm/semaphore.h>
31972 +#include <asm/dma.h>
31974 +#include "pxa-audio.h"
31977 +#define AUDIO_NBFRAGS_DEFAULT 8
31978 +#define AUDIO_FRAGSIZE_DEFAULT 8192
31980 +#define MAX_DMA_SIZE 4096
31981 +#define DMA_DESC_SIZE sizeof(pxa_dma_desc)
31985 + * This function frees all buffers
31987 +#define audio_clear_buf pxa_audio_clear_buf
31989 +void pxa_audio_clear_buf(audio_stream_t * s)
31991 + DECLARE_WAITQUEUE(wait, current);
31997 + /* Ensure DMA isn't running */
31998 + set_current_state(TASK_UNINTERRUPTIBLE);
31999 + add_wait_queue(&s->stop_wq, &wait);
32000 + DCSR(s->dma_ch) = DCSR_STOPIRQEN;
32002 + remove_wait_queue(&s->stop_wq, &wait);
32004 + /* free DMA buffers */
32005 + for (frag = 0; frag < s->nbfrags; frag++) {
32006 + audio_buf_t *b = &s->buffers[frag];
32009 + consistent_free(b->data, b->master, b->dma_desc->dsadr);
32012 + /* free descriptor ring */
32013 + if (s->buffers->dma_desc)
32014 + consistent_free(s->buffers->dma_desc,
32015 + s->nbfrags * s->descs_per_frag * DMA_DESC_SIZE,
32016 + s->dma_desc_phys);
32018 + /* free buffer structure array */
32019 + kfree(s->buffers);
32020 + s->buffers = NULL;
32024 + * This function allocates the DMA descriptor array and buffer data space
32025 + * according to the current number of fragments and fragment size.
32027 +static int audio_setup_buf(audio_stream_t * s)
32029 + pxa_dma_desc *dma_desc;
32030 + dma_addr_t dma_desc_phys;
32031 + int nb_desc, frag, i, buf_size = 0;
32032 + char *dma_buf = NULL;
32033 + dma_addr_t dma_buf_phys = 0;
32038 + /* Our buffer structure array */
32039 + s->buffers = kmalloc(sizeof(audio_buf_t) * s->nbfrags, GFP_KERNEL);
32042 + memzero(s->buffers, sizeof(audio_buf_t) * s->nbfrags);
32045 + * Our DMA descriptor array:
32046 + * for Each fragment we have one checkpoint descriptor plus one
32047 + * descriptor per MAX_DMA_SIZE byte data blocks.
32049 + nb_desc = (1 + (s->fragsize + MAX_DMA_SIZE - 1)/MAX_DMA_SIZE) * s->nbfrags;
32050 + dma_desc = consistent_alloc(GFP_KERNEL,
32051 + nb_desc * DMA_DESC_SIZE,
32056 + s->descs_per_frag = nb_desc / s->nbfrags;
32057 + s->buffers->dma_desc = dma_desc;
32058 + s->dma_desc_phys = dma_desc_phys;
32059 + for (i = 0; i < nb_desc - 1; i++)
32060 + dma_desc[i].ddadr = dma_desc_phys + (i + 1) * DMA_DESC_SIZE;
32061 + dma_desc[i].ddadr = dma_desc_phys;
32063 + /* Our actual DMA buffers */
32064 + for (frag = 0; frag < s->nbfrags; frag++) {
32065 + audio_buf_t *b = &s->buffers[frag];
32068 + * Let's allocate non-cached memory for DMA buffers.
32069 + * We try to allocate all memory at once.
32070 + * If this fails (a common reason is memory fragmentation),
32071 + * then we'll try allocating smaller buffers.
32074 + buf_size = (s->nbfrags - frag) * s->fragsize;
32076 + dma_buf = consistent_alloc(GFP_KERNEL,
32081 + buf_size -= s->fragsize;
32082 + } while (!dma_buf && buf_size);
32085 + b->master = buf_size;
32086 + memzero(dma_buf, buf_size);
32090 + * Set up our checkpoint descriptor. Since the count
32091 + * is always zero, we'll abuse the dsadr and dtadr fields
32092 + * just in case this one is picked up by the hardware
32093 + * while processing SOUND_DSP_GETPTR.
32095 + dma_desc->dsadr = dma_buf_phys;
32096 + dma_desc->dtadr = dma_buf_phys;
32097 + dma_desc->dcmd = DCMD_ENDIRQEN;
32098 + if (s->output && !s->mapped)
32099 + dma_desc->ddadr |= DDADR_STOP;
32100 + b->dma_desc = dma_desc++;
32102 + /* set up the actual data descriptors */
32103 + for (i = 0; (i * MAX_DMA_SIZE) < s->fragsize; i++) {
32104 + dma_desc[i].dsadr = (s->output) ?
32105 + (dma_buf_phys + i*MAX_DMA_SIZE) : s->dev_addr;
32106 + dma_desc[i].dtadr = (s->output) ?
32107 + s->dev_addr : (dma_buf_phys + i*MAX_DMA_SIZE);
32108 + dma_desc[i].dcmd = s->dcmd |
32109 + ((s->fragsize < MAX_DMA_SIZE) ?
32110 + s->fragsize : MAX_DMA_SIZE);
32114 + /* handle buffer pointers */
32115 + b->data = dma_buf;
32116 + dma_buf += s->fragsize;
32117 + dma_buf_phys += s->fragsize;
32118 + buf_size -= s->fragsize;
32121 + s->usr_frag = s->dma_frag = 0;
32122 + s->bytecount = 0;
32123 + s->fragcount = 0;
32124 + sema_init(&s->sem, (s->output) ? s->nbfrags : 0);
32128 + printk("pxa-audio: unable to allocate audio memory\n ");
32129 + audio_clear_buf(s);
32134 + * Our DMA interrupt handler
32136 +static void audio_dma_irq(int ch, void *dev_id, struct pt_regs *regs)
32138 + audio_stream_t *s = dev_id;
32142 + DCSR(ch) = dcsr & ~DCSR_STOPIRQEN;
32144 + if (!s->buffers) {
32145 + printk("AC97 DMA: wow... received IRQ for channel %d but no buffer exists\n", ch);
32149 + if (dcsr & DCSR_BUSERR)
32150 + printk("AC97 DMA: bus error interrupt on channel %d\n", ch);
32152 + if (dcsr & DCSR_ENDINTR) {
32153 + u_long cur_dma_desc;
32154 + u_int cur_dma_frag;
32157 + * Find out which DMA desc is current. Note that DDADR
32158 + * points to the next desc, not the current one.
32160 + cur_dma_desc = DDADR(ch) - s->dma_desc_phys - DMA_DESC_SIZE;
32163 + * Let the compiler nicely optimize constant divisors into
32164 + * multiplications for the common cases which is much faster.
32165 + * Common cases: x = 1 + (1 << y) for y = [0..3]
32167 + switch (s->descs_per_frag) {
32168 + case 2: cur_dma_frag = cur_dma_desc / (2*DMA_DESC_SIZE); break;
32169 + case 3: cur_dma_frag = cur_dma_desc / (3*DMA_DESC_SIZE); break;
32170 + case 5: cur_dma_frag = cur_dma_desc / (5*DMA_DESC_SIZE); break;
32171 + case 9: cur_dma_frag = cur_dma_desc / (9*DMA_DESC_SIZE); break;
32172 + default: cur_dma_frag =
32173 + cur_dma_desc / (s->descs_per_frag * DMA_DESC_SIZE);
32176 + /* Account for possible wrap back of cur_dma_desc above */
32177 + if (cur_dma_frag >= s->nbfrags)
32178 + cur_dma_frag = s->nbfrags - 1;
32180 + while (s->dma_frag != cur_dma_frag) {
32181 + if (!s->mapped) {
32183 + * This fragment is done - set the checkpoint
32184 + * descriptor to STOP until it is gets
32185 + * processed by the read or write function.
32187 + s->buffers[s->dma_frag].dma_desc->ddadr |= DDADR_STOP;
32190 + if (++s->dma_frag >= s->nbfrags)
32194 + s->bytecount += s->fragsize;
32198 + /* ... and for polling processes */
32199 + wake_up(&s->frag_wq);
32202 + if ((dcsr & DCSR_STOPIRQEN) && (dcsr & DCSR_STOPSTATE))
32203 + wake_up(&s->stop_wq);
32207 + * Validate and sets up buffer fragments, etc.
32209 +static int audio_set_fragments(audio_stream_t *s, int val)
32211 + if (s->mapped || DCSR(s->dma_ch) & DCSR_RUN)
32214 + audio_clear_buf(s);
32215 + s->nbfrags = (val >> 16) & 0x7FFF;
32221 + s->fragsize = 1 << val;
32222 + if (s->nbfrags < 2)
32224 + if (s->nbfrags * s->fragsize > 256 * 1024)
32225 + s->nbfrags = 256 * 1024 / s->fragsize;
32226 + if (audio_setup_buf(s))
32228 + return val|(s->nbfrags << 16);
32233 + * The fops functions
32236 +static int audio_write(struct file *file, const char *buffer,
32237 + size_t count, loff_t * ppos)
32239 + const char *buffer0 = buffer;
32240 + audio_state_t *state = (audio_state_t *)file->private_data;
32241 + audio_stream_t *s = state->output_stream;
32242 + int chunksize, ret = 0;
32244 + if (ppos != &file->f_pos)
32248 + if (!s->buffers && audio_setup_buf(s))
32251 + while (count > 0) {
32252 + audio_buf_t *b = &s->buffers[s->usr_frag];
32254 + /* Grab a fragment */
32255 + if (file->f_flags & O_NONBLOCK) {
32257 + if (down_trylock(&s->sem))
32260 + ret = -ERESTARTSYS;
32261 + if (down_interruptible(&s->sem))
32265 + /* Feed the current buffer */
32266 + chunksize = s->fragsize - b->offset;
32267 + if (chunksize > count)
32268 + chunksize = count;
32269 + if (copy_from_user(b->data + b->offset, buffer, chunksize)) {
32273 + b->offset += chunksize;
32274 + buffer += chunksize;
32275 + count -= chunksize;
32276 + if (b->offset < s->fragsize) {
32282 + * Activate DMA on current buffer.
32283 + * We unlock this fragment's checkpoint descriptor and
32284 + * kick DMA if it is idle. Using checkpoint descriptors
32285 + * allows for control operations without the need for
32286 + * stopping the DMA channel if it is already running.
32289 + b->dma_desc->ddadr &= ~DDADR_STOP;
32290 + if (DCSR(s->dma_ch) & DCSR_STOPSTATE) {
32291 + DDADR(s->dma_ch) = b->dma_desc->ddadr;
32292 + DCSR(s->dma_ch) = DCSR_RUN;
32295 + /* move the index to the next fragment */
32296 + if (++s->usr_frag >= s->nbfrags)
32300 + if ((buffer - buffer0))
32301 + ret = buffer - buffer0;
32306 +static int audio_read(struct file *file, char *buffer,
32307 + size_t count, loff_t * ppos)
32309 + char *buffer0 = buffer;
32310 + audio_state_t *state = file->private_data;
32311 + audio_stream_t *s = state->input_stream;
32312 + int chunksize, ret = 0;
32314 + if (ppos != &file->f_pos)
32318 + if (!s->buffers && audio_setup_buf(s))
32321 + while (count > 0) {
32322 + audio_buf_t *b = &s->buffers[s->usr_frag];
32325 + if (DCSR(s->dma_ch) & DCSR_STOPSTATE) {
32326 + DDADR(s->dma_ch) =
32327 + s->buffers[s->dma_frag].dma_desc->ddadr;
32328 + DCSR(s->dma_ch) = DCSR_RUN;
32331 + /* Wait for a buffer to become full */
32332 + if (file->f_flags & O_NONBLOCK) {
32334 + if (down_trylock(&s->sem))
32337 + ret = -ERESTARTSYS;
32338 + if (down_interruptible(&s->sem))
32342 + /* Grab data from current buffer */
32343 + chunksize = s->fragsize - b->offset;
32344 + if (chunksize > count)
32345 + chunksize = count;
32346 + if (copy_to_user(buffer, b->data + b->offset, chunksize)) {
32350 + b->offset += chunksize;
32351 + buffer += chunksize;
32352 + count -= chunksize;
32353 + if (b->offset < s->fragsize) {
32359 + * Make this buffer available for DMA again.
32360 + * We unlock this fragment's checkpoint descriptor and
32361 + * kick DMA if it is idle. Using checkpoint descriptors
32362 + * allows for control operations without the need for
32363 + * stopping the DMA channel if it is already running.
32366 + b->dma_desc->ddadr &= ~DDADR_STOP;
32368 + /* move the index to the next fragment */
32369 + if (++s->usr_frag >= s->nbfrags)
32373 + if ((buffer - buffer0))
32374 + ret = buffer - buffer0;
32379 +static int audio_sync(struct file *file)
32381 + audio_state_t *state = file->private_data;
32382 + audio_stream_t *s = state->output_stream;
32384 + pxa_dma_desc *final_desc;
32385 + u_long dcmd_save = 0;
32386 + DECLARE_WAITQUEUE(wait, current);
32388 + if (!(file->f_mode & FMODE_WRITE) || !s->buffers || s->mapped)
32392 + * Send current buffer if it contains data. Be sure to send
32393 + * a full sample count.
32395 + final_desc = NULL;
32396 + b = &s->buffers[s->usr_frag];
32397 + if (b->offset &= ~3) {
32398 + final_desc = &b->dma_desc[1 + b->offset/MAX_DMA_SIZE];
32399 + b->offset &= (MAX_DMA_SIZE-1);
32400 + dcmd_save = final_desc->dcmd;
32401 + final_desc->dcmd = b->offset | s->dcmd | DCMD_ENDIRQEN;
32402 + final_desc->ddadr |= DDADR_STOP;
32404 + b->dma_desc->ddadr &= ~DDADR_STOP;
32405 + if (DCSR(s->dma_ch) & DCSR_STOPSTATE) {
32406 + DDADR(s->dma_ch) = b->dma_desc->ddadr;
32407 + DCSR(s->dma_ch) = DCSR_RUN;
32411 + /* Wait for DMA to complete. */
32412 + set_current_state(TASK_INTERRUPTIBLE);
32415 + * The STOPSTATE IRQ never seem to occur if DCSR_STOPIRQEN is set
32416 + * along wotj DCSR_RUN. Silicon bug?
32418 + add_wait_queue(&s->stop_wq, &wait);
32419 + DCSR(s->dma_ch) |= DCSR_STOPIRQEN;
32422 + add_wait_queue(&s->frag_wq, &wait);
32423 + while ((DCSR(s->dma_ch) & DCSR_RUN) && !signal_pending(current)) {
32425 + set_current_state(TASK_INTERRUPTIBLE);
32428 + set_current_state(TASK_RUNNING);
32429 + remove_wait_queue(&s->frag_wq, &wait);
32431 + /* Restore the descriptor chain. */
32432 + if (final_desc) {
32433 + final_desc->dcmd = dcmd_save;
32434 + final_desc->ddadr &= ~DDADR_STOP;
32435 + b->dma_desc->ddadr |= DDADR_STOP;
32441 +static unsigned int audio_poll(struct file *file,
32442 + struct poll_table_struct *wait)
32444 + audio_state_t *state = file->private_data;
32445 + audio_stream_t *is = state->input_stream;
32446 + audio_stream_t *os = state->output_stream;
32447 + unsigned int mask = 0;
32449 + if (file->f_mode & FMODE_READ) {
32450 + /* Start audio input if not already active */
32451 + if (!is->buffers && audio_setup_buf(is))
32453 + if (DCSR(is->dma_ch) & DCSR_STOPSTATE) {
32454 + DDADR(is->dma_ch) =
32455 + is->buffers[is->dma_frag].dma_desc->ddadr;
32456 + DCSR(is->dma_ch) = DCSR_RUN;
32458 + poll_wait(file, &is->frag_wq, wait);
32461 + if (file->f_mode & FMODE_WRITE) {
32462 + if (!os->buffers && audio_setup_buf(os))
32464 + poll_wait(file, &os->frag_wq, wait);
32467 + if (file->f_mode & FMODE_READ)
32468 + if (( is->mapped && is->bytecount > 0) ||
32469 + (!is->mapped && atomic_read(&is->sem.count) > 0))
32470 + mask |= POLLIN | POLLRDNORM;
32472 + if (file->f_mode & FMODE_WRITE)
32473 + if (( os->mapped && os->bytecount > 0) ||
32474 + (!os->mapped && atomic_read(&os->sem.count) > 0))
32475 + mask |= POLLOUT | POLLWRNORM;
32481 +static int audio_ioctl( struct inode *inode, struct file *file,
32482 + uint cmd, ulong arg)
32484 + audio_state_t *state = file->private_data;
32485 + audio_stream_t *os = state->output_stream;
32486 + audio_stream_t *is = state->input_stream;
32490 + case OSS_GETVERSION:
32491 + return put_user(SOUND_VERSION, (int *)arg);
32493 + case SNDCTL_DSP_GETBLKSIZE:
32494 + if (file->f_mode & FMODE_WRITE)
32495 + return put_user(os->fragsize, (int *)arg);
32497 + return put_user(is->fragsize, (int *)arg);
32499 + case SNDCTL_DSP_GETCAPS:
32500 + val = DSP_CAP_REALTIME|DSP_CAP_TRIGGER|DSP_CAP_MMAP;
32502 + val |= DSP_CAP_DUPLEX;
32503 + return put_user(val, (int *)arg);
32505 + case SNDCTL_DSP_SETFRAGMENT:
32506 + if (get_user(val, (long *) arg))
32508 + if (file->f_mode & FMODE_READ) {
32509 + int ret = audio_set_fragments(is, val);
32512 + ret = put_user(ret, (int *)arg);
32516 + if (file->f_mode & FMODE_WRITE) {
32517 + int ret = audio_set_fragments(os, val);
32520 + ret = put_user(ret, (int *)arg);
32526 + case SNDCTL_DSP_SYNC:
32527 + return audio_sync(file);
32529 + case SNDCTL_DSP_SETDUPLEX:
32532 + case SNDCTL_DSP_POST:
32535 + case SNDCTL_DSP_GETTRIGGER:
32537 + if (file->f_mode & FMODE_READ && DCSR(is->dma_ch) & DCSR_RUN)
32538 + val |= PCM_ENABLE_INPUT;
32539 + if (file->f_mode & FMODE_WRITE && DCSR(os->dma_ch) & DCSR_RUN)
32540 + val |= PCM_ENABLE_OUTPUT;
32541 + return put_user(val, (int *)arg);
32543 + case SNDCTL_DSP_SETTRIGGER:
32544 + if (get_user(val, (int *)arg))
32546 + if (file->f_mode & FMODE_READ) {
32547 + if (val & PCM_ENABLE_INPUT) {
32548 + if (!is->buffers && audio_setup_buf(is))
32550 + if (!(DCSR(is->dma_ch) & DCSR_RUN)) {
32551 + audio_buf_t *b = &is->buffers[is->dma_frag];
32552 + DDADR(is->dma_ch) = b->dma_desc->ddadr;
32553 + DCSR(is->dma_ch) = DCSR_RUN;
32556 + DCSR(is->dma_ch) = 0;
32559 + if (file->f_mode & FMODE_WRITE) {
32560 + if (val & PCM_ENABLE_OUTPUT) {
32561 + if (!os->buffers && audio_setup_buf(os))
32563 + if (!(DCSR(os->dma_ch) & DCSR_RUN)) {
32564 + audio_buf_t *b = &os->buffers[os->dma_frag];
32565 + DDADR(os->dma_ch) = b->dma_desc->ddadr;
32566 + DCSR(os->dma_ch) = DCSR_RUN;
32569 + DCSR(os->dma_ch) = 0;
32574 + case SNDCTL_DSP_GETOSPACE:
32575 + case SNDCTL_DSP_GETISPACE:
32577 + audio_buf_info inf = { 0, };
32578 + audio_stream_t *s = (cmd == SNDCTL_DSP_GETOSPACE) ? os : is;
32580 + if ((s == is && !(file->f_mode & FMODE_READ)) ||
32581 + (s == os && !(file->f_mode & FMODE_WRITE)))
32583 + if (!s->buffers && audio_setup_buf(s))
32585 + inf.bytes = atomic_read(&s->sem.count) * s->fragsize;
32586 + inf.bytes -= s->buffers[s->usr_frag].offset;
32587 + inf.fragments = inf.bytes / s->fragsize;
32588 + inf.fragsize = s->fragsize;
32589 + inf.fragstotal = s->nbfrags;
32590 + return copy_to_user((void *)arg, &inf, sizeof(inf));
32593 + case SNDCTL_DSP_GETOPTR:
32594 + case SNDCTL_DSP_GETIPTR:
32596 + count_info inf = { 0, };
32597 + audio_stream_t *s = (cmd == SNDCTL_DSP_GETOPTR) ? os : is;
32599 + int bytecount, offset, flags;
32601 + if ((s == is && !(file->f_mode & FMODE_READ)) ||
32602 + (s == os && !(file->f_mode & FMODE_WRITE)))
32604 + if (DCSR(s->dma_ch) & DCSR_RUN) {
32606 + save_flags_cli(flags);
32607 + ptr = (s->output) ? DSADR(s->dma_ch) : DTADR(s->dma_ch);
32608 + b = &s->buffers[s->dma_frag];
32609 + offset = ptr - b->dma_desc->dsadr;
32610 + if (offset >= s->fragsize)
32611 + offset = s->fragsize - 4;
32613 + save_flags(flags);
32616 + inf.ptr = s->dma_frag * s->fragsize + offset;
32617 + bytecount = s->bytecount + offset;
32618 + s->bytecount = -offset;
32619 + inf.blocks = s->fragcount;
32620 + s->fragcount = 0;
32621 + restore_flags(flags);
32622 + if (bytecount < 0)
32624 + inf.bytes = bytecount;
32625 + return copy_to_user((void *)arg, &inf, sizeof(inf));
32628 + case SNDCTL_DSP_NONBLOCK:
32629 + file->f_flags |= O_NONBLOCK;
32632 + case SNDCTL_DSP_RESET:
32633 + if (file->f_mode & FMODE_WRITE)
32634 + audio_clear_buf(os);
32635 + if (file->f_mode & FMODE_READ)
32636 + audio_clear_buf(is);
32640 + return state->client_ioctl(inode, file, cmd, arg);
32647 +static int audio_mmap(struct file *file, struct vm_area_struct *vma)
32649 + audio_state_t *state = file->private_data;
32650 + audio_stream_t *s;
32651 + unsigned long size, vma_addr;
32654 + if (vma->vm_pgoff != 0)
32657 + if (vma->vm_flags & VM_WRITE) {
32658 + if (!state->wr_ref)
32660 + s = state->output_stream;
32661 + } else if (vma->vm_flags & VM_READ) {
32662 + if (!state->rd_ref)
32664 + s = state->input_stream;
32665 + } else return -EINVAL;
32669 + size = vma->vm_end - vma->vm_start;
32670 + if (size != s->fragsize * s->nbfrags)
32672 + if (!s->buffers && audio_setup_buf(s))
32674 + vma_addr = vma->vm_start;
32675 + for (i = 0; i < s->nbfrags; i++) {
32676 + audio_buf_t *buf = &s->buffers[i];
32677 + if (!buf->master)
32679 + ret = remap_page_range(vma_addr, buf->dma_desc->dsadr,
32680 + buf->master, vma->vm_page_prot);
32683 + vma_addr += buf->master;
32685 + for (i = 0; i < s->nbfrags; i++)
32686 + s->buffers[i].dma_desc->ddadr &= ~DDADR_STOP;
32692 +static int audio_release(struct inode *inode, struct file *file)
32694 + audio_state_t *state = file->private_data;
32696 + down(&state->sem);
32698 + if (file->f_mode & FMODE_READ) {
32699 + audio_clear_buf(state->input_stream);
32700 + *state->input_stream->drcmr = 0;
32701 + pxa_free_dma(state->input_stream->dma_ch);
32702 + state->rd_ref = 0;
32705 + if (file->f_mode & FMODE_WRITE) {
32706 + audio_sync(file);
32707 + audio_clear_buf(state->output_stream);
32708 + *state->output_stream->drcmr = 0;
32709 + pxa_free_dma(state->output_stream->dma_ch);
32710 + state->wr_ref = 0;
32718 +int pxa_audio_attach(struct inode *inode, struct file *file,
32719 + audio_state_t *state)
32721 + audio_stream_t *is = state->input_stream;
32722 + audio_stream_t *os = state->output_stream;
32725 + down(&state->sem);
32727 + /* access control */
32729 + if ((file->f_mode & FMODE_WRITE) && !os)
32731 + if ((file->f_mode & FMODE_READ) && !is)
32734 + if ((file->f_mode & FMODE_WRITE) && state->wr_ref)
32736 + if ((file->f_mode & FMODE_READ) && state->rd_ref)
32739 + /* request DMA channels */
32740 + if (file->f_mode & FMODE_WRITE) {
32741 + err = pxa_request_dma(os->name, DMA_PRIO_LOW,
32742 + audio_dma_irq, os);
32745 + os->dma_ch = err;
32747 + if (file->f_mode & FMODE_READ) {
32748 + err = pxa_request_dma(is->name, DMA_PRIO_LOW,
32749 + audio_dma_irq, is);
32751 + if (file->f_mode & FMODE_WRITE) {
32753 + pxa_free_dma(os->dma_ch);
32757 + is->dma_ch = err;
32760 + file->private_data = state;
32761 + file->f_op->release = audio_release;
32762 + file->f_op->write = audio_write;
32763 + file->f_op->read = audio_read;
32764 + file->f_op->mmap = audio_mmap;
32765 + file->f_op->poll = audio_poll;
32766 + file->f_op->ioctl = audio_ioctl;
32767 + file->f_op->llseek = no_llseek;
32769 + if ((file->f_mode & FMODE_WRITE)) {
32770 + state->wr_ref = 1;
32771 + os->fragsize = AUDIO_FRAGSIZE_DEFAULT;
32772 + os->nbfrags = AUDIO_NBFRAGS_DEFAULT;
32775 + init_waitqueue_head(&os->frag_wq);
32776 + init_waitqueue_head(&os->stop_wq);
32777 + *os->drcmr = os->dma_ch | DRCMR_MAPVLD;
32779 + if (file->f_mode & FMODE_READ) {
32780 + state->rd_ref = 1;
32781 + is->fragsize = AUDIO_FRAGSIZE_DEFAULT;
32782 + is->nbfrags = AUDIO_NBFRAGS_DEFAULT;
32785 + init_waitqueue_head(&is->frag_wq);
32786 + init_waitqueue_head(&is->stop_wq);
32787 + *is->drcmr = is->dma_ch | DRCMR_MAPVLD;
32797 +EXPORT_SYMBOL(pxa_audio_attach);
32798 +EXPORT_SYMBOL(pxa_audio_clear_buf);
32801 +++ linux-2.4.27/drivers/sound/pxa-audio.h
32804 + * linux/drivers/sound/pxa-audio.h -- audio interface for the Cotula chip
32806 + * Author: Nicolas Pitre
32807 + * Created: Aug 15, 2001
32808 + * Copyright: MontaVista Software Inc.
32810 + * This program is free software; you can redistribute it and/or modify
32811 + * it under the terms of the GNU General Public License version 2 as
32812 + * published by the Free Software Foundation.
32816 + int offset; /* current buffer position */
32817 + char *data; /* actual buffer */
32818 + pxa_dma_desc *dma_desc; /* pointer to the starting desc */
32819 + int master; /* owner for buffer allocation, contain size whn true */
32823 + char *name; /* stream identifier */
32824 + audio_buf_t *buffers; /* pointer to audio buffer array */
32825 + u_int usr_frag; /* user fragment index */
32826 + u_int dma_frag; /* DMA fragment index */
32827 + u_int fragsize; /* fragment size */
32828 + u_int nbfrags; /* number of fragments */
32829 + u_int dma_ch; /* DMA channel number */
32830 + dma_addr_t dma_desc_phys; /* phys addr of descriptor ring */
32831 + u_int descs_per_frag; /* nbr descriptors per fragment */
32832 + int bytecount; /* nbr of processed bytes */
32833 + int fragcount; /* nbr of fragment transitions */
32834 + struct semaphore sem; /* account for fragment usage */
32835 + wait_queue_head_t frag_wq; /* for poll(), etc. */
32836 + wait_queue_head_t stop_wq; /* for users of DCSR_STOPIRQEN */
32837 + u_long dcmd; /* DMA descriptor dcmd field */
32838 + volatile u32 *drcmr; /* the DMA request channel to use */
32839 + u_long dev_addr; /* device physical address for DMA */
32840 + int mapped:1; /* mmap()'ed buffers */
32841 + int output:1; /* 0 for input, 1 for output */
32845 + audio_stream_t *output_stream;
32846 + audio_stream_t *input_stream;
32847 + int dev_dsp; /* audio device handle */
32848 + int rd_ref:1; /* open reference for recording */
32849 + int wr_ref:1; /* open reference for playback */
32850 + int (*client_ioctl)(struct inode *, struct file *, uint, ulong);
32851 + struct semaphore sem; /* prevent races in attach/release */
32854 +extern int pxa_audio_attach(struct inode *inode, struct file *file,
32855 + audio_state_t *state);
32856 +extern void pxa_audio_clear_buf(audio_stream_t *s);
32858 --- linux-2.4.27/drivers/sound/sa1100-audio.c~2.4.27-vrs1-pxa1
32859 +++ linux-2.4.27/drivers/sound/sa1100-audio.c
32860 @@ -148,7 +148,8 @@
32862 dmabuf = consistent_alloc(GFP_KERNEL|GFP_DMA,
32868 dmasize -= s->fragsize;
32869 } while (!dmabuf && dmasize);
32870 --- linux-2.4.27/drivers/video/Config.in~2.4.27-vrs1-pxa1
32871 +++ linux-2.4.27/drivers/video/Config.in
32873 if [ "$CONFIG_FB_SA1100" = "y" -a "$CONFIG_SA1100_CERF_CPLD" = "y" ]; then
32874 bool 'Cerfboard Backlight (CerfPDA)' CONFIG_SA1100_CERF_LCD_BACKLIGHT
32876 + tristate ' PXA LCD support' CONFIG_FB_PXA $CONFIG_ARCH_PXA
32877 + if [ "$CONFIG_FB_PXA" != "n" ]; then
32878 + choice 'LCD Bit Depth' \
32879 + "8-Bpp CONFIG_FB_PXA_8BPP \
32880 + 16-Bpp CONFIG_FB_PXA_16BPP" Bit-Depth
32882 + if [ "$CONFIG_FB_PXA" != "n" -a "$CONFIG_ARCH_LUBBOCK" = "y" ]; then
32883 + bool ' Lubbock QVGA LCD support instead of DSTN' CONFIG_FB_PXA_QVGA
32886 dep_tristate ' CyberPro 2000/2010/5000 support' CONFIG_FB_CYBER2000 $CONFIG_PCI
32887 if [ "$CONFIG_APOLLO" = "y" ]; then
32888 @@ -295,7 +304,7 @@
32889 if [ "$CONFIG_FB_ACORN" = "y" -o "$CONFIG_FB_MAC" = "y" -o \
32890 "$CONFIG_FB_SA1100" = "y" -o "$CONFIG_FB_VIRTUAL" = "y" -o \
32891 "$CONFIG_FB_TX3912" = "y" -o "$CONFIG_FB_CLPS711X" = "y" -o \
32892 - "$CONFIG_FB_DBMX1" = "y" ]; then
32893 + "$CONFIG_FB_DBMX1" = "y" -o "$CONFIG_FB_PXA" = "y" ]; then
32894 define_tristate CONFIG_FBCON_CFB2 y
32895 define_tristate CONFIG_FBCON_CFB4 y
32897 @@ -329,7 +338,7 @@
32898 "$CONFIG_FB_SIS" = "y" -o "$CONFIG_FB_NEOMAGIC" = "y" -o \
32899 "$CONFIG_FB_STI" = "y" -o "$CONFIG_FB_HP300" = "y" -o \
32900 "$CONFIG_FB_INTEL" = "y" -o \
32901 - "$CONFIG_FB_DBMX1" = "y" ]; then
32902 + "$CONFIG_FB_DBMX1" = "y" -o "$CONFIG_FB_PXA" = "y" ]; then
32903 define_tristate CONFIG_FBCON_CFB8 y
32905 if [ "$CONFIG_FB_ACORN" = "m" -o "$CONFIG_FB_ATARI" = "m" -o \
32906 @@ -372,7 +381,7 @@
32907 "$CONFIG_FB_SIS" = "y" -o "$CONFIG_FB_SA1100" = "y" -o \
32908 "$CONFIG_FB_PVR2" = "y" -o "$CONFIG_FB_VOODOO1" = "y" -o \
32909 "$CONFIG_FB_NEOMAGIC" = "y" -o "$CONFIG_FB_INTEL" = "y" -o \
32910 - "$CONFIG_FB_ANAKIN" = "y" -o \
32911 + "$CONFIG_FB_ANAKIN" = "y" -o "$CONFIG_FB_PXA" = "y" -o \
32912 "$CONFIG_FB_DBMX1" = "y" ]; then
32913 define_tristate CONFIG_FBCON_CFB16 y
32915 --- linux-2.4.27/drivers/video/Makefile~2.4.27-vrs1-pxa1
32916 +++ linux-2.4.27/drivers/video/Makefile
32918 fbcon-vga.o fbcon-iplan2p2.o fbcon-iplan2p4.o \
32919 fbcon-iplan2p8.o fbcon-vga-planes.o fbcon-cfb16.o \
32920 fbcon-cfb2.o fbcon-cfb24.o fbcon-cfb32.o fbcon-cfb4.o \
32921 - fbcon-cfb8.o fbcon-mac.o fbcon-mfb.o \
32922 + fbcon-cfb8.o fbcon-mac.o fbcon-mfb.o pxafb.o \
32923 cyber2000fb.o sa1100fb.o fbcon-hga.o fbgen.o
32925 # Each configuration option enables a list of files.
32926 @@ -129,6 +129,10 @@
32927 obj-$(CONFIG_FB_BWTWO) += bwtwofb.o
32928 obj-$(CONFIG_FB_HGA) += hgafb.o
32929 obj-$(CONFIG_FB_SA1100) += sa1100fb.o
32930 +obj-$(CONFIG_FB_PXA) += pxafb.o
32931 +ifeq ($(CONFIG_PXA_CERF_PDA),y)
32932 + obj-$(CONFIG_FB_PXA) += lcdctrl.o lcdctrl_cerf.o
32934 obj-$(CONFIG_FB_DBMX1) += dbmx1fb.o
32935 obj-$(CONFIG_FB_VIRTUAL) += vfb.o
32936 obj-$(CONFIG_FB_HIT) += hitfb.o fbgen.o
32937 --- linux-2.4.27/drivers/video/fbmem.c~2.4.27-vrs1-pxa1
32938 +++ linux-2.4.27/drivers/video/fbmem.c
32939 @@ -109,6 +109,7 @@
32940 extern int chips_init(void);
32941 extern int g364fb_init(void);
32942 extern int sa1100fb_init(void);
32943 +extern int pxafb_init(void);
32944 extern int fm2fb_init(void);
32945 extern int fm2fb_setup(char*);
32946 extern int q40fb_init(void);
32947 @@ -305,6 +306,9 @@
32948 #ifdef CONFIG_FB_SA1100
32949 { "sa1100", sa1100fb_init, NULL },
32951 +#ifdef CONFIG_FB_PXA
32952 + { "pxa", pxafb_init, NULL },
32954 #ifdef CONFIG_FB_SUN3
32955 { "sun3", sun3fb_init, sun3fb_setup },
32957 @@ -677,13 +681,13 @@
32958 #elif defined(__i386__) || defined(__x86_64__)
32959 if (boot_cpu_data.x86 > 3)
32960 pgprot_val(vma->vm_page_prot) |= _PAGE_PCD;
32961 -#elif defined(__arm__) || defined(__mips__)
32962 +#elif defined(__mips__)
32963 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
32964 #elif defined(__sh__)
32965 pgprot_val(vma->vm_page_prot) &= ~_PAGE_CACHABLE;
32966 #elif defined(__hppa__)
32967 pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE;
32968 -#elif defined(__ia64__)
32969 +#elif defined(__ia64__) || defined(__arm__)
32970 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
32971 #elif defined(__hppa__)
32972 pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE;
32974 +++ linux-2.4.27/drivers/video/lcdctrl.c
32979 + * Generic LCD control for brightness, contrast, etc.
32980 + * Device specific drivers implement a lcdctrl_device and
32981 + * provides access to it via lcdctrl_device_get_ops().
32983 + * Copyright (C) 2002 Intrinsyc Software Inc.
32985 + * This program is free software; you can redistribute it and/or modify
32986 + * it under the terms of the GNU General Public License version 2 as
32987 + * published by the Free Software Foundation.
32990 + * Mar 2002: Initial version [FB]
32994 +#include <linux/config.h>
32995 +#include <linux/module.h>
32996 +#include <linux/kernel.h>
32997 +#include <linux/sched.h>
32998 +#include <linux/errno.h>
32999 +#include <linux/string.h>
33000 +#include <linux/ctype.h>
33001 +#include <linux/mm.h>
33002 +#include <linux/init.h>
33003 +#include <linux/delay.h>
33005 +#include <asm/system.h>
33006 +#include <asm/hardware.h>
33007 +#include <asm/io.h>
33008 +#include <asm/irq.h>
33009 +#include <asm/uaccess.h>
33011 +#include <video/lcdctrl.h>
33014 + * Set this to zero to remove all the debug statements via
33015 + * dead code elimination.
33017 +#define DEBUGGING 0
33020 +static unsigned int lcd_debug = DEBUGGING;
33022 +#define lcd_debug 0
33025 +/* -- prototypes -- */
33027 +static int lcdctrl_ioctl(struct inode * inode, struct file *filp,
33028 + unsigned int cmd , unsigned long arg);
33029 +static int lcdctrl_open(struct inode *inode, struct file *filp);
33030 +static int lcdctrl_close(struct inode *inode, struct file *filp);
33032 +/* -- variables -- */
33034 +struct lcdctrl_device *lcd_device;
33036 +static int intensity;
33037 +static int brightness;
33038 +static int contrast;
33040 +static int enabled;
33041 +static int sync_needed;
33042 +static int chrdev_major;
33044 +static struct file_operations lcdctrl_fops = {
33045 + ioctl: lcdctrl_ioctl,
33046 + open: lcdctrl_open,
33047 + release: lcdctrl_close
33052 +static int lcdctrl_ioctl(struct inode * inode, struct file *filp,
33053 + unsigned int cmd , unsigned long arg)
33059 + printk(KERN_INFO "lcdctrl_ioctl: cmd=%d, arg=%ld\n", cmd, arg);
33063 + case _LCDCTRL_IOCTL_ON:
33064 + ret = lcdctrl_enable();
33066 + case _LCDCTRL_IOCTL_OFF:
33067 + ret = lcdctrl_disable();
33069 + case _LCDCTRL_IOCTL_INTENSITY:
33070 + if ((arg >=0) && (arg <= 100))
33071 + ret = lcdctrl_set_intensity(arg);
33073 + case _LCDCTRL_IOCTL_BRIGHTNESS:
33074 + if ((arg >=0) && (arg <= 100))
33075 + ret = lcdctrl_set_brightness(arg);
33077 + case _LCDCTRL_IOCTL_CONTRAST:
33078 + if ((arg >=0) && (arg <= 100))
33079 + ret = lcdctrl_set_contrast(arg, LCD_NO_SYNC);
33081 + case _LCDCTRL_IOCTL_GET_BRIGHTNESS:
33082 + ret = brightness;
33084 + case _LCDCTRL_IOCTL_GET_CONTRAST:
33087 + case _LCDCTRL_IOCTL_GET_INTENSITY:
33092 + printk(KERN_ERR "lcdctrl_ioctl: invalid ioctl\n");
33099 +static int lcdctrl_open(struct inode *inode, struct file *filp)
33101 +// MOD_INC_USE_COUNT;
33105 +static int lcdctrl_close(struct inode *inode, struct file *filp)
33107 +// MOD_DEC_USE_COUNT;
33113 +int lcdctrl_enable( void)
33117 + if( enabled) return 0;
33119 + result = lcd_device->enable();
33121 + lcdctrl_set_intensity( intensity);
33122 + lcdctrl_set_brightness( brightness);
33123 + lcdctrl_set_contrast( contrast, sync_needed);
33124 + sync_needed = LCD_NO_SYNC;
33130 +int lcdctrl_disable( void)
33133 + return lcd_device->disable();
33136 +int lcdctrl_set_intensity( int i)
33139 + return lcd_device->set_intensity( i);
33142 +int lcdctrl_set_brightness( int b)
33145 + return lcd_device->set_brightness( b);
33148 +int lcdctrl_set_contrast( int c, int sync)
33151 + return lcd_device->set_contrast( c, sync);
33154 +int lcdctrl_get_intensity( void)
33156 + return intensity;
33159 +int lcdctrl_get_brightness( void)
33161 + return brightness;
33164 +int lcdctrl_get_contrast( void)
33171 +/* the device specific driver should implement this */
33172 +struct lcdctrl_device *lcdctrl_device_get_ops(void);
33174 +int lcdctrl_init( void)
33178 + lcd_device = lcdctrl_device_get_ops();
33182 + printk(KERN_ERR "lcdctrl_init: No lcd_device registered.\n");
33186 + ret = lcd_device->init( &intensity, &brightness, &contrast);
33188 + sync_needed = LCD_SYNC_NEEDED;
33193 + register_chrdev( 0,_LCD_CONTROL_NAME,&lcdctrl_fops);
33195 + printk(KERN_INFO "lcdctrl_init: OK\n");
33200 +++ linux-2.4.27/drivers/video/lcdctrl_cerf.c
33205 + * Cerf LCD control for brightness and contrast.
33207 + * Copyright (C) 2002 Intrinsyc Software Inc.
33209 + * This program is free software; you can redistribute it and/or modify
33210 + * it under the terms of the GNU General Public License version 2 as
33211 + * published by the Free Software Foundation.
33214 + * Mar 2002: Initial version [FB]
33217 +#include <linux/config.h>
33218 +#include <linux/module.h>
33219 +#include <linux/kernel.h>
33220 +#include <linux/sched.h>
33221 +#include <linux/errno.h>
33222 +#include <linux/string.h>
33223 +#include <linux/ctype.h>
33224 +#include <linux/mm.h>
33225 +#include <linux/init.h>
33226 +#include <linux/delay.h>
33228 +#include <asm/system.h>
33229 +#include <asm/hardware.h>
33230 +#include <asm/io.h>
33231 +#include <asm/irq.h>
33232 +#include <asm/uaccess.h>
33233 +#include <asm/arch/cerf_ucb1400gpio.h>
33235 +#include <video/lcdctrl.h>
33238 + * Set this to zero to remove all the debug statements via
33239 + * dead code elimination.
33241 +#define DEBUGGING 0
33244 +static unsigned int lcd_debug = DEBUGGING;
33246 +#define lcd_debug 0
33249 +#define LCD_MAX_INTENSITY 0
33250 +#define LCD_MAX_BRIGHTNESS 15
33251 +#define LCD_MAX_CONTRAST 100
33253 +#define LCD_DEFAULT_INTENSITY 0
33254 +#define LCD_DEFAULT_BRIGHTNESS 14*100/(LCD_MAX_BRIGHTNESS)
33255 +#define LCD_DEFAULT_CONTRAST 90*100/(LCD_MAX_CONTRAST)
33260 +/* -- prototypes -- */
33262 +static int cerf_lcdctrl_init( int *intensity, int *brightness, int *contrast);
33263 +static int cerf_lcdctrl_enable(void);
33264 +static int cerf_lcdctrl_disable(void);
33265 +static int cerf_lcdctrl_set_intensity( int i);
33266 +static int cerf_lcdctrl_set_brightness( int b);
33267 +static int cerf_lcdctrl_set_contrast( int c, int sync);
33269 +static void cerf_lcdctrl_contrast_step( int direction);
33271 +/* -- variables -- */
33273 +static int dev_contrast;
33277 +static struct lcdctrl_device cerf_dev = {
33278 + init: cerf_lcdctrl_init,
33279 + enable: cerf_lcdctrl_enable,
33280 + disable: cerf_lcdctrl_disable,
33281 + set_intensity: cerf_lcdctrl_set_intensity,
33282 + set_brightness: cerf_lcdctrl_set_brightness,
33283 + set_contrast: cerf_lcdctrl_set_contrast
33286 +static int cerf_lcdctrl_enable( void)
33288 + cerf_ucb1400gpio_lcd_enable();
33293 +static int cerf_lcdctrl_disable( void)
33295 + cerf_ucb1400gpio_lcd_disable();
33300 +static int cerf_lcdctrl_set_intensity( int i)
33302 + int dev_intensity = LCD_MAX_INTENSITY*i/100;
33304 + printk(KERN_INFO "cerf_lcdctrl_set_intensity: "
33305 + "dev_intensity = %d\n", dev_intensity);
33309 +static int cerf_lcdctrl_set_brightness( int b)
33311 + int dev_brightness = LCD_MAX_BRIGHTNESS*b/100;
33312 + outw( dev_brightness, CERF_PDA_CPLD+CERF_PDA_CPLD_BRIGHTNESS);
33314 + printk(KERN_INFO "cerf_lcdctrl_set_brightness: "
33315 + "dev_brightness = %d\n", dev_brightness);
33319 +static int cerf_lcdctrl_set_contrast( int c, int sync)
33321 + int new_dev_contrast = LCD_MAX_CONTRAST*c/100;
33324 + int direction = UP;
33325 + if( sync == LCD_SYNC_NEEDED)
33327 + /* In order to sync we step down to the lowest contrast level */
33328 + for( i=0; i<LCD_MAX_CONTRAST; i++)
33329 + cerf_lcdctrl_contrast_step(DOWN);
33330 + dev_contrast = 0;
33333 + count = new_dev_contrast - dev_contrast;
33336 + /* new contrast is lower then current setting */
33337 + direction = DOWN;
33341 + for( i=0; i<count; i++)
33342 + cerf_lcdctrl_contrast_step(direction);
33345 + printk(KERN_INFO "cerf_lcdctrl_set_contrast: "
33346 + "dev_contrast = %d\n", new_dev_contrast);
33347 + dev_contrast = new_dev_contrast;
33354 +static void cerf_lcdctrl_contrast_step( int direction)
33356 + cerf_ucb1400gpio_lcd_contrast_step( direction);
33361 +static int cerf_lcdctrl_init( int *intensity, int *brightness, int *contrast)
33363 + *intensity = LCD_DEFAULT_INTENSITY;
33364 + *brightness = LCD_DEFAULT_BRIGHTNESS;
33365 + *contrast = LCD_DEFAULT_CONTRAST;
33368 + printk(KERN_INFO "cerf_lcdctrl_init: OK\n");
33372 +/* this is the hook for lcdctrl to access to the device specifics */
33373 +struct lcdctrl_device *lcdctrl_device_get_ops(void)
33375 + return &cerf_dev;
33378 +++ linux-2.4.27/drivers/video/pxafb.c
33381 + * linux/drivers/video/pxafb.c
33383 + * Copyright (C) 1999 Eric A. Thomas
33384 + * Based on acornfb.c Copyright (C) Russell King.
33386 + * This file is subject to the terms and conditions of the GNU General Public
33387 + * License. See the file COPYING in the main directory of this archive for
33390 + * Intel PXA250/210 LCD Controller Frame Buffer Driver
33392 + * Please direct your questions and comments on this driver to the following
33395 + * linux-arm-kernel@lists.arm.linux.org.uk
33400 + * 2001/08/03: <cbrake@accelent.com>
33401 + * - Ported from SA1100 to PXA250
33404 +#include <linux/config.h>
33405 +#include <linux/module.h>
33406 +#include <linux/kernel.h>
33407 +#include <linux/sched.h>
33408 +#include <linux/errno.h>
33409 +#include <linux/string.h>
33410 +#include <linux/interrupt.h>
33411 +#include <linux/slab.h>
33412 +#include <linux/fb.h>
33413 +#include <linux/delay.h>
33414 +#include <linux/pm.h>
33415 +#include <linux/init.h>
33416 +#include <linux/notifier.h>
33417 +#include <linux/cpufreq.h>
33419 +#include <asm/hardware.h>
33420 +#include <asm/io.h>
33421 +#include <asm/irq.h>
33422 +#include <asm/mach-types.h>
33423 +#include <asm/uaccess.h>
33425 +#include <video/fbcon.h>
33426 +#include <video/fbcon-mfb.h>
33427 +#include <video/fbcon-cfb4.h>
33428 +#include <video/fbcon-cfb8.h>
33429 +#include <video/fbcon-cfb16.h>
33430 +#include <video/lcdctrl.h> /* brightness, contrast, etc. control */
33437 + * Complain if VAR is out of range.
33439 +#define DEBUG_VAR 1
33441 +#undef ASSABET_PAL_VIDEO
33443 +#include "pxafb.h"
33445 +void (*pxafb_blank_helper)(int blank);
33446 +EXPORT_SYMBOL(pxafb_blank_helper);
33449 + * IMHO this looks wrong. In 8BPP, length should be 8.
33451 +static struct pxafb_rgb rgb_8 = {
33452 + red: { offset: 0, length: 4, },
33453 + green: { offset: 0, length: 4, },
33454 + blue: { offset: 0, length: 4, },
33455 + transp: { offset: 0, length: 0, },
33458 +static struct pxafb_rgb def_rgb_16 = {
33459 + red: { offset: 11, length: 5, },
33460 + green: { offset: 5, length: 6, },
33461 + blue: { offset: 0, length: 5, },
33462 + transp: { offset: 0, length: 0, },
33465 +static struct pxafb_mach_info pxa_fb_info __initdata = {
33466 + pixclock: LCD_PIXCLOCK, /* clock period in ps */
33470 + hsync_len: LCD_HORIZONTAL_SYNC_PULSE_WIDTH,
33471 + vsync_len: LCD_VERTICAL_SYNC_PULSE_WIDTH,
33472 + left_margin: LCD_BEGIN_OF_LINE_WAIT_COUNT,
33473 + upper_margin: LCD_BEGIN_FRAME_WAIT_COUNT,
33474 + right_margin: LCD_END_OF_LINE_WAIT_COUNT,
33475 + lower_margin: LCD_END_OF_FRAME_WAIT_COUNT,
33477 + lccr0: LCD_LCCR0,
33481 +static struct pxafb_mach_info * __init
33482 +pxafb_get_machine_info(struct pxafb_info *fbi)
33484 + return &pxa_fb_info;
33487 +static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *);
33488 +static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
33490 +static inline void pxafb_schedule_task(struct pxafb_info *fbi, u_int state)
33492 + unsigned long flags;
33494 + local_irq_save(flags);
33496 + * We need to handle two requests being made at the same time.
33497 + * There are two important cases:
33498 + * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
33499 + * We must perform the unblanking, which will do our REENABLE for us.
33500 + * 2. When we are blanking, but immediately unblank before we have
33501 + * blanked. We do the "REENABLE" thing here as well, just to be sure.
33503 + if (fbi->task_state == C_ENABLE && state == C_REENABLE)
33504 + state = (u_int) -1;
33505 + if (fbi->task_state == C_DISABLE && state == C_ENABLE)
33506 + state = C_REENABLE;
33508 + if (state != (u_int)-1) {
33509 + fbi->task_state = state;
33510 + schedule_task(&fbi->task);
33512 + local_irq_restore(flags);
33516 + * Get the VAR structure pointer for the specified console
33518 +static inline struct fb_var_screeninfo *get_con_var(struct fb_info *info, int con)
33520 + struct pxafb_info *fbi = (struct pxafb_info *)info;
33521 + return (con == fbi->currcon || con == -1) ? &fbi->fb.var : &fb_display[con].var;
33525 + * Get the DISPLAY structure pointer for the specified console
33527 +static inline struct display *get_con_display(struct fb_info *info, int con)
33529 + struct pxafb_info *fbi = (struct pxafb_info *)info;
33530 + return (con < 0) ? fbi->fb.disp : &fb_display[con];
33534 + * Get the CMAP pointer for the specified console
33536 +static inline struct fb_cmap *get_con_cmap(struct fb_info *info, int con)
33538 + struct pxafb_info *fbi = (struct pxafb_info *)info;
33539 + return (con == fbi->currcon || con == -1) ? &fbi->fb.cmap : &fb_display[con].cmap;
33542 +static inline u_int
33543 +chan_to_field(u_int chan, struct fb_bitfield *bf)
33546 + chan >>= 16 - bf->length;
33547 + return chan << bf->offset;
33551 +pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
33552 + u_int trans, struct fb_info *info)
33554 + struct pxafb_info *fbi = (struct pxafb_info *)info;
33555 + u_int val, ret = 1;
33557 + if (regno < fbi->palette_size) {
33558 + val = ((red >> 0) & 0xf800);
33559 + val |= ((green >> 5) & 0x07e0);
33560 + val |= ((blue >> 11) & 0x001f);
33562 + fbi->palette_cpu[regno] = val;
33569 +pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
33570 + u_int trans, struct fb_info *info)
33572 + struct pxafb_info *fbi = (struct pxafb_info *)info;
33577 + * If greyscale is true, then we convert the RGB value
33578 + * to greyscale no mater what visual we are using.
33580 + if (fbi->fb.var.grayscale)
33581 + red = green = blue = (19595 * red + 38470 * green +
33582 + 7471 * blue) >> 16;
33584 + switch (fbi->fb.disp->visual) {
33585 + case FB_VISUAL_TRUECOLOR:
33586 + case FB_VISUAL_DIRECTCOLOR:
33588 + * 12 or 16-bit True Colour. We encode the RGB value
33589 + * according to the RGB bitfield information.
33591 + if (regno <= 16) {
33592 + u16 *pal = fbi->fb.pseudo_palette;
33594 + val = chan_to_field(red, &fbi->fb.var.red);
33595 + val |= chan_to_field(green, &fbi->fb.var.green);
33596 + val |= chan_to_field(blue, &fbi->fb.var.blue);
33598 + pal[regno] = val;
33603 + case FB_VISUAL_PSEUDOCOLOR:
33604 + ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
33612 + * pxafb_decode_var():
33613 + * Get the video params out of 'var'. If a value doesn't fit, round it up,
33614 + * if it's too big, return -EINVAL.
33616 + * Suggestion: Round up in the following order: bits_per_pixel, xres,
33617 + * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
33618 + * bitfields, horizontal timing, vertical timing.
33620 +static int pxafb_validate_var(struct fb_var_screeninfo *var,
33621 + struct pxafb_info *fbi)
33623 + int ret = -EINVAL;
33625 + if (var->xres < MIN_XRES)
33626 + var->xres = MIN_XRES;
33627 + if (var->yres < MIN_YRES)
33628 + var->yres = MIN_YRES;
33629 + if (var->xres > fbi->max_xres)
33630 + var->xres = fbi->max_xres;
33631 + if (var->yres > fbi->max_yres)
33632 + var->yres = fbi->max_yres;
33633 + var->xres_virtual =
33634 + var->xres_virtual < var->xres ? var->xres : var->xres_virtual;
33635 + var->yres_virtual =
33636 + var->yres_virtual < var->yres ? var->yres : var->yres_virtual;
33638 + DPRINTK("var->bits_per_pixel=%d\n", var->bits_per_pixel);
33639 + switch (var->bits_per_pixel) {
33640 +#ifdef FBCON_HAS_CFB4
33641 + case 4: ret = 0; break;
33643 +#ifdef FBCON_HAS_CFB8
33644 + case 8: ret = 0; break;
33646 +#ifdef FBCON_HAS_CFB16
33648 + /* make sure we are in passive mode */
33649 + if (!(fbi->lccr0 & LCCR0_PAS))
33655 + * 16 bits works apparemtly fine in passive mode for those,
33656 + * so don't complain
33658 + if (machine_is_lubbock() ||
33659 + machine_is_pxa_cerf()) {
33662 + /* make sure we are in active mode */
33663 + if ((fbi->lccr0 & LCCR0_PAS))
33674 +static inline void pxafb_set_truecolor(u_int is_true_color)
33676 + DPRINTK("true_color = %d\n", is_true_color);
33680 +pxafb_hw_set_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
33683 + fb_set_cmap(&fbi->fb.cmap, 1, pxafb_setcolreg, &fbi->fb);
33685 + /* Set board control register to handle new color depth */
33686 + pxafb_set_truecolor(var->bits_per_pixel >= 16);
33688 + pxafb_activate_var(var, fbi);
33693 + * pxafb_set_var():
33694 + * Set the user defined part of the display for the specified console
33697 +pxafb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *info)
33699 + struct pxafb_info *fbi = (struct pxafb_info *)info;
33700 + struct fb_var_screeninfo *dvar = get_con_var(&fbi->fb, con);
33701 + struct display *display = get_con_display(&fbi->fb, con);
33702 + int err, chgvar = 0, rgbidx;
33704 + DPRINTK("set_var\n");
33707 + * Decode var contents into a par structure, adjusting any
33708 + * out of range values.
33710 + err = pxafb_validate_var(var, fbi);
33714 + if (var->activate & FB_ACTIVATE_TEST)
33717 + if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_NOW)
33720 + if (dvar->xres != var->xres)
33722 + if (dvar->yres != var->yres)
33724 + if (dvar->xres_virtual != var->xres_virtual)
33726 + if (dvar->yres_virtual != var->yres_virtual)
33728 + if (dvar->bits_per_pixel != var->bits_per_pixel)
33733 + switch (var->bits_per_pixel) {
33734 +#ifdef FBCON_HAS_CFB4
33736 + if (fbi->cmap_static)
33737 + display->visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
33739 + display->visual = FB_VISUAL_PSEUDOCOLOR;
33740 + display->line_length = var->xres / 2;
33741 + display->dispsw = &fbcon_cfb4;
33745 +#ifdef FBCON_HAS_CFB8
33747 + if (fbi->cmap_static)
33748 + display->visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
33750 + display->visual = FB_VISUAL_PSEUDOCOLOR;
33751 + display->line_length = var->xres;
33752 + display->dispsw = &fbcon_cfb8;
33756 +#ifdef FBCON_HAS_CFB16
33759 + display->visual = FB_VISUAL_TRUECOLOR;
33760 + display->line_length = var->xres * 2;
33761 + display->dispsw = &fbcon_cfb16;
33762 + display->dispsw_data = fbi->fb.pseudo_palette;
33768 + display->dispsw = &fbcon_dummy;
33772 + display->screen_base = fbi->screen_cpu;
33773 + display->next_line = display->line_length;
33774 + display->type = fbi->fb.fix.type;
33775 + display->type_aux = fbi->fb.fix.type_aux;
33776 + display->ypanstep = fbi->fb.fix.ypanstep;
33777 + display->ywrapstep = fbi->fb.fix.ywrapstep;
33778 + display->can_soft_blank = 1;
33779 + display->inverse = 0;
33782 + dvar->activate &= ~FB_ACTIVATE_ALL;
33785 + * Copy the RGB parameters for this display
33786 + * from the machine specific parameters.
33788 + dvar->red = fbi->rgb[rgbidx]->red;
33789 + dvar->green = fbi->rgb[rgbidx]->green;
33790 + dvar->blue = fbi->rgb[rgbidx]->blue;
33791 + dvar->transp = fbi->rgb[rgbidx]->transp;
33793 + DPRINTK("RGBT length = %d:%d:%d:%d\n",
33794 + dvar->red.length, dvar->green.length, dvar->blue.length,
33795 + dvar->transp.length);
33797 + DPRINTK("RGBT offset = %d:%d:%d:%d\n",
33798 + dvar->red.offset, dvar->green.offset, dvar->blue.offset,
33799 + dvar->transp.offset);
33802 + * Update the old var. The fbcon drivers still use this.
33803 + * Once they are using fbi->fb.var, this can be dropped.
33805 + display->var = *dvar;
33808 + * If we are setting all the virtual consoles, also set the
33809 + * defaults used to create new consoles.
33811 + if (var->activate & FB_ACTIVATE_ALL)
33812 + fbi->fb.disp->var = *dvar;
33815 + * If the console has changed and the console has defined
33816 + * a changevar function, call that function.
33818 + if (chgvar && info && fbi->fb.changevar)
33819 + fbi->fb.changevar(con);
33821 + /* If the current console is selected, activate the new var. */
33822 + if (con != fbi->currcon)
33825 + pxafb_hw_set_var(dvar, fbi);
33831 +__do_set_cmap(struct fb_cmap *cmap, int kspc, int con,
33832 + struct fb_info *info)
33834 + struct pxafb_info *fbi = (struct pxafb_info *)info;
33835 + struct fb_cmap *dcmap = get_con_cmap(info, con);
33839 + con = fbi->currcon;
33841 + /* no colormap allocated? (we always have "this" colour map allocated) */
33843 + err = fb_alloc_cmap(&fb_display[con].cmap, fbi->palette_size, 0);
33845 + if (!err && con == fbi->currcon)
33846 + err = fb_set_cmap(cmap, kspc, pxafb_setcolreg, info);
33849 + fb_copy_cmap(cmap, dcmap, kspc ? 0 : 1);
33855 +pxafb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
33856 + struct fb_info *info)
33858 + struct display *disp = get_con_display(info, con);
33860 + if (disp->visual == FB_VISUAL_TRUECOLOR)
33863 + return __do_set_cmap(cmap, kspc, con, info);
33867 +pxafb_get_fix(struct fb_fix_screeninfo *fix, int con, struct fb_info *info)
33869 + struct display *display = get_con_display(info, con);
33871 + *fix = info->fix;
33873 + fix->line_length = display->line_length;
33874 + fix->visual = display->visual;
33879 +pxafb_get_var(struct fb_var_screeninfo *var, int con, struct fb_info *info)
33881 + *var = *get_con_var(info, con);
33886 +pxafb_get_cmap(struct fb_cmap *cmap, int kspc, int con, struct fb_info *info)
33888 + struct fb_cmap *dcmap = get_con_cmap(info, con);
33889 + fb_copy_cmap(dcmap, cmap, kspc ? 0 : 2);
33893 +static struct fb_ops pxafb_ops = {
33894 + owner: THIS_MODULE,
33895 + fb_get_fix: pxafb_get_fix,
33896 + fb_get_var: pxafb_get_var,
33897 + fb_set_var: pxafb_set_var,
33898 + fb_get_cmap: pxafb_get_cmap,
33899 + fb_set_cmap: pxafb_set_cmap,
33903 + * pxafb_switch():
33904 + * Change to the specified console. Palette and video mode
33905 + * are changed to the console's stored parameters.
33907 + * Uh oh, this can be called from a tasklet (IRQ)
33909 +static int pxafb_switch(int con, struct fb_info *info)
33911 + struct pxafb_info *fbi = (struct pxafb_info *)info;
33912 + struct display *disp;
33913 + struct fb_cmap *cmap;
33915 + DPRINTK("con=%d info->modename=%s\n", con, fbi->fb.modename);
33917 + if (con == fbi->currcon)
33920 + if (fbi->currcon >= 0) {
33921 + disp = fb_display + fbi->currcon;
33924 + * Save the old colormap and video mode.
33926 + disp->var = fbi->fb.var;
33928 + if (disp->cmap.len)
33929 + fb_copy_cmap(&fbi->fb.cmap, &disp->cmap, 0);
33932 + fbi->currcon = con;
33933 + disp = fb_display + con;
33936 + * Make sure that our colourmap contains 256 entries.
33938 + fb_alloc_cmap(&fbi->fb.cmap, 256, 0);
33940 + if (disp->cmap.len)
33941 + cmap = &disp->cmap;
33943 + cmap = fb_default_cmap(1 << disp->var.bits_per_pixel);
33945 + fb_copy_cmap(cmap, &fbi->fb.cmap, 0);
33947 + fbi->fb.var = disp->var;
33948 + fbi->fb.var.activate = FB_ACTIVATE_NOW;
33950 + pxafb_set_var(&fbi->fb.var, con, info);
33955 + * Formal definition of the VESA spec:
33957 + * This refers to the state of the display when it is in full operation
33959 + * This defines an optional operating state of minimal power reduction with
33960 + * the shortest recovery time
33962 + * This refers to a level of power management in which substantial power
33963 + * reduction is achieved by the display. The display can have a longer
33964 + * recovery time from this state than from the Stand-by state
33966 + * This indicates that the display is consuming the lowest level of power
33967 + * and is non-operational. Recovery from this state may optionally require
33968 + * the user to manually power on the monitor
33970 + * Now, the fbdev driver adds an additional state, (blank), where they
33971 + * turn off the video (maybe by colormap tricks), but don't mess with the
33972 + * video itself: think of it semantically between on and Stand-By.
33974 + * So here's what we should do in our fbdev blank routine:
33976 + * VESA_NO_BLANKING (mode 0) Video on, front/back light on
33977 + * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
33978 + * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
33979 + * VESA_POWERDOWN (mode 3) Video off, front/back light off
33981 + * This will match the matrox implementation.
33985 + * Blank the display by setting all palette values to zero. Note, the
33986 + * 12 and 16 bpp modes don't really use the palette, so this will not
33987 + * blank the display in all modes.
33989 +static void pxafb_blank(int blank, struct fb_info *info)
33991 + struct pxafb_info *fbi = (struct pxafb_info *)info;
33994 + DPRINTK("pxafb_blank: blank=%d info->modename=%s\n", blank,
33995 + fbi->fb.modename);
33998 + case VESA_POWERDOWN:
33999 + case VESA_VSYNC_SUSPEND:
34000 + case VESA_HSYNC_SUSPEND:
34001 + if (fbi->fb.disp->visual == FB_VISUAL_PSEUDOCOLOR ||
34002 + fbi->fb.disp->visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
34003 + for (i = 0; i < fbi->palette_size; i++)
34004 + pxafb_setpalettereg(i, 0, 0, 0, 0, info);
34005 + pxafb_schedule_task(fbi, C_DISABLE);
34006 + if (pxafb_blank_helper)
34007 + pxafb_blank_helper(blank);
34010 + case VESA_NO_BLANKING:
34011 + if (pxafb_blank_helper)
34012 + pxafb_blank_helper(blank);
34013 + if (fbi->fb.disp->visual == FB_VISUAL_PSEUDOCOLOR ||
34014 + fbi->fb.disp->visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
34015 + fb_set_cmap(&fbi->fb.cmap, 1, pxafb_setcolreg, info);
34016 + pxafb_schedule_task(fbi, C_ENABLE);
34020 +static int pxafb_updatevar(int con, struct fb_info *info)
34022 + DPRINTK("entered\n");
34027 + * Calculate the PCD value from the clock rate (in picoseconds).
34028 + * We take account of the PPCR clock setting.
34030 +static inline int get_pcd(unsigned int pixclock)
34032 + unsigned int pcd;
34035 + pcd = get_lclk_frequency_10khz() * pixclock;
34036 + pcd /= 100000000;
34037 + pcd += 1; /* make up for integer math truncations */
34039 + printk(KERN_WARNING "Please convert me to use the PCD calculations\n");
34046 + * pxafb_activate_var():
34047 + * Configures LCD Controller based on entries in var parameter. Settings are
34048 + * only written to the controller if changes were made.
34050 +static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
34052 + struct pxafb_lcd_reg new_regs;
34053 +// u_int pcd = get_pcd(var->pixclock);
34056 + DPRINTK("Configuring PXA LCD\n");
34058 + DPRINTK("var: xres=%d hslen=%d lm=%d rm=%d\n",
34059 + var->xres, var->hsync_len,
34060 + var->left_margin, var->right_margin);
34061 + DPRINTK("var: yres=%d vslen=%d um=%d bm=%d\n",
34062 + var->yres, var->vsync_len,
34063 + var->upper_margin, var->lower_margin);
34066 + if (var->xres < 16 || var->xres > 1024)
34067 + printk(KERN_ERR "%s: invalid xres %d\n",
34068 + fbi->fb.fix.id, var->xres);
34069 + if (var->hsync_len < 1 || var->hsync_len > 64)
34070 + printk(KERN_ERR "%s: invalid hsync_len %d\n",
34071 + fbi->fb.fix.id, var->hsync_len);
34072 + if (var->left_margin < 1 || var->left_margin > 255)
34073 + printk(KERN_ERR "%s: invalid left_margin %d\n",
34074 + fbi->fb.fix.id, var->left_margin);
34075 + if (var->right_margin < 1 || var->right_margin > 255)
34076 + printk(KERN_ERR "%s: invalid right_margin %d\n",
34077 + fbi->fb.fix.id, var->right_margin);
34078 + if (var->yres < 1 || var->yres > 1024)
34079 + printk(KERN_ERR "%s: invalid yres %d\n",
34080 + fbi->fb.fix.id, var->yres);
34081 + if (var->vsync_len < 1 || var->vsync_len > 64)
34082 + printk(KERN_ERR "%s: invalid vsync_len %d\n",
34083 + fbi->fb.fix.id, var->vsync_len);
34084 + if (var->upper_margin < 0 || var->upper_margin > 255)
34085 + printk(KERN_ERR "%s: invalid upper_margin %d\n",
34086 + fbi->fb.fix.id, var->upper_margin);
34087 + if (var->lower_margin < 0 || var->lower_margin > 255)
34088 + printk(KERN_ERR "%s: invalid lower_margin %d\n",
34089 + fbi->fb.fix.id, var->lower_margin);
34092 +#if defined (CONFIG_PXA_CERF_PDA)
34093 + new_regs.lccr0 = fbi->lccr0;
34095 + LCCR1_DisWdth(var->xres) +
34096 + LCCR1_HorSnchWdth(var->hsync_len) +
34097 + LCCR1_BegLnDel(var->left_margin) +
34098 + LCCR1_EndLnDel(var->right_margin);
34101 + LCCR2_DisHght(var->yres) +
34102 + LCCR2_VrtSnchWdth(var->vsync_len) +
34103 + LCCR2_BegFrmDel(var->upper_margin) +
34104 + LCCR2_EndFrmDel(var->lower_margin);
34106 + new_regs.lccr3 = fbi->lccr3
34108 + (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
34109 + (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
34110 +#elif defined (CONFIG_FB_PXA_QVGA)
34111 + new_regs.lccr0 = fbi->lccr0;
34113 + LCCR1_DisWdth(var->xres) +
34114 + LCCR1_HorSnchWdth(var->hsync_len) +
34115 + LCCR1_BegLnDel(var->left_margin) +
34116 + LCCR1_EndLnDel(var->right_margin);
34118 + LCCR2_DisHght(var->yres) +
34119 + LCCR2_VrtSnchWdth(var->vsync_len) +
34120 + LCCR2_BegFrmDel(var->upper_margin) +
34121 + LCCR2_EndFrmDel(var->lower_margin);
34122 + new_regs.lccr3 = fbi->lccr3;
34124 + // FIXME using hardcoded values for now
34125 + new_regs.lccr0 = fbi->lccr0;
34127 +// LCCR0_LEN | LCCR0_LDM | LCCR0_BAM |
34128 +// LCCR0_ERM | LCCR0_LtlEnd | LCCR0_DMADel(0);
34130 + new_regs.lccr1 = 0x3030A7F;
34131 +// LCCR1_DisWdth(var->xres) +
34132 +// LCCR1_HorSnchWdth(var->hsync_len) +
34133 +// LCCR1_BegLnDel(var->left_margin) +
34134 +// LCCR1_EndLnDel(var->right_margin);
34136 + new_regs.lccr2 = 0x4EF;
34137 +// LCCR2_DisHght(var->yres) +
34138 +// LCCR2_VrtSnchWdth(var->vsync_len) +
34139 +// LCCR2_BegFrmDel(var->upper_margin) +
34140 +// LCCR2_EndFrmDel(var->lower_margin);
34142 + new_regs.lccr3 = fbi->lccr3;
34144 +// (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
34145 +// (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL) |
34146 +// LCCR3_ACBsCntOff;
34150 +// new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
34152 + DPRINTK("nlccr0 = 0x%08x\n", new_regs.lccr0);
34153 + DPRINTK("nlccr1 = 0x%08x\n", new_regs.lccr1);
34154 + DPRINTK("nlccr2 = 0x%08x\n", new_regs.lccr2);
34155 + DPRINTK("nlccr3 = 0x%08x\n", new_regs.lccr3);
34157 + /* Update shadow copy atomically */
34158 + local_irq_save(flags);
34160 + /* setup dma descriptors */
34161 + fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16);
34162 + fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16);
34163 + fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16);
34165 + fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
34166 + fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
34167 + fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
34169 + #define BYTES_PER_PANEL ((fbi->lccr0 & LCCR0_SDS) ? (var->xres * var->yres * var->bits_per_pixel / 8 / 2) : \
34170 + (var->xres * var->yres * var->bits_per_pixel / 8))
34172 + /* populate descriptors */
34173 + fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
34174 + fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
34175 + fbi->dmadesc_fblow_cpu->fidr = 0;
34176 + fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
34178 + fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
34180 + fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
34181 + fbi->dmadesc_fbhigh_cpu->fidr = 0;
34182 + fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
34184 + fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
34185 + fbi->dmadesc_palette_cpu->fidr = 0;
34186 + fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
34188 + if( var->bits_per_pixel < 12)
34190 + /* assume any mode with <12 bpp is palette driven */
34191 + fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
34192 + fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
34193 + fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */
34197 + /* palette shouldn't be loaded in true-color mode */
34198 + fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
34199 + fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
34202 + DPRINTK("fbi->dmadesc_fblow_cpu = 0x%x\n", fbi->dmadesc_fblow_cpu);
34203 + DPRINTK("fbi->dmadesc_fbhigh_cpu = 0x%x\n", fbi->dmadesc_fbhigh_cpu);
34204 + DPRINTK("fbi->dmadesc_palette_cpu = 0x%x\n", fbi->dmadesc_palette_cpu);
34205 + DPRINTK("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma);
34206 + DPRINTK("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma);
34207 + DPRINTK("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma);
34209 + DPRINTK("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr);
34210 + DPRINTK("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr);
34211 + DPRINTK("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr);
34213 + DPRINTK("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr);
34214 + DPRINTK("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr);
34215 + DPRINTK("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr);
34217 + DPRINTK("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd);
34218 + DPRINTK("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd);
34219 + DPRINTK("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd);
34221 + fbi->reg_lccr0 = new_regs.lccr0;
34222 + fbi->reg_lccr1 = new_regs.lccr1;
34223 + fbi->reg_lccr2 = new_regs.lccr2;
34224 + fbi->reg_lccr3 = new_regs.lccr3;
34225 + local_irq_restore(flags);
34228 + * Only update the registers if the controller is enabled
34229 + * and something has changed.
34231 + if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
34232 + (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
34233 + (FDADR0 != fbi->fdadr0) || (FDADR1 != fbi->fdadr1))
34234 + pxafb_schedule_task(fbi, C_REENABLE);
34240 + * NOTE! The following functions are purely helpers for set_ctrlr_state.
34241 + * Do not call them directly; set_ctrlr_state does the correct serialisation
34242 + * to ensure that things happen in the right way 100% of time time.
34247 + * FIXME: move LCD power stuff into pxafb_power_up_lcd()
34248 + * Also, I'm expecting that the backlight stuff should
34249 + * be handled differently.
34251 +static void pxafb_backlight_on(struct pxafb_info *fbi)
34253 + DPRINTK("backlight on\n");
34255 +#ifdef CONFIG_ARCH_PXA_IDP
34256 + if(machine_is_pxa_idp()) {
34257 + FB_BACKLIGHT_ON();
34263 + * FIXME: move LCD power stuf into pxafb_power_down_lcd()
34264 + * Also, I'm expecting that the backlight stuff should
34265 + * be handled differently.
34267 +static void pxafb_backlight_off(struct pxafb_info *fbi)
34269 + DPRINTK("backlight off\n");
34271 +#ifdef CONFIG_ARCH_PXA_IDP
34272 + if(machine_is_pxa_idp()) {
34273 + FB_BACKLIGHT_OFF();
34279 +static void pxafb_power_up_lcd(struct pxafb_info *fbi)
34281 + DPRINTK("LCD power on\n");
34282 + CKEN |= CKEN16_LCD;
34284 + if(machine_is_pxa_cerf()) {
34285 + lcdctrl_enable();
34288 +#if CONFIG_ARCH_PXA_IDP
34289 + /* set GPIOs, etc */
34290 + if(machine_is_pxa_idp()) {
34291 + // FIXME need to add proper delays
34293 + FB_VLCD_ON(); // FIXME this should be after scanning starts
34298 +static void pxafb_power_down_lcd(struct pxafb_info *fbi)
34300 + DPRINTK("LCD power off\n");
34301 + CKEN &= ~CKEN16_LCD;
34303 + if(machine_is_pxa_cerf()) {
34304 + lcdctrl_disable();
34307 + /* set GPIOs, etc */
34308 +#if CONFIG_ARCH_PXA_IDP
34309 + if(machine_is_pxa_idp()) {
34310 + // FIXME need to add proper delays
34312 + FB_VLCD_OFF(); // FIXME this should be before scanning stops
34318 +static void pxafb_setup_gpio(struct pxafb_info *fbi)
34320 + unsigned int lccr0;
34323 + * setup is based on type of panel supported
34326 + lccr0 = fbi->lccr0;
34328 + /* 4 bit interface */
34329 + if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
34332 + GPDR1 |= (0xf << 26);
34333 + GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
34336 + GPDR2 |= (0xf << 10);
34337 + GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
34340 + /* 8 bit interface */
34341 + else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
34342 + (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
34345 + GPDR1 |= (0x3f << 26);
34348 + GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
34349 + GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
34352 + GPDR2 |= (0xf << 10);
34353 + GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
34356 + /* 16 bit interface */
34357 + else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
34360 + GPDR1 |= (0x3f << 26);
34361 + GPDR2 |= 0x00003fff;
34363 + GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
34364 + GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
34368 + printk( KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
34372 +static void pxafb_enable_controller(struct pxafb_info *fbi)
34374 + DPRINTK("Enabling LCD controller\n");
34376 + /* Sequence from 11.7.10 */
34377 + LCCR3 = fbi->reg_lccr3;
34378 + LCCR2 = fbi->reg_lccr2;
34379 + LCCR1 = fbi->reg_lccr1;
34380 + LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
34382 + /* FIXME we used to have LCD power control here */
34384 + FDADR0 = fbi->fdadr0;
34385 + FDADR1 = fbi->fdadr1;
34386 + LCCR0 |= LCCR0_ENB;
34388 + DPRINTK("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
34389 + DPRINTK("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
34390 + DPRINTK("LCCR0 = 0x%08x\n", (unsigned int)LCCR0);
34391 + DPRINTK("LCCR1 = 0x%08x\n", (unsigned int)LCCR1);
34392 + DPRINTK("LCCR2 = 0x%08x\n", (unsigned int)LCCR2);
34393 + DPRINTK("LCCR3 = 0x%08x\n", (unsigned int)LCCR3);
34396 +static void pxafb_disable_controller(struct pxafb_info *fbi)
34398 + DECLARE_WAITQUEUE(wait, current);
34400 + DPRINTK("Disabling LCD controller\n");
34402 + /* FIXME add power down GPIO stuff here */
34404 + add_wait_queue(&fbi->ctrlr_wait, &wait);
34405 + set_current_state(TASK_UNINTERRUPTIBLE);
34407 + LCSR = 0xffffffff; /* Clear LCD Status Register */
34408 + LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
34409 + LCCR0 &= ~LCCR0_ENB; /* Disable LCD Controller */
34411 + schedule_timeout(20 * HZ / 1000);
34412 + current->state = TASK_RUNNING;
34413 + remove_wait_queue(&fbi->ctrlr_wait, &wait);
34417 + * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
34419 +static void pxafb_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
34421 + struct pxafb_info *fbi = dev_id;
34422 + unsigned int lcsr = LCSR;
34424 + if (lcsr & LCSR_LDD) {
34425 + LCCR0 |= LCCR0_LDM;
34426 + wake_up(&fbi->ctrlr_wait);
34433 + * This function must be called from task context only, since it will
34434 + * sleep when disabling the LCD controller, or if we get two contending
34435 + * processes trying to alter state.
34437 +static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
34441 + down(&fbi->ctrlr_sem);
34443 + old_state = fbi->state;
34446 + case C_DISABLE_CLKCHANGE:
34448 + * Disable controller for clock change. If the
34449 + * controller is already disabled, then do nothing.
34451 + if (old_state != C_DISABLE) {
34452 + fbi->state = state;
34453 + pxafb_disable_controller(fbi);
34459 + * Disable controller
34461 + if (old_state != C_DISABLE) {
34462 + fbi->state = state;
34464 + pxafb_backlight_off(fbi);
34465 + if (old_state != C_DISABLE_CLKCHANGE)
34466 + pxafb_disable_controller(fbi);
34467 + pxafb_power_down_lcd(fbi);
34471 + case C_ENABLE_CLKCHANGE:
34473 + * Enable the controller after clock change. Only
34474 + * do this if we were disabled for the clock change.
34476 + if (old_state == C_DISABLE_CLKCHANGE) {
34477 + fbi->state = C_ENABLE;
34478 + pxafb_enable_controller(fbi);
34484 + * Re-enable the controller only if it was already
34485 + * enabled. This is so we reprogram the control
34488 + if (old_state == C_ENABLE) {
34489 + pxafb_disable_controller(fbi);
34490 + pxafb_setup_gpio(fbi);
34491 + pxafb_enable_controller(fbi);
34497 + * Power up the LCD screen, enable controller, and
34498 + * turn on the backlight.
34500 + if (old_state != C_ENABLE) {
34501 + fbi->state = C_ENABLE;
34502 + pxafb_setup_gpio(fbi);
34503 + pxafb_power_up_lcd(fbi);
34504 + pxafb_enable_controller(fbi);
34505 + pxafb_backlight_on(fbi);
34509 + up(&fbi->ctrlr_sem);
34513 + * Our LCD controller task (which is called when we blank or unblank)
34516 +static void pxafb_task(void *dummy)
34518 + struct pxafb_info *fbi = dummy;
34519 + u_int state = xchg(&fbi->task_state, -1);
34521 + set_ctrlr_state(fbi, state);
34524 +#ifdef CONFIG_CPU_FREQ
34526 + * CPU clock speed change handler. We need to adjust the LCD timing
34527 + * parameters when the CPU clock is adjusted by the power management
34531 +pxafb_clkchg_notifier(struct notifier_block *nb, unsigned long val,
34534 + struct pxafb_info *fbi = TO_INF(nb, clockchg);
34538 + case CPUFREQ_MINMAX:
34539 + /* todo: fill in min/max values */
34542 + case CPUFREQ_PRECHANGE:
34543 + set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
34546 + case CPUFREQ_POSTCHANGE:
34547 + pcd = get_pcd(fbi->fb.var.pixclock);
34548 + fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
34549 + set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
34558 + * Power management hook. Note that we won't be called from IRQ context,
34559 + * unlike the blank functions above, so we may sleep.
34562 +pxafb_pm_callback(struct pm_dev *pm_dev, pm_request_t req, void *data)
34564 + struct pxafb_info *fbi = pm_dev->data;
34566 + DPRINTK("pm_callback: %d\n", req);
34568 + if (req == PM_SUSPEND || req == PM_RESUME) {
34569 + int state = (int)data;
34571 + if (state == 0) {
34573 + set_ctrlr_state(fbi, C_ENABLE);
34575 + /* Enter D1-D3. Disable the LCD controller. */
34576 + set_ctrlr_state(fbi, C_DISABLE);
34579 + DPRINTK("done\n");
34585 + * pxafb_map_video_memory():
34586 + * Allocates the DRAM memory for the frame buffer. This buffer is
34587 + * remapped into a non-cached, non-buffered, memory region to
34588 + * allow palette and pixel writes to occur without flushing the
34589 + * cache. Once this area is remapped, all virtual memory
34590 + * access to the video memory should occur at the new region.
34592 +static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
34594 + u_long palette_mem_size;
34597 + * We reserve one page for the palette, plus the size
34598 + * of the framebuffer.
34600 + * layout of stuff in memory
34602 + * fblow descriptor
34603 + * fbhigh descriptor
34604 + * palette descriptor
34606 + * page boundary->
34609 + fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
34610 + fbi->map_cpu = consistent_alloc(GFP_KERNEL, fbi->map_size,
34611 + &fbi->map_dma, PTE_BUFFERABLE);
34613 + if (fbi->map_cpu) {
34614 + fbi->screen_cpu = fbi->map_cpu + PAGE_SIZE;
34615 + fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
34616 + fbi->fb.fix.smem_start = fbi->screen_dma;
34618 + fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
34620 + palette_mem_size = fbi->palette_size * sizeof(u16);
34622 + DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
34624 + fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
34625 + fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
34629 + return fbi->map_cpu ? 0 : -ENOMEM;
34632 +/* Fake monspecs to fill in fbinfo structure */
34633 +static struct fb_monspecs monspecs __initdata = {
34634 + 30000, 70000, 50, 65, 0 /* Generic */
34638 +static struct pxafb_info * __init pxafb_init_fbinfo(void)
34640 + struct pxafb_mach_info *inf;
34641 + struct pxafb_info *fbi;
34643 + fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(struct display) +
34644 + sizeof(u16) * 16, GFP_KERNEL);
34648 + memset(fbi, 0, sizeof(struct pxafb_info) + sizeof(struct display));
34650 + fbi->currcon = -1;
34652 + strcpy(fbi->fb.fix.id, PXA_NAME);
34654 + fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
34655 + fbi->fb.fix.type_aux = 0;
34656 + fbi->fb.fix.xpanstep = 0;
34657 + fbi->fb.fix.ypanstep = 0;
34658 + fbi->fb.fix.ywrapstep = 0;
34659 + fbi->fb.fix.accel = FB_ACCEL_NONE;
34661 + fbi->fb.var.nonstd = 0;
34662 + fbi->fb.var.activate = FB_ACTIVATE_NOW;
34663 + fbi->fb.var.height = -1;
34664 + fbi->fb.var.width = -1;
34665 + fbi->fb.var.accel_flags = 0;
34666 + fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
34668 + strcpy(fbi->fb.modename, PXA_NAME);
34669 + strcpy(fbi->fb.fontname, "Acorn8x8");
34671 + fbi->fb.fbops = &pxafb_ops;
34672 + fbi->fb.changevar = NULL;
34673 + fbi->fb.switch_con = pxafb_switch;
34674 + fbi->fb.updatevar = pxafb_updatevar;
34675 + fbi->fb.blank = pxafb_blank;
34676 + fbi->fb.flags = FBINFO_FLAG_DEFAULT;
34677 + fbi->fb.node = -1;
34678 + fbi->fb.monspecs = monspecs;
34679 + fbi->fb.disp = (struct display *)(fbi + 1);
34680 + fbi->fb.pseudo_palette = (void *)(fbi->fb.disp + 1);
34682 + fbi->rgb[RGB_8] = &rgb_8;
34683 + fbi->rgb[RGB_16] = &def_rgb_16;
34685 + inf = pxafb_get_machine_info(fbi);
34687 + fbi->max_xres = inf->xres;
34688 + fbi->fb.var.xres = inf->xres;
34689 + fbi->fb.var.xres_virtual = inf->xres;
34690 + fbi->max_yres = inf->yres;
34691 + fbi->fb.var.yres = inf->yres;
34692 + fbi->fb.var.yres_virtual = inf->yres;
34693 + fbi->max_bpp = inf->bpp;
34694 + fbi->fb.var.bits_per_pixel = inf->bpp;
34695 + fbi->fb.var.pixclock = inf->pixclock;
34696 + fbi->fb.var.hsync_len = inf->hsync_len;
34697 + fbi->fb.var.left_margin = inf->left_margin;
34698 + fbi->fb.var.right_margin = inf->right_margin;
34699 + fbi->fb.var.vsync_len = inf->vsync_len;
34700 + fbi->fb.var.upper_margin = inf->upper_margin;
34701 + fbi->fb.var.lower_margin = inf->lower_margin;
34702 + fbi->fb.var.sync = inf->sync;
34703 + fbi->fb.var.grayscale = inf->cmap_greyscale;
34704 + fbi->cmap_inverse = inf->cmap_inverse;
34705 + fbi->cmap_static = inf->cmap_static;
34706 + fbi->lccr0 = inf->lccr0;
34707 + fbi->lccr3 = inf->lccr3;
34708 + fbi->state = C_DISABLE;
34709 + fbi->task_state = (u_char)-1;
34710 + fbi->fb.fix.smem_len = fbi->max_xres * fbi->max_yres *
34711 + fbi->max_bpp / 8;
34713 + init_waitqueue_head(&fbi->ctrlr_wait);
34714 + INIT_TQUEUE(&fbi->task, pxafb_task, fbi);
34715 + init_MUTEX(&fbi->ctrlr_sem);
34720 +int __init pxafb_init(void)
34722 + struct pxafb_info *fbi;
34725 + fbi = pxafb_init_fbinfo();
34730 + if(machine_is_pxa_cerf()) {
34731 + // brightness&contrast is handled via lcdctrl.
34735 + /* Initialize video memory */
34736 + ret = pxafb_map_video_memory(fbi);
34740 + ret = request_irq(IRQ_LCD, pxafb_handle_irq, SA_INTERRUPT,
34743 + printk(KERN_ERR "pxafb: failed in request_irq: %d\n", ret);
34747 + pxafb_set_var(&fbi->fb.var, -1, &fbi->fb);
34749 + ret = register_framebuffer(&fbi->fb);
34755 + * Note that the console registers this as well, but we want to
34756 + * power down the display prior to sleeping.
34758 + fbi->pm = pm_register(PM_SYS_DEV, PM_SYS_VGA, pxafb_pm_callback);
34760 + fbi->pm->data = fbi;
34762 +#ifdef CONFIG_CPU_FREQ
34763 + fbi->clockchg.notifier_call = pxafb_clkchg_notifier;
34764 + cpufreq_register_notifier(&fbi->clockchg);
34768 + * Ok, now enable the LCD controller
34770 + set_ctrlr_state(fbi, C_ENABLE);
34772 + /* This driver cannot be unloaded at the moment */
34773 + MOD_INC_USE_COUNT;
34785 +module_init(pxafb_init);
34788 +MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
34789 +MODULE_LICENSE("GPL");
34791 +++ linux-2.4.27/drivers/video/pxafb.h
34794 + * linux/drivers/video/pxafb.h
34795 + * -- Intel PXA250/210 LCD Controller Frame Buffer Device
34797 + * Copyright (C) 1999 Eric A. Thomas
34798 + * Based on acornfb.c Copyright (C) Russell King.
34800 + * 2001-08-03: Cliff Brake <cbrake@acclent.com>
34801 + * - ported SA1100 code to PXA
34803 + * This file is subject to the terms and conditions of the GNU General Public
34804 + * License. See the file COPYING in the main directory of this archive
34805 + * for more details.
34809 + * These are the bitfields for each
34810 + * display depth that we support.
34812 +struct pxafb_rgb {
34813 + struct fb_bitfield red;
34814 + struct fb_bitfield green;
34815 + struct fb_bitfield blue;
34816 + struct fb_bitfield transp;
34820 + * This structure describes the machine which we are running on.
34822 +struct pxafb_mach_info {
34829 + u_char hsync_len;
34830 + u_char left_margin;
34831 + u_char right_margin;
34833 + u_char vsync_len;
34834 + u_char upper_margin;
34835 + u_char lower_margin;
34838 + u_int cmap_greyscale:1,
34847 +/* Shadows for LCD controller registers */
34848 +struct pxafb_lcd_reg {
34849 + unsigned int lccr0;
34850 + unsigned int lccr1;
34851 + unsigned int lccr2;
34852 + unsigned int lccr3;
34855 +/* PXA LCD DMA descriptor */
34856 +struct pxafb_dma_descriptor {
34857 + unsigned int fdadr;
34858 + unsigned int fsadr;
34859 + unsigned int fidr;
34860 + unsigned int ldcmd;
34864 +#define RGB_16 (1)
34867 +struct pxafb_info {
34868 + struct fb_info fb;
34869 + signed int currcon;
34871 + struct pxafb_rgb *rgb[NR_RGB];
34878 + * These are the addresses we mapped
34879 + * the framebuffer memory region to.
34882 + /* raw memory addresses */
34883 + dma_addr_t map_dma; /* physical */
34884 + u_char * map_cpu; /* virtual */
34887 + /* addresses of pieces placed in raw buffer */
34888 + u_char * screen_cpu; /* virtual address of frame buffer */
34889 + dma_addr_t screen_dma; /* physical address of frame buffer */
34890 + u16 * palette_cpu; /* virtual address of palette memory */
34891 + dma_addr_t palette_dma; /* physical address of palette memory */
34892 + u_int palette_size;
34894 + /* DMA descriptors */
34895 + struct pxafb_dma_descriptor * dmadesc_fblow_cpu;
34896 + dma_addr_t dmadesc_fblow_dma;
34897 + struct pxafb_dma_descriptor * dmadesc_fbhigh_cpu;
34898 + dma_addr_t dmadesc_fbhigh_dma;
34899 + struct pxafb_dma_descriptor * dmadesc_palette_cpu;
34900 + dma_addr_t dmadesc_palette_dma;
34902 + dma_addr_t fdadr0;
34903 + dma_addr_t fdadr1;
34907 + u_int cmap_inverse:1,
34916 + volatile u_char state;
34917 + volatile u_char task_state;
34918 + struct semaphore ctrlr_sem;
34919 + wait_queue_head_t ctrlr_wait;
34920 + struct tq_struct task;
34923 + struct pm_dev *pm;
34925 +#ifdef CONFIG_CPU_FREQ
34926 + struct notifier_block clockchg;
34930 +#define __type_entry(ptr,type,member) ((type *)((char *)(ptr)-offsetof(type,member)))
34932 +#define TO_INF(ptr,member) __type_entry(ptr,struct pxafb_info,member)
34935 + * These are the actions for set_ctrlr_state
34937 +#define C_DISABLE (0)
34938 +#define C_ENABLE (1)
34939 +#define C_DISABLE_CLKCHANGE (2)
34940 +#define C_ENABLE_CLKCHANGE (3)
34941 +#define C_REENABLE (4)
34943 +#define PXA_NAME "PXA"
34949 +# define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
34951 +# define DPRINTK(fmt, args...)
34955 + * Minimum X and Y resolutions
34957 +#define MIN_XRES 64
34958 +#define MIN_YRES 64
34961 + * Are we configured for 8 or 16 bits per pixel?
34963 +#ifdef CONFIG_FB_PXA_8BPP
34964 +# define PXAFB_BPP 8
34965 +# define PXAFB_BPP_BITS 0x03
34966 +#elif CONFIG_FB_PXA_16BPP
34967 +# define PXAFB_BPP 16
34968 +# define PXAFB_BPP_BITS 0x04
34971 +#if defined(CONFIG_ARCH_LUBBOCK)
34972 +#define LCD_PIXCLOCK 150000
34973 +#define LCD_BPP PXAFB_BPP
34974 +#ifdef CONFIG_FB_PXA_QVGA
34975 +#define LCD_XRES 320
34976 +#define LCD_YRES 240
34977 +#define LCD_HORIZONTAL_SYNC_PULSE_WIDTH 51
34978 +#define LCD_VERTICAL_SYNC_PULSE_WIDTH 1
34979 +#define LCD_BEGIN_OF_LINE_WAIT_COUNT 1
34980 +#define LCD_BEGIN_FRAME_WAIT_COUNT 8
34981 +#define LCD_END_OF_LINE_WAIT_COUNT 1
34982 +#define LCD_END_OF_FRAME_WAIT_COUNT 1
34983 +#define LCD_SYNC (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT)
34984 +#define LCD_LCCR0 0x003008F8
34985 +#define LCD_LCCR3 (0x0040FF0C | (PXAFB_BPP_BITS << 24))
34987 +#define LCD_XRES 640
34988 +#define LCD_YRES 480
34989 +#define LCD_HORIZONTAL_SYNC_PULSE_WIDTH 1
34990 +#define LCD_VERTICAL_SYNC_PULSE_WIDTH 1
34991 +#define LCD_BEGIN_OF_LINE_WAIT_COUNT 3
34992 +#define LCD_BEGIN_FRAME_WAIT_COUNT 0
34993 +#define LCD_END_OF_LINE_WAIT_COUNT 3
34994 +#define LCD_END_OF_FRAME_WAIT_COUNT 0
34995 +#define LCD_SYNC (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT)
34996 +#define LCD_LCCR0 0x0030087C
34997 +#define LCD_LCCR3 (0x0040FF0C | (PXAFB_BPP_BITS << 24))
35000 +#elif defined (CONFIG_ARCH_PXA_IDP)
35001 +#define LCD_PIXCLOCK 150000
35002 +#define LCD_BPP PXAFB_BPP
35003 +#define LCD_XRES 640
35004 +#define LCD_YRES 480
35005 +#define LCD_HORIZONTAL_SYNC_PULSE_WIDTH 1
35006 +#define LCD_VERTICAL_SYNC_PULSE_WIDTH 1
35007 +#define LCD_BEGIN_OF_LINE_WAIT_COUNT 3
35008 +#define LCD_BEGIN_FRAME_WAIT_COUNT 0
35009 +#define LCD_END_OF_LINE_WAIT_COUNT 3
35010 +#define LCD_END_OF_FRAME_WAIT_COUNT 0
35011 +#define LCD_SYNC (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT)
35012 +#define LCD_LCCR0 0x0030087C
35013 +#define LCD_LCCR3 (0x0040FF0C | (PXAFB_BPP_BITS << 24))
35015 +#elif defined CONFIG_PXA_CERF_PDA
35016 +#define LCD_PIXCLOCK 171521
35017 +#define LCD_BPP PXAFB_BPP
35018 +#define LCD_XRES 240
35019 +#define LCD_YRES 320
35020 +#define LCD_HORIZONTAL_SYNC_PULSE_WIDTH 7
35021 +#define LCD_VERTICAL_SYNC_PULSE_WIDTH 2
35022 +#define LCD_BEGIN_OF_LINE_WAIT_COUNT 17
35023 +#define LCD_BEGIN_FRAME_WAIT_COUNT 0
35024 +#define LCD_END_OF_LINE_WAIT_COUNT 17
35025 +#define LCD_END_OF_FRAME_WAIT_COUNT 0
35026 +#define LCD_SYNC (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT)
35027 +#define LCD_LCCR0 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | LCCR0_QDM | LCCR0_BM | LCCR0_OUM)
35028 +#define LCD_LCCR3 (LCCR3_PCP | LCCR3_PixClkDiv(0x12) | LCCR3_Bpp(PXAFB_BPP_BITS) | LCCR3_Acb(0x18))
35031 --- linux-2.4.27/drivers/video/sa1100fb.c~2.4.27-vrs1-pxa1
35032 +++ linux-2.4.27/drivers/video/sa1100fb.c
35033 @@ -2175,7 +2175,7 @@
35035 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
35036 fbi->map_cpu = consistent_alloc(GFP_KERNEL, fbi->map_size,
35038 + &fbi->map_dma, PTE_BUFFERABLE);
35040 if (fbi->map_cpu) {
35041 fbi->screen_cpu = fbi->map_cpu + PAGE_SIZE;
35042 --- linux-2.4.27/fs/Config.in~2.4.27-vrs1-pxa1
35043 +++ linux-2.4.27/fs/Config.in
35045 int 'JFFS2 debugging verbosity (0 = quiet, 2 = noisy)' CONFIG_JFFS2_FS_DEBUG 0
35047 tristate 'Compressed ROM file system support' CONFIG_CRAMFS
35048 +dep_mbool ' Use linear addressing for cramfs' CONFIG_CRAMFS_LINEAR $CONFIG_CRAMFS
35049 +dep_bool ' Support XIP on linear cramfs' CONFIG_CRAMFS_LINEAR_XIP $CONFIG_CRAMFS_LINEAR
35050 +dep_bool ' Root file system on linear cramfs' CONFIG_ROOT_CRAMFS_LINEAR $CONFIG_CRAMFS_LINEAR
35051 bool 'Virtual memory file system support (former shm fs)' CONFIG_TMPFS
35052 define_bool CONFIG_RAMFS y
35054 --- linux-2.4.27/fs/cramfs/inode.c~2.4.27-vrs1-pxa1
35055 +++ linux-2.4.27/fs/cramfs/inode.c
35057 * Copyright (C) 1999 Linus Torvalds.
35059 * This file is released under the GPL.
35064 * These are the VFS interfaces to the compressed rom filesystem.
35065 * The actual compression is based on zlib, see the other files.
35067 + * Linear Addressing code
35068 + * Copyright (C) 2000 Shane Nay.
35070 + * Allows you to have a linearly addressed cramfs filesystem.
35071 + * Saves the need for buffer, and the munging of the buffer.
35072 + * Savings a bit over 32k with default PAGE_SIZE, BUFFER_SIZE
35073 + * etc. Usefull on embedded platform with ROM :-).
35075 + * Downsides- Currently linear addressed cramfs partitions
35076 + * don't co-exist with block cramfs partitions.
35078 + * 28-Dec-2000: XIP mode for linear cramfs
35079 + * Copyright (C) 2000 Robert Leslie <rob@mars.org>
35081 + * Dynamic allocation of linear cramfs space by Nicolas Pitre
35082 + * Copyright (C) 2003 Monta Vista Software, Inc.
35084 + * Linear cramfs now requires that you pass the physaddr= parameter to
35085 + * the mount process. Allows for multiple linear cramfs partitions.
35088 #include <linux/module.h>
35089 @@ -16,10 +34,12 @@
35090 #include <linux/pagemap.h>
35091 #include <linux/init.h>
35092 #include <linux/string.h>
35093 +#include <linux/kernel.h>
35094 #include <linux/locks.h>
35095 #include <linux/blkdev.h>
35096 #include <linux/cramfs_fs.h>
35097 #include <asm/semaphore.h>
35098 +#include <asm/io.h>
35100 #include <asm/uaccess.h>
35103 #define CRAMFS_SB_BLOCKS u.cramfs_sb.blocks
35104 #define CRAMFS_SB_FILES u.cramfs_sb.files
35105 #define CRAMFS_SB_FLAGS u.cramfs_sb.flags
35106 +#define CRAMFS_SB_LINEAR_PHYS_ADDR u.cramfs_sb.linear_phys_addr
35107 +#define CRAMFS_SB_LINEAR_VIRT_ADDR u.cramfs_sb.linear_virt_addr
35109 static struct super_operations cramfs_ops;
35110 static struct inode_operations cramfs_dir_inode_operations;
35112 #define CRAMINO(x) ((x)->offset?(x)->offset<<2:1)
35113 #define OFFSET(x) ((x)->i_ino)
35116 +#ifdef CONFIG_CRAMFS_LINEAR_XIP
35118 +static int cramfs_mmap(struct file *file, struct vm_area_struct *vma)
35120 + unsigned long address, length;
35121 + struct inode *inode = file->f_dentry->d_inode;
35122 + struct super_block *sb = inode->i_sb;
35124 + /* this is only used in the case of read-only maps for XIP */
35126 + if (vma->vm_flags & VM_WRITE)
35127 + return generic_file_mmap(file, vma);
35129 + if ((vma->vm_flags & VM_SHARED) && (vma->vm_flags & VM_MAYWRITE))
35132 + address = PAGE_ALIGN(sb->CRAMFS_SB_LINEAR_PHYS_ADDR + OFFSET(inode));
35133 + address += vma->vm_pgoff << PAGE_SHIFT;
35135 + length = vma->vm_end - vma->vm_start;
35137 + if (length > inode->i_size)
35138 + length = inode->i_size;
35140 + length = PAGE_ALIGN(length);
35144 + /* Doing the following makes it slower and more broken. bdl */
35146 + * Accessing memory above the top the kernel knows about or
35147 + * through a file pointer that was marked O_SYNC will be
35148 + * done non-cached.
35150 + vma->vm_page_prot =
35151 + __pgprot((pgprot_val(vma->vm_page_prot) & ~_CACHE_MASK)
35152 + | _CACHE_UNCACHED);
35156 + * Don't dump addresses that are not real memory to a core file.
35158 + vma->vm_flags |= VM_IO;
35159 + flush_tlb_page(vma, address);
35160 + if (remap_page_range(vma->vm_start, address, length,
35161 + vma->vm_page_prot))
35164 +#ifdef DEBUG_CRAMFS_XIP
35165 + printk("cramfs_mmap: mapped %s at 0x%08lx, length %lu to vma 0x%08lx"
35166 + ", page_prot 0x%08lx\n",
35167 + file->f_dentry->d_name.name, address, length,
35168 + vma->vm_start, pgprot_val(vma->vm_page_prot));
35174 +static struct file_operations cramfs_linear_xip_fops = {
35175 + read: generic_file_read,
35176 + mmap: cramfs_mmap,
35179 +#define CRAMFS_INODE_IS_XIP(x) ((x)->i_mode & S_ISVTX)
35183 static struct inode *get_cramfs_inode(struct super_block *sb, struct cramfs_inode * cramfs_inode)
35185 struct inode * inode = new_inode(sb);
35186 @@ -60,7 +150,11 @@
35187 without -noleaf option. */
35188 insert_inode_hash(inode);
35189 if (S_ISREG(inode->i_mode)) {
35190 +#ifdef CONFIG_CRAMFS_LINEAR_XIP
35191 + inode->i_fop = CRAMFS_INODE_IS_XIP(inode) ? &cramfs_linear_xip_fops : &generic_ro_fops;
35193 inode->i_fop = &generic_ro_fops;
35195 inode->i_data.a_ops = &cramfs_aops;
35196 } else if (S_ISDIR(inode->i_mode)) {
35197 inode->i_op = &cramfs_dir_inode_operations;
35198 @@ -76,6 +170,18 @@
35202 +#ifdef CONFIG_CRAMFS_LINEAR
35204 + * Return a pointer to the block in the linearly addressed cramfs image.
35206 +static void *cramfs_read(struct super_block *sb, unsigned int offset, unsigned int len)
35210 + return (void*)(sb->CRAMFS_SB_LINEAR_VIRT_ADDR + offset);
35213 +#else /* Not linear addressing - aka regular block mode. */
35215 * We have our own block cache: don't fill up the buffer cache
35216 * with the rom-image, because the way the filesystem is set
35217 @@ -192,19 +298,59 @@
35219 return read_buffers[buffer] + offset;
35222 +#endif /* !CONFIG_CRAMFS_LINEAR */
35224 static struct super_block * cramfs_read_super(struct super_block *sb, void *data, int silent)
35226 +#ifndef CONFIG_CRAMFS_LINEAR
35231 struct cramfs_super super;
35232 unsigned long root_offset;
35233 struct super_block * retval = NULL;
35235 +#ifndef CONFIG_CRAMFS_LINEAR
35236 /* Invalidate the read buffers on mount: think disk change.. */
35237 for (i = 0; i < READ_BUFFERS; i++)
35238 buffer_blocknr[i] = -1;
35243 + * The physical location of the cramfs image is specified as
35244 + * a mount parameter. This parameter is mandatory for obvious
35245 + * reasons. Some validation is made on the phys address but this
35246 + * is not exhaustive and we count on the fact that someone using
35247 + * this feature is supposed to know what he/she's doing.
35249 + if (!data || !(p = strstr((char *)data, "physaddr="))) {
35250 + printk(KERN_ERR "cramfs: unknown physical address for linear cramfs image\n");
35253 + sb->CRAMFS_SB_LINEAR_PHYS_ADDR = simple_strtoul(p + 9, NULL, 0);
35254 + if (sb->CRAMFS_SB_LINEAR_PHYS_ADDR & (PAGE_SIZE-1)) {
35255 + printk(KERN_ERR "cramfs: physical address 0x%lx for linear cramfs isn't aligned to a page boundary\n",
35256 + sb->CRAMFS_SB_LINEAR_PHYS_ADDR);
35259 + if (sb->CRAMFS_SB_LINEAR_PHYS_ADDR == 0) {
35260 + printk(KERN_ERR "cramfs: physical address for linear cramfs image can't be 0\n");
35263 + printk(KERN_INFO "cramfs: checking physical address 0x%lx for linear cramfs image\n",
35264 + sb->CRAMFS_SB_LINEAR_PHYS_ADDR);
35266 + /* Map only one page for now. Will remap it when fs size is known. */
35267 + sb->CRAMFS_SB_LINEAR_VIRT_ADDR =
35268 + ioremap(sb->CRAMFS_SB_LINEAR_PHYS_ADDR, PAGE_SIZE);
35269 + if (!sb->CRAMFS_SB_LINEAR_VIRT_ADDR) {
35270 + printk(KERN_ERR "cramfs: ioremap of the linear cramfs image failed\n");
35276 /* Read the first block and get the superblock from it */
35277 memcpy(&super, cramfs_read(sb, 0, sizeof(super)), sizeof(super));
35278 @@ -256,8 +402,26 @@
35279 /* Set it all up.. */
35280 sb->s_op = &cramfs_ops;
35281 sb->s_root = d_alloc_root(get_cramfs_inode(sb, &super.root));
35283 +#ifdef CONFIG_CRAMFS_LINEAR
35284 + /* Remap the whole filesystem now */
35285 + iounmap(sb->CRAMFS_SB_LINEAR_VIRT_ADDR);
35286 + printk(KERN_INFO "cramfs: linear cramfs image appears to be %lu KB in size\n",
35287 + sb->CRAMFS_SB_SIZE/1024);
35288 + sb->CRAMFS_SB_LINEAR_VIRT_ADDR =
35289 + ioremap(sb->CRAMFS_SB_LINEAR_PHYS_ADDR, sb->CRAMFS_SB_SIZE);
35290 + if (!sb->CRAMFS_SB_LINEAR_VIRT_ADDR) {
35291 + printk(KERN_ERR "cramfs: ioremap of the linear cramfs image failed\n");
35298 +#ifdef CONFIG_CRAMFS_LINEAR
35299 + if (!retval && sb->CRAMFS_SB_LINEAR_VIRT_ADDR)
35300 + iounmap(sb->CRAMFS_SB_LINEAR_VIRT_ADDR);
35305 @@ -390,6 +554,18 @@
35307 maxblock = (inode->i_size + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT;
35309 +#ifdef CONFIG_CRAMFS_LINEAR_XIP
35310 + if (page->index < maxblock && CRAMFS_INODE_IS_XIP(inode)) {
35311 + struct super_block *sb = inode->i_sb;
35312 + u32 blkptr_offset = PAGE_ALIGN(OFFSET(inode)) +
35313 + page->index * PAGE_CACHE_SIZE;
35314 + memcpy( page_address(page),
35315 + (void*)(sb->CRAMFS_SB_LINEAR_VIRT_ADDR + blkptr_offset),
35316 + PAGE_CACHE_SIZE );
35317 + bytes_filled = PAGE_CACHE_SIZE;
35318 + pgdata = kmap(page);
35321 if (page->index < maxblock) {
35322 struct super_block *sb = inode->i_sb;
35323 u32 blkptr_offset = OFFSET(inode) + page->index*4;
35324 @@ -446,7 +622,11 @@
35325 statfs: cramfs_statfs,
35328 +#ifndef CONFIG_CRAMFS_LINEAR
35329 static DECLARE_FSTYPE_DEV(cramfs_fs_type, "cramfs", cramfs_read_super);
35331 +static DECLARE_FSTYPE(cramfs_fs_type, "cramfs", cramfs_read_super, 0);
35334 static int __init init_cramfs_fs(void)
35337 +++ linux-2.4.27/fs/cramfs/mkcramfs.c
35340 + * mkcramfs - make a cramfs file system, optionally with XIP files.
35342 + * Copyright (C) 1999-2001 Transmeta Corporation
35344 + * This program is free software; you can redistribute it and/or modify
35345 + * it under the terms of the GNU General Public License as published by
35346 + * the Free Software Foundation; either version 2 of the License, or
35347 + * (at your option) any later version.
35349 + * This program is distributed in the hope that it will be useful,
35350 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
35351 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35352 + * GNU General Public License for more details.
35354 + * You should have received a copy of the GNU General Public License
35355 + * along with this program; if not, write to the Free Software
35356 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
35359 +#include <sys/types.h>
35360 +#include <stdio.h>
35361 +#include <sys/stat.h>
35362 +#include <unistd.h>
35363 +#include <sys/mman.h>
35364 +#include <sys/fcntl.h>
35365 +#include <dirent.h>
35366 +#include <stdlib.h>
35367 +#include <errno.h>
35368 +#include <string.h>
35369 +#include <assert.h>
35370 +#include <getopt.h>
35371 +#include <linux/cramfs_fs.h>
35374 +#define PAD_SIZE 512 /* only 0 and 512 supported by kernel */
35376 +static const char *progname = "mkcramfs";
35378 +/* N.B. If you change the disk format of cramfs, please update fs/cramfs/README. */
35380 +/* Input status of 0 to print help and exit without an error. */
35381 +static void usage(int status)
35383 + FILE *stream = status ? stderr : stdout;
35385 + fprintf(stream, "usage: %s [-h] [-e edition] [-i file] [-n name] dirname outfile\n"
35386 + " -h print this help\n"
35387 + " -E make all warnings errors (non-zero exit status)\n"
35388 + " -e edition set edition number (part of fsid)\n"
35389 + " -i file insert a file image into the filesystem (requires >= 2.4.0)\n"
35390 + " -n name set name of cramfs filesystem\n"
35391 + " -p pad by %d bytes for boot code\n"
35392 + " -s sort directory entries (old option, ignored)\n"
35393 + " -x make marked files eXecute In Place\n"
35394 + " -z make explicit holes (requires >= 2.3.39)\n"
35395 + " dirname root of the filesystem to be compressed\n"
35396 + " outfile output file\n", progname, PAD_SIZE);
35401 +#define PAGE_SIZE (4096)
35402 +#define PAGE_ALIGN(x) (((x) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1))
35403 +#define ROM_OFFSET 0
35404 +#define ROM_ALIGN(x) (PAGE_ALIGN((x) + ROM_OFFSET) - ROM_OFFSET)
35405 +#define PAGE_CACHE_SIZE (4096)
35406 +/* The kernel assumes PAGE_CACHE_SIZE as block size. */
35407 +static unsigned int blksize = PAGE_CACHE_SIZE;
35408 +static long total_blocks = 0, total_nodes = 1; /* pre-count the root node */
35409 +static int image_length = 0;
35412 + * If opt_holes is set, then mkcramfs can create explicit holes in the
35413 + * data, which saves 26 bytes per hole (which is a lot smaller a
35414 + * saving than most most filesystems).
35416 + * Note that kernels up to at least 2.3.39 don't support cramfs holes,
35417 + * which is why this is turned off by default.
35419 +static int opt_edition = 0;
35420 +static int opt_errors = 0;
35421 +static int opt_holes = 0;
35422 +static int opt_xip = 0;
35423 +static int opt_pad = 0;
35424 +static char *opt_image = NULL;
35425 +static char *opt_name = NULL;
35427 +static int warn_dev, warn_gid, warn_namelen, warn_skip, warn_size, warn_uid;
35430 +# define MIN(_a,_b) ((_a) < (_b) ? (_a) : (_b))
35433 +/* In-core version of inode / directory entry. */
35437 + unsigned int mode, size, uid, gid;
35440 + void *uncompressed;
35441 + /* points to other identical file */
35442 + struct entry *same;
35443 + unsigned int offset; /* pointer to compressed data in archive */
35444 + unsigned int dir_offset; /* Where in the archive is the directory entry? */
35446 + /* organization */
35447 + struct entry *child; /* null for non-directories and empty directories */
35448 + struct entry *next;
35452 + * The longest file name component to allow for in the input directory tree.
35453 + * Ext2fs (and many others) allow up to 255 bytes. A couple of filesystems
35454 + * allow longer (e.g. smbfs 1024), but there isn't much use in supporting
35455 + * >255-byte names in the input directory tree given that such names get
35456 + * truncated to 255 bytes when written to cramfs.
35458 +#define MAX_INPUT_NAMELEN 255
35460 +static int find_identical_file(struct entry *orig,struct entry *newfile)
35462 + if(orig==newfile) return 1;
35463 + if(!orig) return 0;
35464 + if(orig->size==newfile->size && orig->uncompressed && !memcmp(orig->uncompressed,newfile->uncompressed,orig->size)) {
35465 + newfile->same=orig;
35468 + return find_identical_file(orig->child,newfile) ||
35469 + find_identical_file(orig->next,newfile);
35472 +static void eliminate_doubles(struct entry *root,struct entry *orig) {
35474 + if(orig->size && orig->uncompressed)
35475 + find_identical_file(root,orig);
35476 + eliminate_doubles(root,orig->child);
35477 + eliminate_doubles(root,orig->next);
35482 + * We define our own sorting function instead of using alphasort which
35483 + * uses strcoll and changes ordering based on locale information.
35485 +static int cramsort (const void *a, const void *b)
35487 + return strcmp ((*(const struct dirent **) a)->d_name,
35488 + (*(const struct dirent **) b)->d_name);
35491 +static unsigned int parse_directory(struct entry *root_entry, const char *name, struct entry **prev, loff_t *fslen_ub)
35493 + struct dirent **dirlist;
35494 + int totalsize = 0, dircount, dirindex;
35495 + char *path, *endpath;
35496 + size_t len = strlen(name);
35498 + /* Set up the path. */
35499 + /* TODO: Reuse the parent's buffer to save memcpy'ing and duplication. */
35500 + path = malloc(len + 1 + MAX_INPUT_NAMELEN + 1);
35505 + memcpy(path, name, len);
35506 + endpath = path + len;
35510 + /* read in the directory and sort */
35511 + dircount = scandir(name, &dirlist, 0, cramsort);
35513 + if (dircount < 0) {
35518 + /* process directory */
35519 + for (dirindex = 0; dirindex < dircount; dirindex++) {
35520 + struct dirent *dirent;
35521 + struct entry *entry;
35526 + dirent = dirlist[dirindex];
35528 + /* Ignore "." and ".." - we won't be adding them to the archive */
35529 + if (dirent->d_name[0] == '.') {
35530 + if (dirent->d_name[1] == '\0')
35532 + if (dirent->d_name[1] == '.') {
35533 + if (dirent->d_name[2] == '\0')
35537 + namelen = strlen(dirent->d_name);
35538 + if (namelen > MAX_INPUT_NAMELEN) {
35540 + "Very long (%u bytes) filename `%s' found.\n"
35541 + " Please increase MAX_INPUT_NAMELEN in mkcramfs.c and recompile. Exiting.\n",
35542 + namelen, dirent->d_name);
35545 + memcpy(endpath, dirent->d_name, namelen + 1);
35547 + if (lstat(path, &st) < 0) {
35552 + entry = calloc(1, sizeof(struct entry));
35557 + entry->name = strdup(dirent->d_name);
35558 + if (!entry->name) {
35562 + if (namelen > 255) {
35563 + /* Can't happen when reading from ext2fs. */
35565 + /* TODO: we ought to avoid chopping in half
35566 + multi-byte UTF8 characters. */
35567 + entry->name[namelen = 255] = '\0';
35568 + warn_namelen = 1;
35570 + entry->mode = st.st_mode;
35571 + entry->size = st.st_size;
35572 + entry->uid = st.st_uid;
35573 + if (entry->uid >= 1 << CRAMFS_UID_WIDTH)
35575 + entry->gid = st.st_gid;
35576 + if (entry->gid >= 1 << CRAMFS_GID_WIDTH)
35577 + /* TODO: We ought to replace with a default
35578 + gid instead of truncating; otherwise there
35579 + are security problems. Maybe mode should
35580 + be &= ~070. Same goes for uid once Linux
35581 + supports >16-bit uids. */
35583 + size = sizeof(struct cramfs_inode) + ((namelen + 3) & ~3);
35584 + *fslen_ub += size;
35585 + if (S_ISDIR(st.st_mode)) {
35586 + entry->size = parse_directory(root_entry, path, &entry->child, fslen_ub);
35587 + } else if (S_ISREG(st.st_mode)) {
35588 + /* TODO: We ought to open files in do_compress, one
35589 + at a time, instead of amassing all these memory
35590 + maps during parse_directory (which don't get used
35591 + until do_compress anyway). As it is, we tend to
35592 + get EMFILE errors (especially if mkcramfs is run
35595 + While we're at it, do analagously for symlinks
35596 + (which would just save a little memory). */
35597 + int fd = open(path, O_RDONLY);
35603 + if (entry->size) {
35604 + if ((entry->size >= 1 << CRAMFS_SIZE_WIDTH)) {
35606 + entry->size = (1 << CRAMFS_SIZE_WIDTH) - 1;
35609 + entry->uncompressed = mmap(NULL, entry->size, PROT_READ, MAP_PRIVATE, fd, 0);
35610 + if (-1 == (int) (long) entry->uncompressed) {
35616 + } else if (S_ISLNK(st.st_mode)) {
35617 + entry->uncompressed = malloc(entry->size);
35618 + if (!entry->uncompressed) {
35622 + if (readlink(path, entry->uncompressed, entry->size) < 0) {
35627 + } else if (S_ISFIFO(st.st_mode) || S_ISSOCK(st.st_mode)) {
35628 + /* maybe we should skip sockets */
35631 + entry->size = st.st_rdev;
35632 + if (entry->size & -(1<<CRAMFS_SIZE_WIDTH))
35636 + if (S_ISREG(st.st_mode) || S_ISLNK(st.st_mode)) {
35637 + int blocks = ((entry->size - 1) / blksize + 1);
35639 + /* block pointers & data expansion allowance + data */
35641 + *fslen_ub += (4+26)*blocks + entry->size + 3;
35644 + if (opt_xip && entry->mode & S_ISVTX) {
35645 + /* worse case, depending on where the offsets falls,
35646 + * a single XIP entry could expand the sizeof the
35647 + * file system by 8k, since we're aligning the start
35648 + * and end on page boundary.
35650 + *fslen_ub += 2*PAGE_CACHE_SIZE;
35653 + /* Link it into the list */
35655 + prev = &entry->next;
35656 + totalsize += size;
35659 + free(dirlist); /* allocated by scandir() with malloc() */
35660 + return totalsize;
35663 +/* Returns sizeof(struct cramfs_super), which includes the root inode. */
35664 +static unsigned int write_superblock(struct entry *root, char *base, int size)
35666 + struct cramfs_super *super = (struct cramfs_super *) base;
35667 + unsigned int offset = sizeof(struct cramfs_super) + image_length;
35670 + offset += opt_pad;
35673 + super->magic = CRAMFS_MAGIC;
35674 + super->flags = CRAMFS_FLAG_FSID_VERSION_2 | CRAMFS_FLAG_SORTED_DIRS;
35676 + super->flags |= CRAMFS_FLAG_HOLES;
35677 + if (image_length > 0)
35678 + super->flags |= CRAMFS_FLAG_SHIFTED_ROOT_OFFSET;
35679 + super->size = size;
35680 + memcpy(super->signature, CRAMFS_SIGNATURE, sizeof(super->signature));
35682 + super->fsid.crc = crc32(0L, Z_NULL, 0);
35683 + super->fsid.edition = opt_edition;
35684 + super->fsid.blocks = total_blocks;
35685 + super->fsid.files = total_nodes;
35687 + memset(super->name, 0x00, sizeof(super->name));
35689 + strncpy(super->name, opt_name, sizeof(super->name));
35691 + strncpy(super->name, "Compressed", sizeof(super->name));
35693 + super->root.mode = root->mode;
35694 + super->root.uid = root->uid;
35695 + super->root.gid = root->gid;
35696 + super->root.size = root->size;
35697 + super->root.offset = offset >> 2;
35702 +static void set_data_offset(struct entry *entry, char *base, unsigned long offset)
35704 + struct cramfs_inode *inode = (struct cramfs_inode *) (base + entry->dir_offset);
35706 + assert ((offset & 3) == 0);
35707 +#endif /* DEBUG */
35708 + if (offset >= (1 << (2 + CRAMFS_OFFSET_WIDTH))) {
35709 + fprintf(stderr, "filesystem too big. Exiting.\n");
35712 + inode->offset = (offset >> 2);
35717 + * We do a width-first printout of the directory
35718 + * entries, using a stack to remember the directories
35721 +#define MAXENTRIES (100)
35722 +static unsigned int write_directory_structure(struct entry *entry, char *base, unsigned int offset)
35724 + int stack_entries = 0;
35725 + struct entry *entry_stack[MAXENTRIES];
35728 + int dir_start = stack_entries;
35730 + struct cramfs_inode *inode = (struct cramfs_inode *) (base + offset);
35731 + size_t len = strlen(entry->name);
35733 + entry->dir_offset = offset;
35735 + inode->mode = entry->mode;
35736 + inode->uid = entry->uid;
35737 + inode->gid = entry->gid;
35738 + inode->size = entry->size;
35739 + inode->offset = 0;
35740 + /* Non-empty directories, regfiles and symlinks will
35741 + write over inode->offset later. */
35743 + offset += sizeof(struct cramfs_inode);
35744 + total_nodes++; /* another node */
35745 + memcpy(base + offset, entry->name, len);
35746 + /* Pad up the name to a 4-byte boundary */
35747 + while (len & 3) {
35748 + *(base + offset + len) = '\0';
35751 + inode->namelen = len >> 2;
35754 + /* TODO: this may get it wrong for chars >= 0x80.
35755 + Most filesystems use UTF8 encoding for filenames,
35756 + whereas the console is a single-byte character
35757 + set like iso-latin-1. */
35758 + printf(" %s\n", entry->name);
35759 + if (entry->child) {
35760 + if (stack_entries >= MAXENTRIES) {
35761 + fprintf(stderr, "Exceeded MAXENTRIES. Raise this value in mkcramfs.c and recompile. Exiting.\n");
35764 + entry_stack[stack_entries] = entry;
35767 + entry = entry->next;
35771 + * Reverse the order the stack entries pushed during
35772 + * this directory, for a small optimization of disk
35773 + * access in the created fs. This change makes things
35774 + * `ls -UR' order.
35777 + struct entry **lo = entry_stack + dir_start;
35778 + struct entry **hi = entry_stack + stack_entries;
35779 + struct entry *tmp;
35781 + while (lo < --hi) {
35788 + /* Pop a subdirectory entry from the stack, and recurse. */
35789 + if (!stack_entries)
35792 + entry = entry_stack[stack_entries];
35794 + set_data_offset(entry, base, offset);
35795 + printf("'%s':\n", entry->name);
35796 + entry = entry->child;
35801 +static int is_zero(char const *begin, unsigned len)
35804 + /* Returns non-zero iff the first LEN bytes from BEGIN are
35806 + return (len-- == 0 ||
35807 + (begin[0] == '\0' &&
35809 + (begin[1] == '\0' &&
35811 + (begin[2] == '\0' &&
35813 + (begin[3] == '\0' &&
35814 + memcmp(begin, begin + 4, len) == 0))))))));
35816 + /* Never create holes. */
35820 +static unsigned int do_xip(char *base, unsigned int offset,
35821 + char const *name, char *uncompressed,
35822 + unsigned int size)
35824 + unsigned int start, end;
35826 + /* align to page boundary */
35828 + start = ROM_ALIGN(offset);
35829 + memset(base + offset, 0, start - offset);
35831 + memcpy(base + start, uncompressed, size);
35833 + /* pad to page boundary */
35835 + end = ROM_ALIGN(start + size);
35836 + memset(base + start + size, 0, end - (start + size));
35838 + printf("XIP (%u+%u bytes)\toffset %u\t%s\n",
35839 + size, (end - offset) - size, offset, name);
35845 + * One 4-byte pointer per block and then the actual blocked
35846 + * output. The first block does not need an offset pointer,
35847 + * as it will start immediately after the pointer block;
35848 + * so the i'th pointer points to the end of the i'th block
35849 + * (i.e. the start of the (i+1)'th block or past EOF).
35851 + * Note that size > 0, as a zero-sized file wouldn't ever
35852 + * have gotten here in the first place.
35854 +static unsigned int do_compress(char *base, unsigned int offset, char const *name, char *uncompressed, unsigned int size)
35856 + unsigned long original_size = size;
35857 + unsigned long original_offset = offset;
35858 + unsigned long new_size;
35859 + unsigned long blocks = (size - 1) / blksize + 1;
35860 + unsigned long curr = offset + 4 * blocks;
35863 + total_blocks += blocks;
35866 + unsigned long len = 2 * blksize;
35867 + unsigned int input = size;
35868 + if (input > blksize)
35871 + if (!is_zero (uncompressed, input)) {
35872 + compress(base + curr, &len, uncompressed, input);
35875 + uncompressed += input;
35877 + if (len > blksize*2) {
35878 + /* (I don't think this can happen with zlib.) */
35879 + printf("AIEEE: block \"compressed\" to > 2*blocklength (%ld)\n", len);
35883 + *(u32 *) (base + offset) = curr;
35887 + curr = (curr + 3) & ~3;
35888 + new_size = curr - original_offset;
35889 + /* TODO: Arguably, original_size in these 2 lines should be
35890 + st_blocks * 512. But if you say that then perhaps
35891 + administrative data should also be included in both. */
35892 + change = new_size - original_size;
35893 + printf("%6.2f%% (%+d bytes)\toffset %lu\t%s\n",
35894 + (change * 100) / (double) original_size, change, original_offset, name);
35901 + * Traverse the entry tree, writing data for every item that has
35902 + * non-null entry->compressed (i.e. every symlink and non-empty
35905 +static unsigned int write_data(struct entry *entry, char *base, unsigned int offset)
35908 + if (entry->uncompressed) {
35909 + if(entry->same) {
35910 + set_data_offset(entry, base, entry->same->offset);
35911 + entry->offset=entry->same->offset;
35913 + set_data_offset(entry, base, offset);
35914 + entry->offset=offset;
35915 + if (opt_xip && entry->mode & S_ISVTX)
35916 + offset = do_xip(base, offset, entry->name, entry->uncompressed, entry->size);
35918 + offset = do_compress(base, offset, entry->name, entry->uncompressed, entry->size);
35921 + else if (entry->child)
35922 + offset = write_data(entry->child, base, offset);
35923 + entry=entry->next;
35928 +static unsigned int write_file(char *file, char *base, unsigned int offset)
35933 + fd = open(file, O_RDONLY);
35938 + buf = mmap(NULL, image_length, PROT_READ, MAP_PRIVATE, fd, 0);
35939 + memcpy(base + offset, buf, image_length);
35940 + munmap(buf, image_length);
35942 + /* Pad up the image_length to a 4-byte boundary */
35943 + while (image_length & 3) {
35944 + *(base + offset + image_length) = '\0';
35947 + return (offset + image_length);
35951 + * Maximum size fs you can create is roughly 256MB. (The last file's
35952 + * data must begin within 256MB boundary but can extend beyond that.)
35954 + * Note that if you want it to fit in a ROM then you're limited to what the
35955 + * hardware and kernel can support (64MB?).
35957 +#define MAXFSLEN ((((1 << CRAMFS_OFFSET_WIDTH) - 1) << 2) /* offset */ \
35958 + + (1 << CRAMFS_SIZE_WIDTH) - 1 /* filesize */ \
35959 + + (1 << CRAMFS_SIZE_WIDTH) * 4 / PAGE_CACHE_SIZE /* block pointers */ )
35965 + * mkcramfs directory-name outfile
35967 + * where "directory-name" is simply the root of the directory
35968 + * tree that we want to generate a compressed filesystem out
35971 +int main(int argc, char **argv)
35973 + struct stat st; /* used twice... */
35974 + struct entry *root_entry;
35976 + ssize_t offset, written;
35978 + /* initial guess (upper-bound) of required filesystem size */
35979 + loff_t fslen_ub = sizeof(struct cramfs_super);
35980 + char const *dirname, *outfile;
35981 + u32 crc = crc32(0L, Z_NULL, 0);
35982 + int c; /* for getopt */
35984 + total_blocks = 0;
35987 + progname = argv[0];
35989 + /* command line options */
35990 + while ((c = getopt(argc, argv, "hEe:i:n:psxz")) != EOF) {
35998 + opt_edition = atoi(optarg);
36001 + opt_image = optarg;
36002 + if (lstat(opt_image, &st) < 0) {
36003 + perror(opt_image);
36006 + image_length = st.st_size; /* may be padded later */
36007 + fslen_ub += (image_length + 3); /* 3 is for padding */
36010 + opt_name = optarg;
36013 + opt_pad = PAD_SIZE;
36014 + fslen_ub += PAD_SIZE;
36017 + /* old option, ignored */
36028 + if ((argc - optind) != 2)
36030 + dirname = argv[optind];
36031 + outfile = argv[optind + 1];
36033 + if (stat(dirname, &st) < 0) {
36037 + fd = open(outfile, O_WRONLY | O_CREAT | O_TRUNC, 0666);
36039 + root_entry = calloc(1, sizeof(struct entry));
36040 + if (!root_entry) {
36044 + root_entry->mode = st.st_mode;
36045 + root_entry->uid = st.st_uid;
36046 + root_entry->gid = st.st_gid;
36048 + root_entry->size = parse_directory(root_entry, dirname, &root_entry->child, &fslen_ub);
36050 + /* always allocate a multiple of blksize bytes because that's
36051 + what we're going to write later on */
36052 + fslen_ub = ((fslen_ub - 1) | (blksize - 1)) + 1;
36054 + if (fslen_ub > MAXFSLEN) {
36056 + "warning: guestimate of required size (upper bound) is %LdMB, but maximum image size is %uMB. We might die prematurely.\n",
36059 + fslen_ub = MAXFSLEN;
36062 + /* find duplicate files. TODO: uses the most inefficient algorithm
36064 + eliminate_doubles(root_entry,root_entry);
36066 + /* TODO: Why do we use a private/anonymous mapping here
36067 + followed by a write below, instead of just a shared mapping
36068 + and a couple of ftruncate calls? Is it just to save us
36069 + having to deal with removing the file afterwards? If we
36070 + really need this huge anonymous mapping, we ought to mmap
36071 + in smaller chunks, so that the user doesn't need nn MB of
36072 + RAM free. If the reason is to be able to write to
36073 + un-mmappable block devices, then we could try shared mmap
36074 + and revert to anonymous mmap if the shared mmap fails. */
36075 + rom_image = mmap(NULL, fslen_ub?fslen_ub:1, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
36077 + if (-1 == (int) (long) rom_image) {
36078 + perror("ROM image map");
36082 + /* Skip the first opt_pad bytes for boot loader code */
36083 + offset = opt_pad;
36084 + memset(rom_image, 0x00, opt_pad);
36086 + /* Skip the superblock and come back to write it later. */
36087 + offset += sizeof(struct cramfs_super);
36089 + /* Insert a file image. */
36091 + printf("Including: %s\n", opt_image);
36092 + offset = write_file(opt_image, rom_image, offset);
36095 + offset = write_directory_structure(root_entry->child, rom_image, offset);
36096 + printf("Directory data: %d bytes\n", offset);
36098 + offset = write_data(root_entry, rom_image, offset);
36100 + /* We always write a multiple of blksize bytes, so that
36101 + losetup works. */
36102 + offset = ((offset - 1) | (blksize - 1)) + 1;
36103 + printf("Everything: %d kilobytes\n", offset >> 10);
36105 + /* Write the superblock now that we can fill in all of the fields. */
36106 + write_superblock(root_entry, rom_image+opt_pad, offset);
36107 + printf("Super block: %d bytes\n", sizeof(struct cramfs_super));
36109 + /* Put the checksum in. */
36110 + crc = crc32(crc, (rom_image+opt_pad), (offset-opt_pad));
36111 + ((struct cramfs_super *) (rom_image+opt_pad))->fsid.crc = crc;
36112 + printf("CRC: %x\n", crc);
36114 + /* Check to make sure we allocated enough space. */
36115 + if (fslen_ub < offset) {
36116 + fprintf(stderr, "not enough space allocated for ROM image (%Ld allocated, %d used)\n",
36117 + fslen_ub, offset);
36121 + written = write(fd, rom_image, offset);
36122 + if (written < 0) {
36123 + perror("ROM image");
36126 + if (offset != written) {
36127 + fprintf(stderr, "ROM image write failed (%d %d)\n", written, offset);
36131 + /* (These warnings used to come at the start, but they scroll off the
36132 + screen too quickly.) */
36133 + if (warn_namelen) /* (can't happen when reading from ext2fs) */
36134 + fprintf(stderr, /* bytes, not chars: think UTF8. */
36135 + "warning: filenames truncated to 255 bytes.\n");
36137 + fprintf(stderr, "warning: files were skipped due to errors.\n");
36140 + "warning: file sizes truncated to %luMB (minus 1 byte).\n",
36141 + 1L << (CRAMFS_SIZE_WIDTH - 20));
36142 + if (warn_uid) /* (not possible with current Linux versions) */
36144 + "warning: uids truncated to %u bits. (This may be a security concern.)\n",
36145 + CRAMFS_UID_WIDTH);
36148 + "warning: gids truncated to %u bits. (This may be a security concern.)\n",
36149 + CRAMFS_GID_WIDTH);
36152 + "WARNING: device numbers truncated to %u bits. This almost certainly means\n"
36153 + "that some device files will be wrong.\n",
36154 + CRAMFS_OFFSET_WIDTH);
36155 + if (opt_errors &&
36156 + (warn_namelen||warn_skip||warn_size||warn_uid||warn_gid||warn_dev))
36161 +++ linux-2.4.27/include/asm-arm/arch-pxa/bitfield.h
36164 + * FILE bitfield.h
36167 + * Author Copyright (c) Marc A. Viredaz, 1998
36168 + * DEC Western Research Laboratory, Palo Alto, CA
36169 + * Date April 1998 (April 1997)
36170 + * System Advanced RISC Machine (ARM)
36171 + * Language C or ARM Assembly
36172 + * Purpose Definition of macros to operate on bit fields.
36177 +#ifndef __BITFIELD_H
36178 +#define __BITFIELD_H
36180 +#ifndef __ASSEMBLY__
36181 +#define UData(Data) ((unsigned long) (Data))
36183 +#define UData(Data) (Data)
36191 + * The macro "Fld" encodes a bit field, given its size and its shift value
36192 + * with respect to bit 0.
36195 + * A more intuitive way to encode bit fields would have been to use their
36196 + * mask. However, extracting size and shift value information from a bit
36197 + * field's mask is cumbersome and might break the assembler (255-character
36198 + * line-size limit).
36201 + * Size Size of the bit field, in number of bits.
36202 + * Shft Shift value of the bit field with respect to bit 0.
36205 + * Fld Encoded bit field.
36208 +#define Fld(Size, Shft) (((Size) << 16) + (Shft))
36212 + * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
36215 + * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
36216 + * the size, shift value, mask, aligned mask, and first bit of a
36220 + * Field Encoded bit field (using the macro "Fld").
36223 + * FSize Size of the bit field, in number of bits.
36224 + * FShft Shift value of the bit field with respect to bit 0.
36225 + * FMsk Mask for the bit field.
36226 + * FAlnMsk Mask for the bit field, aligned on bit 0.
36227 + * F1stBit First bit of the bit field.
36230 +#define FSize(Field) ((Field) >> 16)
36231 +#define FShft(Field) ((Field) & 0x0000FFFF)
36232 +#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
36233 +#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
36234 +#define F1stBit(Field) (UData (1) << FShft (Field))
36241 + * The macro "FInsrt" inserts a value into a bit field by shifting the
36242 + * former appropriately.
36245 + * Value Bit-field value.
36246 + * Field Encoded bit field (using the macro "Fld").
36249 + * FInsrt Bit-field value positioned appropriately.
36252 +#define FInsrt(Value, Field) \
36253 + (UData (Value) << FShft (Field))
36260 + * The macro "FExtr" extracts the value of a bit field by masking and
36261 + * shifting it appropriately.
36264 + * Data Data containing the bit-field to be extracted.
36265 + * Field Encoded bit field (using the macro "Fld").
36268 + * FExtr Bit-field value.
36271 +#define FExtr(Data, Field) \
36272 + ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
36275 +#endif /* __BITFIELD_H */
36277 +++ linux-2.4.27/include/asm-arm/arch-pxa/cerf.h
36280 + * linux/include/asm-arm/arch-pxa/cerf.h
36282 + * This program is free software; you can redistribute it and/or modify
36283 + * it under the terms of the GNU General Public License version 2 as
36284 + * published by the Free Software Foundation.
36288 + * Add CerfBoard Specifics here...
36295 +#define CERF_RAM_BASE 0xa0000000
36297 +#ifdef CONFIG_PXA_CERF_RAM_128MB
36298 +#define CERF_RAM_SIZE 128*1024*1024
36300 +#elif defined (CONFIG_PXA_CERF_RAM_64MB)
36301 +#define CERF_RAM_SIZE 64*1024*1024
36303 +#elif defined (CONFIG_PXA_CERF_RAM_32MB)
36304 +#define CERF_RAM_SIZE 32*1024*1024
36306 +#elif defined (CONFIG_PXA_CERF_RAM_16MB)
36307 +#define CERF_RAM_SIZE 16*1024*1024
36311 + * CS memory timing via Static Memory Control Register (MSC0-2)
36314 +#define MSC_CS(cs,val) ((val)<<((cs&1)<<4))
36316 +#define MSC_RBUFF_SHIFT 15
36317 +#define MSC_RBUFF_SLOW (0)
36318 +#define MSC_RBUFF_FAST (1)
36319 +#define MSC_RBUFF(x) ((x)<<MSC_RBUFF_SHIFT)
36321 +#define MSC_RRR_SHIFT 12
36322 +#define MSC_RRR(x) ((x)<<MSC_RRR_SHIFT)
36324 +#define MSC_RDN_SHIFT 8
36325 +#define MSC_RDN(x) ((x)<<MSC_RDN_SHIFT)
36327 +#define MSC_RDF_SHIFT 4
36328 +#define MSC_RDF(x) ((x)<<MSC_RDF_SHIFT)
36330 +#define MSC_RBW_SHIFT 3
36331 +#define MSC_RBW(x) ((x)<<MSC_RBW_SHIFT)
36333 +#define MSC_RT_SHIFT 0
36334 +#define MSC_RT(x) ((x)<<MSC_RT_SHIFT)
36337 + * IO Pins for devices
36340 +#define CERF_FLASH_BASE 0xe8000000
36341 +#define CERF_FLASH_SIZE 0x02000000
36342 +#define CERF_FLASH_PHYS PXA_CS0_PHYS
36344 +#define CERF_ETH_BASE 0xf0000000
36345 +#define CERF_ETH_SIZE 0x00100000
36346 +#define CERF_ETH_PHYS PXA_CS1_PHYS
36348 +#define CERF_BT_BASE 0xf2000000
36349 +#define CERF_BT_SIZE 0x00100000
36350 +#define CERF_BT_PHYS PXA_CS2_PHYS
36352 +#define CERF_SERIAL_BASE 0xf3000000
36353 +#define CERF_SERIAL_SIZE 0x00100000
36354 +#define CERF_SERIAL_PHYS PXA_CS3_PHYS
36356 +#define CERF_CPLD_BASE 0xf1000000
36357 +#define CERF_CPLD_SIZE 0x00100000
36358 +#define CERF_CPLD_PHYS PXA_CS4_PHYS
36360 +#define CERF_PDA_CPLD_WRCLRINT (0x0)
36361 +#define CERF_PDA_CPLD_BRIGHTNESS (0x2)
36362 +#define CERF_PDA_CPLD_KEYPAD_A (0x6)
36363 +#define CERF_PDA_CPLD_BATTFAULT (0x8)
36364 +#define CERF_PDA_CPLD_KEYPAD_B (0xa)
36365 +#define CERF_PDA_CPLD_SOUND_ENA (0xc)
36367 +#define CERF_PDA_SOUND_ENABLE 0x1
36368 +#define CERF_PDA_DEFAULT_BRIGHTNESS 0x9
36371 + * Access functions (registers are 4-bit wide)
36374 +#define CERF_PDA_CPLD CERF_CPLD_BASE
36376 +#define CERF_PDA_CPLD_Get(x, y) (*((char*)(CERF_PDA_CPLD + (x))) & (y))
36377 +#define CERF_PDA_CPLD_Set(x, y, z) (*((char*)(CERF_PDA_CPLD + (x))) = (*((char*)(CERF_PDA_CPLD + (x))) & ~(z)) | (y))
36378 +#define CERF_PDA_CPLD_UnSet(x, y, z) (*((char*)(CERF_PDA_CPLD + (x))) = (*((char*)(CERF_PDA_CPLD + (x))) & ~(z)) & ~(y))
36381 + * IO and IRQ settings for cs8900 ethernet chip
36383 +#define CERF_ETH_IO CERF_ETH_BASE
36384 +#define CERF_ETH_IRQ GPIO_2_80_TO_IRQ(21)
36387 + * We only have one LED on the XScale CerfPDA so only the
36388 + * time or idle should ever be selected.
36390 +#define CERF_HEARTBEAT_LED 0x1
36391 +#define CERF_SYS_BUSY_LED 0x2
36393 +#define CERF_HEARTBEAT_LED_GPIO 16 // GPIO 4
36394 +#define CERF_SYS_BUSY_LED_GPIO 16 // GPIO 4
36396 +#define CERF_HEARTBEAT_LED_ON (GPSR0 = CERF_HEARTBEAT_LED_GPIO)
36397 +#define CERF_HEARTBEAT_LED_OFF (GPCR0 = CERF_HEARTBEAT_LED_GPIO)
36398 +#define CERF_SYS_BUSY_LED_ON (GPSR0 = CERF_SYS_BUSY_LED_GPIO)
36399 +#define CERF_SYS_BUSY_LED_OFF (GPCR0 = CERF_SYS_BUSY_LED_GPIO)
36405 +#define CERF_GPIO_UCB1400_IRQ 32
36407 +#define UCB_IO_0 (1 << 0)
36408 +#define UCB_IO_1 (1 << 1)
36409 +#define UCB_IO_2 (1 << 2)
36410 +#define UCB_IO_3 (1 << 3)
36411 +#define UCB_IO_4 (1 << 4)
36412 +#define UCB_IO_5 (1 << 5)
36413 +#define UCB_IO_6 (1 << 6)
36414 +#define UCB_IO_7 (1 << 7)
36415 +#define UCB_IO_8 (1 << 8)
36416 +#define UCB_IO_9 (1 << 9)
36418 +#define UCB1400_GPIO_CONT_CS UCB_IO_0
36419 +#define UCB1400_GPIO_CONT_DOWN UCB_IO_1
36420 +#define UCB1400_GPIO_CONT_INC UCB_IO_2
36421 +#define UCB1400_GPIO_CONT_ENA UCB_IO_3
36422 +#define UCB1400_GPIO_LCD_RESET UCB_IO_4
36423 +#define UCB1400_GPIO_IRDA_ENABLE UCB_IO_5
36424 +#define UCB1400_GPIO_BT_ENABLE UCB_IO_6
36425 +#define UCB1400_GPIO_TEST_P1 UCB_IO_7
36426 +#define UCB1400_GPIO_TEST_P2 UCB_IO_8
36427 +#define UCB1400_GPIO_TEST_P3 UCB_IO_9
36430 + * IRQ for devices
36432 +#define UCB1400_IRQ(x) (NR_IRQS + 1 + (x))
36434 +#define IRQ_UCB1400_IO0 UCB1400_IRQ(0)
36435 +#define IRQ_UCB1400_IO1 UCB1400_IRQ(1)
36436 +#define IRQ_UCB1400_IO2 UCB1400_IRQ(2)
36437 +#define IRQ_UCB1400_IO3 UCB1400_IRQ(3)
36438 +#define IRQ_UCB1400_IO4 UCB1400_IRQ(4)
36439 +#define IRQ_UCB1400_IO5 UCB1400_IRQ(5)
36440 +#define IRQ_UCB1400_IO6 UCB1400_IRQ(6)
36441 +#define IRQ_UCB1400_IO7 UCB1400_IRQ(7)
36442 +#define IRQ_UCB1400_IO8 UCB1400_IRQ(8)
36443 +#define IRQ_UCB1400_IO9 UCB1400_IRQ(9)
36445 +#define IRQ_UCB1400_CONT_CS IRQ_UCB1400_IO0
36446 +#define IRQ_UCB1400_CONT_DOWN IRQ_UCB1400_IO1
36447 +#define IRQ_UCB1400_CONT_INC IRQ_UCB1400_IO2
36448 +#define IRQ_UCB1400_CONT_ENA IRQ_UCB1400_IO3
36449 +#define IRQ_UCB1400_LCD_RESET IRQ_UCB1400_IO4
36450 +#define IRQ_UCB1400_IRDA_ENABLE IRQ_UCB1400_IO5
36451 +#define IRQ_UCB1400_BT_ENABLE IRQ_UCB1400_IO6
36452 +#define IRQ_UCB1400_TEST_P1 IRQ_UCB1400_IO7
36453 +#define IRQ_UCB1400_TEST_P2 IRQ_UCB1400_IO8
36454 +#define IRQ_UCB1400_TEST_P3 IRQ_UCB1400_IO9
36457 +++ linux-2.4.27/include/asm-arm/arch-pxa/cerf_ucb1400gpio.h
36460 + * cerf_ucb1400gpio.h
36462 + * UCB1400 GPIO control stuff for the cerf.
36464 + * Copyright (C) 2002 Intrinsyc Software Inc.
36466 + * This program is free software; you can redistribute it and/or modify
36467 + * it under the terms of the GNU General Public License version 2 as
36468 + * published by the Free Software Foundation.
36471 + * Mar 2002: Initial version [FB]
36475 +extern void cerf_ucb1400gpio_lcd_enable( void);
36476 +extern void cerf_ucb1400gpio_lcd_disable( void);
36477 +extern void cerf_ucb1400gpio_lcd_contrast_step( int direction);
36480 +extern void cerf_ucb1400gpio_irda_enable( void);
36481 +extern void cerf_ucb1400gpio_irda_disable( void);
36484 +extern void cerf_ucb1400gpio_bt_enable( void);
36485 +extern void cerf_ucb1400gpio_bt_disable( void);
36488 +extern int cerf_ucb1400gpio_init(void);
36490 +++ linux-2.4.27/include/asm-arm/arch-pxa/csb226.h
36493 + * linux/include/asm-arm/arch-pxa/csb226.h
36495 + * Author: Robert Schwebel (stolen from lubbock.h)
36496 + * Created: Oct 30, 2002
36497 + * Copyright: Pengutronix
36499 + * This program is free software; you can redistribute it and/or modify
36500 + * it under the terms of the GNU General Public License version 2 as
36501 + * published by the Free Software Foundation.
36504 +#define CSB226_FPGA_PHYS PXA_CS2_PHYS
36506 +#define CSB226_FPGA_VIRT (0xf0000000) /* phys 0x08000000 */
36507 +#define CSB226_ETH_BASE (0xf1000000) /* phys 0x0c000000 */
36509 +#define CSB226_P2V(x) ((x) - CSB226_FPGA_PHYS + CSB226_FPGA_VIRT)
36510 +#define CSB226_V2P(x) ((x) - CSB226_FPGA_VIRT + CSB226_FPGA_PHYS)
36512 +#ifndef __ASSEMBLY__
36513 +# define __CSB226_REG(x) (*((volatile unsigned long *)CSB226_P2V(x)))
36515 +# define __CSB226_REG(x) CSB226_P2V(x)
36519 +/* register physical addresses */
36520 +#define _CSB226_MISC_WR (CSB226_FPGA_PHYS + 0x080)
36521 +#define _CSB226_MISC_RD (CSB226_FPGA_PHYS + 0x090)
36522 +#define _CSB226_IRQ_MASK_EN (CSB226_FPGA_PHYS + 0x0C0)
36523 +#define _CSB226_IRQ_SET_CLR (CSB226_FPGA_PHYS + 0x0D0)
36524 +#define _CSB226_GP (CSB226_FPGA_PHYS + 0x100)
36528 +/* register virtual addresses */
36530 +#define CSB226_MISC_WR __CSB226_REG(_CSB226_MISC_WR)
36531 +#define CSB226_MISC_RD __CSB226_REG(_CSB226_MISC_RD)
36532 +#define CSB226_IRQ_MASK_EN __CSB226_REG(_CSB226_IRQ_MASK_EN)
36533 +#define CSB226_IRQ_SET_CLR __CSB226_REG(_CSB226_IRQ_SET_CLR)
36534 +#define CSB226_GP __CSB226_REG(_CSB226_GP)
36539 +#define GPIO_CSB226_IRQ 0
36540 +#define IRQ_GPIO_CSB226_IRQ IRQ_GPIO0
36547 +// #define LEDS_BASE LUB_DISC_BLNK_LED
36549 +// 8 discrete leds available for general use:
36562 +/* Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays so
36563 +* be sure to not monkey with them here.
36567 +#define HEARTBEAT_LED D28
36568 +#define SYS_BUSY_LED D27
36569 +#define HEXLEDS_BASE LUB_HEXLED
36571 +#define HEARTBEAT_LED_ON (LEDS_BASE &= ~HEARTBEAT_LED)
36572 +#define HEARTBEAT_LED_OFF (LEDS_BASE |= HEARTBEAT_LED)
36573 +#define SYS_BUSY_LED_OFF (LEDS_BASE |= SYS_BUSY_LED)
36574 +#define SYS_BUSY_LED_ON (LEDS_BASE &= ~SYS_BUSY_LED)
36576 +// use x = D26-D21 for these, please...
36577 +#define DISCRETE_LED_ON(x) (LEDS_BASE &= ~(x))
36578 +#define DISCRETE_LED_OFF(x) (LEDS_BASE |= (x))
36581 +#ifndef __ASSEMBLY__
36583 +//extern int hexled_val = 0;
36588 +#define BUMP_COUNTER (HEXLEDS_BASE = hexled_val++)
36589 +#define DEC_COUNTER (HEXLEDS_BASE = hexled_val--)
36592 +++ linux-2.4.27/include/asm-arm/arch-pxa/dma.h
36595 + * linux/include/asm-arm/arch-pxa/dma.h
36597 + * Author: Nicolas Pitre
36598 + * Created: Jun 15, 2001
36599 + * Copyright: MontaVista Software, Inc.
36601 + * This program is free software; you can redistribute it and/or modify
36602 + * it under the terms of the GNU General Public License version 2 as
36603 + * published by the Free Software Foundation.
36605 +#ifndef __ASM_ARCH_DMA_H
36606 +#define __ASM_ARCH_DMA_H
36608 +#define MAX_DMA_ADDRESS 0xffffffff
36610 +/* No DMA as the rest of the world see it */
36611 +#define MAX_DMA_CHANNELS 0
36614 + * Descriptor structure for PXA's DMA engine
36615 + * Note: this structure must always be aligned to a 16-byte boundary.
36619 + volatile u32 ddadr; /* Points to the next descriptor + flags */
36620 + volatile u32 dsadr; /* DSADR value for the current transfer */
36621 + volatile u32 dtadr; /* DTADR value for the current transfer */
36622 + volatile u32 dcmd; /* DCMD value for the current transfer */
36626 + * DMA registration
36630 + DMA_PRIO_HIGH = 0,
36631 + DMA_PRIO_MEDIUM = 4,
36635 +int pxa_request_dma (char *name,
36636 + pxa_dma_prio prio,
36637 + void (*irq_handler)(int, void *, struct pt_regs *),
36640 +void pxa_free_dma (int dma_ch);
36642 +#endif /* _ASM_ARCH_DMA_H */
36644 +++ linux-2.4.27/include/asm-arm/arch-pxa/hardware.h
36647 + * linux/include/asm-arm/arch-pxa/hardware.h
36649 + * Author: Nicolas Pitre
36650 + * Created: Jun 15, 2001
36651 + * Copyright: MontaVista Software Inc.
36653 + * This program is free software; you can redistribute it and/or modify
36654 + * it under the terms of the GNU General Public License version 2 as
36655 + * published by the Free Software Foundation.
36658 +#ifndef __ASM_ARCH_HARDWARE_H
36659 +#define __ASM_ARCH_HARDWARE_H
36661 +#include <linux/config.h>
36662 +#include <asm/mach-types.h>
36666 + * These are statically mapped PCMCIA IO space for designs using it as a
36667 + * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc.
36668 + * The actual PCMCIA code is mapping required IO region at run time.
36670 +#define PCMCIA_IO_0_BASE 0xf6000000
36671 +#define PCMCIA_IO_1_BASE 0xf7000000
36675 + * XIP kernel text mapping.
36676 + * Note: the exact virtual address is also specified in arch/arm/Makefile.
36678 +#ifdef CONFIG_XIP_KERNEL
36679 +#define KERNEL_XIP_BASE_PHYS (CONFIG_XIP_PHYS_ADDR & 0xffe00000)
36680 +#define KERNEL_XIP_BASE_VIRT 0xe8000000
36685 + * We requires absolute addresses.
36687 +#define PCIO_BASE 0
36690 + * Workarounds for at least 2 errata so far require this.
36691 + * The mapping is set in mach-pxa/generic.c.
36693 +#define UNCACHED_PHYS_0 0xff000000
36694 +#define UNCACHED_ADDR UNCACHED_PHYS_0
36697 + * Intel PXA internal I/O mappings:
36699 + * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
36700 + * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
36701 + * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
36704 +#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
36705 +#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
36707 +#ifndef __ASSEMBLY__
36710 +# define __REG(x) (*((volatile u32 *)io_p2v(x)))
36713 + * This __REG() version gives the same results as the one above, except
36714 + * that we are fooling gcc somehow so it generates far better and smaller
36715 + * assembly code for access to contigous registers. It's a shame that gcc
36716 + * doesn't guess this by itself.
36718 +#include <asm/types.h>
36719 +typedef struct { volatile u32 offset[4096]; } __regbase;
36720 +# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
36721 +# define __REG(x) __REGP(io_p2v(x))
36724 +/* Let's kick gcc's ass again... */
36725 +# define __REG2(x,y) \
36726 + ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
36727 + : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
36729 +# define __PREG(x) (io_v2p((u32)&(x)))
36733 +# define __REG(x) io_p2v(x)
36734 +# define __PREG(x) io_v2p(x)
36738 +#include "pxa-regs.h"
36740 +#ifndef __ASSEMBLY__
36743 + * GPIO edge detection for IRQs:
36744 + * IRQs are generated on Falling-Edge, Rising-Edge, or both.
36745 + * This must be called *before* the corresponding IRQ is registered.
36746 + * Use this instead of directly setting GRER/GFER.
36748 +#define GPIO_FALLING_EDGE 1
36749 +#define GPIO_RISING_EDGE 2
36750 +#define GPIO_BOTH_EDGES 3
36751 +extern void set_GPIO_IRQ_edge( int gpio_nr, int edge_mask );
36754 + * Handy routine to set GPIO alternate functions
36756 +extern void set_GPIO_mode( int gpio_mode );
36759 + * return current lclk frequency in units of 10kHz
36761 +extern unsigned int get_lclk_frequency_10khz(void);
36764 + * return current clk frequency in units of 1kHz
36766 +extern unsigned int get_clk_frequency_khz( int info);
36772 + * Implementation specifics
36775 +//#ifdef CONFIG_ARCH_LUBBOCK
36776 +#include "lubbock.h"
36779 +//#ifdef CONFIG_ARCH_PXA_IDP
36783 +//#ifdef CONFIG_ARCH_PXA_CERF
36787 +#endif /* _ASM_ARCH_HARDWARE_H */
36789 +++ linux-2.4.27/include/asm-arm/arch-pxa/ide.h
36792 + * linux/include/asm-arm/arch-pxa/ide.h
36794 + * Author: George Davis
36795 + * Created: Jan 10, 2002
36796 + * Copyright: MontaVista Software Inc.
36798 + * This program is free software; you can redistribute it and/or modify
36799 + * it under the terms of the GNU General Public License version 2 as
36800 + * published by the Free Software Foundation.
36803 + * Originally based upon linux/include/asm-arm/arch-sa1100/ide.h
36807 +#include <linux/config.h>
36808 +#include <asm/irq.h>
36809 +#include <asm/hardware.h>
36810 +#include <asm/mach-types.h>
36814 + * Set up a hw structure for a specified data port, control port and IRQ.
36815 + * This should follow whatever the default interface uses.
36817 +static __inline__ void
36818 +ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int *irq)
36822 + memset(hw, 0, sizeof(*hw));
36824 + reg = (ide_ioreg_t)data_port;
36826 + hw->io_ports[IDE_DATA_OFFSET] = reg + 0;
36827 + hw->io_ports[IDE_ERROR_OFFSET] = reg + 1;
36828 + hw->io_ports[IDE_NSECTOR_OFFSET] = reg + 2;
36829 + hw->io_ports[IDE_SECTOR_OFFSET] = reg + 3;
36830 + hw->io_ports[IDE_LCYL_OFFSET] = reg + 4;
36831 + hw->io_ports[IDE_HCYL_OFFSET] = reg + 5;
36832 + hw->io_ports[IDE_SELECT_OFFSET] = reg + 6;
36833 + hw->io_ports[IDE_STATUS_OFFSET] = reg + 7;
36835 + hw->io_ports[IDE_CONTROL_OFFSET] = (ide_ioreg_t) ctrl_port;
36843 + * Register the standard ports for this architecture with the IDE driver.
36845 +static __inline__ void
36846 +ide_init_default_hwifs(void)
36848 + /* Nothing to declare... */
36851 +++ linux-2.4.27/include/asm-arm/arch-pxa/idp.h
36854 + * linux/include/asm-arm/arch-pxa/idp.h
36856 + * This program is free software; you can redistribute it and/or modify
36857 + * it under the terms of the GNU General Public License version 2 as
36858 + * published by the Free Software Foundation.
36860 + * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
36862 + * 2001-09-13: Cliff Brake <cbrake@accelent.com>
36869 + * Note: this file must be safe to include in assembly files
36872 +/* comment out following if you have a rev01 board */
36873 +#define PXA_IDP_REV02 1
36874 +//#undef PXA_IDP_REV02
36876 +#ifdef PXA_IDP_REV02
36878 +//Use this as well for 0017-x004 and greater pcb's:
36879 +#define PXA_IDP_REV04 1
36881 +#define IDP_FLASH_PHYS (PXA_CS0_PHYS)
36882 +#define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS)
36883 +#define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS)
36884 +#define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000)
36885 +#define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000)
36886 +#define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000)
36887 +#define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000)
36891 + * virtual memory map
36894 +#define IDP_IDE_BASE (0xf0000000)
36895 +#define IDP_IDE_SIZE (1*1024*1024)
36897 +#define IDP_ETH_BASE (IDP_IDE_BASE + IDP_IDE_SIZE)
36898 +#define IDP_ETH_SIZE (1*1024*1024)
36899 +#define ETH_BASE IDP_ETH_BASE //smc9194 driver compatibility issue
36901 +#define IDP_COREVOLT_BASE (IDP_ETH_BASE + IDP_ETH_SIZE)
36902 +#define IDP_COREVOLT_SIZE (1*1024*1024)
36904 +#define IDP_CPLD_BASE (IDP_COREVOLT_BASE + IDP_COREVOLT_SIZE)
36905 +#define IDP_CPLD_SIZE (1*1024*1024)
36907 +#if (IDP_CPLD_BASE + IDP_CPLD_SIZE) > 0xfc000000
36908 +#error Your custom IO space is getting a bit large !!
36911 +#define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_BASE)
36912 +#define CPLD_V2P(x) ((x) - IDP_CPLD_BASE + IDP_CPLD_PHYS)
36914 +#ifndef __ASSEMBLY__
36915 +# define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x)))
36917 +# define __CPLD_REG(x) CPLD_P2V(x)
36920 +/* board level registers in the CPLD: (offsets from CPLD_BASE) */
36922 +#define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00)
36923 +#define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04)
36924 +#define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08)
36925 +#define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C)
36926 +#define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10)
36927 +#define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14)
36928 +#define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18)
36929 +#define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C)
36930 +#define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20)
36931 +#define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24)
36932 +#define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28)
36933 +#define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C)
36934 +#define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30)
36935 +#define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34)
36937 +#define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50)
36938 +#define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54)
36939 +#define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58)
36940 +#define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C)
36942 +/* FPGA register virtual addresses */
36944 +#define IDP_CPLD_REV __CPLD_REG(_IDP_CPLD_REV)
36945 +#define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR)
36946 +#define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL)
36947 +#define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH)
36948 +#define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW)
36949 +#define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN)
36950 +#define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR)
36951 +#define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE)
36952 +#define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR)
36953 +#define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE)
36954 +#define IDP_CPLD_PCCARD_PWR __CPLD_REG(_IDP_CPLD_PCCARD_PWR)
36955 +#define IDP_CPLD_MISC_CTRL __CPLD_REG(_IDP_CPLD_MISC_CTRL)
36956 +#define IDP_CPLD_LCD __CPLD_REG(_IDP_CPLD_LCD)
36957 +#define IDP_CPLD_FLASH_WE __CPLD_REG(_IDP_CPLD_FLASH_WE)
36959 +#define IDP_CPLD_KB_ROW __CPLD_REG(_IDP_CPLD_KB_ROW)
36960 +#define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS)
36961 +#define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS)
36962 +#define IDP_CPLD_MISC_STATUS __CPLD_REG(_IDP_CPLD_MISC_STATUS)
36966 + * Bit masks for various registers
36968 +// IDP_CPLD_PCCARD_PWR
36969 +#define PCC0_PWR0 (1 << 0)
36970 +#define PCC0_PWR1 (1 << 1)
36971 +#define PCC0_PWR2 (1 << 2)
36972 +#define PCC0_PWR3 (1 << 3)
36973 +#define PCC1_PWR0 (1 << 4)
36974 +#define PCC1_PWR1 (1 << 5)
36975 +#define PCC1_PWR2 (1 << 6)
36976 +#define PCC1_PWR3 (1 << 7)
36978 +// IDP_CPLD_PCCARD_EN
36979 +#define PCC0_RESET (1 << 6)
36980 +#define PCC1_RESET (1 << 7)
36981 +#define PCC0_ENABLE (1 << 0)
36982 +#define PCC1_ENABLE (1 << 1)
36984 +// IDP_CPLD_PCCARDx_STATUS
36985 +#define _PCC_WRPROT (1 << 7) // 7-4 read as low true
36986 +#define _PCC_RESET (1 << 6)
36987 +#define _PCC_IRQ (1 << 5)
36988 +#define _PCC_INPACK (1 << 4)
36989 +#define PCC_BVD2 (1 << 3)
36990 +#define PCC_BVD1 (1 << 2)
36991 +#define PCC_VS2 (1 << 1)
36992 +#define PCC_VS1 (1 << 0)
36994 +#define PCC_DETECT(x) (GPLR(7 + (x)) & GPIO_bit(7 + (x)))
36997 + * Macros for LCD Driver
37000 +#ifdef CONFIG_FB_PXA
37002 +#define FB_BACKLIGHT_ON() (IDP_CPLD_LCD |= (1<<1))
37003 +#define FB_BACKLIGHT_OFF() (IDP_CPLD_LCD &= ~(1<<1))
37005 +#define FB_PWR_ON() (IDP_CPLD_LCD |= (1<< 0))
37006 +#define FB_PWR_OFF() (IDP_CPLD_LCD &= ~(1<<0))
37008 +#define FB_VLCD_ON() (IDP_CPLD_LCD |= (1<<2))
37009 +#define FB_VLCD_OFF() (IDP_CPLD_LCD &= ~(1<<2))
37013 +/* A listing of interrupts used by external hardware devices */
37015 +#ifdef PXA_IDP_REV04
37016 +#define TOUCH_PANEL_IRQ IRQ_GPIO(5)
37017 +#define IDE_IRQ IRQ_GPIO(21)
37019 +#define TOUCH_PANEL_IRQ IRQ_GPIO(21)
37020 +#define IDE_IRQ IRQ_GPIO(5)
37023 +#define TOUCH_PANEL_IRQ_EDGE GPIO_FALLING_EDGE
37025 +#define IDE_IRQ_EDGE GPIO_RISING_EDGE
37027 +#define ETHERNET_IRQ IRQ_GPIO(4)
37028 +#define ETHERNET_IRQ_EDGE GPIO_RISING_EDGE
37030 +#define IDE_IRQ_EDGE GPIO_RISING_EDGE
37032 +#define PCMCIA_S0_CD_VALID IRQ_GPIO(7)
37033 +#define PCMCIA_S0_CD_VALID_EDGE GPIO_BOTH_EDGES
37035 +#define PCMCIA_S1_CD_VALID IRQ_GPIO(8)
37036 +#define PCMCIA_S1_CD_VALID_EDGE GPIO_BOTH_EDGES
37038 +#define PCMCIA_S0_RDYINT IRQ_GPIO(19)
37039 +#define PCMCIA_S1_RDYINT IRQ_GPIO(22)
37042 + * Macros for LED Driver
37046 +#define IDP_HB_LED (1<<5)
37047 +#define IDP_BUSY_LED (1<<6)
37049 +#define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED)
37051 +#define IDP_WRITE_LEDS(value) (IDP_CPLD_LED_CONTROL = (IDP_CPLD_LED_CONTROL & (~(IDP_LEDS_MASK)) | value))
37054 + * macros for MTD driver
37057 +#define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1))
37058 +#define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1))
37061 + * macros for matrix keyboard driver
37064 +#define KEYBD_MATRIX_NUMBER_INPUTS 7
37065 +#define KEYBD_MATRIX_NUMBER_OUTPUTS 14
37067 +#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC FALSE
37068 +#define KEYBD_MATRIX_INVERT_INPUT_LOGIC FALSE
37070 +#define KEYBD_MATRIX_SETTLING_TIME_US 100
37071 +#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT 2
37073 +#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \
37075 + IDP_CPLD_KB_COL_LOW = outputs;\
37076 + IDP_CPLD_KB_COL_HIGH = outputs >> 7;\
37079 +#define KEYBD_MATRIX_GET_INPUTS(inputs) \
37081 + inputs = (IDP_CPLD_KB_ROW & 0x7f);\
37084 +//------------------------------------------------------------------------------
37086 +#else // must be rev 01
37088 +/* -----------------------------------------------------------------------------
37089 + * following is for rev01 boards only
37092 +#define IDP_FLASH_PHYS (PXA_CS0_PHYS)
37093 +#define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS)
37094 +#define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS)
37095 +#define IDP_CTRL_PORT_PHYS (PXA_CS5_PHYS + 0x02C00000)
37096 +#define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000)
37097 +#define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000)
37098 +#define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000)
37099 +#define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000)
37103 + * virtual memory map
37106 +#define IDP_CTRL_PORT_BASE (0xf0000000)
37107 +#define IDP_CTRL_PORT_SIZE (1*1024*1024)
37109 +#define IDP_IDE_BASE (IDP_CTRL_PORT_BASE + IDP_CTRL_PORT_SIZE)
37110 +#define IDP_IDE_SIZE (1*1024*1024)
37112 +#define IDP_ETH_BASE (IDP_IDE_BASE + IDP_IDE_SIZE)
37113 +#define IDP_ETH_SIZE (1*1024*1024)
37115 +#define IDP_COREVOLT_BASE (IDP_ETH_BASE + IDP_ETH_SIZE)
37116 +#define IDP_COREVOLT_SIZE (1*1024*1024)
37118 +#define IDP_CPLD_BASE (IDP_COREVOLT_BASE + IDP_COREVOLT_SIZE)
37119 +#define IDP_CPLD_SIZE (1*1024*1024)
37121 +#if (IDP_CPLD_BASE + IDP_CPLD_SIZE) > 0xfc000000
37122 +#error Your custom IO space is getting a bit large !!
37125 +#define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_BASE)
37126 +#define CPLD_V2P(x) ((x) - IDP_CPLD_BASE + IDP_CPLD_PHYS)
37128 +#ifndef __ASSEMBLY__
37129 +# define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x)))
37131 +# define __CPLD_REG(x) CPLD_P2V(x)
37134 +/* board level registers in the CPLD: (offsets from CPLD_BASE) */
37136 +#define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x00)
37137 +#define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04)
37138 +#define _IDP_CPLD_CIR (IDP_CPLD_PHYS + 0x08)
37139 +#define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C)
37140 +#define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10)
37141 +#define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14)
37142 +#define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18)
37143 +#define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C)
37144 +#define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20)
37145 +#define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24)
37146 +#define _IDP_CPLD_MISC (IDP_CPLD_PHYS + 0x28)
37147 +#define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x2C)
37148 +#define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x30)
37150 +/* FPGA register virtual addresses */
37151 +#define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL) /* write only */
37152 +#define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR) /* write only */
37153 +#define IDP_CPLD_CIR __CPLD_REG(_IDP_CPLD_CIR) /* write only */
37154 +#define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH) /* write only */
37155 +#define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW) /* write only */
37156 +#define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN) /* write only */
37157 +#define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR) /* write only */
37158 +#define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE) /* write only */
37159 +#define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR) /* write only */
37160 +#define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE) /* write only */
37161 +#define IDP_CPLD_MISC __CPLD_REG(_IDP_CPLD_MISC) /* read only */
37162 +#define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS) /* read only */
37163 +#define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS) /* read only */
37166 +#ifndef __ASSEMBLY__
37168 +/* shadow registers for write only registers */
37169 +extern unsigned int idp_cpld_led_control_shadow;
37170 +extern unsigned int idp_cpld_periph_pwr_shadow;
37171 +extern unsigned int idp_cpld_cir_shadow;
37172 +extern unsigned int idp_cpld_kb_col_high_shadow;
37173 +extern unsigned int idp_cpld_kb_col_low_shadow;
37174 +extern unsigned int idp_cpld_pccard_en_shadow;
37175 +extern unsigned int idp_cpld_gpioh_dir_shadow;
37176 +extern unsigned int idp_cpld_gpioh_value_shadow;
37177 +extern unsigned int idp_cpld_gpiol_dir_shadow;
37178 +extern unsigned int idp_cpld_gpiol_value_shadow;
37180 +extern unsigned int idp_control_port_shadow;
37183 + * macros to write to write only register
37185 + * none of these macros are protected from
37186 + * multiple drivers using them in interrupt context.
37189 +#define WRITE_IDP_CPLD_LED_CONTROL(value, mask) \
37191 + idp_cpld_led_control_shadow = ((value & mask) | (idp_cpld_led_control_shadow & ~mask));\
37192 + IDP_CPLD_LED_CONTROL = idp_cpld_led_control_shadow;\
37194 +#define WRITE_IDP_CPLD_PERIPH_PWR(value, mask) \
37196 + idp_cpld_periph_pwr_shadow = ((value & mask) | (idp_cpld_periph_pwr_shadow & ~mask));\
37197 + IDP_CPLD_PERIPH_PWR = idp_cpld_periph_pwr_shadow;\
37199 +#define WRITE_IDP_CPLD_CIR(value, mask) \
37201 + idp_cpld_cir_shadow = ((value & mask) | (idp_cpld_cir_shadow & ~mask));\
37202 + IDP_CPLD_CIR = idp_cpld_cir_shadow;\
37204 +#define WRITE_IDP_CPLD_KB_COL_HIGH(value, mask) \
37206 + idp_cpld_kb_col_high_shadow = ((value & mask) | (idp_cpld_kb_col_high_shadow & ~mask));\
37207 + IDP_CPLD_KB_COL_HIGH = idp_cpld_kb_col_high_shadow;\
37209 +#define WRITE_IDP_CPLD_KB_COL_LOW(value, mask) \
37211 + idp_cpld_kb_col_low_shadow = ((value & mask) | (idp_cpld_kb_col_low_shadow & ~mask));\
37212 + IDP_CPLD_KB_COL_LOW = idp_cpld_kb_col_low_shadow;\
37214 +#define WRITE_IDP_CPLD_PCCARD_EN(value, mask) \
37216 + idp_cpld_ = ((value & mask) | (idp_cpld_led_control_shadow & ~mask));\
37217 + IDP_CPLD_LED_CONTROL = idp_cpld_led_control_shadow;\
37219 +#define WRITE_IDP_CPLD_GPIOH_DIR(value, mask) \
37221 + idp_cpld_gpioh_dir_shadow = ((value & mask) | (idp_cpld_gpioh_dir_shadow & ~mask));\
37222 + IDP_CPLD_GPIOH_DIR = idp_cpld_gpioh_dir_shadow;\
37224 +#define WRITE_IDP_CPLD_GPIOH_VALUE(value, mask) \
37226 + idp_cpld_gpioh_value_shadow = ((value & mask) | (idp_cpld_gpioh_value_shadow & ~mask));\
37227 + IDP_CPLD_GPIOH_VALUE = idp_cpld_gpioh_value_shadow;\
37229 +#define WRITE_IDP_CPLD_GPIOL_DIR(value, mask) \
37231 + idp_cpld_gpiol_dir_shadow = ((value & mask) | (idp_cpld_gpiol_dir_shadow & ~mask));\
37232 + IDP_CPLD_GPIOL_DIR = idp_cpld_gpiol_dir_shadow;\
37234 +#define WRITE_IDP_CPLD_GPIOL_VALUE(value, mask) \
37236 + idp_cpld_gpiol_value_shadow = ((value & mask) | (idp_cpld_gpiol_value_shadow & ~mask));\
37237 + IDP_CPLD_GPIOL_VALUE = idp_cpld_gpiol_value_shadow;\
37240 +#define WRITE_IDP_CONTROL_PORT(value, mask) \
37242 + idp_control_port_shadow = ((value & mask) | (idp_control_port_shadow & ~mask));\
37243 + (*((volatile unsigned long *)IDP_CTRL_PORT_BASE)) = idp_control_port_shadow;\
37248 +/* A listing of interrupts used by external hardware devices */
37250 +#define TOUCH_PANEL_IRQ IRQ_GPIO(21)
37251 +#define TOUCH_PANEL_IRQ_EGDE GPIO_FALLING_EDGE
37253 +#define ETHERNET_IRQ IRQ_GPIO(4)
37254 +#define ETHERNET_IRQ_EDGE GPIO_RISING_EDGE
37257 + * Bit masks for various registers
37261 +/* control port */
37262 +#define IDP_CONTROL_PORT_PCSLOT0_0 (1 << 0)
37263 +#define IDP_CONTROL_PORT_PCSLOT0_1 (1 << 1)
37264 +#define IDP_CONTROL_PORT_PCSLOT0_2 (1 << 2)
37265 +#define IDP_CONTROL_PORT_PCSLOT0_3 (1 << 3)
37266 +#define IDP_CONTROL_PORT_PCSLOT1_1 (1 << 4)
37267 +#define IDP_CONTROL_PORT_PCSLOT1_2 (1 << 5)
37268 +#define IDP_CONTROL_PORT_PCSLOT1_3 (1 << 6)
37269 +#define IDP_CONTROL_PORT_PCSLOT1_4 (1 << 7)
37270 +#define IDP_CONTROL_PORT_SERIAL1_EN (1 << 9)
37271 +#define IDP_CONTROL_PORT_SERIAL2_EN (1 << 10)
37272 +#define IDP_CONTROL_PORT_SERIAL3_EN (1 << 11)
37273 +#define IDP_CONTROL_PORT_IRDA_FIR (1 << 12)
37274 +#define IDP_CONTROL_PORT_IRDA_M0 (1 << 13)
37275 +#define IDP_CONTROL_PORT_IRDA_M1 (1 << 14)
37276 +#define IDP_CONTROL_PORT_I2S_PWR (1 << 15)
37277 +#define IDP_CONTROL_PORT_FLASH_WP (1 << 19)
37278 +#define IDP_CONTROL_PORT_MILL_EN (1 << 20)
37279 +#define IDP_CONTROL_PORT_LCD_PWR (1 << 21)
37280 +#define IDP_CONTROL_PORT_LCD_BKLEN (1 << 22)
37281 +#define IDP_CONTROL_PORT_LCD_ENAVLCD (1 << 23)
37284 + * Macros for LCD Driver
37287 +#ifdef CONFIG_FB_PXA
37289 +#define FB_BACKLIGHT_ON() WRITE_IDP_CONTROL_PORT(IDP_CONTROL_PORT_LCD_BKLEN, IDP_CONTROL_PORT_LCD_BKLEN)
37290 +#define FB_BACKLIGHT_OFF() WRITE_IDP_CONTROL_PORT(0, IDP_CONTROL_PORT_LCD_BKLEN)
37292 +#define FB_PWR_ON() WRITE_IDP_CONTROL_PORT(IDP_CONTROL_PORT_LCD_PWR, IDP_CONTROL_PORT_LCD_PWR)
37293 +#define FB_PWR_OFF() WRITE_IDP_CONTROL_PORT(0, IDP_CONTROL_PORT_LCD_PWR)
37295 +#define FB_VLCD_ON() WRITE_IDP_CONTROL_PORT(IDP_CONTROL_PORT_LCD_ENAVLCD, IDP_CONTROL_PORT_LCD_ENAVLCD)
37296 +#define FB_VLCD_OFF() WRITE_IDP_CONTROL_PORT(0, IDP_CONTROL_PORT_LCD_ENAVLCD)
37302 + * Macros for LED Driver
37306 +#define IDP_HB_LED 0x1
37307 +#define IDP_BUSY_LED 0x2
37309 +#define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED)
37311 +#define IDP_WRITE_LEDS(value) WRITE_IDP_CPLD_LED_CONTROL(value, IDP_LEDS_MASK)
37314 + * macros for MTD driver
37317 +#define FLASH_WRITE_PROTECT_DISABLE() WRITE_IDP_CONTROL_PORT(0, IDP_CONTROL_PORT_FLASH_WP)
37318 +#define FLASH_WRITE_PROTECT_ENABLE() WRITE_IDP_CONTROL_PORT(IDP_CONTROL_PORT_FLASH_WP, IDP_CONTROL_PORT_FLASH_WP)
37322 +++ linux-2.4.27/include/asm-arm/arch-pxa/innokom.h
37325 + * linux/include/asm-arm/arch-pxa/innokom.h
37327 + * (c) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
37329 + * This program is free software; you can redistribute it and/or modify
37330 + * it under the terms of the GNU General Public License as published by
37331 + * the Free Software Foundation; either version 2 of the License, or
37332 + * (at your option) any later version.
37334 + * This program is distributed in the hope that it will be useful,
37335 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
37336 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37337 + * GNU General Public License for more details.
37339 + * You should have received a copy of the GNU General Public License
37340 + * along with this program; if not, write to the Free Software
37341 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
37347 +#define GPIO_INNOKOM_RESET 3
37348 +#define GPIO_INNOKOM_SW_UPDATE 11
37349 +#define GPIO_INNOKOM_ETH 59
37352 + * ethernet chip (SMSC91C111)
37354 +#define INNOKOM_ETH_PHYS PXA_CS5_PHYS
37355 +#define INNOKOM_ETH_BASE (0xf0000000) /* phys 0x14000000 */
37356 +#define INNOKOM_ETH_SIZE (1*1024*1024)
37357 +#define INNOKOM_ETH_IRQ IRQ_GPIO(GPIO_INNOKOM_ETH)
37358 +#define INNOKOM_ETH_IRQ_EDGE GPIO_RISING_EDGE
37361 + * virtual to physical conversion macros
37363 +#define INNOKOM_P2V(x) ((x) - INNOKOM_FPGA_PHYS + INNOKOM_FPGA_VIRT)
37364 +#define INNOKOM_V2P(x) ((x) - INNOKOM_FPGA_VIRT + INNOKOM_FPGA_PHYS)
37366 +#ifndef __ASSEMBLY__
37367 +# define __INNOKOM_REG(x) (*((volatile unsigned long *)INNOKOM_P2V(x)))
37369 +# define __INNOKOM_REG(x) INNOKOM_P2V(x)
37372 +++ linux-2.4.27/include/asm-arm/arch-pxa/io.h
37375 + * linux/include/asm-arm/arch-pxa/io.h
37377 + * Author: Nicolas Pitre
37378 + * Created: Jun 15, 2001
37379 + * Copyright: MontaVista Software Inc.
37381 + * This program is free software; you can redistribute it and/or modify
37382 + * it under the terms of the GNU General Public License version 2 as
37383 + * published by the Free Software Foundation.
37385 +#ifndef __ASM_ARM_ARCH_IO_H
37386 +#define __ASM_ARM_ARCH_IO_H
37388 +#define IO_SPACE_LIMIT 0xffffffff
37391 + * We don't actually have real ISA nor PCI buses, but there is so many
37392 + * drivers out there that might just work if we fake them...
37394 +#define __io(a) (a)
37395 +#define __mem_pci(a) ((unsigned long)(a))
37396 +#define __mem_isa(a) ((unsigned long)(a))
37399 + * Generic virtual read/write
37401 +#define __arch_getw(a) (*(volatile unsigned short *)(a))
37402 +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
37404 +#define iomem_valid_addr(iomem,sz) (1)
37405 +#define iomem_to_phys(iomem) (iomem)
37409 +++ linux-2.4.27/include/asm-arm/arch-pxa/irq.h
37412 + * linux/include/asm-arm/arch-pxa/irq.h
37414 + * Author: Nicolas Pitre
37415 + * Created: Jun 15, 2001
37416 + * Copyright: MontaVista Software Inc.
37418 + * This program is free software; you can redistribute it and/or modify
37419 + * it under the terms of the GNU General Public License version 2 as
37420 + * published by the Free Software Foundation.
37423 +#define fixup_irq(x) (x)
37426 + * This prototype is required for cascading of multiplexed interrupts.
37427 + * Since it doesn't exist elsewhere, we'll put it here for now.
37429 +extern void do_IRQ(int irq, struct pt_regs *regs);
37431 +++ linux-2.4.27/include/asm-arm/arch-pxa/irqs.h
37434 + * linux/include/asm-arm/arch-pxa/irqs.h
37436 + * Author: Nicolas Pitre
37437 + * Created: Jun 15, 2001
37438 + * Copyright: MontaVista Software Inc.
37440 + * This program is free software; you can redistribute it and/or modify
37441 + * it under the terms of the GNU General Public License version 2 as
37442 + * published by the Free Software Foundation.
37445 +#define PXA_IRQ_SKIP 7 /* The first 7 IRQs are not yet used */
37446 +#define PXA_IRQ(x) ((x) - PXA_IRQ_SKIP)
37448 +#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error */
37449 +#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */
37450 +#define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */
37451 +#define IRQ_GPIO_2_80 PXA_IRQ(10) /* GPIO[2-80] Edge Detect */
37452 +#define IRQ_USB PXA_IRQ(11) /* USB Service */
37453 +#define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */
37454 +#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt */
37455 +#define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */
37456 +#define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request */
37457 +#define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request */
37458 +#define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */
37459 +#define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */
37460 +#define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */
37461 +#define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */
37462 +#define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */
37463 +#define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/
37464 +#define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */
37465 +#define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */
37466 +#define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */
37467 +#define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */
37468 +#define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */
37469 +#define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */
37470 +#define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */
37471 +#define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */
37472 +#define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */
37474 +#define GPIO_2_80_TO_IRQ(x) \
37475 + PXA_IRQ((x) - 2 + 32)
37476 +#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_80_TO_IRQ(x))
37478 +#define IRQ_TO_GPIO_2_80(i) \
37479 + ((i) - PXA_IRQ(32) + 2)
37480 +#define IRQ_TO_GPIO(i) ((i) - (((i) > IRQ_GPIO1) ? IRQ_GPIO(2) - 2 : IRQ_GPIO(0)))
37482 +#define NR_IRQS (IRQ_GPIO(80) + 1)
37484 +#if defined(CONFIG_SA1111)
37486 +#define IRQ_SA1111_START (IRQ_GPIO(80) + 1)
37487 +#define SA1111_IRQ(x) (IRQ_SA1111_START + (x))
37489 +#define IRQ_GPAIN0 SA1111_IRQ(0)
37490 +#define IRQ_GPAIN1 SA1111_IRQ(1)
37491 +#define IRQ_GPAIN2 SA1111_IRQ(2)
37492 +#define IRQ_GPAIN3 SA1111_IRQ(3)
37493 +#define IRQ_GPBIN0 SA1111_IRQ(4)
37494 +#define IRQ_GPBIN1 SA1111_IRQ(5)
37495 +#define IRQ_GPBIN2 SA1111_IRQ(6)
37496 +#define IRQ_GPBIN3 SA1111_IRQ(7)
37497 +#define IRQ_GPBIN4 SA1111_IRQ(8)
37498 +#define IRQ_GPBIN5 SA1111_IRQ(9)
37499 +#define IRQ_GPCIN0 SA1111_IRQ(10)
37500 +#define IRQ_GPCIN1 SA1111_IRQ(11)
37501 +#define IRQ_GPCIN2 SA1111_IRQ(12)
37502 +#define IRQ_GPCIN3 SA1111_IRQ(13)
37503 +#define IRQ_GPCIN4 SA1111_IRQ(14)
37504 +#define IRQ_GPCIN5 SA1111_IRQ(15)
37505 +#define IRQ_GPCIN6 SA1111_IRQ(16)
37506 +#define IRQ_GPCIN7 SA1111_IRQ(17)
37507 +#define IRQ_MSTXINT SA1111_IRQ(18)
37508 +#define IRQ_MSRXINT SA1111_IRQ(19)
37509 +#define IRQ_MSSTOPERRINT SA1111_IRQ(20)
37510 +#define IRQ_TPTXINT SA1111_IRQ(21)
37511 +#define IRQ_TPRXINT SA1111_IRQ(22)
37512 +#define IRQ_TPSTOPERRINT SA1111_IRQ(23)
37513 +#define SSPXMTINT SA1111_IRQ(24)
37514 +#define SSPRCVINT SA1111_IRQ(25)
37515 +#define SSPROR SA1111_IRQ(26)
37516 +#define AUDXMTDMADONEA SA1111_IRQ(32)
37517 +#define AUDRCVDMADONEA SA1111_IRQ(33)
37518 +#define AUDXMTDMADONEB SA1111_IRQ(34)
37519 +#define AUDRCVDMADONEB SA1111_IRQ(35)
37520 +#define AUDTFSR SA1111_IRQ(36)
37521 +#define AUDRFSR SA1111_IRQ(37)
37522 +#define AUDTUR SA1111_IRQ(38)
37523 +#define AUDROR SA1111_IRQ(39)
37524 +#define AUDDTS SA1111_IRQ(40)
37525 +#define AUDRDD SA1111_IRQ(41)
37526 +#define AUDSTO SA1111_IRQ(42)
37527 +#define USBPWR SA1111_IRQ(43)
37528 +#define NIRQHCIM SA1111_IRQ(44)
37529 +#define HCIBUFFACC SA1111_IRQ(45)
37530 +#define HCIRMTWKP SA1111_IRQ(46)
37531 +#define NHCIMFCIR SA1111_IRQ(47)
37532 +#define PORT_RESUME SA1111_IRQ(48)
37533 +#define S0_READY_NINT SA1111_IRQ(49)
37534 +#define S1_READY_NINT SA1111_IRQ(50)
37535 +#define S0_CD_VALID SA1111_IRQ(51)
37536 +#define S1_CD_VALID SA1111_IRQ(52)
37537 +#define S0_BVD1_STSCHG SA1111_IRQ(53)
37538 +#define S1_BVD1_STSCHG SA1111_IRQ(54)
37540 +#define SA1111_IRQ_MAX SA1111_IRQ(54)
37543 +#define NR_IRQS (SA1111_IRQ_MAX + 1)
37545 +#endif // defined(CONFIG_SA1111)
37547 +#if defined(CONFIG_ARCH_LUBBOCK) || defined(CONFIG_ARCH_PXA_IDP)
37549 +#define LUBBOCK_IRQ(x) (SA1111_IRQ_MAX + 1 + (x))
37551 +#define LUBBOCK_IRQ(x) (IRQ_GPIO(80) + 1 + (x))
37554 +#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0)
37555 +#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1)
37556 +#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2)
37557 +#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3)
37558 +#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4)
37559 +#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5)
37560 +#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */
37561 +#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6)
37564 +#define NR_IRQS (LUBBOCK_LAST_IRQ + 1)
37566 +#endif // CONFIG_ARCH_LUBBOCK
37571 +++ linux-2.4.27/include/asm-arm/arch-pxa/keyboard.h
37574 + * linux/include/asm-arm/arch-pxa/keyboard.h
37576 + * This file contains the architecture specific keyboard definitions
37579 +#ifndef _PXA_KEYBOARD_H
37580 +#define _PXA_KEYBOARD_H
37582 +#include <linux/config.h>
37583 +#include <asm/mach-types.h>
37584 +#include <asm/hardware.h>
37586 +extern struct kbd_ops_struct *kbd_ops;
37588 +#define kbd_disable_irq() do { } while(0);
37589 +#define kbd_enable_irq() do { } while(0);
37591 +extern int sa1111_kbd_init_hw(void);
37593 +static inline void kbd_init_hw(void)
37595 + if (machine_is_lubbock())
37596 + sa1111_kbd_init_hw();
37600 +#endif /* _PXA_KEYBOARD_H */
37603 +++ linux-2.4.27/include/asm-arm/arch-pxa/lubbock.h
37606 + * linux/include/asm-arm/arch-pxa/lubbock.h
37608 + * Author: Nicolas Pitre
37609 + * Created: Jun 15, 2001
37610 + * Copyright: MontaVista Software Inc.
37612 + * This program is free software; you can redistribute it and/or modify
37613 + * it under the terms of the GNU General Public License version 2 as
37614 + * published by the Free Software Foundation.
37617 +#define LUBBOCK_FPGA_PHYS PXA_CS2_PHYS
37618 +#define LUBBOCK_FPGA_VIRT (0xf0000000) /* phys 0x08000000 */
37619 +#define LUBBOCK_ETH_PHYS PXA_CS3_PHYS
37620 +#define LUBBOCK_ETH_VIRT (0xf1000000)
37621 +#define LUBBOCK_SA1111_BASE (0xf4000000) /* phys 0x10000000 */
37623 +#define LUB_P2V(x) ((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT)
37624 +#define LUB_V2P(x) ((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS)
37626 +#ifndef __ASSEMBLY__
37627 +# define __LUB_REG(x) (*((volatile unsigned long *)LUB_P2V(x)))
37629 +# define __LUB_REG(x) LUB_P2V(x)
37632 +/* board level registers in the CPLD: (offsets from CPLD_BASE) */
37634 +#define WHOAMI 0 // card ID's (see programmers manual)
37635 +#define HEX_LED 0x10 // R/W access to 8 7 segment displays
37636 +#define DISC_BLNK_LED 0x40 // R/W [15-8] enables for hex leds, [7-0] discrete LEDs
37637 +#define CONF_SWITCHES 0x50 // RO [1] flash wrt prot, [0] 0= boot from rom, 1= flash
37638 +#define USER_SWITCHES 0x60 // RO [15-8] dip switches, [7-0] 2 hex encoding switches
37639 +#define MISC_WR 0x80 // R/W various system controls -see manual
37640 +#define MISC_RD 0x90 // RO various system status bits -see manual
37641 +//#define LUB_IRQ_MASK_EN 0xC0 // R/W 0= mask, 1= enable of TS, codec, ethernet, USB, SA1111, and card det. irq's
37642 +//#define LUB_IRQ_SET_CLR 0xD0 // R/W 1= set, 0 = clear IRQ's from TS, codec, etc...
37643 +//#define LUB_GP 0x100 // R/W [15-0] 16 bits of general purpose I/o for hacking
37646 +/* FPGA register physical addresses */
37647 +#define _LUB_WHOAMI (LUBBOCK_FPGA_PHYS + 0x000)
37648 +#define _LUB_HEXLED (LUBBOCK_FPGA_PHYS + 0x010)
37649 +#define _LUB_DISC_BLNK_LED (LUBBOCK_FPGA_PHYS + 0x040)
37650 +#define _LUB_CONF_SWITCHES (LUBBOCK_FPGA_PHYS + 0x050)
37651 +#define _LUB_USER_SWITCHES (LUBBOCK_FPGA_PHYS + 0x060)
37652 +#define _LUB_MISC_WR (LUBBOCK_FPGA_PHYS + 0x080)
37653 +#define _LUB_MISC_RD (LUBBOCK_FPGA_PHYS + 0x090)
37654 +#define _LUB_IRQ_MASK_EN (LUBBOCK_FPGA_PHYS + 0x0C0)
37655 +#define _LUB_IRQ_SET_CLR (LUBBOCK_FPGA_PHYS + 0x0D0)
37656 +#define _LUB_GP (LUBBOCK_FPGA_PHYS + 0x100)
37658 +/* FPGA register virtual addresses */
37659 +#define LUB_WHOAMI __LUB_REG(_LUB_WHOAMI)
37660 +#define LUB_HEXLED __LUB_REG(_LUB_HEXLED)
37661 +#define LUB_DISC_BLNK_LED __LUB_REG(_LUB_DISC_BLNK_LED)
37662 +#define LUB_CONF_SWITCHES __LUB_REG(_LUB_CONF_SWITCHES)
37663 +#define LUB_USER_SWITCHES __LUB_REG(_LUB_USER_SWITCHES)
37664 +#define LUB_MISC_WR __LUB_REG(_LUB_MISC_WR)
37665 +#define LUB_MISC_RD __LUB_REG(_LUB_MISC_RD)
37666 +#define LUB_IRQ_MASK_EN __LUB_REG(_LUB_IRQ_MASK_EN)
37667 +#define LUB_IRQ_SET_CLR __LUB_REG(_LUB_IRQ_SET_CLR)
37668 +#define LUB_GP __LUB_REG(_LUB_GP)
37672 +#define GPIO_LUBBOCK_IRQ 0
37673 +#define IRQ_GPIO_LUBBOCK_IRQ IRQ_GPIO0
37680 +#define LEDS_BASE LUB_DISC_BLNK_LED
37682 +// 8 discrete leds available for general use:
37693 +/* Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays so
37694 +* be sure to not monkey with them here.
37697 +#define HEARTBEAT_LED D28
37698 +#define SYS_BUSY_LED D27
37699 +#define HEXLEDS_BASE LUB_HEXLED
37701 +#define HEARTBEAT_LED_ON (LEDS_BASE &= ~HEARTBEAT_LED)
37702 +#define HEARTBEAT_LED_OFF (LEDS_BASE |= HEARTBEAT_LED)
37703 +#define SYS_BUSY_LED_OFF (LEDS_BASE |= SYS_BUSY_LED)
37704 +#define SYS_BUSY_LED_ON (LEDS_BASE &= ~SYS_BUSY_LED)
37706 +// use x = D26-D21 for these, please...
37707 +#define DISCRETE_LED_ON(x) (LEDS_BASE &= ~(x))
37708 +#define DISCRETE_LED_OFF(x) (LEDS_BASE |= (x))
37710 +#ifndef __ASSEMBLY__
37712 +//extern int hexled_val = 0;
37716 +#define BUMP_COUNTER (HEXLEDS_BASE = hexled_val++)
37717 +#define DEC_COUNTER (HEXLEDS_BASE = hexled_val--)
37719 +++ linux-2.4.27/include/asm-arm/arch-pxa/memory.h
37722 + * linux/include/asm-arm/arch-pxa/memory.h
37724 + * Author: Nicolas Pitre
37725 + * Copyright: (C) 2001 MontaVista Software Inc.
37727 + * This program is free software; you can redistribute it and/or modify
37728 + * it under the terms of the GNU General Public License version 2 as
37729 + * published by the Free Software Foundation.
37732 +#ifndef __ASM_ARCH_MEMORY_H
37733 +#define __ASM_ARCH_MEMORY_H
37739 +#define TASK_SIZE (0xc0000000UL)
37740 +#define TASK_SIZE_26 (0x04000000UL)
37743 + * This decides where the kernel will search for a free chunk of vm
37744 + * space during mmap's.
37746 +#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
37749 + * Page offset: 3GB
37751 +#define PAGE_OFFSET (0xc0000000UL)
37754 + * Physical DRAM offset.
37756 +#define PHYS_OFFSET (0xa0000000UL)
37759 + * physical vs virtual ram conversion
37761 +#define __virt_to_phys__is_a_macro
37762 +#define __phys_to_virt__is_a_macro
37763 +#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET)
37764 +#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET)
37767 + * Virtual view <-> DMA view memory address translations
37768 + * virt_to_bus: Used to translate the virtual address to an
37769 + * address suitable to be passed to set_dma_addr
37770 + * bus_to_virt: Used to convert an address for DMA operations
37771 + * to an address that the kernel can use.
37773 +#define __virt_to_bus__is_a_macro
37774 +#define __bus_to_virt__is_a_macro
37775 +#define __virt_to_bus(x) __virt_to_phys(x)
37776 +#define __bus_to_virt(x) __phys_to_virt(x)
37778 +#ifdef CONFIG_DISCONTIGMEM
37780 + * The nodes are matched with the physical SDRAM banks as follows:
37782 + * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff
37783 + * node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff
37784 + * node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff
37785 + * node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff
37788 +#define NR_NODES 4
37791 + * Given a kernel address, find the home node of the underlying memory.
37793 +#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 26)
37796 + * Given a page frame number, convert it to a node id.
37798 +#define PFN_TO_NID(pfn) (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
37801 + * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
37802 + * and returns the mem_map of that node.
37804 +#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
37807 + * Given a page frame number, find the owning node of the memory
37808 + * and returns the mem_map of that node.
37810 +#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
37813 + * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
37814 + * and returns the index corresponding to the appropriate page in the
37815 + * node's mem_map.
37817 +#define LOCAL_MAP_NR(addr) \
37818 + (((unsigned long)(addr) & 0x03ffffff) >> PAGE_SHIFT)
37822 +#define PFN_TO_NID(addr) (0)
37828 +++ linux-2.4.27/include/asm-arm/arch-pxa/param.h
37831 + * linux/include/asm-arm/arch-pxa/param.h
37834 +++ linux-2.4.27/include/asm-arm/arch-pxa/pcmcia.h
37837 + * linux/include/asm-arm/arch-pxa/pcmcia.h
37839 + * Author: George Davis
37840 + * Created: Jan 10, 2002
37841 + * Copyright: MontaVista Software Inc.
37843 + * This program is free software; you can redistribute it and/or modify
37844 + * it under the terms of the GNU General Public License version 2 as
37845 + * published by the Free Software Foundation.
37848 + * Originally based upon linux/include/asm-arm/arch-sa1100/pcmcia.h
37852 +#ifndef _ASM_ARCH_PCMCIA
37853 +#define _ASM_ARCH_PCMCIA
37856 +/* Ideally, we'd support up to MAX_SOCK sockets, but PXA250 only
37857 + * provides support for a maximum of two.
37859 +#define PXA_PCMCIA_MAX_SOCK (2)
37862 +#ifndef __ASSEMBLY__
37864 +struct pcmcia_init {
37865 + void (*handler)(int irq, void *dev, struct pt_regs *regs);
37868 +struct pcmcia_state {
37869 + unsigned detect: 1,
37878 +struct pcmcia_state_array {
37879 + unsigned int size;
37880 + struct pcmcia_state *state;
37883 +struct pcmcia_irq_info {
37884 + unsigned int sock;
37885 + unsigned int irq;
37888 +struct pcmcia_low_level {
37889 + int (*init)(struct pcmcia_init *);
37890 + int (*shutdown)(void);
37891 + int (*socket_state)(struct pcmcia_state_array *);
37892 + int (*get_irq_info)(struct pcmcia_irq_info *);
37893 + int (*configure_socket)(unsigned int, socket_state_t *);
37896 +extern struct pcmcia_low_level *pcmcia_low_level;
37898 +#endif /* __ASSEMBLY__ */
37902 +++ linux-2.4.27/include/asm-arm/arch-pxa/pxa-regs.h
37905 + * linux/include/asm-arm/arch-pxa/pxa-regs.h
37907 + * Author: Nicolas Pitre
37908 + * Created: Jun 15, 2001
37909 + * Copyright: MontaVista Software Inc.
37911 + * This program is free software; you can redistribute it and/or modify
37912 + * it under the terms of the GNU General Public License version 2 as
37913 + * published by the Free Software Foundation.
37915 +#ifndef _PXA_REGS_H_
37916 +#define _PXA_REGS_H_
37918 +#include "bitfield.h"
37921 +// FIXME hack so that SA-1111.h will work [cb]
37923 +#ifndef __ASSEMBLY__
37924 +typedef unsigned short Word16 ;
37925 +typedef unsigned int Word32 ;
37926 +typedef Word32 Word ;
37927 +typedef Word Quad [4] ;
37928 +typedef void *Address ;
37929 +typedef void (*ExcpHndlr) (void) ;
37933 + * PXA Chip selects
37936 +#define PXA_CS0_PHYS 0x00000000
37937 +#define PXA_CS1_PHYS 0x04000000
37938 +#define PXA_CS2_PHYS 0x08000000
37939 +#define PXA_CS3_PHYS 0x0C000000
37940 +#define PXA_CS4_PHYS 0x10000000
37941 +#define PXA_CS5_PHYS 0x14000000
37945 + * Personal Computer Memory Card International Association (PCMCIA) sockets
37948 +#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
37949 +#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
37950 +#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
37951 +#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
37952 +#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
37954 +#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
37955 +#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
37956 +#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
37957 +#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
37959 +#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
37960 +#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
37961 +#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
37962 +#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
37964 +#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
37965 + (0x20000000 + (Nb)*PCMCIASp)
37966 +#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
37967 +#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
37968 + (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
37969 +#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
37970 + (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
37972 +#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
37973 +#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
37974 +#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
37975 +#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
37977 +#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
37978 +#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
37979 +#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
37980 +#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
37988 +#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
37989 +#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
37990 +#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
37991 +#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
37992 +#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
37993 +#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
37994 +#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
37995 +#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
37996 +#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
37997 +#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
37998 +#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
37999 +#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
38000 +#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
38001 +#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
38002 +#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
38003 +#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
38005 +#define DCSR(x) __REG2(0x40000000, (x) << 2)
38007 +#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
38008 +#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
38009 +#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
38010 +#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
38011 +#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
38012 +#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
38013 +#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
38014 +#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
38016 +#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
38018 +#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
38019 +#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
38020 +#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
38021 +#define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
38022 +#define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
38023 +#define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
38024 +#define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
38025 +#define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
38026 +#define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
38027 +#define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
38028 +#define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
38029 +#define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
38030 +#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
38031 +#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
38032 +#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
38033 +#define DRCMR15 __REG(0x4000013c) /* Reserved */
38034 +#define DRCMR16 __REG(0x40000140) /* Reserved */
38035 +#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
38036 +#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
38037 +#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
38038 +#define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
38039 +#define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
38040 +#define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
38041 +#define DRCMR23 __REG(0x4000015c) /* Reserved */
38042 +#define DRCMR24 __REG(0x40000160) /* Reserved */
38043 +#define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
38044 +#define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
38045 +#define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
38046 +#define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
38047 +#define DRCMR29 __REG(0x40000174) /* Reserved */
38048 +#define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
38049 +#define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
38050 +#define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
38051 +#define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
38052 +#define DRCMR34 __REG(0x40000188) /* Reserved */
38053 +#define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
38054 +#define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
38055 +#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
38056 +#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
38057 +#define DRCMR39 __REG(0x4000019C) /* Reserved */
38059 +#define DRCMRRXSADR DRCMR2
38060 +#define DRCMRTXSADR DRCMR3
38061 +#define DRCMRRXBTRBR DRCMR4
38062 +#define DRCMRTXBTTHR DRCMR5
38063 +#define DRCMRRXFFRBR DRCMR6
38064 +#define DRCMRTXFFTHR DRCMR7
38065 +#define DRCMRRXMCDR DRCMR8
38066 +#define DRCMRRXMODR DRCMR9
38067 +#define DRCMRTXMODR DRCMR10
38068 +#define DRCMRRXPCDR DRCMR11
38069 +#define DRCMRTXPCDR DRCMR12
38070 +#define DRCMRRXSSDR DRCMR13
38071 +#define DRCMRTXSSDR DRCMR14
38072 +#define DRCMRRXICDR DRCMR17
38073 +#define DRCMRTXICDR DRCMR18
38074 +#define DRCMRRXSTRBR DRCMR19
38075 +#define DRCMRTXSTTHR DRCMR20
38076 +#define DRCMRRXMMC DRCMR21
38077 +#define DRCMRTXMMC DRCMR22
38079 +#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
38080 +#define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */
38082 +#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
38083 +#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
38084 +#define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
38085 +#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
38086 +#define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
38087 +#define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
38088 +#define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
38089 +#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
38090 +#define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
38091 +#define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
38092 +#define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
38093 +#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
38094 +#define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
38095 +#define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
38096 +#define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
38097 +#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
38098 +#define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
38099 +#define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
38100 +#define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
38101 +#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
38102 +#define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
38103 +#define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
38104 +#define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
38105 +#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
38106 +#define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
38107 +#define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
38108 +#define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
38109 +#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
38110 +#define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
38111 +#define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
38112 +#define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
38113 +#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
38114 +#define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
38115 +#define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
38116 +#define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
38117 +#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
38118 +#define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
38119 +#define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
38120 +#define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
38121 +#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
38122 +#define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
38123 +#define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
38124 +#define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
38125 +#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
38126 +#define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
38127 +#define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
38128 +#define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
38129 +#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
38130 +#define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
38131 +#define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
38132 +#define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
38133 +#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
38134 +#define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
38135 +#define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
38136 +#define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
38137 +#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
38138 +#define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
38139 +#define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
38140 +#define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
38141 +#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
38142 +#define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
38143 +#define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
38144 +#define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
38145 +#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
38147 +#define DDADR(x) __REG2(0x40000200, (x) << 4)
38148 +#define DSADR(x) __REG2(0x40000204, (x) << 4)
38149 +#define DTADR(x) __REG2(0x40000208, (x) << 4)
38150 +#define DCMD(x) __REG2(0x4000020c, (x) << 4)
38152 +#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
38153 +#define DDADR_STOP (1 << 0) /* Stop (read / write) */
38155 +#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
38156 +#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
38157 +#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
38158 +#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
38159 +#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
38160 +#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
38161 +#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
38162 +#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
38163 +#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
38164 +#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
38165 +#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
38166 +#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
38167 +#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
38168 +#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
38170 +/* default combinations */
38171 +#define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
38172 +#define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
38173 +#define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
38180 +/* Full Function UART (FFUART) */
38181 +#define FFUART FFRBR
38182 +#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
38183 +#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
38184 +#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
38185 +#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
38186 +#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
38187 +#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
38188 +#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
38189 +#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
38190 +#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
38191 +#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
38192 +#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
38193 +#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
38194 +#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
38196 +/* Bluetooth UART (BTUART) */
38197 +#define BTUART BTRBR
38198 +#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
38199 +#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
38200 +#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
38201 +#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
38202 +#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
38203 +#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
38204 +#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
38205 +#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
38206 +#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
38207 +#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
38208 +#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
38209 +#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
38210 +#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
38212 +/* Standard UART (STUART) */
38213 +#define STUART STRBR
38214 +#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
38215 +#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
38216 +#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
38217 +#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
38218 +#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
38219 +#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
38220 +#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
38221 +#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
38222 +#define STMSR __REG(0x40700018) /* Reserved */
38223 +#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
38224 +#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
38225 +#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
38226 +#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
38228 +#define IER_DMAE (1 << 7) /* DMA Requests Enable */
38229 +#define IER_UUE (1 << 6) /* UART Unit Enable */
38230 +#define IER_NRZE (1 << 5) /* NRZ coding Enable */
38231 +#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
38232 +#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
38233 +#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
38234 +#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
38235 +#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
38237 +#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
38238 +#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
38239 +#define IIR_TOD (1 << 3) /* Time Out Detected */
38240 +#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
38241 +#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
38242 +#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
38244 +#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
38245 +#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
38246 +#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
38247 +#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
38248 +#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
38249 +#define FCR_ITL_1 (0)
38250 +#define FCR_ITL_8 (FCR_ITL1)
38251 +#define FCR_ITL_16 (FCR_ITL2)
38252 +#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
38254 +#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
38255 +#define LCR_SB (1 << 6) /* Set Break */
38256 +#define LCR_STKYP (1 << 5) /* Sticky Parity */
38257 +#define LCR_EPS (1 << 4) /* Even Parity Select */
38258 +#define LCR_PEN (1 << 3) /* Parity Enable */
38259 +#define LCR_STB (1 << 2) /* Stop Bit */
38260 +#define LCR_WLS1 (1 << 1) /* Word Length Select */
38261 +#define LCR_WLS0 (1 << 0) /* Word Length Select */
38263 +#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
38264 +#define LSR_TEMT (1 << 6) /* Transmitter Empty */
38265 +#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
38266 +#define LSR_BI (1 << 4) /* Break Interrupt */
38267 +#define LSR_FE (1 << 3) /* Framing Error */
38268 +#define LSR_PE (1 << 2) /* Parity Error */
38269 +#define LSR_OE (1 << 1) /* Overrun Error */
38270 +#define LSR_DR (1 << 0) /* Data Ready */
38272 +#define MCR_LOOP (1 << 4) */
38273 +#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
38274 +#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
38275 +#define MCR_RTS (1 << 1) /* Request to Send */
38276 +#define MCR_DTR (1 << 0) /* Data Terminal Ready */
38278 +#define MSR_DCD (1 << 7) /* Data Carrier Detect */
38279 +#define MSR_RI (1 << 6) /* Ring Indicator */
38280 +#define MSR_DSR (1 << 5) /* Data Set Ready */
38281 +#define MSR_CTS (1 << 4) /* Clear To Send */
38282 +#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
38283 +#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
38284 +#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
38285 +#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
38288 + * IrSR (Infrared Selection Register)
38290 +#define STISR_RXPL (1 << 4) /* Receive Data Polarity */
38291 +#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
38292 +#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
38293 +#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
38294 +#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
38301 +#define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
38302 +#define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
38303 +#define ICR __REG(0x40301690) /* I2C Control Register - ICR */
38304 +#define ISR __REG(0x40301698) /* I2C Status Register - ISR */
38305 +#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
38307 +#define ICR_START (1 << 0) /* start bit */
38308 +#define ICR_STOP (1 << 1) /* stop bit */
38309 +#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
38310 +#define ICR_TB (1 << 3) /* transfer byte bit */
38311 +#define ICR_MA (1 << 4) /* master abort */
38312 +#define ICR_SCLE (1 << 5) /* master clock enable */
38313 +#define ICR_IUE (1 << 6) /* unit enable */
38314 +#define ICR_GCD (1 << 7) /* general call disable */
38315 +#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
38316 +#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
38317 +#define ICR_BEIE (1 << 10) /* enable bus error ints */
38318 +#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
38319 +#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
38320 +#define ICR_SADIE (1 << 13) /* slave address detected int enable */
38321 +#define ICR_UR (1 << 14) /* unit reset */
38323 +#define ISR_RWM (1 << 0) /* read/write mode */
38324 +#define ISR_ACKNAK (1 << 1) /* ack/nak status */
38325 +#define ISR_UB (1 << 2) /* unit busy */
38326 +#define ISR_IBB (1 << 3) /* bus busy */
38327 +#define ISR_SSD (1 << 4) /* slave stop detected */
38328 +#define ISR_ALD (1 << 5) /* arbitration loss detected */
38329 +#define ISR_ITE (1 << 6) /* tx buffer empty */
38330 +#define ISR_IRF (1 << 7) /* rx buffer full */
38331 +#define ISR_GCAD (1 << 8) /* general call address detected */
38332 +#define ISR_SAD (1 << 9) /* slave address detected */
38333 +#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
38337 + * Serial Audio Controller
38340 +/* FIXME: This clash with SA1111 defines */
38341 +#ifndef CONFIG_SA1111
38342 +#define SACR0 __REG(0x40400000) /* Global Control Register */
38343 +#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
38344 +#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
38345 +#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
38346 +#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
38347 +#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
38348 +#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
38353 + * AC97 Controller registers
38356 +#define POCR __REG(0x40500000) /* PCM Out Control Register */
38357 +#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
38359 +#define PICR __REG(0x40500004) /* PCM In Control Register */
38360 +#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
38362 +#define MCCR __REG(0x40500008) /* Mic In Control Register */
38363 +#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
38365 +#define GCR __REG(0x4050000C) /* Global Control Register */
38366 +#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
38367 +#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
38368 +#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
38369 +#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
38370 +#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
38371 +#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
38372 +#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
38373 +#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
38374 +#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
38375 +#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
38377 +#define POSR __REG(0x40500010) /* PCM Out Status Register */
38378 +#define POSR_FIFOE (1 << 4) /* FIFO error */
38380 +#define PISR __REG(0x40500014) /* PCM In Status Register */
38381 +#define PISR_FIFOE (1 << 4) /* FIFO error */
38383 +#define MCSR __REG(0x40500018) /* Mic In Status Register */
38384 +#define MCSR_FIFOE (1 << 4) /* FIFO error */
38386 +#define GSR __REG(0x4050001C) /* Global Status Register */
38387 +#define GSR_CDONE (1 << 19) /* Command Done */
38388 +#define GSR_SDONE (1 << 18) /* Status Done */
38389 +#define GSR_RDCS (1 << 15) /* Read Completion Status */
38390 +#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
38391 +#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
38392 +#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
38393 +#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
38394 +#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
38395 +#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
38396 +#define GSR_PCR (1 << 8) /* Primary Codec Ready */
38397 +#define GSR_MINT (1 << 7) /* Mic In Interrupt */
38398 +#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
38399 +#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
38400 +#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
38401 +#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
38402 +#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
38404 +#define CAR __REG(0x40500020) /* CODEC Access Register */
38405 +#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
38407 +#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
38408 +#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
38410 +#define MOCR __REG(0x40500100) /* Modem Out Control Register */
38411 +#define MOCR_FEIE (1 << 3) /* FIFO Error */
38413 +#define MICR __REG(0x40500108) /* Modem In Control Register */
38414 +#define MICR_FEIE (1 << 3) /* FIFO Error */
38416 +#define MOSR __REG(0x40500110) /* Modem Out Status Register */
38417 +#define MOSR_FIFOE (1 << 4) /* FIFO error */
38419 +#define MISR __REG(0x40500118) /* Modem In Status Register */
38420 +#define MISR_FIFOE (1 << 4) /* FIFO error */
38422 +#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
38424 +#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
38425 +#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
38426 +#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
38427 +#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
38431 + * USB Device Controller
38433 +#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
38434 +#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
38435 +#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
38437 +#define UDCCR __REG(0x40600000) /* UDC Control Register */
38438 +#define UDCCR_UDE (1 << 0) /* UDC enable */
38439 +#define UDCCR_UDA (1 << 1) /* UDC active */
38440 +#define UDCCR_RSM (1 << 2) /* Device resume */
38441 +#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
38442 +#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
38443 +#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
38444 +#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
38445 +#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
38447 +#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
38448 +#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
38449 +#define UDCCS0_IPR (1 << 1) /* IN packet ready */
38450 +#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
38451 +#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
38452 +#define UDCCS0_SST (1 << 4) /* Sent stall */
38453 +#define UDCCS0_FST (1 << 5) /* Force stall */
38454 +#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
38455 +#define UDCCS0_SA (1 << 7) /* Setup active */
38457 +/* Bulk IN - Endpoint 1,6,11 */
38458 +#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
38459 +#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
38460 +#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
38462 +#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
38463 +#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
38464 +#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
38465 +#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
38466 +#define UDCCS_BI_SST (1 << 4) /* Sent stall */
38467 +#define UDCCS_BI_FST (1 << 5) /* Force stall */
38468 +#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
38470 +/* Bulk OUT - Endpoint 2,7,12 */
38471 +#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
38472 +#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
38473 +#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
38475 +#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
38476 +#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
38477 +#define UDCCS_BO_DME (1 << 3) /* DMA enable */
38478 +#define UDCCS_BO_SST (1 << 4) /* Sent stall */
38479 +#define UDCCS_BO_FST (1 << 5) /* Force stall */
38480 +#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
38481 +#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
38483 +/* Isochronous IN - Endpoint 3,8,13 */
38484 +#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
38485 +#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
38486 +#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
38488 +#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
38489 +#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
38490 +#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
38491 +#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
38492 +#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
38494 +/* Isochronous OUT - Endpoint 4,9,14 */
38495 +#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
38496 +#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
38497 +#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
38499 +#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
38500 +#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
38501 +#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
38502 +#define UDCCS_IO_DME (1 << 3) /* DMA enable */
38503 +#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
38504 +#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
38506 +/* Interrupt IN - Endpoint 5,10,15 */
38507 +#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
38508 +#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
38509 +#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
38511 +#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
38512 +#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
38513 +#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
38514 +#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
38515 +#define UDCCS_INT_SST (1 << 4) /* Sent stall */
38516 +#define UDCCS_INT_FST (1 << 5) /* Force stall */
38517 +#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
38519 +#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
38520 +#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
38521 +#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
38522 +#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
38523 +#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
38524 +#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
38525 +#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
38526 +#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
38527 +#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
38528 +#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
38529 +#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
38530 +#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
38531 +#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
38532 +#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
38533 +#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
38534 +#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
38535 +#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
38536 +#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
38537 +#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
38538 +#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
38539 +#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
38540 +#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
38541 +#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
38542 +#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
38544 +#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
38546 +#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
38547 +#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
38548 +#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
38549 +#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
38550 +#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
38551 +#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
38552 +#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
38553 +#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
38555 +#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
38557 +#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
38558 +#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
38559 +#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
38560 +#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
38561 +#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
38562 +#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
38563 +#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
38564 +#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
38566 +#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
38568 +#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
38569 +#define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */
38570 +#define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */
38571 +#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
38572 +#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
38573 +#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
38574 +#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
38575 +#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
38577 +#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
38579 +#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
38580 +#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
38581 +#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
38582 +#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
38583 +#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
38584 +#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
38585 +#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
38586 +#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
38590 + * Fast Infrared Communication Port
38593 +#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
38594 +#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
38595 +#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
38596 +#define ICDR __REG(0x4080000c) /* ICP Data Register */
38597 +#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
38598 +#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
38600 +#define ICCR0_AME (1 << 7) /* Adress match enable */
38601 +#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
38602 +#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
38603 +#define ICCR0_RXE (1 << 4) /* Receive enable */
38604 +#define ICCR0_TXE (1 << 3) /* Transmit enable */
38605 +#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
38606 +#define ICCR0_LBM (1 << 1) /* Loopback mode */
38607 +#define ICCR0_ITR (1 << 0) /* IrDA transmission */
38609 +#define ICSR0_FRE (1 << 5) /* Framing error */
38610 +#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
38611 +#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
38612 +#define ICSR0_RAB (1 << 2) /* Receiver abort */
38613 +#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
38614 +#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
38616 +#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
38617 +#define ICSR1_CRE (1 << 5) /* CRC error */
38618 +#define ICSR1_EOF (1 << 4) /* End of frame */
38619 +#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
38620 +#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
38621 +#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
38622 +#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
38626 + * Real Time Clock
38629 +#define RCNR __REG(0x40900000) /* RTC Count Register */
38630 +#define RTAR __REG(0x40900004) /* RTC Alarm Register */
38631 +#define RTSR __REG(0x40900008) /* RTC Status Register */
38632 +#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
38634 +#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
38635 +#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
38636 +#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
38637 +#define RTSR_AL (1 << 0) /* RTC alarm detected */
38641 + * OS Timer & Match Registers
38644 +#define OSMR0 __REG(0x40A00000) /* */
38645 +#define OSMR1 __REG(0x40A00004) /* */
38646 +#define OSMR2 __REG(0x40A00008) /* */
38647 +#define OSMR3 __REG(0x40A0000C) /* */
38648 +#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
38649 +#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
38650 +#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
38651 +#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
38653 +#define OSSR_M3 (1 << 3) /* Match status channel 3 */
38654 +#define OSSR_M2 (1 << 2) /* Match status channel 2 */
38655 +#define OSSR_M1 (1 << 1) /* Match status channel 1 */
38656 +#define OSSR_M0 (1 << 0) /* Match status channel 0 */
38658 +#define OWER_WME (1 << 0) /* Watchdog Match Enable */
38660 +#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
38661 +#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
38662 +#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
38663 +#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
38667 + * Pulse Width Modulator
38670 +#define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */
38671 +#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
38672 +#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
38674 +#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
38675 +#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
38676 +#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
38680 + * Interrupt Controller
38683 +#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
38684 +#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
38685 +#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
38686 +#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
38687 +#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
38688 +#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
38692 + * General Purpose I/O
38695 +#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
38696 +#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
38697 +#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
38699 +#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
38700 +#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
38701 +#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
38703 +#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
38704 +#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
38705 +#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
38707 +#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
38708 +#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
38709 +#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
38711 +#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
38712 +#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
38713 +#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
38715 +#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
38716 +#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
38717 +#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
38719 +#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
38720 +#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
38721 +#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
38723 +#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
38724 +#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
38725 +#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
38726 +#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
38727 +#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
38728 +#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */
38730 +/* More handy macros. The argument is a literal GPIO number. */
38732 +#define GPIO_bit(x) (1 << ((x) & 0x1f))
38733 +#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
38734 +#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
38735 +#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
38736 +#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
38737 +#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
38738 +#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
38739 +#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
38740 +#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
38742 +/* GPIO alternate function assignments */
38744 +#define GPIO1_RST 1 /* reset */
38745 +#define GPIO6_MMCCLK 6 /* MMC Clock */
38746 +#define GPIO8_48MHz 7 /* 48 MHz clock output */
38747 +#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */
38748 +#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */
38749 +#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */
38750 +#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */
38751 +#define GPIO12_32KHz 12 /* 32 kHz out */
38752 +#define GPIO13_MBGNT 13 /* memory controller grant */
38753 +#define GPIO14_MBREQ 14 /* alternate bus master request */
38754 +#define GPIO15_nCS_1 15 /* chip select 1 */
38755 +#define GPIO16_PWM0 16 /* PWM0 output */
38756 +#define GPIO17_PWM1 17 /* PWM1 output */
38757 +#define GPIO18_RDY 18 /* Ext. Bus Ready */
38758 +#define GPIO19_DREQ1 19 /* External DMA Request */
38759 +#define GPIO20_DREQ0 20 /* External DMA Request */
38760 +#define GPIO23_SCLK 23 /* SSP clock */
38761 +#define GPIO24_SFRM 24 /* SSP Frame */
38762 +#define GPIO25_STXD 25 /* SSP transmit */
38763 +#define GPIO26_SRXD 26 /* SSP receive */
38764 +#define GPIO27_SEXTCLK 27 /* SSP ext_clk */
38765 +#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */
38766 +#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */
38767 +#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */
38768 +#define GPIO31_SYNC 31 /* AC97/I2S sync */
38769 +#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */
38770 +#define GPIO33_nCS_5 33 /* chip select 5 */
38771 +#define GPIO34_FFRXD 34 /* FFUART receive */
38772 +#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */
38773 +#define GPIO35_FFCTS 35 /* FFUART Clear to send */
38774 +#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */
38775 +#define GPIO37_FFDSR 37 /* FFUART data set ready */
38776 +#define GPIO38_FFRI 38 /* FFUART Ring Indicator */
38777 +#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */
38778 +#define GPIO39_FFTXD 39 /* FFUART transmit data */
38779 +#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
38780 +#define GPIO41_FFRTS 41 /* FFUART request to send */
38781 +#define GPIO42_BTRXD 42 /* BTUART receive data */
38782 +#define GPIO43_BTTXD 43 /* BTUART transmit data */
38783 +#define GPIO44_BTCTS 44 /* BTUART clear to send */
38784 +#define GPIO45_BTRTS 45 /* BTUART request to send */
38785 +#define GPIO46_ICPRXD 46 /* ICP receive data */
38786 +#define GPIO46_STRXD 46 /* STD_UART receive data */
38787 +#define GPIO47_ICPTXD 47 /* ICP transmit data */
38788 +#define GPIO47_STTXD 47 /* STD_UART transmit data */
38789 +#define GPIO48_nPOE 48 /* Output Enable for Card Space */
38790 +#define GPIO49_nPWE 49 /* Write Enable for Card Space */
38791 +#define GPIO50_nPIOR 50 /* I/O Read for Card Space */
38792 +#define GPIO51_nPIOW 51 /* I/O Write for Card Space */
38793 +#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */
38794 +#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */
38795 +#define GPIO53_MMCCLK 53 /* MMC Clock */
38796 +#define GPIO54_MMCCLK 54 /* MMC Clock */
38797 +#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */
38798 +#define GPIO55_nPREG 55 /* Card Address bit 26 */
38799 +#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */
38800 +#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */
38801 +#define GPIO58_LDD_0 58 /* LCD data pin 0 */
38802 +#define GPIO59_LDD_1 59 /* LCD data pin 1 */
38803 +#define GPIO60_LDD_2 60 /* LCD data pin 2 */
38804 +#define GPIO61_LDD_3 61 /* LCD data pin 3 */
38805 +#define GPIO62_LDD_4 62 /* LCD data pin 4 */
38806 +#define GPIO63_LDD_5 63 /* LCD data pin 5 */
38807 +#define GPIO64_LDD_6 64 /* LCD data pin 6 */
38808 +#define GPIO65_LDD_7 65 /* LCD data pin 7 */
38809 +#define GPIO66_LDD_8 66 /* LCD data pin 8 */
38810 +#define GPIO66_MBREQ 66 /* alternate bus master req */
38811 +#define GPIO67_LDD_9 67 /* LCD data pin 9 */
38812 +#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */
38813 +#define GPIO68_LDD_10 68 /* LCD data pin 10 */
38814 +#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */
38815 +#define GPIO69_LDD_11 69 /* LCD data pin 11 */
38816 +#define GPIO69_MMCCLK 69 /* MMC_CLK */
38817 +#define GPIO70_LDD_12 70 /* LCD data pin 12 */
38818 +#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */
38819 +#define GPIO71_LDD_13 71 /* LCD data pin 13 */
38820 +#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */
38821 +#define GPIO72_LDD_14 72 /* LCD data pin 14 */
38822 +#define GPIO72_32kHz 72 /* 32 kHz clock */
38823 +#define GPIO73_LDD_15 73 /* LCD data pin 15 */
38824 +#define GPIO73_MBGNT 73 /* Memory controller grant */
38825 +#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */
38826 +#define GPIO75_LCD_LCLK 75 /* LCD line clock */
38827 +#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */
38828 +#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */
38829 +#define GPIO78_nCS_2 78 /* chip select 2 */
38830 +#define GPIO79_nCS_3 79 /* chip select 3 */
38831 +#define GPIO80_nCS_4 80 /* chip select 4 */
38833 +/* GPIO alternate function mode & direction */
38835 +#define GPIO_IN 0x000
38836 +#define GPIO_OUT 0x080
38837 +#define GPIO_ALT_FN_1_IN 0x100
38838 +#define GPIO_ALT_FN_1_OUT 0x180
38839 +#define GPIO_ALT_FN_2_IN 0x200
38840 +#define GPIO_ALT_FN_2_OUT 0x280
38841 +#define GPIO_ALT_FN_3_IN 0x300
38842 +#define GPIO_ALT_FN_3_OUT 0x380
38843 +#define GPIO_MD_MASK_NR 0x07f
38844 +#define GPIO_MD_MASK_DIR 0x080
38845 +#define GPIO_MD_MASK_FN 0x300
38847 +#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN)
38848 +#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT)
38849 +#define GPIO8_48MHz_MD ( 8 | GPIO_ALT_FN_1_OUT)
38850 +#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT)
38851 +#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT)
38852 +#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT)
38853 +#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT)
38854 +#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT)
38855 +#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT)
38856 +#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN)
38857 +#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT)
38858 +#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT)
38859 +#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT)
38860 +#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
38861 +#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
38862 +#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
38863 +#define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT)
38864 +#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
38865 +#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
38866 +#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
38867 +#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)
38868 +#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)
38869 +#define GPIO28_BITCLK_I2S_MD (28 | GPIO_ALT_FN_2_IN)
38870 +#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
38871 +#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)
38872 +#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)
38873 +#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
38874 +#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)
38875 +#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)
38876 +#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)
38877 +#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT)
38878 +#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
38879 +#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)
38880 +#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
38881 +#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)
38882 +#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)
38883 +#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)
38884 +#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)
38885 +#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
38886 +#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
38887 +#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
38888 +#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
38889 +#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
38890 +#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
38891 +#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
38892 +#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
38893 +#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
38894 +#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
38895 +#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
38896 +#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
38897 +#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
38898 +#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
38899 +#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
38900 +#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
38901 +#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
38902 +#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)
38903 +#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)
38904 +#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)
38905 +#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)
38906 +#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)
38907 +#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)
38908 +#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)
38909 +#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)
38910 +#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT)
38911 +#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT)
38912 +#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT)
38913 +#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT)
38914 +#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT)
38915 +#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT)
38916 +#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT)
38917 +#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN)
38918 +#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT)
38919 +#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT)
38920 +#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT)
38921 +#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT)
38922 +#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT)
38923 +#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT)
38924 +#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT)
38925 +#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT)
38926 +#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT)
38927 +#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT)
38928 +#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT)
38929 +#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT)
38930 +#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT)
38931 +#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT)
38932 +#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT)
38933 +#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT)
38934 +#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT)
38935 +#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT)
38936 +#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT)
38937 +#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
38938 +#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
38945 +#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
38946 +#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
38947 +#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
38948 +#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
38949 +#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
38950 +#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
38951 +#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
38952 +#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
38953 +#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
38954 +#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
38955 +#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
38956 +#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
38958 +#define PSSR_RDH (1 << 5) /* Read Disable Hold */
38959 +#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
38960 +#define PSSR_VFS (1 << 2) /* VDD Fault Status */
38961 +#define PSSR_BFS (1 << 1) /* Battery Fault Status */
38962 +#define PSSR_SSS (1 << 0) /* Software Sleep Status */
38964 +#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
38965 +#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
38966 +#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
38967 +#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
38969 +#define RCSR_GPR (1 << 3) /* GPIO Reset */
38970 +#define RCSR_SMR (1 << 2) /* Sleep Mode */
38971 +#define RCSR_WDR (1 << 1) /* Watchdog Reset */
38972 +#define RCSR_HWR (1 << 0) /* Hardware Reset */
38976 + * SSP Serial Port Registers
38979 +#define SSCR0 __REG(0x41000000) /* SSP Control Register 0 */
38980 +#define SSCR1 __REG(0x41000004) /* SSP Control Register 1 */
38981 +#define SSSR __REG(0x41000008) /* SSP Status Register */
38982 +#define SSITR __REG(0x4100000C) /* SSP Interrupt Test Register */
38983 +#define SSDR __REG(0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
38987 + * MultiMediaCard (MMC) controller
38990 +#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */
38991 +#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */
38992 +#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */
38993 +#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */
38994 +#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */
38995 +#define MMC_RESTO __REG(0x41100014) /* Expected response time out */
38996 +#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */
38997 +#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */
38998 +#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */
38999 +#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */
39000 +#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */
39001 +#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */
39002 +#define MMC_CMD __REG(0x41100030) /* Index of current command */
39003 +#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */
39004 +#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */
39005 +#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */
39006 +#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */
39007 +#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */
39014 +#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
39015 +#define CKEN __REG(0x41300004) /* Clock Enable Register */
39016 +#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
39018 +#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
39019 +#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
39020 +#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
39022 +#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
39023 +#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
39024 +#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
39025 +#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
39026 +#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
39027 +#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
39028 +#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
39029 +#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
39030 +#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
39031 +#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
39032 +#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
39033 +#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */
39034 +#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */
39036 +#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
39037 +#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
39044 +#define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */
39045 +#define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */
39046 +#define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */
39047 +#define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */
39048 +#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
39049 +#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
39050 +#define LCSR __REG(0x44000038) /* LCD Controller Status Register */
39051 +#define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */
39052 +#define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */
39053 +#define TMEDCR __REG(0x44000044) /* TMED Control Register */
39055 +#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
39056 +#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */
39057 +#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */
39058 +#define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */
39059 +#define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */
39060 +#define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */
39061 +#define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */
39062 +#define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */
39064 +#define LCCR0_ENB (1 << 0) /* LCD Controller enable */
39065 +#define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */
39066 +#define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */
39067 +#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
39068 +#define LCCR0_SFM (1 << 4) /* Start of frame mask */
39069 +#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
39070 +#define LCCR0_EFM (1 << 6) /* End of Frame mask */
39071 +#define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */
39072 +#define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */
39073 +#define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */
39074 +#define LCCR0_DIS (1 << 10) /* LCD Disable */
39075 +#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
39076 +#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
39077 +#define LCCR0_PDD_S 12
39078 +#define LCCR0_BM (1 << 20) /* Branch mask */
39079 +#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
39081 +#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
39082 +#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \
39083 + (((Pixel) - 1) << FShft (LCCR1_PPL))
39085 +#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
39086 +#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
39087 + /* pulse Width [1..64 Tpix] */ \
39088 + (((Tpix) - 1) << FShft (LCCR1_HSW))
39090 +#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
39091 + /* count - 1 [Tpix] */
39092 +#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
39093 + /* [1..256 Tpix] */ \
39094 + (((Tpix) - 1) << FShft (LCCR1_ELW))
39096 +#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
39097 + /* Wait count - 1 [Tpix] */
39098 +#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
39099 + /* [1..256 Tpix] */ \
39100 + (((Tpix) - 1) << FShft (LCCR1_BLW))
39103 +#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
39104 +#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
39105 + (((Line) - 1) << FShft (LCCR2_LPP))
39107 +#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
39108 + /* Width - 1 [Tln] (L_FCLK) */
39109 +#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
39110 + /* Width [1..64 Tln] */ \
39111 + (((Tln) - 1) << FShft (LCCR2_VSW))
39113 +#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
39114 + /* count [Tln] */
39115 +#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
39116 + /* [0..255 Tln] */ \
39117 + ((Tln) << FShft (LCCR2_EFW))
39119 +#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
39120 + /* Wait count [Tln] */
39121 +#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
39122 + /* [0..255 Tln] */ \
39123 + ((Tln) << FShft (LCCR2_BFW))
39126 +#define LCCR3_PCD (0xff) /* Pixel clock divisor */
39127 +#define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */
39128 +#define LCCR3_ACB_S 8
39131 +#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
39132 +#define LCCR3_API_S 16
39133 +#define LCCR3_VSP (1 << 20) /* vertical sync polarity */
39134 +#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
39135 +#define LCCR3_PCP (1 << 22) /* pixel clock polarity */
39136 +#define LCCR3_OEP (1 << 23) /* output enable polarity */
39138 +#define LCCR3_BPP (7 << 24) /* bits per pixel */
39139 +#define LCCR3_BPP_S 24
39141 +#define LCCR3_DPC (1 << 27) /* double pixel clock mode */
39144 +#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
39145 +#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \
39146 + (((Div) << FShft (LCCR3_PCD)))
39149 +#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
39150 +#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \
39151 + (((Bpp) << FShft (LCCR3_BPP)))
39153 +#define LCCR3_ACB Fld (8, 8) /* AC Bias */
39154 +#define LCCR3_Acb(Acb) /* BAC Bias */ \
39155 + (((Acb) << FShft (LCCR3_ACB)))
39157 +#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
39158 + /* pulse active High */
39159 +#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
39161 +#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
39162 + /* active High */
39163 +#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
39166 +#define LCSR_LDD (1 << 0) /* LCD Disable Done */
39167 +#define LCSR_SOF (1 << 1) /* Start of frame */
39168 +#define LCSR_BER (1 << 2) /* Bus error */
39169 +#define LCSR_ABC (1 << 3) /* AC Bias count */
39170 +#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
39171 +#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
39172 +#define LCSR_OU (1 << 6) /* output FIFO underrun */
39173 +#define LCSR_QD (1 << 7) /* quick disable */
39174 +#define LCSR_EOF (1 << 8) /* end of frame */
39175 +#define LCSR_BS (1 << 9) /* branch status */
39176 +#define LCSR_SINT (1 << 10) /* subsequent interrupt */
39178 +#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
39180 +#define LCSR_LDD (1 << 0) /* LCD Disable Done */
39181 +#define LCSR_SOF (1 << 1) /* Start of frame */
39182 +#define LCSR_BER (1 << 2) /* Bus error */
39183 +#define LCSR_ABC (1 << 3) /* AC Bias count */
39184 +#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
39185 +#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
39186 +#define LCSR_OU (1 << 6) /* output FIFO underrun */
39187 +#define LCSR_QD (1 << 7) /* quick disable */
39188 +#define LCSR_EOF (1 << 8) /* end of frame */
39189 +#define LCSR_BS (1 << 9) /* branch status */
39190 +#define LCSR_SINT (1 << 10) /* subsequent interrupt */
39192 +#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
39195 + * Memory controller
39198 +#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
39199 +#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
39200 +#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
39201 +#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
39202 +#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
39203 +#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
39204 +#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
39205 +#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
39206 +#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
39207 +#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
39208 +#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
39209 +#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
39210 +#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
39211 +#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
39212 +#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
39213 +#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
39214 +#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
39216 +#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
39217 +#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
39218 +#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
39219 +#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
39220 +#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
39221 +#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
39222 +#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
39223 +#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
39224 +#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
39225 +#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
39226 +#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
39227 +#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
39228 +#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
39232 +++ linux-2.4.27/include/asm-arm/arch-pxa/serial.h
39235 + * linux/include/asm-arm/arch-pxa/serial.h
39237 + * Author: Nicolas Pitre
39238 + * Copyright: (C) 2001 MontaVista Software Inc.
39240 + * This program is free software; you can redistribute it and/or modify
39241 + * it under the terms of the GNU General Public License version 2 as
39242 + * published by the Free Software Foundation.
39246 +#define BAUD_BASE 921600
39248 +/* Standard COM flags */
39249 +#define STD_COM_FLAGS (ASYNC_SKIP_TEST)
39251 +#define STD_SERIAL_PORT_DEFNS \
39253 + type: PORT_PXA, \
39254 + xmit_fifo_size: 32, \
39255 + baud_base: BAUD_BASE, \
39256 + iomem_base: (void *)&FFUART,\
39257 + iomem_reg_shift: 2, \
39258 + io_type: SERIAL_IO_MEM32,\
39259 + irq: IRQ_FFUART, \
39260 + flags: STD_COM_FLAGS, \
39262 + type: PORT_PXA, \
39263 + xmit_fifo_size: 32, \
39264 + baud_base: BAUD_BASE, \
39265 + iomem_base: (void *)&BTUART,\
39266 + iomem_reg_shift: 2, \
39267 + io_type: SERIAL_IO_MEM32,\
39268 + irq: IRQ_BTUART, \
39269 + flags: STD_COM_FLAGS, \
39271 + type: PORT_PXA, \
39272 + xmit_fifo_size: 32, \
39273 + baud_base: BAUD_BASE, \
39274 + iomem_base: (void *)&STUART,\
39275 + iomem_reg_shift: 2, \
39276 + io_type: SERIAL_IO_MEM32,\
39277 + irq: IRQ_STUART, \
39278 + flags: STD_COM_FLAGS, \
39281 +#define RS_TABLE_SIZE 8
39283 +#define EXTRA_SERIAL_PORT_DEFNS
39286 +++ linux-2.4.27/include/asm-arm/arch-pxa/system.h
39289 + * linux/include/asm-arm/arch-pxa/system.h
39291 + * Author: Nicolas Pitre
39292 + * Created: Jun 15, 2001
39293 + * Copyright: MontaVista Software Inc.
39295 + * This program is free software; you can redistribute it and/or modify
39296 + * it under the terms of the GNU General Public License version 2 as
39297 + * published by the Free Software Foundation.
39300 +#include "hardware.h"
39302 +static inline void arch_idle(void)
39307 +static inline void arch_reset(char mode)
39309 + if (mode == 's') {
39310 + /* Jump into ROM at address 0 */
39313 + /* Initialize the watchdog and let it fire */
39316 + OSMR3 = OSCR + 368640; /* ... in 100 ms */
39321 +++ linux-2.4.27/include/asm-arm/arch-pxa/time.h
39324 + * linux/include/asm-arm/arch-pxa/time.h
39326 + * Author: Nicolas Pitre
39327 + * Created: Jun 15, 2001
39328 + * Copyright: MontaVista Software Inc.
39330 + * This program is free software; you can redistribute it and/or modify
39331 + * it under the terms of the GNU General Public License version 2 as
39332 + * published by the Free Software Foundation.
39336 +static inline unsigned long pxa_get_rtc_time(void)
39341 +static int pxa_set_rtc(void)
39343 + unsigned long current_time = xtime.tv_sec;
39345 + if (RTSR & RTSR_ALE) {
39346 + /* make sure not to forward the clock over an alarm */
39347 + unsigned long alarm = RTAR;
39348 + if (current_time >= alarm && alarm >= RCNR)
39349 + return -ERESTARTSYS;
39351 + RCNR = current_time;
39355 +/* IRQs are disabled before entering here from do_gettimeofday() */
39356 +static unsigned long pxa_gettimeoffset (void)
39358 + unsigned long ticks_to_match, elapsed, usec;
39360 + /* Get ticks before next timer match */
39361 + ticks_to_match = OSMR0 - OSCR;
39363 + /* We need elapsed ticks since last match */
39364 + elapsed = LATCH - ticks_to_match;
39366 + /* Now convert them to usec */
39367 + usec = (unsigned long)(elapsed*tick)/LATCH;
39372 +static void pxa_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
39377 + do_profile(regs);
39379 + /* Loop until we get ahead of the free running timer.
39380 + * This ensures an exact clock tick count and time acuracy.
39381 + * IRQs are disabled inside the loop to ensure coherence between
39382 + * lost_ticks (updated in do_timer()) and the match reg value, so we
39383 + * can use do_gettimeofday() from interrupt handlers.
39388 + save_flags_cli( flags );
39390 + OSSR = OSSR_M0; /* Clear match on timer 0 */
39391 + next_match = (OSMR0 += LATCH);
39392 + restore_flags( flags );
39393 + } while( (signed long)(next_match - OSCR) <= 0 );
39396 +extern inline void setup_timer (void)
39398 + gettimeoffset = pxa_gettimeoffset;
39399 + set_rtc = pxa_set_rtc;
39400 + xtime.tv_sec = pxa_get_rtc_time();
39401 + timer_irq.handler = pxa_timer_interrupt;
39402 + OSMR0 = 0; /* set initial match at 0 */
39403 + OSSR = 0xf; /* clear status on all timers */
39404 + setup_arm_irq(IRQ_OST0, &timer_irq);
39405 + OIER |= OIER_E0; /* enable match on timer 0 to cause interrupts */
39406 + OSCR = 0; /* initialize free-running timer, force first match */
39410 +++ linux-2.4.27/include/asm-arm/arch-pxa/timex.h
39413 + * linux/include/asm-arm/arch-pxa/timex.h
39415 + * Author: Nicolas Pitre
39416 + * Created: Jun 15, 2001
39417 + * Copyright: MontaVista Software Inc.
39419 + * This program is free software; you can redistribute it and/or modify
39420 + * it under the terms of the GNU General Public License version 2 as
39421 + * published by the Free Software Foundation.
39425 + * PXA250/210 timer
39427 +#define CLOCK_TICK_RATE 3686400
39428 +#define CLOCK_TICK_FACTOR 80
39430 +++ linux-2.4.27/include/asm-arm/arch-pxa/trizeps2.h
39433 + * linux/include/asm-arm/arch-pxa/trizeps2.h
39435 + * This program is free software; you can redistribute it and/or modify
39436 + * it under the terms of the GNU General Public License version 2 as
39437 + * published by the Free Software Foundation.
39439 + * Copyright (c) 2002 Luc De Cock, Teradyne DS, Ltd.
39441 + * 2002-10-10: Initial code started from idp.h
39446 + * Note: this file must be safe to include in assembly files
39449 +/* comment out following if you have a board with 32MB RAM */
39450 +//#define PXA_TRIZEPS2_64MB 1
39451 +#undef PXA_TRIZEPS2_64MB
39453 +#define TRIZEPS2_FLASH_PHYS (PXA_CS0_PHYS)
39454 +#define TRIZEPS2_ALT_FLASH_PHYS (PXA_CS1_PHYS)
39455 +#define TRIZEPS2_MEDIAQ_PHYS (PXA_CS3_PHYS)
39456 +#define TRIZEPS2_IDE_PHYS (PXA_CS5_PHYS + 0x03000000)
39457 +#define TRIZEPS2_ETH_PHYS (0x0C800000)
39458 +#define TRIZEPS2_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000)
39459 +#define TRIZEPS2_BCR_PHYS (0x0E000000)
39460 +#define TRIZEPS2_CPLD_PHYS (0x0C000000)
39463 + * virtual memory map
39466 +#define TRIZEPS2_IDE_BASE (0xf0000000)
39467 +#define TRIZEPS2_IDE_SIZE (1*1024*1024)
39469 +#define TRIZEPS2_ETH_BASE (0xf1000000)
39470 +#define TRIZEPS2_ETH_SIZE (1*1024*1024)
39471 +#define ETH_BASE TRIZEPS2_ETH_BASE //smc9194 driver compatibility issue
39473 +#define TRIZEPS2_COREVOLT_BASE (TRIZEPS2_ETH_BASE + TRIZEPS2_ETH_SIZE)
39474 +#define TRIZEPS2_COREVOLT_SIZE (1*1024*1024)
39476 +#define TRIZEPS2_BCR_BASE (0xf0000000)
39477 +#define TRIZEPS2_BCR_SIZE (1*1024*1024)
39479 +#define BCR_P2V(x) ((x) - TRIZEPS2_BCR_PHYS + TRIZEPS2_BCR_BASE)
39480 +#define BCR_V2P(x) ((x) - TRIZEPS2_BCR_BASE + TRIZEPS2_BCR_PHYS)
39482 +#ifndef __ASSEMBLY__
39483 +# define __BCR_REG(x) (*((volatile unsigned short *)BCR_P2V(x)))
39485 +# define __BCR_REG(x) BCR_P2V(x)
39488 +/* board level registers */
39489 +#define TRIZEPS2_CPLD_BASE (0xf0100000)
39490 +#define CPLD_P2V(x) ((x) - TRIZEPS2_CPLD_PHYS + TRIZEPS2_CPLD_BASE)
39491 +#define CPLD_V2P(x) ((x) - TRIZEPS2_CPLD_BASE + TRIZEPS2_CPLD_PHYS)
39493 +#ifndef __ASSEMBLY__
39494 +# define __CPLD_REG(x) (*((volatile unsigned short *)CPLD_P2V(x)))
39496 +# define __CPLD_REG(x) CPLD_P2V(x)
39499 +#define _TRIZEPS2_PCCARD_STATUS (0x0c000000)
39500 +#define TRIZEPS2_PCCARD_STATUS __CPLD_REG(_TRIZEPS2_PCCARD_STATUS)
39503 + * CS memory timing via Static Memory Control Register (MSC0-2)
39506 +#define MSC_CS(cs,val) ((val)<<((cs&1)<<4))
39508 +#define MSC_RBUFF_SHIFT 15
39509 +#define MSC_RBUFF(x) ((x)<<MSC_RBUFF_SHIFT)
39510 +#define MSC_RBUFF_SLOW MSC_RBUFF(0)
39511 +#define MSC_RBUFF_FAST MSC_RBUFF(1)
39513 +#define MSC_RRR_SHIFT 12
39514 +#define MSC_RRR(x) ((x)<<MSC_RRR_SHIFT)
39516 +#define MSC_RDN_SHIFT 8
39517 +#define MSC_RDN(x) ((x)<<MSC_RDN_SHIFT)
39519 +#define MSC_RDF_SHIFT 4
39520 +#define MSC_RDF(x) ((x)<<MSC_RDF_SHIFT)
39522 +#define MSC_RBW_SHIFT 3
39523 +#define MSC_RBW(x) ((x)<<MSC_RBW_SHIFT)
39524 +#define MSC_RBW_16 MSC_RBW(1)
39525 +#define MSC_RBW_32 MSC_RBW(0)
39527 +#define MSC_RT_SHIFT 0
39528 +#define MSC_RT(x) ((x)<<MSC_RT_SHIFT)
39532 + * Bit masks for various registers
39534 +// TRIZEPS2_BCR_PCCARD_PWR
39535 +#define PCC_3V (1 << 0)
39536 +#define PCC_5V (1 << 1)
39537 +#define PCC_EN1 (1 << 2)
39538 +#define PCC_EN0 (1 << 3)
39540 +// TRIZEPS2_BCR_PCCARD_EN
39541 +#define PCC_RESET (1 << 6)
39542 +#define PCC_ENABLE (1 << 0)
39544 +// TRIZEPS2_BSR_PCCARDx_STATUS
39545 +#define _PCC_WRPROT (1 << 7) // 7-4 read as low true
39546 +#define _PCC_RESET (1 << 6)
39547 +#define _PCC_IRQ (1 << 5)
39548 +#define _PCC_INPACK (1 << 4)
39549 +#define PCC_BVD1 (1 << 0)
39550 +#define PCC_BVD2 (1 << 1)
39551 +#define PCC_VS1 (1 << 2)
39552 +#define PCC_VS2 (1 << 3)
39554 +// TRIZEPS2_BCR_CONTROL bits
39555 +#define BCR_LCD_ON (1 << 4)
39556 +#define BCR_LCD_OFF (0)
39557 +#define BCR_LCD_MASK (1 << 4)
39558 +#define BCR_PCMCIA_RESET (1 << 7)
39559 +#define BCR_PCMCIA_NORMAL (0)
39561 +#define PCC_DETECT (GPLR(24) & GPIO_bit(24))
39562 +#define PCC_READY (GPLR(1) & GPIO_bit(1))
39564 +// Board Control Register
39565 +#define _TRIZEPS2_BCR_CONTROL (TRIZEPS2_BCR_PHYS)
39566 +#define TRIZEPS2_BCR_CONTROL __BCR_REG(_TRIZEPS2_BCR_CONTROL)
39568 +// Board TTL-IO register
39569 +#define TRIZEPS2_TTLIO_PHYS (0x0d800000)
39570 +#define TRIZEPS2_TTLIO_BASE (0xf2000000)
39571 +// various ioctl cmds
39572 +#define TTLIO_RESET 0
39573 +#define TTLIO_GET 1
39574 +#define TTLIO_SET 2
39575 +#define TTLIO_UNSET 3
39578 + * Macros for LCD Driver
39581 +#ifdef CONFIG_FB_PXA
39583 +#define FB_BACKLIGHT_ON()
39584 +#define FB_BACKLIGHT_OFF()
39586 +#define FB_PWR_ON()
39587 +#define FB_PWR_OFF()
39589 +#define FB_VLCD_ON() WRITE_TRIZEPS2_BCR(BCR_LCD_ON,BCR_LCD_MASK);
39590 +#define FB_VLCD_OFF() WRITE_TRIZEPS2_BCR(BCR_LCD_OFF,BCR_LCD_MASK);
39594 +/* A listing of interrupts used by external hardware devices */
39596 +#define GPIO_TOUCH_PANEL_IRQ 2
39597 +#define TOUCH_PANEL_IRQ IRQ_GPIO(GPIO_TOUCH_PANEL_IRQ)
39598 +#define GPIO_ETHERNET_IRQ 19
39599 +#define ETHERNET_IRQ IRQ_GPIO(GPIO_ETHERNET_IRQ)
39600 +#define GPIO_TTLIO_IRQ 23
39601 +#define TTLIO_IRQ IRQ_GPIO(GPIO_TTLIO_IRQ)
39603 +#define TOUCH_PANEL_IRQ_EDGE GPIO_FALLING_EDGE
39604 +#define IDE_IRQ_EDGE GPIO_RISING_EDGE
39605 +#define ETHERNET_IRQ_EDGE GPIO_RISING_EDGE
39607 +#define PCMCIA_S_CD_VALID IRQ_GPIO(24)
39608 +#define PCMCIA_S_CD_VALID_EDGE GPIO_BOTH_EDGES
39610 +#define PCMCIA_S_RDYINT IRQ_GPIO(1)
39611 +#define PCMCIA_S_RDYINT_EDGE GPIO_FALLING_EDGE
39614 + * macros for MTD driver
39617 +#define FLASH_WRITE_PROTECT_DISABLE() // ((TRIZEPS2_CPLD_FLASH_WE) &= ~(0x1))
39618 +#define FLASH_WRITE_PROTECT_ENABLE() // ((TRIZEPS2_CPLD_FLASH_WE) |= (0x1))
39620 +/* shadow registers for write only registers */
39621 +#ifndef __ASSEMBLY__
39622 +extern unsigned short trizeps2_bcr_shadow;
39626 + * macros to write to write only register
39628 + * none of these macros are protected from
39629 + * multiple drivers using them in interrupt context.
39632 +#define WRITE_TRIZEPS2_BCR(value, mask) \
39634 + trizeps2_bcr_shadow = ((value & mask) | (trizeps2_bcr_shadow & ~mask));\
39635 + TRIZEPS2_BCR_CONTROL = trizeps2_bcr_shadow;\
39639 +++ linux-2.4.27/include/asm-arm/arch-pxa/uncompress.h
39642 + * linux/include/asm-arm/arch-pxa/uncompress.h
39644 + * Author: Nicolas Pitre
39645 + * Copyright: (C) 2001 MontaVista Software Inc.
39647 + * This program is free software; you can redistribute it and/or modify
39648 + * it under the terms of the GNU General Public License version 2 as
39649 + * published by the Free Software Foundation.
39652 +#define FFUART ((volatile unsigned long *)0x40100000)
39653 +#define BTUART ((volatile unsigned long *)0x40200000)
39654 +#define STUART ((volatile unsigned long *)0x40700000)
39656 +#define UART FFUART
39659 +static __inline__ void putc(char c)
39661 + while (!(UART[5] & 0x20));
39666 + * This does not append a newline
39668 +static void puts(const char *s)
39681 +#define arch_decomp_setup()
39682 +#define arch_decomp_wdog()
39684 +++ linux-2.4.27/include/asm-arm/arch-pxa/vmalloc.h
39687 + * linux/include/asm-arm/arch-pxa/vmalloc.h
39689 + * Author: Nicolas Pitre
39690 + * Copyright: (C) 2001 MontaVista Software Inc.
39692 + * This program is free software; you can redistribute it and/or modify
39693 + * it under the terms of the GNU General Public License version 2 as
39694 + * published by the Free Software Foundation.
39698 + * Just any arbitrary offset to the start of the vmalloc VM area: the
39699 + * current 8MB value just means that there will be a 8MB "hole" after the
39700 + * physical memory until the kernel virtual memory starts. That means that
39701 + * any out-of-bounds memory accesses will hopefully be caught.
39702 + * The vmalloc() routines leaves a hole of 4kB between each vmalloced
39703 + * area for the same reason. ;)
39705 +#define VMALLOC_OFFSET (8*1024*1024)
39706 +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
39707 +#define VMALLOC_VMADDR(x) ((unsigned long)(x))
39708 +#define VMALLOC_END (0xe8000000)
39709 --- linux-2.4.27/include/asm-arm/assembler.h~2.4.27-vrs1-pxa1
39710 +++ linux-2.4.27/include/asm-arm/assembler.h
39713 #include <asm/proc/ptrace.h>
39714 #include <asm/proc/assembler.h>
39717 + * Endian independent macros for shifting bytes within registers.
39722 +#define byte(x) (x*8)
39726 +#define byte(x) ((3-x)*8)
39730 + * Data preload for architectures that support it
39732 +#if __LINUX_ARM_ARCH__ >= 5
39733 +#define PLD(code...) code
39735 +#define PLD(code...)
39738 --- linux-2.4.27/include/asm-arm/bitops.h~2.4.27-vrs1-pxa1
39739 +++ linux-2.4.27/include/asm-arm/bitops.h
39741 return (((unsigned char *) addr)[nr >> 3] >> (nr & 7)) & 1;
39744 +#if __LINUX_ARM_ARCH__ < 5
39747 * ffz = Find First Zero in word. Undefined if no zero exists,
39748 * so code should check against ~0UL first..
39749 @@ -117,6 +119,23 @@
39751 #define ffs(x) generic_ffs(x)
39756 + * On ARMv5 and above those functions can be implemented around
39757 + * the clz instruction for much better code efficiency.
39760 +extern __inline__ int generic_fls(int x);
39762 + ( __builtin_constant_p(x) ? generic_fls(x) : \
39763 + ({ int __r; asm("clz%?\t%0, %1" : "=r"(__r) : "r"(x)); 32-__r; }) )
39764 +#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
39765 +#define __ffs(x) (ffs(x) - 1)
39766 +#define ffz(x) __ffs( ~(x) )
39771 * hweightN: returns the hamming weight (i.e. the number
39772 * of bits set) of a N-bit word
39773 --- linux-2.4.27/include/asm-arm/io.h~2.4.27-vrs1-pxa1
39774 +++ linux-2.4.27/include/asm-arm/io.h
39775 @@ -168,7 +168,7 @@
39776 * devices. This is the "generic" version. The PCI specific version
39779 -extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
39780 +extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle, unsigned long flags);
39781 extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
39782 extern void consistent_sync(void *vaddr, size_t size, int rw);
39784 --- linux-2.4.27/include/asm-arm/memory.h~2.4.27-vrs1-pxa1
39785 +++ linux-2.4.27/include/asm-arm/memory.h
39786 @@ -123,6 +123,9 @@
39787 ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size)); \
39790 +/* We want large page mapping possible */
39791 +#define VMALLOC_ALIGN 0x10000
39796 --- linux-2.4.27/include/asm-arm/proc-armv/pgtable.h~2.4.27-vrs1-pxa1
39797 +++ linux-2.4.27/include/asm-arm/proc-armv/pgtable.h
39799 #ifndef __ASM_PROC_PGTABLE_H
39800 #define __ASM_PROC_PGTABLE_H
39802 -#include <asm/proc/domain.h>
39803 -#include <asm/arch/vmalloc.h>
39806 * entries per page directory level: they are two-level, so
39807 * we don't really have any PMD directory.
39808 @@ -26,27 +23,92 @@
39809 #define PTRS_PER_PMD 1
39810 #define PTRS_PER_PGD 4096
39816 -/* PMD types (actually level 1 descriptor) */
39817 -#define PMD_TYPE_MASK 0x0003
39818 -#define PMD_TYPE_FAULT 0x0000
39819 -#define PMD_TYPE_TABLE 0x0001
39820 -#define PMD_TYPE_SECT 0x0002
39821 -#define PMD_UPDATABLE 0x0010
39822 -#define PMD_SECT_CACHEABLE 0x0008
39823 -#define PMD_SECT_BUFFERABLE 0x0004
39824 -#define PMD_SECT_AP_WRITE 0x0400
39825 -#define PMD_SECT_AP_READ 0x0800
39827 + * Hardware page table definitions.
39829 + * + Level 1 descriptor (PMD)
39832 +#define PMD_TYPE_MASK (3 << 0)
39833 +#define PMD_TYPE_FAULT (0 << 0)
39834 +#define PMD_TYPE_TABLE (1 << 0)
39835 +#define PMD_TYPE_SECT (2 << 0)
39836 +#define PMD_UPDATABLE (1 << 4)
39837 #define PMD_DOMAIN(x) ((x) << 5)
39838 +#define PMD_PROTECTION (1 << 9) /* v5 */
39842 +#define PMD_SECT_BUFFERABLE (1 << 2)
39843 +#define PMD_SECT_CACHEABLE (1 << 3)
39844 +#define PMD_SECT_AP_WRITE (1 << 10)
39845 +#define PMD_SECT_AP_READ (1 << 11)
39846 +#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
39852 + * + Level 2 descriptor (PTE)
39855 +#define PTE_TYPE_MASK (3 << 0)
39856 +#define PTE_TYPE_FAULT (0 << 0)
39857 +#define PTE_TYPE_LARGE (1 << 0)
39858 +#define PTE_TYPE_SMALL (2 << 0)
39859 +#define PTE_TYPE_EXT (3 << 0) /* v5 */
39860 +#define PTE_BUFFERABLE (1 << 2)
39861 +#define PTE_CACHEABLE (1 << 3)
39864 + * - extended small page/tiny page
39866 +#define PTE_EXT_AP_UNO_SRO (0 << 4)
39867 +#define PTE_EXT_AP_UNO_SRW (1 << 4)
39868 +#define PTE_EXT_AP_URO_SRW (2 << 4)
39869 +#define PTE_EXT_AP_URW_SRW (3 << 4)
39870 +#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
39875 +#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
39876 +#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
39877 +#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
39878 +#define PTE_SMALL_AP_URW_SRW (0xff << 4)
39879 +#define PTE_AP_READ PTE_SMALL_AP_URO_SRW
39880 +#define PTE_AP_WRITE PTE_SMALL_AP_UNO_SRW
39883 + * "Linux" PTE definitions.
39885 + * We keep two sets of PTEs - the hardware and the linux version.
39886 + * This allows greater flexibility in the way we map the Linux bits
39887 + * onto the hardware tables, and allows us to have YOUNG and DIRTY
39890 + * The PTE table pointer refers to the hardware entries; the "Linux"
39891 + * entries are stored 1024 bytes below.
39893 +#define L_PTE_PRESENT (1 << 0)
39894 +#define L_PTE_YOUNG (1 << 1)
39895 +#define L_PTE_BUFFERABLE (1 << 2) /* matches PTE */
39896 +#define L_PTE_CACHEABLE (1 << 3) /* matches PTE */
39897 +#define L_PTE_USER (1 << 4)
39898 +#define L_PTE_WRITE (1 << 5)
39899 +#define L_PTE_EXEC (1 << 6)
39900 +#define L_PTE_DIRTY (1 << 7)
39902 +#ifndef __ASSEMBLY__
39904 +#include <asm/proc/domain.h>
39905 +#include <asm/arch/vmalloc.h>
39907 #define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_DOMAIN(DOMAIN_USER))
39908 #define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_DOMAIN(DOMAIN_KERNEL))
39910 #define pmd_bad(pmd) (pmd_val(pmd) & 2)
39911 -#define set_pmd(pmdp,pmd) cpu_set_pmd(pmdp,pmd)
39912 +#define set_pmd(pmdp,pmd) cpu_set_pmd(pmdp, pmd)
39914 static inline pmd_t __mk_pmd(pte_t *ptep, unsigned long prot)
39916 @@ -75,49 +137,8 @@
39917 return __phys_to_virt(ptr);
39924 -/* PTE types (actually level 2 descriptor) */
39925 -#define PTE_TYPE_MASK 0x0003
39926 -#define PTE_TYPE_FAULT 0x0000
39927 -#define PTE_TYPE_LARGE 0x0001
39928 -#define PTE_TYPE_SMALL 0x0002
39929 -#define PTE_AP_READ 0x0aa0
39930 -#define PTE_AP_WRITE 0x0550
39931 -#define PTE_CACHEABLE 0x0008
39932 -#define PTE_BUFFERABLE 0x0004
39934 #define set_pte(ptep, pte) cpu_set_pte(ptep,pte)
39936 -/* We now keep two sets of ptes - the physical and the linux version.
39937 - * This gives us many advantages, and allows us greater flexibility.
39939 - * The Linux pte's contain:
39943 - * 2 bufferable - matches physical pte
39944 - * 3 cacheable - matches physical pte
39950 - * 12-31 virtual page address
39952 - * These are stored at the pte pointer; the physical PTE is at -1024bytes
39954 -#define L_PTE_PRESENT (1 << 0)
39955 -#define L_PTE_YOUNG (1 << 1)
39956 -#define L_PTE_BUFFERABLE (1 << 2)
39957 -#define L_PTE_CACHEABLE (1 << 3)
39958 -#define L_PTE_USER (1 << 4)
39959 -#define L_PTE_WRITE (1 << 5)
39960 -#define L_PTE_EXEC (1 << 6)
39961 -#define L_PTE_DIRTY (1 << 7)
39964 * The following macros handle the cache and bufferable bits...
39966 @@ -162,5 +183,8 @@
39967 * Mark the prot value as uncacheable and unbufferable.
39969 #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) & ~(L_PTE_CACHEABLE | L_PTE_BUFFERABLE))
39970 +#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~L_PTE_CACHEABLE)
39972 +#endif /* __ASSEMBLY__ */
39974 #endif /* __ASM_PROC_PGTABLE_H */
39975 --- linux-2.4.27/include/asm-arm/proc-armv/processor.h~2.4.27-vrs1-pxa1
39976 +++ linux-2.4.27/include/asm-arm/proc-armv/processor.h
39978 #define KERNEL_STACK_SIZE PAGE_SIZE
39980 struct context_save_struct {
39981 +#ifdef CONFIG_CPU_XSCALE
39984 unsigned long cpsr;
39991 +#ifdef CONFIG_CPU_XSCALE
39992 +#define INIT_CSS (struct context_save_struct){ 0, SVC_MODE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
39994 #define INIT_CSS (struct context_save_struct){ SVC_MODE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
39997 #define EXTRA_THREAD_STRUCT \
39998 unsigned int domain;
39999 --- linux-2.4.27/include/asm-arm/proc-fns.h~2.4.27-vrs1-pxa1
40000 +++ linux-2.4.27/include/asm-arm/proc-fns.h
40001 @@ -124,6 +124,14 @@
40002 # define CPU_NAME sa1100
40005 +# ifdef CONFIG_CPU_XSCALE
40008 +# define MULTI_CPU
40010 +# define CPU_NAME xscale
40016 --- linux-2.4.27/include/asm-arm/procinfo.h~2.4.27-vrs1-pxa1
40017 +++ linux-2.4.27/include/asm-arm/procinfo.h
40019 #define HWCAP_FAST_MULT 16
40020 #define HWCAP_FPA 32
40021 #define HWCAP_VFP 64
40022 -#define HWCAP_EDSP 128
40023 +#define HWCAP_EDSP 128 /* El Segundo */
40024 #define HWCAP_JAVA 256
40025 +#define HWCAP_XSCALE 512 /* XScale DSP co-processor */
40028 --- linux-2.4.27/include/asm-arm/uaccess.h~2.4.27-vrs1-pxa1
40029 +++ linux-2.4.27/include/asm-arm/uaccess.h
40031 __get_user_x(__r1, __p, __e, 1, "lr"); \
40034 - __get_user_x(__r1, __p, __e, 2, "r2", "lr"); \
40035 + __get_user_x(__r1, __p, __e, 2, "ip", "lr"); \
40038 __get_user_x(__r1, __p, __e, 4, "lr"); \
40039 --- linux-2.4.27/include/linux/cramfs_fs_sb.h~2.4.27-vrs1-pxa1
40040 +++ linux-2.4.27/include/linux/cramfs_fs_sb.h
40042 unsigned long blocks;
40043 unsigned long files;
40044 unsigned long flags;
40045 +#ifdef CONFIG_CRAMFS_LINEAR
40046 + unsigned long linear_phys_addr;
40047 + char * linear_virt_addr;
40052 --- linux-2.4.27/include/linux/i2c-id.h~2.4.27-vrs1-pxa1
40053 +++ linux-2.4.27/include/linux/i2c-id.h
40054 @@ -100,6 +100,10 @@
40055 #define I2C_DRIVERID_SAA7191 57 /* video decoder */
40056 #define I2C_DRIVERID_INDYCAM 58 /* SGI IndyCam */
40058 +#define I2C_DRIVERID_DS1307 46 /* real time clock: DS1307 */
40059 +#define I2C_DRIVERID_24LC64 47 /* EEprom 24LC64 */
40060 +#define I2C_DRIVERID_FM24CLB4 48 /* EEprom FM24CLB4 */
40062 #define I2C_DRIVERID_EXP0 0xF0 /* experimental use id's */
40063 #define I2C_DRIVERID_EXP1 0xF1
40064 #define I2C_DRIVERID_EXP2 0xF2
40065 @@ -172,6 +176,8 @@
40067 #define I2C_ALGO_OCP 0x120000 /* IBM or otherwise On-chip I2C algorithm */
40069 +#define I2C_ALGO_PXA 0x400000 /* Intel PXA I2C algorithm */
40071 #define I2C_ALGO_EXP 0x800000 /* experimental */
40073 #define I2C_ALGO_MASK 0xff0000 /* Mask for algorithms */
40074 --- linux-2.4.27/include/linux/serial.h~2.4.27-vrs1-pxa1
40075 +++ linux-2.4.27/include/linux/serial.h
40076 @@ -75,11 +75,13 @@
40077 #define PORT_16654 11
40078 #define PORT_16850 12
40079 #define PORT_RSA 13 /* RSA-DV II/S card */
40080 -#define PORT_MAX 13
40081 +#define PORT_PXA 14
40082 +#define PORT_MAX 14
40084 #define SERIAL_IO_PORT 0
40085 #define SERIAL_IO_HUB6 1
40086 #define SERIAL_IO_MEM 2
40087 +#define SERIAL_IO_MEM32 3
40089 struct serial_uart_config {
40091 --- linux-2.4.27/include/linux/serial_reg.h~2.4.27-vrs1-pxa1
40092 +++ linux-2.4.27/include/linux/serial_reg.h
40093 @@ -119,6 +119,14 @@
40094 #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
40097 + * The Intel PXA250/210 chip defines those bits
40099 +#define UART_IER_DMAE 0x80 /* DMA Requests Enable */
40100 +#define UART_IER_UUE 0x40 /* UART Unit Enable */
40101 +#define UART_IER_NRZE 0x20 /* NRZ coding Enable */
40102 +#define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */
40105 * These are the definitions for the Modem Control Register
40107 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C750) */
40109 +++ linux-2.4.27/include/mmc/ioctl.h
40112 + * linux/include/linux/mmc/ioctl.h
40114 + * Author: Vladimir Shebordaev
40115 + * Copyright: MontaVista Software Inc.
40117 + * $Id: ioctl.h,v 0.2 2002/07/11 16:28:21 ted Exp ted $
40119 + * This program is free software; you can redistribute it and/or modify
40120 + * it under the terms of the GNU General Public License version 2 as
40121 + * published by the Free Software Foundation.
40123 +#ifndef __MMC_IOCTL_H__
40124 +#define __MMC_IOCTL_H__
40126 +#include <asm/ioctl.h>
40128 +/* IOCTL commands provided by MMC subsystem */
40129 +#define IOCMMCSTRNSMODE _IOW('I',0x0f01,int)
40130 +#define IOCMMCGTRNSMODE _IOR('I',0x0f02,int)
40131 +#define IOCMMCGCARDESC _IOR('I',0x0f03,int) /* FIXME */
40132 +#define IOCMMCGBLKSZMAX _IOR('I',0x0f04,ssize_t)
40133 +#define IOCMMCGNOBMAX _IOR('I',0x0f05,ssize_t)
40135 +#endif /* __MMC_IOCTL_H__ */
40137 +++ linux-2.4.27/include/mmc/mmc.h
40140 + * linux/include/linux/mmc/mmc.h
40142 + * Author: Vladimir Shebordaev
40143 + * Copyright: MontaVista Software Inc.
40145 + * $Id: mmc.h,v 0.2.1.2 2002/07/25 16:29:47 ted Exp ted $
40147 + * This program is free software; you can redistribute it and/or modify
40148 + * it under the terms of the GNU General Public License version 2 as
40149 + * published by the Free Software Foundation.
40154 +#include <linux/types.h>
40155 +#include <mmc/types.h>
40161 + MMC_CARD_TYPE_RO = 1,
40162 + MMC_CARD_TYPE_RW,
40170 + MMC_CARD_STATE_IDLE = 1,
40171 + MMC_CARD_STATE_READY,
40172 + MMC_CARD_STATE_IDENT,
40173 + MMC_CARD_STATE_STNBY,
40174 + MMC_CARD_STATE_TRAN,
40175 + MMC_CARD_STATE_DATA,
40176 + MMC_CARD_STATE_RCV,
40177 + MMC_CARD_STATE_DIS,
40178 + MMC_CARD_STATE_UNPLUGGED=0xff
40182 + * Data transfer mode
40184 +enum _mmc_transfer_mode {
40185 + MMC_TRANSFER_MODE_STREAM = 1,
40186 + MMC_TRANSFER_MODE_BLOCK_SINGLE,
40187 + MMC_TRANSFER_MODE_BLOCK_MULTIPLE,
40188 + MMC_TRANSFER_MODE_UNDEFINED = -1
40191 +struct _mmc_card_csd_rec { /* CSD register contents */
40192 +/* FIXME: BYTE_ORDER */
40195 + tmp_write_protect:1,
40196 + perm_write_protect:1,
40198 + file_format_grp:1;
40199 + u64 content_prot_app:1,
40201 + write_bl_partial:1,
40207 + erase_grp_mult:5,
40208 + erase_grp_size:5,
40210 + vdd_w_curr_max:3,
40211 + vdd_w_curr_min:3,
40212 + vdd_r_curr_max:3,
40213 + vdd_r_curr_min:3,
40217 + read_blk_misalign:1,
40218 + write_blk_misalign:1,
40219 + read_bl_partial:1;
40221 + u16 read_bl_len:4,
40231 +struct _mmc_card_cid_rec { /* CID register contents */
40232 +/* FIXME: BYTE_ORDER */
40244 + * Public card description
40246 +struct _mmc_card_info_rec {
40248 + mmc_transfer_mode_t transfer_mode; /* current data transfer mode */
40249 + __u16 rca; /* card's RCA assigned during initialization */
40250 + struct _mmc_card_csd_rec csd;
40251 + struct _mmc_card_cid_rec cid;
40252 + __u32 tran_speed; /* kbits */
40253 + __u16 read_bl_len;
40254 + __u16 write_bl_len;
40255 + size_t capacity; /* card's capacity in bytes */
40259 + * Micsellaneous defines
40262 +#define SEEK_SET (0)
40266 +#define SEEK_CUR (1)
40270 +#define SEEK_END (2)
40281 +#endif /* __MMC_H__ */
40283 +++ linux-2.4.27/include/mmc/types.h
40286 + * linux/include/linux/mmc/types.h
40288 + * Author: Vladimir Shebordaev
40289 + * Copyright: MontaVista Software Inc.
40291 + * $Id: types.h,v 0.2 2002/07/11 16:28:21 ted Exp ted $
40293 + * This program is free software; you can redistribute it and/or modify
40294 + * it under the terms of the GNU General Public License version 2 as
40295 + * published by the Free Software Foundation.
40297 +#ifndef __MMC_TYPES_H__
40298 +#define __MMC_TYPES_H__
40301 +typedef enum _mmc_type mmc_type_t;
40302 +typedef enum _mmc_state mmc_state_t;
40303 +typedef enum _mmc_transfer_mode mmc_transfer_mode_t;
40305 +typedef struct _mmc_card_csd_rec mmc_card_csd_rec_t;
40306 +typedef struct _mmc_card_cid_rec mmc_card_cid_rec_t;
40308 +typedef struct _mmc_card_info_rec mmc_card_info_rec_t;
40309 +typedef struct _mmc_card_info_rec *mmc_card_info_t;
40311 +typedef enum _mmc_error mmc_error_t;
40313 +#endif /* __MMC_TYPES_H__ */
40315 +++ linux-2.4.27/include/video/lcdctrl.h
40320 + * Generic LCD control for brightness, contrast, etc.
40321 + * Device specific drivers implement a lcdctrl_device and
40322 + * provides access to it via lcdctrl_device_get_ops().
40324 + * Copyright (C) 2002 Intrinsyc Software Inc.
40326 + * This program is free software; you can redistribute it and/or modify
40327 + * it under the terms of the GNU General Public License version 2 as
40328 + * published by the Free Software Foundation.
40331 + * Mar 2002: Initial version [FB]
40334 +#ifndef __LCD_CONTROL_H
40335 +#define __LCD_CONTROL_H
40337 +#define _LCDCTRL_IOCTL_ON 1
40338 +#define _LCDCTRL_IOCTL_OFF 2
40339 +#define _LCDCTRL_IOCTL_INTENSITY 3
40340 +#define _LCDCTRL_IOCTL_BRIGHTNESS 4
40341 +#define _LCDCTRL_IOCTL_CONTRAST 5
40342 +#define _LCDCTRL_IOCTL_GET_BRIGHTNESS 6
40343 +#define _LCDCTRL_IOCTL_GET_CONTRAST 7
40344 +#define _LCDCTRL_IOCTL_GET_INTENSITY 8
40346 +#define _LCD_CONTROL_NAME "lcdctrl"
40348 +#define LCD_NO_SYNC 0
40349 +#define LCD_SYNC_NEEDED 1
40351 +int lcdctrl_enable( void);
40352 +int lcdctrl_disable( void);
40354 +/* intensity, contrast, and brightness take values
40355 + * between 0..100.
40357 +int lcdctrl_set_intensity( int intensity);
40358 +int lcdctrl_set_contrast( int contrast, int sync);
40359 +int lcdctrl_set_brightness( int brightness);
40361 +int lcdctrl_get_intensity( void);
40362 +int lcdctrl_get_contrast( void);
40363 +int lcdctrl_get_brightness( void);
40365 +struct lcdctrl_device
40367 + int (*init)( int*, int*, int*);
40368 + int (*enable)(void);
40369 + int (*disable)(void);
40370 + int (*set_intensity)( int i);
40371 + int (*set_brightness)( int b);
40372 + int (*set_contrast)( int c, int sync);
40375 +int lcdctrl_init( void);
40378 --- linux-2.4.27/init/do_mounts.c~2.4.27-vrs1-pxa1
40379 +++ linux-2.4.27/init/do_mounts.c
40380 @@ -394,6 +394,16 @@
40384 +#ifdef CONFIG_ROOT_CRAMFS_LINEAR
40385 +static int __init mount_linear_cramfs_root(void)
40387 + void *data = root_mount_data;
40388 + if (sys_mount("/dev/root","/root","cramfs",root_mountflags,data) == 0)
40394 static int __init create_dev(char *name, kdev_t dev, char *devfs_name)
40397 @@ -759,6 +769,16 @@
40399 static void __init mount_root(void)
40401 +#ifdef CONFIG_ROOT_CRAMFS_LINEAR
40402 + if (ROOT_DEV == MKDEV(0, 0)) {
40403 + if (mount_linear_cramfs_root()) {
40404 + sys_chdir("/root");
40405 + ROOT_DEV = current->fs->pwdmnt->mnt_sb->s_dev;
40406 + printk("VFS: Mounted root (linear cramfs filesystem).\n");
40411 #ifdef CONFIG_ROOT_NFS
40412 if (MAJOR(ROOT_DEV) == NFS_MAJOR
40413 && MINOR(ROOT_DEV) == NFS_MINOR) {
40414 --- linux-2.4.27/mm/memory.c~2.4.27-vrs1-pxa1
40415 +++ linux-2.4.27/mm/memory.c
40416 @@ -1018,6 +1018,41 @@
40417 return 1; /* Minor fault */
40420 + if (pte_present(pte) && pte_read(pte)) {
40422 + * Handle COW of XIP memory.
40423 + * Note that the source memory actually isn't a ram page so
40424 + * no struct page is associated to the source pte.
40429 + spin_unlock(&mm->page_table_lock);
40430 + new_page = alloc_page(GFP_HIGHUSER);
40434 + /* copy XIP data to memory */
40435 + dst = kmap_atomic(new_page, KM_USER0);
40436 + ret = copy_from_user(dst, (void*)address, PAGE_SIZE);
40437 + kunmap_atomic(dst, KM_USER0);
40439 + /* make sure pte didn't change while we dropped the lock */
40440 + spin_lock(&mm->page_table_lock);
40441 + if (!ret && pte_same(*page_table, pte)) {
40443 + break_cow(vma, new_page, address, page_table);
40444 + lru_cache_add(new_page);
40445 + spin_unlock(&mm->page_table_lock);
40446 + return 1; /* Minor fault */
40449 + /* pte changed: back off */
40450 + spin_unlock(&mm->page_table_lock);
40451 + page_cache_release(new_page);
40452 + return ret ? -1 : 1;
40455 spin_unlock(&mm->page_table_lock);
40456 printk("do_wp_page: bogus page at address %08lx\n", address);