1 --- linux-2.6.11.2/arch/arm/mm/proc-xscale.S 2005-03-09 00:12:44.000000000 -0800
2 +++ linux-2.6.11.2/arch/arm/mm/proc-xscale.S 2005-06-18 15:39:22.701222319 -0700
4 * same state as it would be if it had been reset, and branch
5 * to what would be the reset vector.
7 + * This code is ixp425 specific with respect to the reset of
8 + * the 'configuration register' - to be found at address
9 + * 0xC40000020 'IXP425_EXP_CNFGO'
11 * loc: location to jump to for soft reset
14 ENTRY(cpu_xscale_reset)
15 + @ always branch to 0
18 + @ disable both FIQ and IRQ, put us into 32 bit
19 + @ SVC mode (no thumb).
20 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
21 msr cpsr_c, r1 @ reset CPSR
22 - mrc p15, 0, r1, c1, c0, 0 @ ctrl register
23 - bic r1, r1, #0x0086 @ ........B....CA.
24 - bic r1, r1, #0x3900 @ ..VIZ..S........
25 - mcr p15, 0, r1, c1, c0, 0 @ ctrl register
26 - mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
27 - bic r1, r1, #0x0001 @ ...............M
28 - mcr p15, 0, r1, c1, c0, 0 @ ctrl register
29 - @ CAUTION: MMU turned off from this point. We count on the pipeline
30 - @ already containing those two last instructions to survive.
32 + @ disable debug, clock and power registers are
34 + mcr p14, 0, r0, c10, c0, 0 @ disable debug
36 + @ disable the performance monitor
37 + mcr p14, 0, r0, c0, c1, 0 @ PMNC (ctrl reg)
38 + mcr p14, 0, r0, c4, c1, 0 @ INTEN (intrpt enable)
40 + @ wait for p14 to complete
41 + mrc p14, 0, ip, c4, c1, 0 @ arbitrary read
44 + @ clear the PID register
45 + mcr p15, 0, r0, c13, c0, 0 @ OR nothing with address!
47 + @ unlock the TLBs and the I/D cache locks
48 + mcr p15, 0, r0, c10, c8, 1 @ data TLB unlocked
49 + mcr p15, 0, r0, c10, c4, 1 @ instruction TLB unlocked
50 + mcr p15, 0, r0, c9, c2, 1 @ unlock data cache
51 + mcr p15, 0, r0, c9, c1, 1 @ unlock instruction cache
53 + @ zap the minidata cache to write through with write coalescing
55 + mov r1, #0x21 @ MD=b10, K=1
56 + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
57 + mrc p15, 0, ip, c1, c0, 0 @ read of ctrl register
59 + mcr p15, 0, r1, c1, c0, 1 @ write through, no coalesc
61 + @ set the control register, the MMU is enabled but everything else
62 + @ is disabled at this point, r1 contains the control register flags
63 + @ the process is now in little-endian mode (no matter, we aren't
64 + @ going to do any <word access)
65 + mov r1, #0x79 @ 00vIz0rs.b1111caM
66 + orr r1, r1, #0x1000 @ I-cache enable
67 + mcr p15, 0, r1, c1, c0, 0
68 + mrc p15, 0, ip, c1, c0, 0
69 + mov ip, ip @ sync to coproc
70 + mov r1, #0x78 @ 00viz0rs.b1111cam
72 + @ and flush the I/D cache and BTB
73 + mcr p15, 0, r0, c7, c7, 0
75 + @ that's most of the work. The only thing which remains is to
76 + @ remap the flash memory and disable the MMU. Do some setup
77 + @ for this, also get ready to set the LED to red and put in
80 + @ get ready to reset the configuration registers in the expansion
81 + @ bus. CFGN1 disables byte swap and interrupt.
82 + ldr r3, =IXP4XX_PERIPHERAL_BASE_VIRT
83 + ldr r4, [r3, #IXP4XX_EXP_CFG1_OFFSET]
84 + bic r4, r4, #0x13 @ -BYTE_SWAP_EN, -SW_INT?
85 + str r4, [r3, #IXP4XX_EXP_CFG1_OFFSET]
87 + @ load the current configuration register from its
88 + @ virtual address and set the MEM_MAP bit ready to map the
89 + @ flash back to address 0, but don't write it yet.
90 + ldr r4, [r3, #IXP4XX_EXP_CFG0_OFFSET]
91 + orr r4, r4, #0x80000000
93 + @ load the GPIO OUTR register address and current value,
94 + @ set the low nibble to just red LED on.
95 + ldr r5, =IXP4XX_GPIO_BASE_VIRT
96 + ldr r6, [r5, #IXP4XX_GPIO_GPOUTR_OFFSET]
100 + @ load the watchdog timer virtual address, set the key and
101 + @ the timer and start the down counter
102 + ldr r7, =IXP4XX_TIMER_BASE_VIRT
103 + ldr r8, =IXP4XX_WDT_KEY @ set key
104 + str r8, [r7, #IXP4XX_OSWK_OFFSET]
105 + mov r8, #0x1000000 @ about 0.25 seconds
106 + str r8, [r7, #IXP4XX_OSWT_OFFSET] @ set timer
107 + mov r8, #(IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE)
108 + str r8, [r7, #IXP4XX_OSWE_OFFSET] @ enable reset
110 + @ invalidate the TLBs to ensure that there isn't a match for
112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
114 + mrc p15, 0, ip, c1, c0, 0 @ read of ctrl register
117 + @ remap the flash (after preloading instructions into the
118 + @ I-cache) then turn off the MMU and branch to 0 when it is
119 + @ off. It seems that RedBoot relies on the page tables being
120 + @ set up on boot, so set the page table head register too.
121 + mov r7, #0x4000 @ flash page table
122 + ldr r8, =IXP4XX_GPIO_BASE_PHYS @ for led setting
123 + bic r9, r6, #0xc @ disk1+disk2 led on
124 + str r6, [r5, #IXP4XX_GPIO_GPOUTR_OFFSET] @ red led
127 + @ cached instructions These 8 instructions are valid in the cache
128 + @ along with the associated TLB as soon as the first is executed.
129 + @ They are used to effect the transition back into the flash
132 +cache: str r4, [r3, #IXP4XX_EXP_CFG0_OFFSET] @0 no memory!
133 + mcr p15, 0, r7, c2, c0, 0 @1 set translation table base
134 + mcr p15, 0, r1, c1, c0, 0 @2 no MMU!
135 + mrc p15, 0, ip, c2, c0, 0 @3 arbitrary read of cp15
136 + str r9, [r8, #IXP4XX_GPIO_GPOUTR_OFFSET] @4 red+disk1+disk2 led
137 + sub pc, r0, ip, LSR #32 @5 sync and branch to zero
142 * cpu_xscale_do_idle()
146 ENTRY(cpu_xscale_do_idle)
148 - mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
149 + @ NSLU2/ixp420: not implemented in the hardware, docs
150 + @ say do not write!
152 + @mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
155 /* ================================= CACHE ================================ */