1 --- 050125/include/asm-arm/proc-armv/ptrace.h Tue Jan 25 00:22:44 2005
2 +++ 050218/include/asm-arm/proc-armv/ptrace.h Thu Feb 17 16:13:54 2005
7 +#if defined(CONFIG_CPU_PXA27X)
9 + long mmx[ 16*2 + 6 + 1 ];
13 #define ARM_cpsr uregs[16]
14 --- 050125/include/asm-arm/sigcontext.h Tue Jan 25 00:22:42 2005
15 +++ 050218/include/asm-arm/sigcontext.h Thu Feb 17 18:16:28 2005
18 unsigned long arm_cpsr;
19 unsigned long fault_address;
20 +#if defined(CONFIG_CPU_PXA27X)
21 + unsigned long arm_cpar;
22 + unsigned long arm_mmx[ 16*2 + 6 + 1 ];
27 --- 050125/include/asm-arm/elf.h Tue Jan 25 00:54:49 2005
28 +++ 050218/include/asm-arm/elf.h Thu Feb 17 16:19:02 2005
30 #ifndef __ASMARM_ELF_H
31 #define __ASMARM_ELF_H
33 +#include <linux/config.h>
36 * ELF register definitions..
41 #define EF_ARM_APCS26 0x08
42 +#define EF_ARM_SOFT_FLOAT 0x200
44 #define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
45 typedef elf_greg_t elf_gregset_t[ELF_NGREG];
46 --- 050125/arch/arm/kernel/entry-armv.S Tue Jan 25 00:21:45 2005
47 +++ 050218/arch/arm/kernel/entry-armv.S Fri Feb 18 07:29:34 2005
49 tst \irqstat, #IRQ_MASK_DOORBELLHOST
50 movne \irqnr, #IRQ_DOORBELLHOST
54 tst \irqstat, #IRQ_MASK_I2OINPOST
55 movne \irqnr, #IRQ_I2OINPOST
59 #elif defined(CONFIG_ARCH_L7200)
60 #include <asm/hardware.h>
63 .equ irq_base_addr, IO_BASE_2
69 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
70 mov \irqstat, #irq_base_addr @ Virt addr IRQ regs
71 add \irqstat, \irqstat, #0x00001000 @ Status reg
75 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
78 /* Read all interrupts pending... */
79 ldr \irqnr, =IO_ADDRESS(PLAT_PERIPHERAL_BASE) + OMAHA_INTPND
80 ldr \irqstat, [\irqnr] /* INTPND */
88 #elif defined(CONFIG_ARCH_CLPS711X)
96 #elif defined (CONFIG_ARCH_CAMELOT)
97 #include <asm/arch/platform.h>
98 #undef IRQ_MODE /* same name defined in asm/proc/ptrace.h */
99 #include <asm/arch/int_ctrl00.h>
105 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
108 ldr \irqstat, =INT_ID(IO_ADDRESS(EXC_INT_CTRL00_BASE))
109 - ldr \irqnr,[\irqstat]
110 + ldr \irqnr,[\irqstat]
112 subne \irqnr,\irqnr,#1
118 .macro irq_prio_table
120 mov pc, r7 @ check, if this is a relevant code
121 cmp r0, #0 @ check return value
122 beq 1f @ else let linux do what it has to do
127 adrsvc al, r9, 1f @ r9 = normal FP return
129 stmia r5, {r2 - r4} @ Save USR pc, cpsr, old_r0
131 alignment_trap r7, r7, __temp_abt
132 +#ifdef CONFIG_CPU_PXA27X
136 mov r0, r2 @ remove once everyones in sync
138 @@ -1001,6 +1004,9 @@
139 stmia r8, {r5 - r7} @ save pc, psr, old_r0
141 alignment_trap r4, r7, __temp_irq
142 +#ifdef CONFIG_CPU_PXA27X
147 #ifdef CONFIG_PREEMPT
148 @@ -1039,6 +1045,9 @@
149 stmia r8, {r5 - r7} @ Save USR pc, cpsr, old_r0
150 stmdb r8, {sp, lr}^ @ Save user sp, lr
151 alignment_trap r4, r7, __temp_und
152 +#ifdef CONFIG_CPU_PXA27X
156 tst r6, #T_BIT @ Thumb mode
158 @@ -1068,6 +1077,9 @@
159 stmia r8, {r5 - r7} @ Save USR pc, cpsr, old_r0
160 stmdb r8, {sp, lr}^ @ Save sp_usr lr_usr
161 alignment_trap r4, r7, __temp_abt
162 +#ifdef CONFIG_CPU_PXA27X
167 msr cpsr_c, r0 @ Enable interrupts
168 @@ -1394,7 +1406,7 @@
171 mrc p15, 0, r2, c3, c0
177 --- 050125/arch/arm/kernel/entry-header.S Tue Jan 25 00:21:45 2005
178 +++ 050218/arch/arm/kernel/entry-header.S Thu Feb 17 20:15:24 2005
180 @ Stack format (ensured by USER_* and SVC_*)
183 -#define S_FRAME_SIZE 72
186 +#ifdef CONFIG_CPU_PXA27X
189 + #define MMX_WR0 (0x00)
190 + #define MMX_WR1 (0x08)
191 + #define MMX_WR2 (0x10)
192 + #define MMX_WR3 (0x18)
193 + #define MMX_WR4 (0x20)
194 + #define MMX_WR5 (0x28)
195 + #define MMX_WR6 (0x30)
196 + #define MMX_WR7 (0x38)
197 + #define MMX_WR8 (0x40)
198 + #define MMX_WR9 (0x48)
199 + #define MMX_WR10 (0x50)
200 + #define MMX_WR11 (0x58)
201 + #define MMX_WR12 (0x60)
202 + #define MMX_WR13 (0x68)
203 + #define MMX_WR14 (0x70)
204 + #define MMX_WR15 (0x78)
205 + #define MMX_WCSSF (0x80)
206 + #define MMX_WCASF (0x84)
207 + #define MMX_WCGR0 (0x88)
208 + #define MMX_WCGR1 (0x8C)
209 + #define MMX_WCGR2 (0x90)
210 + #define MMX_WCGR3 (0x94)
212 + #define MMX_SIZE (0x98)
214 + #define S_FRAME_SIZE (76+4+MMX_SIZE)
217 + #define S_OLD_R0 68
220 + #define S_FRAME_SIZE 72
221 + #define S_OLD_R0 68
225 #define S_FRAME_SIZE 68
228 set_cpsr_c \temp, #MODE_SVC
231 +#ifdef CONFIG_CPU_PXA27X
232 + .macro save_user_mmx
233 + mrc p15, 0, r0, c15, c1, 0
234 + str r0, [sp, #S_CPAR] @ Save CPAR
237 + add r0,sp,#S_MMX @ StoreMMX
239 + wstrw wCSSF, [r0, #MMX_WCSSF]
240 + wstrw wCASF, [r0, #MMX_WCASF]
241 + wstrw wCGR0, [r0, #MMX_WCGR0]
242 + wstrw wCGR1, [r0, #MMX_WCGR1]
243 + wstrw wCGR2, [r0, #MMX_WCGR2]
244 + wstrw wCGR3, [r0, #MMX_WCGR3]
245 + wstrd wR0, [r0, #MMX_WR0]
246 + wstrd wR1, [r0, #MMX_WR1]
247 + wstrd wR2, [r0, #MMX_WR2]
248 + wstrd wR3, [r0, #MMX_WR3]
249 + wstrd wR4, [r0, #MMX_WR4]
250 + wstrd wR5, [r0, #MMX_WR5]
251 + wstrd wR6, [r0, #MMX_WR6]
252 + wstrd wR7, [r0, #MMX_WR7]
253 + wstrd wR8, [r0, #MMX_WR8]
254 + wstrd wR9, [r0, #MMX_WR9]
255 + wstrd wR10, [r0, #MMX_WR10]
256 + wstrd wR11, [r0, #MMX_WR11]
257 + wstrd wR12, [r0, #MMX_WR12]
258 + wstrd wR13, [r0, #MMX_WR13]
259 + wstrd wR14, [r0, #MMX_WR14]
260 + wstrd wR15, [r0, #MMX_WR15]
263 + mcr p15, 0, r0, c15, c1, 0 @ CP0 Only.
264 + ldr r0, [sp] @ Restore R0
268 .macro save_user_regs
269 sub sp, sp, #S_FRAME_SIZE
270 stmia sp, {r0 - r12} @ Calling r0 - r12
272 str lr, [sp, #S_PC] @ Save calling PC
273 str r8, [sp, #S_PSR] @ Save CPSR
274 str r0, [sp, #S_OLD_R0] @ Save OLD_R0
279 * Must be called with IRQs already disabled.
281 .macro restore_user_regs
282 +#ifdef CONFIG_CPU_PXA27X
283 + ldr r1, [sp, #S_CPAR]
284 + mcr p15, 0, r1, c15, c1, 0
287 + add r1,sp,#S_MMX @ LoadMMX
289 + wldrd wR0, [r1, #MMX_WR0]
290 + wldrd wR1, [r1, #MMX_WR1]
291 + wldrd wR2, [r1, #MMX_WR2]
292 + wldrd wR3, [r1, #MMX_WR3]
293 + wldrd wR4, [r1, #MMX_WR4]
294 + wldrd wR5, [r1, #MMX_WR5]
295 + wldrd wR6, [r1, #MMX_WR6]
296 + wldrd wR7, [r1, #MMX_WR7]
297 + wldrd wR8, [r1, #MMX_WR8]
298 + wldrd wR9, [r1, #MMX_WR9]
299 + wldrd wR10, [r1, #MMX_WR10]
300 + wldrd wR11, [r1, #MMX_WR11]
301 + wldrd wR12, [r1, #MMX_WR12]
302 + wldrd wR13, [r1, #MMX_WR13]
303 + wldrd wR14, [r1, #MMX_WR14]
304 + wldrd wR15, [r1, #MMX_WR15]
305 + wldrw wCSSF, [r1, #MMX_WCSSF]
306 + wldrw wCASF, [r1, #MMX_WCASF]
307 + wldrw wCGR0, [r1, #MMX_WCGR0]
308 + wldrw wCGR1, [r1, #MMX_WCGR1]
309 + wldrw wCGR2, [r1, #MMX_WCGR2]
310 + wldrw wCGR3, [r1, #MMX_WCGR3]
313 ldr r1, [sp, #S_PSR] @ Get calling cpsr
314 ldr lr, [sp, #S_PC]! @ Get PC
315 msr spsr, r1 @ save in spsr_svc
317 * Must be called with IRQs already disabled.
319 .macro fast_restore_user_regs
320 +#ifdef CONFIG_CPU_PXA27X
321 + ldr r1, [sp, #S_OFF + S_CPAR]
322 + mcr p15, 0, r1, c15, c1, 0
325 + add r1,sp,#S_OFF + S_MMX @ LoadMMX
327 + wldrd wR0, [r1, #MMX_WR0]
328 + wldrd wR1, [r1, #MMX_WR1]
329 + wldrd wR2, [r1, #MMX_WR2]
330 + wldrd wR3, [r1, #MMX_WR3]
331 + wldrd wR4, [r1, #MMX_WR4]
332 + wldrd wR5, [r1, #MMX_WR5]
333 + wldrd wR6, [r1, #MMX_WR6]
334 + wldrd wR7, [r1, #MMX_WR7]
335 + wldrd wR8, [r1, #MMX_WR8]
336 + wldrd wR9, [r1, #MMX_WR9]
337 + wldrd wR10, [r1, #MMX_WR10]
338 + wldrd wR11, [r1, #MMX_WR11]
339 + wldrd wR12, [r1, #MMX_WR12]
340 + wldrd wR13, [r1, #MMX_WR13]
341 + wldrd wR14, [r1, #MMX_WR14]
342 + wldrd wR15, [r1, #MMX_WR15]
343 + wldrw wCSSF, [r1, #MMX_WCSSF]
344 + wldrw wCASF, [r1, #MMX_WCASF]
345 + wldrw wCGR0, [r1, #MMX_WCGR0]
346 + wldrw wCGR1, [r1, #MMX_WCGR1]
347 + wldrw wCGR2, [r1, #MMX_WCGR2]
348 + wldrw wCGR3, [r1, #MMX_WCGR3]
351 ldr r1, [sp, #S_OFF + S_PSR] @ get calling cpsr
352 ldr lr, [sp, #S_OFF + S_PC]! @ get pc
353 msr spsr, r1 @ save in spsr_svc
354 --- 050125/arch/arm/kernel/signal.c Tue Jan 25 00:21:45 2005
355 +++ 050218/arch/arm/kernel/signal.c Thu Feb 17 18:22:10 2005
360 +#if defined(CONFIG_CPU_PXA27X)
362 + __get_user_error(regs->cpar, &sc->arm_cpar, err);
363 + for( _m=0; _m<16*2 + 6 + 1; ++_m ) {
364 + __get_user_error(regs->mmx[ _m ], &sc->arm_mmx[ _m ], err);
367 __get_user_error(regs->ARM_r0, &sc->arm_r0, err);
368 __get_user_error(regs->ARM_r1, &sc->arm_r1, err);
369 __get_user_error(regs->ARM_r2, &sc->arm_r2, err);
374 +#if defined(CONFIG_CPU_PXA27X)
376 + __put_user_error(regs->cpar, &sc->arm_cpar, err);
377 + for( _m=0; _m<16*2 + 6 + 1; ++_m ) {
378 + __put_user_error(regs->mmx[ _m ], &sc->arm_mmx[ _m ], err);
381 __put_user_error(regs->ARM_r0, &sc->arm_r0, err);
382 __put_user_error(regs->ARM_r1, &sc->arm_r1, err);
383 __put_user_error(regs->ARM_r2, &sc->arm_r2, err);
384 --- 050125/arch/arm/Makefile Tue Jan 25 00:21:44 2005
385 +++ 050218/arch/arm/Makefile Thu Feb 17 09:38:40 2005
388 ifeq ($(CONFIG_ARCH_SHARP_SL),y)
389 CROSS_COMPILE = arm-linux-
390 -arch-y :=-D__LINUX_ARM_ARCH__=4 -march=armv4 -Wa,-mxscale
391 +#arch-y :=-D__LINUX_ARM_ARCH__=4 -march=armv4 -Wa,-mxscale
392 +arch-y :=-D__LINUX_ARM_ARCH__=4 -Wa,-mcpu=iwmmxt
393 tune-y :=-mtune=strongarm
400 -ifeq ($(CONFIG_XIP_KERNEL),y)
401 +ifeq ($(CONFIG_XIP_KERNEL),y)
402 DATAADDR := $(TEXTADDR)
403 # Replace phys addr with virt addr while keeping offset from base.
404 # Virt base addr also defined in include/asm-arm/arch-*/hardware.h
405 --- 050125/fs/binfmt_elf.c Tue Jan 25 00:22:37 2005
406 +++ 050218/fs/binfmt_elf.c Thu Feb 17 08:52:54 2005
411 +#if defined(CONFIG_CPU_PXA27X)
412 + if( elf_ex.e_flags & EF_ARM_SOFT_FLOAT ) {
413 + regs->cpar = 0x03; //CP0 CP1 Used.
416 + regs->cpar = 0x01; //CP0 Only.
420 start_thread(regs, elf_entry, bprm->p);
421 if (current->ptrace & PT_PTRACED)
422 send_sig(SIGTRAP, current, 0);