org.handhelds.familiar/packages/linux/openzaurus-pxa27x-2.4.20-rmk2-embedix20050602/P02++050226.patch

   1 --- BASE/arch/arm/mach-pxa/pxa27x_power.c       Sat Feb 26 01:35:47 2005
   2 +++ 050226/arch/arm/mach-pxa/pxa27x_power.c     Sat Feb 26 02:01:45 2005
   3 @@ -152,6 +152,10 @@
   4
   5  #if defined(CONFIG_CHANGE_CORE_VOLT)
   6  static unsigned char current_core_voltage = 0x1a;
   7 +static unsigned char core_voltage_value   = 0;
   8 +extern unsigned int CCCR_ValAdr_high;
   9 +#include  <linux/sem.h>
  10 +static DECLARE_MUTEX(core_voltage_sem);
  11  #endif
  12
  13  void PrintParamTable(void);
  14 @@ -397,9 +401,9 @@
  15  }
  16  #endif //DEBUG
  17
  18 +#if !defined(CONFIG_CHANGE_CORE_VOLT)
  19  static void cpu_xscale_voltage_low(void)
  20  {
  21 -
  22    pwr_i2c_open();
  23    pwr_i2c_write( 0x0c, 0x13 );  // 1.00V - SlewRate 1
  24    //pwr_i2c_write( 0x0c, 0x12 );  // 0.95V - SlewRate 1
  25 @@ -409,38 +413,90 @@
  26  static void cpu_xscale_voltage_high(void)
  27  {
  28    pwr_i2c_open();
  29 -#if defined(CONFIG_CHANGE_CORE_VOLT)
  30 -  pwr_i2c_write( 0x0c, current_core_voltage );
  31 -  pwr_i2c_close();
  32 -  printk("current voltage %x\n", current_core_voltage );
  33 -#else
  34    pwr_i2c_write( 0x0c, 0x1a );  // 1.35V - SlewRate 1
  35    pwr_i2c_close();
  36 -#endif
  37  }
  38 +#endif
  39
  40  #if defined(CONFIG_CHANGE_CORE_VOLT)
  41 +static void cpu_xscale_voltage_change(unsigned char value)
  42 +{
  43 +  if(core_voltage_value!=value) {
  44 +    core_voltage_value  = value;
  45 +    pwr_i2c_open();
  46 +    pwr_i2c_write( 0x0c, current_core_voltage );
  47 +    pwr_i2c_close();
  48 +  }
  49 +}
  50 +
  51 +void cpu_xscale_voltage_high(void)
  52 +{
  53 +  down(&core_voltage_sem);
  54 +  cpu_xscale_voltage_change(current_core_voltage);
  55 +  up(&core_voltage_sem);
  56 +}
  57  void cpu_xscale_voltage_write(unsigned char value)
  58  {
  59    if (value > 0x10 )
  60      return;
  61    value += 0x10;
  62 +  down(&core_voltage_sem);
  63 +  core_voltage_value  = value;
  64    pwr_i2c_open();
  65    pwr_i2c_write( 0x0c, value );
  66    pwr_i2c_close();
  67    current_core_voltage = value;
  68 +  up(&core_voltage_sem);
  69    printk("current voltage %x\n", current_core_voltage );
  70
  71  }
  72 +
  73 +void  cpu_xscale_sl_change_speed_high(void)
  74 +{
  75 +  down(&core_voltage_sem);
  76 +  cpu_xscale_voltage_change(current_core_voltage);
  77 +  _cpu_xscale_sl_change_speed_high();
  78 +  up(&core_voltage_sem);
  79 +}
  80 +void  cpu_xscale_sl_change_speed_low(void)
  81 +{
  82 +  down(&core_voltage_sem);
  83 +  _cpu_xscale_sl_change_speed_low();
  84 +  cpu_xscale_voltage_change(0x13);
  85 +  up(&core_voltage_sem);
  86 +}
  87 +void  cpu_xscale_sl_change_speed_91(void)
  88 +{
  89 +  down(&core_voltage_sem);
  90 +  _cpu_xscale_sl_change_speed_91();
  91 +  core_voltage_value  = 0x13;
  92 +  pwr_i2c_open();
  93 +  pwr_i2c_write( 0x0c, core_voltage_value );
  94 +  pwr_i2c_close();
  95 +  up(&core_voltage_sem);
  96 +}
  97 +void  cpu_xscale_sl_change_speed_208(void)
  98 +{
  99 +  down(&core_voltage_sem);
 100 +  core_voltage_value  = current_core_voltage;
 101 +  pwr_i2c_open();
 102 +  pwr_i2c_write( 0x0c, core_voltage_value );
 103 +  pwr_i2c_close();
 104 +  _cpu_xscale_sl_change_speed_208();
 105 +  up(&core_voltage_sem);
 106 +}
 107 +
 108  #endif
 109
 110  #if defined(DEBUG) || defined(CONFIG_CHANGE_CORE_VOLT)
 111  unsigned char cpu_xscale_voltage_read(void)
 112  {
 113    unsigned char value=0xff;
 114 +  down(&core_voltage_sem);
 115    pwr_i2c_open();
 116    pwr_i2c_read( 0x0c, &value );
 117    pwr_i2c_close();
 118 +  up(&core_voltage_sem);
 119    return value;
 120  }
 121  #endif
 122 @@ -520,7 +576,7 @@
 123         sys_ctx.oier = OIER;
 124
 125  #if defined(CONFIG_CPU_PXA27X)
 126 -       if ( CCCR != 0x02000210 ) {
 127 +       if ( CCCR != CCCR_ValAdr_high ) {  //0x02000210 ) {
 128           cpu_xscale_sl_change_speed_high();
 129         }
 130  #endif
 131 @@ -571,8 +627,10 @@
 132         cpu_xscale_sl_disable_fastbus_mode();
 133         udelay(1);
 134         cpu_xscale_sl_change_speed_91();
 135 +#if !defined(CONFIG_CHANGE_CORE_VOLT)
 136         cpu_xscale_voltage_low();
 137  #endif
 138 +#endif
 139
 140         /* Scoop suspend */
 141         sharpsl_check_scoop_reg();
 142 @@ -790,7 +848,9 @@
 143         SCP2_REG_GPWR = sys_ctx.scp2_gpwr;
 144
 145  #if defined(PXA27X_SUSPEND)
 146 +#if !defined(CONFIG_CHANGE_CORE_VOLT)
 147         cpu_xscale_voltage_high();
 148 +#endif
 149         cpu_xscale_sl_change_speed_208();
 150         udelay(1);
 151         cpu_xscale_sl_enable_fastbus_mode();
 152 --- BASE/arch/arm/mach-pxa/sharpsl_apm.c        Sat Feb 26 01:35:52 2005
 153 +++ 050226/arch/arm/mach-pxa/sharpsl_apm.c      Sat Feb 26 01:54:16 2005
 154 @@ -143,6 +143,7 @@
 155  #if defined(CONFIG_CHANGE_CORE_VOLT)
 156  extern unsigned char cpu_xscale_voltage_read(void);
 157  extern void cpu_xscale_voltage_write(unsigned char);
 158 +extern void cpu_xscale_voltage_high(void);
 159  #endif
 160
 161  #if defined(CONFIG_SABINAL_DISCOVERY)
 162 @@ -1389,6 +1390,9 @@
 163
 164  #if defined(CONFIG_CPU_PXA27X)
 165  #if defined(CONFIG_FB_SHARPSL_PXA)
 166 +#if defined(CONFIG_CHANGE_CORE_VOLT)
 167 +    cpu_xscale_voltage_high();
 168 +#endif
 169                 while (1) {
 170                     if (!(LCCR0 & 0x1) || (GPLR(GPIO74_LCD_FCLK) &
 171                                            GPIO_bit(GPIO74_LCD_FCLK)))
 172 --- BASE/arch/arm/mach-pxa/sharpsl_suspend.S    Sat Feb 26 01:35:42 2005
 173 +++ 050226/arch/arm/mach-pxa/sharpsl_suspend.S  Sat Feb 26 01:54:16 2005
 174 @@ -1119,7 +1119,11 @@
 175  MDREFR_ValAdr_high_pre:        .word   0x001BC00B
 176  MDREFR_ValAdr_high:    .word   0x001BC030
 177
 178 +#if defined(CONFIG_CHANGE_CORE_VOLT)
 179 +ENTRY(_cpu_xscale_sl_change_speed_high)
 180 +#else
 181  ENTRY(cpu_xscale_sl_change_speed_high)
 182 +#endif
 183         stmfd   sp!, {r0, r1, r2, r3, r4, lr}
 184
 185         ldr             r0, CMR_BASE
 186 @@ -1168,7 +1172,11 @@
 187  @MDREFR_ValAdr_low:    .word   0x0019C017
 188  MDREFR_ValAdr_low:     .word   0x001BC017
 189
 190 +#if defined(CONFIG_CHANGE_CORE_VOLT)
 191 +ENTRY(_cpu_xscale_sl_change_speed_low)
 192 +#else
 193  ENTRY(cpu_xscale_sl_change_speed_low)
 194 +#endif
 195         stmfd   sp!, {r0, r1, r2, r3, r4, lr}
 196
 197         ldr             r0, CMR_BASE
 198 @@ -1261,7 +1269,11 @@
 199  MDREFR_ValAdr_91_pre:  .word   0x001BC00B
 200  MDREFR_ValAdr_91:      .word   0x001BC013
 201
 202 +#if defined(CONFIG_CHANGE_CORE_VOLT)
 203 +ENTRY(_cpu_xscale_sl_change_speed_91)
 204 +#else
 205  ENTRY(cpu_xscale_sl_change_speed_91)
 206 +#endif
 207         stmfd   sp!, {r0, r1, r2, r3, r4, lr}
 208
 209         ldr             r0, CMR_BASE
 210 @@ -1304,7 +1316,11 @@
 211  MSC2_ValAdr_208:       .word   0x7FF034D4
 212  MDREFR_ValAdr_208:     .word   0x001BC00B
 213
 214 +#if defined(CONFIG_CHANGE_CORE_VOLT)
 215 +ENTRY(_cpu_xscale_sl_change_speed_208)
 216 +#else
 217  ENTRY(cpu_xscale_sl_change_speed_208)
 218 +#endif
 219         stmfd   sp!, {r0, r1, r2, r3, r4, lr}
 220
 221         ldr             r0, CMR_BASE