org.handhelds.familiar/packages/linux/openzaurus-pxa27x-2.4.20-rmk2-embedix20050602/P17-bvdd_050222.patch

   1 diff -Nur c3000_pre/linux/drivers/video/Config.in c3000_work/linux/drivers/video/Config.in
   2 --- c3000_pre/linux/drivers/video/Config.in     2005-02-22 00:14:45.000000000 +0900
   3 +++ c3000_work/linux/drivers/video/Config.in    2005-02-21 23:36:35.000000000 +0900
   4 @@ -86,6 +86,7 @@
   5       dep_bool '  Sharp SL-Series PXA LCD support' CONFIG_FB_SHARPSL_PXA $CONFIG_ARCH_SHARP_SL
   6       if [ "$CONFIG_FB_SHARPSL_PXA" = "y" ]; then
   7         dep_bool '    Cached FB support for Sharp SL PXA LCDC' CONFIG_SHARPSL_PXA_CONSISTENT_ALLOC $CONFIG_FB_SHARPSL_PXA
   8 +       dep_tristate '    PXA270 overlay(bvdd) support(EXPERIMENTAL)' CONFIG_FB_SHARPSL_PXA_BVDD $CONFIG_FB_SHARPSL_PXA
   9       fi
  10       dep_bool '  SHARP LOGO screen support' CONFIG_SHARP_LOGO_SCREEN $CONFIG_ARCH_SHARP_SL
  11       if [ "$CONFIG_FB_PXA" != "n" -a "$CONFIG_ARCH_LUBBOCK" = "y" ]; then
  12 diff -Nur c3000_pre/linux/drivers/video/Makefile c3000_work/linux/drivers/video/Makefile
  13 --- c3000_pre/linux/drivers/video/Makefile      2005-02-22 00:14:45.000000000 +0900
  14 +++ c3000_work/linux/drivers/video/Makefile     2005-02-21 23:40:57.000000000 +0900
  15 @@ -160,6 +160,7 @@
  16  obj-$(CONFIG_FB_CORGI)            += w100fb.o fbgen.o corgi_backlight.o
  17  obj-$(CONFIG_FB_TOSA)             += tc6393fb.o fbgen.o tosa_backlight.o
  18  obj-$(CONFIG_FB_SHARPSL_PXA)      += sharpsl_pxafb.o fbgen.o corgi_backlight.o
  19 +obj-$(CONFIG_FB_SHARPSL_PXA_BVDD) += bvdd.o
  20
  21  # Generic Low Level Drivers
  22
  23 diff -Nur c3000_pre/linux/drivers/video/bvdd.c c3000_work/linux/drivers/video/bvdd.c
  24 --- c3000_pre/linux/drivers/video/bvdd.c        1970-01-01 09:00:00.000000000 +0900
  25 +++ c3000_work/linux/drivers/video/bvdd.c       2005-02-22 00:05:24.000000000 +0900
  26 @@ -0,0 +1,1124 @@
  27 +/*  bvdd.c - Create an input/output character device
  28 + */
  29 +
  30 +#include <linux/kernel.h>   /* We're doing kernel work */
  31 +#include <linux/module.h>   /* Specifically, a module */
  32 +
  33 +#if CONFIG_MODVERSIONS==1
  34 +#define MODVERSIONS
  35 +#include <linux/modversions.h>
  36 +#endif
  37 +
  38 +#include <linux/fs.h>  /* The character device definitions are here */
  39 +#include <linux/wrapper.h>
  40 +#include <linux/mm.h>
  41 +#include <linux/sched.h>
  42 +#include <asm/system.h>
  43 +#include <asm/hardware.h>
  44 +#include <asm/uaccess.h>       /* for get_user and put_user */
  45 +#include <asm/io.h>
  46 +
  47 +/* Our own ioctl numbers */
  48 +#include "bvdd.h"
  49 +#include "bvdd_p.h"
  50 +
  51 +#define SUCCESS 0
  52 +
  53 +#define DEVICE_NAME "bvdd"     /* The name for our device */
  54 +
  55 +#ifdef DEBUG
  56 +# define PRINT_DEBUG(x...) printk(KERN_WARNING DEVICE_NAME ": " x)
  57 +# define PRINT_INFO(x...) printk(KERN_WARNING DEVICE_NAME ": " x)
  58 +# define PRINT_WARN(x...) printk(KERN_WARNING DEVICE_NAME ": " x)
  59 +# define PRINT_ERROR(x...) printk(KERN_ERROR DEVICE_NAME ": " x)
  60 +# define PRINT_FATAL(x...) printk(KERN_FATAL DEVICE_NAME ": " x)
  61 +#else
  62 +# define PRINT_DEBUG(x...)
  63 +# define PRINT_INFO(x...)
  64 +# define PRINT_WARN(x...) printk(KERN_WARNING DEVICE_NAME ": " x)
  65 +# define PRINT_ERROR(x...) printk(KERN_ERROR DEVICE_NAME ": " x)
  66 +# define PRINT_FATAL(x...) printk(KERN_FATAL DEVICE_NAME ": " x)
  67 +#endif
  68 +
  69 +/* Is the device open right now? Used to prevent concurent access into the same device */
  70 +static int device_open = 0;
  71 +
  72 +static dma_addr_t vram_sharpsl_pxafb_phys;
  73 +static void *vram_virt = NULL; /* virtual address of VRAM (if NULL, VRAM is not allocated) */
  74 +static dma_addr_t vram_phys = 0; /* physical address of VRAM */
  75 +static u32 vram_size = 0;      /* VRAM size */
  76 +
  77 +#undef FDADR
  78 +// ----------------------------------------------------------------
  79 +// ¥Ç¥£¥¹¥¯¥ê¥×¥¿
  80 +// aligned on a 16-byte boundary
  81 +
  82 +typedef struct {
  83 +    unsigned long FDADR;       /* frame descriptor address */
  84 +    unsigned long FSADR;      /* DMA Frame Source Address Registers */
  85 +    unsigned long FIDR;                /* frame id reg */
  86 +    unsigned long LDCMD;       /* LCD command reg */
  87 +} descriptor_t;
  88 +
  89 +static descriptor_t *descriptors = NULL;
  90 +#ifndef USE_PXAFB_DESCRIPTOR_AREA
  91 +# define MAX_DESCRIPTORS (PAGE_SIZE / 16)
  92 +static descriptor_t *descriptor_virt; /* ¥Ç¥£¥¹¥¯¥ê¥×¥¿ÇÛÎó¤Î²¾ÁÛ¥¢¥É¥ì¥¹ */
  93 +static dma_addr_t descriptor_phys; /* ¥Ç¥£¥¹¥¯¥ê¥×¥¿ÇÛÎó¤ÎÊªÍý¥¢¥É¥ì¥¹ */
  94 +static u32 descriptor_size;    /* ¥Ç¥£¥¹¥¯¥ê¥×¥¿ÇÛÎó¤Î¥µ¥¤¥º */
  95 +#else
  96 +# define MAX_DESCRIPTORS ((PAGE_SIZE - 16) / 16)
  97 +#endif
  98 +
  99 +// Physical addresses, offsets & lengths
 100 +#define        SRAM_BASE       0xfe100000
 101 +#define        SRAM_BASE_PHYS  0x5c000000
 102 +#define MAX_VRAM_SIZE (1024 * 4)
 103 +static unsigned long offset2phys_map[MAX_VRAM_SIZE >> PAGE_SHIFT];
 104 +#define OFFSET2PHYS_MAP_SRAM_INDEX 0
 105 +
 106 +// vram manager
 107 +typedef struct {
 108 +    unsigned long start_phys;
 109 +    void *start_virt;
 110 +    unsigned long end_phys;
 111 +    unsigned long offset;
 112 +} vram_area_t;
 113 +#define MAX_VRAM_AREAS 128
 114 +static vram_area_t vram_areas[MAX_VRAM_AREAS];
 115 +
 116 +// test
 117 +static volatile unsigned int next_fbr2 = 0;
 118 +static volatile unsigned int next_fbr3 = 0;
 119 +static volatile unsigned int next_fbr4 = 0;
 120 +static wait_queue_head_t fbr2_wait;
 121 +static wait_queue_head_t fbr3_wait;
 122 +static wait_queue_head_t fbr4_wait;
 123 +static wait_queue_head_t wq_lcd_quick_disable_done;
 124 +static wait_queue_head_t wq_lcd_disable_done;
 125 +
 126 +
 127 +#if defined(CONFIG_SL_CCCR_CHANGE)
 128 +extern int read_cccr(void);
 129 +extern void write_cccr(int);
 130 +#endif
 131 +#if defined(CONFIG_CHANGE_CORE_VOLT)
 132 +extern int read_vcore(void);
 133 +extern void write_vcore(int);
 134 +#endif
 135 +
 136 +// ----------------------------------------------------------------
 137 +static void bvdd_vsync();
 138 +
 139 +// ----------------------------------------------------------------
 140 +#if 1
 141 +static void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle);
 142 +static void *l_consistent_alloc2(int gfp, size_t size, dma_addr_t *dma_handle, int pte);
 143 +static void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
 144 +#endif
 145 +
 146 +
 147 +static void inttest(int irq, void *dev_id, struct pt_regs *regs)
 148 +{
 149 +    static int count = 0;
 150 +    static int start = 0;
 151 +    LCSR0_u lcsr0;
 152 +    LCSR1_u lcsr1;
 153 +    int st = 0;
 154 +
 155 +    lcsr1.val = REG_LCSR1;
 156 +    if (lcsr1.f.EOF2 == 1) {
 157 +       LCSR1_u v;
 158 +/*     if ((next_fbr2 != 0) && ((REG_FBR2 & 1) == 0)) { */
 159 +       if ((next_fbr2 != 0)) {
 160 +           REG_FBR2 = next_fbr2 | 3;
 161 +/*         REG_FDADR2 = next_fbr2; */
 162 +/*         wake_up_interruptible(&fbr2_wait); */
 163 +       }
 164 +       v.val = 0;
 165 +       v.f.EOF2 = 1;
 166 +       REG_LCSR1 = v.val;
 167 +    }
 168 +    else if (lcsr1.f.EOF3 == 1) {
 169 +       LCSR1_u v;
 170 +/*     if ((next_fbr3 != 0) && ((REG_FBR3 & 1) == 0)) { */
 171 +       if ((next_fbr3 != 0)) {
 172 +           REG_FBR3 = next_fbr3 | 3;
 173 +/*         REG_FDADR3 = next_fbr3; */
 174 +/*         next_fbr3 = 0; */
 175 +/*         wake_up_interruptible(&fbr3_wait); */
 176 +       }
 177 +       v.val = 0;
 178 +       v.f.EOF3 = 1;
 179 +       REG_LCSR1 = v.val;
 180 +    }
 181 +    else if (lcsr1.f.EOF4 == 1) {
 182 +       LCSR1_u v;
 183 +/*     if ((next_fbr4 != 0) && ((REG_FBR4 & 1) == 0)) { */
 184 +       if ((next_fbr4 != 0)) {
 185 +           REG_FBR4 = next_fbr4 | 3;
 186 +/*         REG_FDADR4 = next_fbr4; */
 187 +/*         next_fbr4 = 0; */
 188 +/*         wake_up_interruptible(&fbr4_wait); */
 189 +       }
 190 +       v.val = 0;
 191 +       v.f.EOF4 = 1;
 192 +       REG_LCSR1 = v.val;
 193 +    }
 194 +    if (REG_LCSR1 & 0x20000) { /* BS2 */
 195 +       next_fbr2 = 0;
 196 +       wake_up_interruptible(&fbr2_wait);
 197 +       REG_LCSR1 = 0x20000;
 198 +    }
 199 +    if (REG_LCSR1 & 0x40000) { /* BS3 */
 200 +       next_fbr3 = 0;
 201 +       wake_up_interruptible(&fbr3_wait);
 202 +       REG_LCSR1 = 0x40000;
 203 +    }
 204 +    if (REG_LCSR1 & 0x80000) { /* BS4 */
 205 +       next_fbr4 = 0;
 206 +       wake_up_interruptible(&fbr4_wait);
 207 +       REG_LCSR1 = 0x80000;
 208 +    }
 209 +
 210 +#if 0
 211 +    lcsr0.val = REG_LCSR0;
 212 +    if (lcsr0.f.QD == 1) {
 213 +       LCSR0_u v;
 214 +       v.val = 0;
 215 +       v.f.QD = 1;
 216 +       REG_LCSR0 = v.val;
 217 +       wake_up_interruptible(&wq_lcd_quick_disable_done);
 218 +    }
 219 +    if (lcsr0.f.LDD == 1) {
 220 +       LCSR0_u v;
 221 +       v.val = 0;
 222 +       v.f.LDD = 1;
 223 +       REG_LCSR0 = v.val;
 224 +       wake_up_interruptible(&wq_lcd_disable_done);
 225 +    }
 226 +#endif
 227 +}
 228 +
 229 +static int setup_vram(int size)
 230 +{
 231 +    int order, i;
 232 +    unsigned int offset = BVDD_VRAM_OFFSET_USER;
 233 +
 234 +    size = PAGE_ALIGN(size);
 235 +    order = get_order(size);
 236 +    PRINT_DEBUG("setup_vram(size=%d)\n", size);
 237 +
 238 +    for (i = 2; i < MAX_VRAM_AREAS - 2; ++i) {
 239 +       vram_area_t *va = &vram_areas[i];
 240 +       va->start_virt = NULL;
 241 +       do {
 242 +/*         if (order > 3) { */
 243 +/*             order --; */
 244 +/*             continue; */
 245 +/*         } */
 246 +           va->start_virt = consistent_alloc(GFP_KERNEL|GFP_DMA, PAGE_SIZE << order, (dma_addr_t *)&va->start_phys);
 247 +           if (va->start_virt == NULL) {
 248 +               order --;
 249 +               if (order < 1)
 250 +                   return -1;
 251 +           }
 252 +       } while (va->start_virt == NULL);
 253 +       va->end_phys = va->start_phys + (PAGE_SIZE << order);
 254 +       va->offset = offset;
 255 +       offset += PAGE_SIZE << order;
 256 +       size -= PAGE_SIZE << order;
 257 +       PRINT_DEBUG("  vram_area[%2d] : 0x%p, %d, 0x%p\n", i, va->start_phys, PAGE_SIZE << order, va->offset);
 258 +       if (size <= 0)
 259 +           break;
 260 +    }
 261 +
 262 +    if (size > 0)
 263 +       return -1;
 264 +    else
 265 +       return 0;
 266 +}
 267 +
 268 +static int free_vram(void)
 269 +{
 270 +    int i;
 271 +    for (i = 2; i < MAX_VRAM_AREAS - 2; ++i) {
 272 +       vram_area_t *va = &vram_areas[i];
 273 +       if (va->start_virt != NULL) {
 274 +           consistent_free(va->start_virt, va->end_phys - va->start_phys, va->start_phys);
 275 +           memset(va, 0, sizeof(vram_area_t));
 276 +       }
 277 +    }
 278 +}
 279 +
 280 +// ----------------------------------------------------------------
 281 +static lcdc_state_t lcdc_state_orig;
 282 +static lcdc_state_t lcdc_state;
 283 +
 284 +static void lcdc_state_read(lcdc_state_t *ls)
 285 +{
 286 +    ls->cken20_intmem = (CKEN & CKEN20_INTMEM) ? 1 : 0;
 287 +    ls->lccr0.val = REG_LCCR0;
 288 +    ls->lccr0.f.reserved1 = 0;
 289 +    ls->lccr0.f.reserved2 = 0;
 290 +    ls->lccr1.val = REG_LCCR1;
 291 +    ls->lccr2.val = REG_LCCR2;
 292 +    ls->lccr3.val = REG_LCCR3;
 293 +    ls->lccr3.f.reserved1 = 0;
 294 +    ls->lccr4.val = REG_LCCR4;
 295 +    ls->lccr4.f.reserved1 = 0;
 296 +    ls->lccr4.f.reserved2 = 0;
 297 +    ls->ovl1c1.val = REG_OVL1C1;
 298 +    ls->ovl1c1.f.reserved1 = 0;
 299 +    ls->ovl1c2.val = REG_OVL1C2;
 300 +    ls->ovl1c2.f.reserved1 = 0;
 301 +    ls->ovl2c1.val = REG_OVL2C1;
 302 +    ls->ovl2c1.f.reserved1 = 0;
 303 +    ls->ovl2c2.val = REG_OVL2C2;
 304 +    ls->ovl2c2.f.reserved1 = 0;
 305 +    ls->fdadr0 = REG_FDADR0;
 306 +    ls->fdadr1 = REG_FDADR1;
 307 +    ls->fdadr2 = REG_FDADR2;
 308 +    ls->fdadr3 = REG_FDADR3;
 309 +    ls->fdadr4 = REG_FDADR4;
 310 +    ls->fdadr5 = REG_FDADR5;
 311 +    ls->fdadr6 = REG_FDADR6;
 312 +}
 313 +
 314 +static void lcdc_state_write(lcdc_state_t *ls)
 315 +{
 316 +    int i;
 317 +
 318 +    ls->cken20_intmem = (CKEN & CKEN20_INTMEM) ? 1 : 0;
 319 +    if (ls->cken20_intmem)
 320 +       CKEN |= CKEN20_INTMEM;
 321 +    else
 322 +       CKEN &= ~CKEN20_INTMEM;
 323 +
 324 +/*     { */
 325 +/*     LCCR0_u v; */
 326 +/*     v.val = 0; */
 327 +/*     v.f.QDM = 1; */
 328 +/*     v.f.LDM = 1; */
 329 +/*     REG_LCCR0 &= ~v.val; */
 330 +/*     } */
 331 +
 332 +    ls->lccr2.f.EFW = 64;
 333 +    ls->lccr2.f.VSW = 64;
 334 +    for (i = 0; i < 2; ++i) {
 335 +       bvdd_vsync();
 336 +       REG_LCCR0 |= 0x400;     /* Disable LCD controller */
 337 +/*     interruptible_sleep_on(&wq_lcd_disable_done); */
 338 +
 339 +       bvdd_vsync();           /* Wait for disabled */
 340 +       REG_LCCR0 &= ~1;        /* Do a quick disable */
 341 +
 342 +       REG_OVL2C1 = ls->ovl2c1.val;
 343 +       REG_OVL2C2 = ls->ovl2c2.val;
 344 +       REG_OVL1C1 = ls->ovl1c1.val;
 345 +       REG_OVL1C2 = ls->ovl1c2.val;
 346 +       REG_LCCR1 = ls->lccr1.val;
 347 +       REG_LCCR2 = ls->lccr2.val;
 348 +       REG_LCCR3 = ls->lccr3.val;
 349 +       REG_LCCR4 = ls->lccr4.val;
 350 +/*     REG_LCCR5 = 0x3F3F3F31; */
 351 +/*     REG_LCCR5 = 0x3F3F313F; /\* EOF *\/ */
 352 +       REG_LCCR5 = 0x3F31313F; /* BSM/EOF */
 353 +
 354 +       REG_LCDBSCNTR = 5;
 355 +
 356 +       REG_LCSR0 = 0x00001FFF;
 357 +       REG_LCSR1 = 0x3E3F3F3F;
 358 +
 359 +       ls->lccr0.f.ENB = 1;
 360 +       REG_LCCR0 = ls->lccr0.val; /* Enable LCD controller */
 361 +
 362 +       REG_LCCR0 &= ~1;        /* Do a quick disable */
 363 +/*     interruptible_sleep_on(&wq_lcd_quick_disable_done); */
 364 +
 365 +       REG_FDADR0 = ls->fdadr0;
 366 +       REG_FDADR1 = ls->fdadr1;
 367 +       REG_FDADR2 = ls->fdadr2;
 368 +       REG_FDADR3 = ls->fdadr3;
 369 +       REG_FDADR4 = ls->fdadr4;
 370 +       REG_FDADR5 = ls->fdadr5;
 371 +       REG_FDADR6 = ls->fdadr6;
 372 +
 373 +       REG_LCCR0 = ls->lccr0.val;
 374 +    }
 375 +}
 376 +
 377 +static void lcdc_state_print_descriptor(int n, unsigned long addr)
 378 +{
 379 +    PRINT_DEBUG("  FDADR%d : 0x%08x         FDADR      FSADR       FIDR      LDCMD\n", n, addr);
 380 +    if (addr == 0)
 381 +       PRINT_DEBUG("                         ---------- ---------- ---------- ----------\n");
 382 +    else {
 383 +       PRINT_DEBUG("                         0x%08x 0x%08x 0x%08x 0x%08x\n",
 384 +                   ((unsigned long *)__phys_to_virt(addr))[0],
 385 +                   ((unsigned long *)__phys_to_virt(addr))[1],
 386 +                   ((unsigned long *)__phys_to_virt(addr))[2],
 387 +                   ((unsigned long *)__phys_to_virt(addr))[3]);
 388 +    }
 389 +}
 390 +
 391 +static void lcdc_state_print(lcdc_state_t *ls)
 392 +{
 393 +    PRINT_DEBUG("lcdc_state_print(lcdc_state_t * = 0x%p)\n", ls);
 394 +    PRINT_DEBUG("  CKEN20_INTMEM : %d\n", ls->cken20_intmem);
 395 +    PRINT_DEBUG("  LCCR0 : 0x%08x\n", ls->lccr0.val);
 396 +    PRINT_DEBUG("    ENB CMS SDS LDM SOFM0 IUM EOFM0 PAS DPD DIS QDM PDD BSM0 OUM LCDT\n");
 397 +    PRINT_DEBUG("    %3d %3d %3d %3d   %3d %3d   %3d %3d %3d %3d %3d %3d  %3d %3d  %3d\n",
 398 +               ls->lccr0.f.ENB, ls->lccr0.f.CMS, ls->lccr0.f.SDS, ls->lccr0.f.LDM, ls->lccr0.f.SOFM0,
 399 +               ls->lccr0.f.IUM, ls->lccr0.f.EOFM0, ls->lccr0.f.PAS, ls->lccr0.f.DPD, ls->lccr0.f.DIS,
 400 +               ls->lccr0.f.QDM, ls->lccr0.f.PDD, ls->lccr0.f.BSM0, ls->lccr0.f.OUM, ls->lccr0.f.LCDT);
 401 +    PRINT_DEBUG("    RDSTM CMDIM OUC LDDALT\n");
 402 +    PRINT_DEBUG("      %3d   %3d %3d    %3d\n",
 403 +               ls->lccr0.f.RDSTM, ls->lccr0.f.CMDIM, ls->lccr0.f.OUC, ls->lccr0.f.LDDALT);
 404 +    PRINT_DEBUG("  LCCR1 : 0x%08x\n", ls->lccr1.val);
 405 +    PRINT_DEBUG("     PPL HSW ELW BLW\n");
 406 +    PRINT_DEBUG("    %4d %3d %3d %3d\n",
 407 +               ls->lccr1.f.PPL, ls->lccr1.f.HSW, ls->lccr1.f.ELW, ls->lccr1.f.BLW);
 408 +    PRINT_DEBUG("  LCCR2 : 0x%08x\n", ls->lccr2.val);
 409 +    PRINT_DEBUG("     LPP VSW EFW BFW\n");
 410 +    PRINT_DEBUG("    %4d %3d %3d %3d\n",
 411 +               ls->lccr2.f.LPP, ls->lccr2.f.VSW, ls->lccr2.f.EFW, ls->lccr2.f.BFW);
 412 +    PRINT_DEBUG("  LCCR3 : 0x%08x\n", ls->lccr3.val);
 413 +    PRINT_DEBUG("    PCD ACB API VSP HSP PCP OEP BPP DPC BPP3 PDFOR\n");
 414 +    PRINT_DEBUG("    %3d %3d %3d %3d %3d %3d %3d %3d %3d  %3d   %3d\n",
 415 +               ls->lccr3.f.PCD, ls->lccr3.f.ACB, ls->lccr3.f.API, ls->lccr3.f.VSP,
 416 +               ls->lccr3.f.HSP, ls->lccr3.f.PCP, ls->lccr3.f.OEP, ls->lccr3.f.BPP,
 417 +               ls->lccr3.f.DPC, ls->lccr3.f.BPP3, ls->lccr3.f.PDFOR);
 418 +    PRINT_DEBUG("  LCCR4 : 0x%08x\n", ls->lccr4.val);
 419 +    PRINT_DEBUG("    K1 K2 K3 PAL_FOR PCDDIV\n");
 420 +    PRINT_DEBUG("    %2d %2d %2d     %3d    %3d\n",
 421 +               ls->lccr4.f.K1, ls->lccr4.f.K2, ls->lccr4.f.K3, ls->lccr4.f.PAL_FOR,
 422 +               ls->lccr4.f.PCDDIV);
 423 +    PRINT_DEBUG("  OVL1C1 : 0x%08x\n", ls->ovl1c1.val);
 424 +    PRINT_DEBUG("    PPL1 LPO1 BPP1 O1EN\n");
 425 +    PRINT_DEBUG("     %3d  %3d  %3d  %3d\n",
 426 +               ls->ovl1c1.f.PPL1, ls->ovl1c1.f.LPO1, ls->ovl1c1.f.BPP1, ls->ovl1c1.f.O1EN);
 427 +    PRINT_DEBUG("  OVL1C2 : 0x%08x\n", ls->ovl1c2.val);
 428 +    PRINT_DEBUG("    O1XPOS O1YPOS\n");
 429 +    PRINT_DEBUG("      %4d   %4d\n",
 430 +               ls->ovl1c2.f.O1XPOS, ls->ovl1c2.f.O1YPOS);
 431 +    PRINT_DEBUG("  OVL2C1 : 0x%08x\n", ls->ovl2c1.val);
 432 +    PRINT_DEBUG("    PPL2 LPO2 BPP2 O2EN\n");
 433 +    PRINT_DEBUG("     %3d  %3d  %3d  %3d\n",
 434 +               ls->ovl2c1.f.PPL2, ls->ovl2c1.f.LPO2, ls->ovl2c1.f.BPP2, ls->ovl2c1.f.O2EN);
 435 +    PRINT_DEBUG("  OVL2C2 : 0x%08x\n", ls->ovl2c2.val);
 436 +    PRINT_DEBUG("    O2XPOS O2YPOS FOR\n");
 437 +    PRINT_DEBUG("      %4d   %4d %3d\n",
 438 +               ls->ovl2c2.f.O2XPOS, ls->ovl2c2.f.O2YPOS, ls->ovl2c2.f.FOR);
 439 +    lcdc_state_print_descriptor(0, ls->fdadr0);
 440 +    lcdc_state_print_descriptor(1, ls->fdadr1);
 441 +    lcdc_state_print_descriptor(2, ls->fdadr2);
 442 +    lcdc_state_print_descriptor(3, ls->fdadr3);
 443 +    lcdc_state_print_descriptor(4, ls->fdadr4);
 444 +    lcdc_state_print_descriptor(5, ls->fdadr5);
 445 +    lcdc_state_print_descriptor(6, ls->fdadr6);
 446 +}
 447 +
 448 +typedef struct {
 449 +    unsigned int offset;
 450 +    int size;
 451 +    unsigned int desc_phys;
 452 +} desc_cache_t;
 453 +
 454 +#define MAX_DESC_CACHE 256
 455 +desc_cache_t desc_cache[MAX_DESC_CACHE];
 456 +int desc_cache_index = 0;
 457 +
 458 +static unsigned int lcdc_set_descriptor(unsigned long offset, int size)
 459 +{
 460 +    descriptor_t *desc, *desc_prev = NULL, *desc_prev2, *desc_first = NULL;
 461 +    int i, count = 0, is_first_desc = 1;
 462 +    unsigned int desc_phys, desc_first_phys;
 463 +    unsigned int offset_orig = offset, size_orig = size;
 464 +
 465 +    PRINT_DEBUG("lcdc_set_descriptor(offset=0x%08x, size=0x%08x)\n", offset, size);
 466 +
 467 +    for (i = 0; i < desc_cache_index; ++i) {
 468 +       if (desc_cache[i].offset == offset && desc_cache[i].size == size)
 469 +           return desc_cache[i].desc_phys;
 470 +    }
 471 +
 472 +    /* build descriptor */
 473 +    while (size > 0) {
 474 +       vram_area_t *va = NULL;
 475 +       unsigned int alen, aoff;
 476 +
 477 +       desc = NULL;
 478 +       for (i = 0; i < MAX_DESCRIPTORS; ++i) {
 479 +           unsigned int fdadr = *(unsigned int *)(&descriptors[i]);
 480 +           if (fdadr == 0) {
 481 +               desc = &descriptors[i];
 482 +               desc_phys = descriptor_phys + (sizeof(descriptor_t) * i);
 483 +               break;
 484 +           }
 485 +       }
 486 +       if (desc == NULL) {
 487 +           // empty
 488 +           return 0;
 489 +       }
 490 +
 491 +       for (i = 0; i < MAX_VRAM_AREAS; ++i) {
 492 +           va = &vram_areas[i];
 493 +           if (va->offset <= offset && offset < (va->offset + (va->end_phys - va->start_phys)))
 494 +               break;
 495 +       }
 496 +       if (i == MAX_VRAM_AREAS) {
 497 +           return 0;
 498 +       }
 499 +
 500 +       aoff = offset - va->offset;
 501 +       if (is_first_desc) {
 502 +           alen = 4 * 1024;
 503 +           is_first_desc = 0;
 504 +       } else {
 505 +           alen = va->end_phys - va->start_phys - aoff;
 506 +           if (alen > size)
 507 +               alen = size;
 508 +       }
 509 +
 510 +       desc->FDADR = desc_phys;
 511 +       desc->FSADR = va->start_phys + aoff;
 512 +       desc->FIDR = 0;
 513 +       desc->LDCMD = alen;
 514 +
 515 +       if (desc_prev != NULL)
 516 +           desc_prev->FDADR = desc_phys;
 517 +       desc_prev2 = desc_prev;
 518 +       desc_prev = desc;
 519 +
 520 +       if (desc_first == NULL) {
 521 +           desc_first = desc;
 522 +           desc_first_phys = desc_phys;
 523 +       }
 524 +
 525 +       size -= alen;
 526 +       offset += alen;
 527 +    }
 528 +
 529 +    /* ÀèÆ¬¤Î¥Ç¥£¥¹¥¯¥ê¥×¥¿¤Ø¥ê¥ó¥¯¤µ¤»¤ë */
 530 +    desc->FDADR = desc_first_phys;
 531 +
 532 +    /* ËöÈø¤Î¥Ç¥£¥¹¥¯¥ê¥×¥¿¤ÏSOF/EOF³ä¤ê¹þ¤ß¤òÈ¯À¸¤µ¤»¤ë */
 533 +/*     desc->LDCMD = desc->LDCMD | 0x400000; */
 534 +/*     desc->LDCMD = desc->LDCMD | 0x200000; */
 535 +    desc_prev2->LDCMD |= 0x200000;
 536 +
 537 +    desc_cache[desc_cache_index].offset = offset_orig;
 538 +    desc_cache[desc_cache_index].size = size_orig;
 539 +    desc_cache[desc_cache_index].desc_phys = desc_first_phys;
 540 +    ++ desc_cache_index;       /* FIXME: buffer overflow */
 541 +
 542 +#if 0
 543 +    desc = desc_first;
 544 +    desc_phys = desc_first_phys;
 545 +    do {
 546 +       lcdc_state_print_descriptor(count++, desc_phys);
 547 +       if (count >= MAX_DESCRIPTORS)
 548 +           break;
 549 +       desc_prev = desc;
 550 +       desc_phys = desc->FDADR;
 551 +    } while (desc_prev->FDADR != desc_first_phys);
 552 +#endif
 553 +
 554 +    return desc_first_phys;
 555 +}
 556 +
 557 +// ----------------------------------------------------------------
 558 +
 559 +static int bvdd_open(struct inode *inode,
 560 +                    struct file *file)
 561 +{
 562 +    int i;
 563 +    printk(DEVICE_NAME ": bvdd_open(0x%p, 0x%p)\n", inode, file);
 564 +
 565 +    if (device_open)
 566 +       return -EBUSY;
 567 +
 568 +    lcdc_state_read(&lcdc_state_orig);
 569 +    lcdc_state_orig.fdadr1 = 0;
 570 +    lcdc_state_orig.fdadr2 = 0;
 571 +    lcdc_state_orig.fdadr3 = 0;
 572 +    lcdc_state_orig.fdadr4 = 0;
 573 +    lcdc_state_orig.fdadr5 = 0;
 574 +    lcdc_state_orig.fdadr6 = 0;
 575 +/*     lcdc_state_print(&lcdc_state_orig); */
 576 +
 577 +    memcpy(&lcdc_state, &lcdc_state_orig, sizeof(lcdc_state));
 578 +    lcdc_state.cken20_intmem = 1;
 579 +
 580 +#ifndef USE_PXAFB_DESCRIPTOR_AREA
 581 +    descriptor_size = PAGE_ALIGN(sizeof(descriptor_t) * MAX_DESCRIPTORS);
 582 +    descriptors = consistent_alloc(GFP_KERNEL|GFP_DMA, descriptor_size, &descriptor_phys);
 583 +    memset(descriptors, 0, sizeof(descriptor_t) * MAX_DESCRIPTORS);
 584 +    printk(DEVICE_NAME ":   descriptor: virt=0x%p, phys=0x%p, size=%d\n",
 585 +          descriptors, descriptor_phys, descriptor_size);
 586 +#else
 587 +    // SHARPSL_PXAFB¤¬³ÎÊÝ¤·¤Æ¤¤¤ëÎÎ°è¤ò¼ÚÍÑ¤¹¤ë¡£
 588 +    // Æ¬¤Î16¥Ð¥¤¥È¤ÏSLARPSL_PXAFB¤¬»È¤Ã¤Æ¤¤¤ë¤Î¤Ç¥¹¥¥Ã¥×¤¹¤ë¡£
 589 +    descriptors = (descriptor_t *)__phys_to_virt((lcdc_state_orig.fdadr0 + 16));
 590 +    PRINT_DEBUG("  descriptors : phys=0x%p, virt=0x%p\n", lcdc_state_orig.fdadr0 + 16, descriptors);
 591 +    memset(descriptors, 0, sizeof(descriptor_t) * MAX_DESCRIPTORS);
 592 +    PRINT_DEBUG("  descriptors : 0x%p, 0x%p\n", &descriptors[0], &descriptors[1]);
 593 +#endif
 594 +
 595 +    init_waitqueue_head(&fbr2_wait);
 596 +    init_waitqueue_head(&fbr3_wait);
 597 +    init_waitqueue_head(&fbr4_wait);
 598 +    init_waitqueue_head(&wq_lcd_quick_disable_done);
 599 +    init_waitqueue_head(&wq_lcd_disable_done);
 600 +
 601 +    next_fbr2 = 0;
 602 +    next_fbr3 = 0;
 603 +    next_fbr4 = 0;
 604 +
 605 +    request_irq(17, inttest, SA_INTERRUPT|SA_SHIRQ, "bvdd", (void *)0xDEADBEAF);
 606 +
 607 +    device_open++;
 608 +
 609 +    MOD_INC_USE_COUNT;
 610 +
 611 +    return 0;
 612 +}
 613 +
 614 +
 615 +static int bvdd_release(struct inode *inode,
 616 +                       struct file *file)
 617 +{
 618 +    PRINT_DEBUG("bvdd_release(0x%p, 0x%p)\n", inode, file);
 619 +    PRINT_DEBUG("  ***** %d\n", REG_LCSR1 & 0x200);
 620 +
 621 +    free_irq(17, (void *)0xDEADBEAF);
 622 +
 623 +    /* restore lcdc state */
 624 +    lcdc_state_write(&lcdc_state_orig);
 625 +    lcdc_state_write(&lcdc_state_orig);
 626 +
 627 +    // free vram
 628 +    if (vram_virt != NULL) {
 629 +       printk(DEVICE_NAME ":  Now freeing vram.\n");
 630 +       consistent_free(vram_virt, vram_size, vram_phys);
 631 +       vram_virt = NULL;
 632 +    } else {
 633 +       printk(DEVICE_NAME ":  vram is not allocated.\n");
 634 +    }
 635 +    free_vram();
 636 +
 637 +#ifndef USE_PXAFB_DESCRIPTOR_AREA
 638 +    // free descriptor
 639 +    consistent_free(descriptors, descriptor_size, descriptor_phys);
 640 +    descriptors = NULL;
 641 +    descriptor_size = 0;
 642 +    descriptor_phys = 0;
 643 +#else
 644 +    descriptors = NULL;
 645 +#endif
 646 +
 647 +    // free descriptor cache
 648 +    desc_cache_index = 0;
 649 +
 650 +    __asm__ __volatile__ ("mcr p15, 0, %0, c15, c1, 0" : :"r"(0));
 651 +
 652 +    /* We're now ready for our next caller */
 653 +    device_open --;
 654 +
 655 +    MOD_DEC_USE_COUNT;
 656 +
 657 +    return 0;
 658 +}
 659 +
 660 +#define SHARPSL_PXA_VSYNC_TIMEOUT 30000 // timeout = 30[ms] > 16.8[ms]
 661 +//
 662 +static void bvdd_vsync()
 663 +{
 664 +    int timeout = SHARPSL_PXA_VSYNC_TIMEOUT;
 665 +
 666 +    while(timeout > 0)
 667 +    {
 668 +       if ((GPLR(GPIO74_LCD_FCLK) & GPIO_bit(GPIO74_LCD_FCLK)))
 669 +           break;
 670 +       udelay(1);
 671 +       timeout--;
 672 +    }
 673 +    while(timeout > 0)
 674 +    {
 675 +       if (!(GPLR(GPIO74_LCD_FCLK) & GPIO_bit(GPIO74_LCD_FCLK)))
 676 +           break;
 677 +       udelay(1);
 678 +       timeout--;
 679 +    }
 680 +}
 681 +
 682 +static int bvdd_setup_frame(int type, bvdd_frame_t *frame_user, int is_branch)
 683 +{
 684 +    bvdd_frame_t frame;
 685 +    int i;
 686 +
 687 +    copy_from_user(&frame, (void *)frame_user, sizeof(frame));
 688 +
 689 +#if 0
 690 +    PRINT_DEBUG("bvdd_setup_frame(type=%d,bvdd_frame_t*=0x%p)\n", type, frame_user);
 691 +    printk(DEVICE_NAME ":   bvdd_frame_t {\n");
 692 +    printk(DEVICE_NAME ":     format=%d\n", frame.format);
 693 +    printk(DEVICE_NAME ":     width=%d\n", frame.width);
 694 +    printk(DEVICE_NAME ":     height=%d\n", frame.height);
 695 +    printk(DEVICE_NAME ":     x=%d\n", frame.x);
 696 +    printk(DEVICE_NAME ":     y=%d\n", frame.y);
 697 +    printk(DEVICE_NAME ":     offset=0x%p\n", frame.offset);
 698 +    printk(DEVICE_NAME ":     u_offset=0x%p\n", frame.u_offset);
 699 +    printk(DEVICE_NAME ":     v_offset=0x%p\n", frame.v_offset);
 700 +    printk(DEVICE_NAME ":   }\n");
 701 +#endif
 702 +
 703 +    if (frame.format > 16) {
 704 +       unsigned int desc, y_stride, uv_stride;
 705 +
 706 +       y_stride = (frame.width + 15) & ~15;
 707 +       uv_stride = y_stride / 2;
 708 +
 709 +/*     lcdc_state.lccr3.f.PDFOR = 3; */
 710 +
 711 +       lcdc_state.ovl2c1.f.O2EN = 1;
 712 +       lcdc_state.ovl2c1.f.LPO2 = frame.height - 1;
 713 +       lcdc_state.ovl2c1.f.PPL2 = y_stride - 1;
 714 +       lcdc_state.ovl2c1.f.BPP2 = 0;
 715 +       lcdc_state.ovl2c2.f.FOR = frame.format - 16;
 716 +/*     lcdc_state.ovl2c2.f.FOR = 4; */
 717 +       lcdc_state.ovl2c2.f.O2XPOS = frame.x;
 718 +       lcdc_state.ovl2c2.f.O2YPOS = frame.y;
 719 +
 720 +       desc = lcdc_set_descriptor(frame.offset, y_stride * frame.height);
 721 +       if (desc == 0) {
 722 +           PRINT_DEBUG("  couldn't set descriptors.\n");
 723 +           return -1;
 724 +       }
 725 +       lcdc_state.fdadr2 = desc;
 726 +
 727 +       desc = lcdc_set_descriptor(frame.u_offset, uv_stride * (frame.height / 2));
 728 +       if (desc == 0) {
 729 +           PRINT_DEBUG("  couldn't set descriptors.\n");
 730 +           lcdc_state.fdadr2 = 0;
 731 +           return -1;
 732 +       }
 733 +       lcdc_state.fdadr3 = desc;
 734 +
 735 +       desc = lcdc_set_descriptor(frame.v_offset, uv_stride * (frame.height / 2));
 736 +       if (desc == 0) {
 737 +           PRINT_DEBUG("  couldn't set descriptors.\n");
 738 +           lcdc_state.fdadr2 = 0;
 739 +           lcdc_state.fdadr3 = 0;
 740 +           return -1;
 741 +       }
 742 +       lcdc_state.fdadr4 = desc;
 743 +
 744 +       if (is_branch) {
 745 +/*         interruptible_sleep_on(&fbr2_wait); */
 746 +/*         interruptible_sleep_on(&fbr3_wait); */
 747 +/*         interruptible_sleep_on(&fbr4_wait); */
 748 +           wait_event_interruptible(fbr2_wait, (next_fbr2 == 0));
 749 +           wait_event_interruptible(fbr3_wait, (next_fbr3 == 0));
 750 +           wait_event_interruptible(fbr4_wait, (next_fbr4 == 0));
 751 +           disable_irq(17);
 752 +           next_fbr2 = lcdc_state.fdadr2;
 753 +           next_fbr3 = lcdc_state.fdadr3;
 754 +           next_fbr4 = lcdc_state.fdadr4;
 755 +           enable_irq(17);
 756 +       } else {
 757 +           lcdc_state_print(&lcdc_state);
 758 +           lcdc_state_write(&lcdc_state);
 759 +       }
 760 +    }
 761 +}
 762 +
 763 +static int bvdd_ioctl(struct inode *inode, struct file *file,
 764 +                     unsigned int ioctl_num, unsigned long ioctl_param)
 765 +{
 766 +    int i;
 767 +    char *temp;
 768 +    char ch;
 769 +
 770 +    switch (ioctl_num) {
 771 +    case BVDD_IOCTL_SETUP_VRAM: {
 772 +       printk(DEVICE_NAME ": BVDD_IOCTL_SETUP_VRAM(0x%08x)\n", ioctl_param);
 773 +#if 0
 774 +       // ´û¤ËVRAM¤¬³ÎÊÝ¤µ¤ì¤Æ¤¤¤ì¤Ð²òÊü¤¹¤ë
 775 +       if (vram_virt != NULL) {
 776 +           printk(DEVICE_NAME ":   now freeing allocated vram\n");
 777 +           consistent_free(vram_virt, vram_size, vram_phys);
 778 +       }
 779 +
 780 +       vram_size = PAGE_ALIGN(ioctl_param + PAGE_SIZE);
 781 +       vram_virt = consistent_alloc(GFP_KERNEL /* | GFP_DMA */, vram_size, &vram_phys);
 782 +       if (vram_virt == NULL) {
 783 +           printk(DEVICE_NAME ":   consistent_alloc failed\n");
 784 +           return -EINVAL;
 785 +       }
 786 +
 787 +       printk(DEVICE_NAME ":   vram_virt=0x%p\n", vram_virt);
 788 +       printk(DEVICE_NAME ":   vram_phys=0x%p\n", vram_phys);
 789 +       printk(DEVICE_NAME ":   vram_size=%d\n", vram_size);
 790 +       vram_areas[2].start_virt = vram_virt;
 791 +       vram_areas[2].start_phys = vram_phys;
 792 +       vram_areas[2].end_phys = vram_phys + vram_size;
 793 +       vram_areas[2].offset = BVDD_VRAM_OFFSET_USER;
 794 +#endif
 795 +       free_vram();
 796 +       if (setup_vram(ioctl_param) < 0)
 797 +           return -EINVAL;
 798 +
 799 +       break;
 800 +    }
 801 +
 802 +    case BVDD_IOCTL_SETUP_BASE_FRAME: {
 803 +       printk(DEVICE_NAME ": BVDD_IOCTL_SETUP_BASE_FRAME(0x%08x)\n", ioctl_param);
 804 +       break;
 805 +    }
 806 +    case BVDD_IOCTL_SETUP_OVERLAY1_FRAME: {
 807 +       break;
 808 +    }
 809 +    case BVDD_IOCTL_SETUP_OVERLAY2_FRAME: {
 810 +       bvdd_frame_t frame;
 811 +       printk(DEVICE_NAME ": BVDD_IOCTL_SETUP_OVERLAY2_FRAME(0x%08x)\n", ioctl_param);
 812 +       bvdd_setup_frame(2, (bvdd_frame_t *)ioctl_param, 0);
 813 +       break;
 814 +    }
 815 +
 816 +    case BVDD_IOCTL_BRANCH_OVERLAY2_FRAME: {
 817 +       bvdd_frame_t frame;
 818 +/*     PRINT_DEBUG("BVDD_IOCTL_BRANCH_OVERLAY2_FRAME(0x%08x)\n", ioctl_param); */
 819 +       bvdd_setup_frame(2, (bvdd_frame_t *)ioctl_param, 1);
 820 +       break;
 821 +    }
 822 +
 823 +    case BVDD_IOCTL_SET_IWMMXT_STATE: {
 824 +       __asm__ __volatile__ ("mcr p15, 0, %0, c15, c1, 0" : :"r"(ioctl_param ? 3 : 0));
 825 +       break;
 826 +    }
 827 +
 828 +#if defined(CONFIG_SL_CCCR_CHANGE)
 829 +    case BVDD_IOCTL_GET_CCCR: {
 830 +      *((int *)ioctl_param) = read_cccr();
 831 +      printk(DEVICE_NAME ": Read CCCR = %x.\n", *((int *)ioctl_param));
 832 +      break;
 833 +    }
 834 +    case BVDD_IOCTL_SET_CCCR: {
 835 +      write_cccr((int)ioctl_param);
 836 +      printk(DEVICE_NAME ": Change CCCR = %x.\n", (int)ioctl_param);
 837 +      break;
 838 +    }
 839 +#endif
 840 +#if defined(CONFIG_CHANGE_CORE_VOLT)
 841 +    case BVDD_IOCTL_GET_VCORE: {
 842 +      *((int *)ioctl_param) = read_vcore();
 843 +      printk(DEVICE_NAME ": Read VCORE = %x.\n", *((int *)ioctl_param));
 844 +      break;
 845 +    }
 846 +    case BVDD_IOCTL_SET_VCORE: {
 847 +      write_vcore((int)ioctl_param);
 848 +      printk(DEVICE_NAME ": Change VCORE = %x.\n", (int)ioctl_param);
 849 +      break;
 850 +    }
 851 +#endif
 852 +
 853 +    case BVDD_IOCTL_DEBUG: {
 854 +       printk(DEVICE_NAME ": BVDD_IOCTL_DEBUG\n");
 855 +       break;
 856 +    }
 857 +    }
 858 +
 859 +    return 0;
 860 +}
 861 +
 862 +/*
 863 +  vma->vm_start, vma->vm_end ¤Ï¡¢mmap°ú¿ô¤¬¥Ú¡¼¥¸¶³¦¤Ç¤Ê¤¯¤È¤â¥¢¥é¥¤¥ó¤µ¤ì¤¿¤â¤Î¤¬¤³¤Î´Ø¿ô¤ËÅÏ¤ë¡£
 864 +  vma->vm_pgoff ¤Ï¡¢mmap°ú¿ô¤¬¥Ú¡¼¥¸¶³¦¤Ç¤Ê¤±¤ì¤Ð¥¨¥é¡¼¤Ë¤Ê¤ë¡£
 865 +*/
 866 +static int bvdd_mmap(struct file *file, struct vm_area_struct *vma)
 867 +{
 868 +    unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
 869 +    struct page *map, *mapend;
 870 +    int i, size;
 871 +    unsigned long vma_start;
 872 +
 873 +    PRINT_DEBUG("bvdd_mmap(file=0x%p, vma=0x%p)\n", file, vma);
 874 +
 875 +/*     if (vram_virt == NULL) { */
 876 +/*     printk(DEVICE_NAME ":   vram is not allocated.\n"); */
 877 +/*     return -EINVAL; */
 878 +/*     } */
 879 +
 880 +    printk(DEVICE_NAME ":   vm_start = 0x%p\n", (uint32_t)vma->vm_start);
 881 +    printk(DEVICE_NAME ":   vm_end   = 0x%p\n", (uint32_t)vma->vm_end);
 882 +    printk(DEVICE_NAME ":   vm_pgoff = 0x%p\n", (uint32_t)vma->vm_pgoff);
 883 +    printk(DEVICE_NAME ":   vm_page_prot.pgprot = 0x%08u\n", (uint32_t)vma->vm_page_prot.pgprot);
 884 +    printk(DEVICE_NAME ":   PAGE_OFFSET = %x\n", (int)PAGE_OFFSET);
 885 +    printk(DEVICE_NAME ":   offset = %x\n", (int)offset);
 886 +    printk(DEVICE_NAME ":   vram_phys = 0x%p\n", vram_phys);
 887 +
 888 +    if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
 889 +       return -EINVAL;
 890 +
 891 +#if 0
 892 +    if ((vma->vm_end - vma->vm_start + offset) > vram_size) {
 893 +       printk(DEVICE_NAME ":   mmap length is too large (vram_size=%d, len=%d\n",
 894 +              vram_size, vma->vm_end - vma->vm_start + offset);
 895 +       return -EINVAL;
 896 +    }
 897 +#endif
 898 +
 899 +    // from fbmem.c
 900 +    vma->vm_flags |= VM_IO;
 901 +    vma->vm_page_prot = __pgprot(pgprot_val(vma->vm_page_prot) | L_PTE_CACHEABLE);
 902 +
 903 +#if 0
 904 +    for (i = vma->vm_pgoff; i < vma->vm_pgoff + ((vma->vm_end - vma->vm_start) >> PAGE_SHIFT); ++i) {
 905 +       if (offset2phys_map[i] == 0) {
 906 +           printk(DEVICE_NAME ":   io_remap_page_range failed.\n");
 907 +           return -EAGAIN;
 908 +       }
 909 +       if (io_remap_page_range(vma->vm_start + (i << PAGE_SHIFT),
 910 +                               offset2phys_map[i],
 911 +                               PAGE_SIZE, vma->vm_page_prot)) {
 912 +           printk(DEVICE_NAME ":   io_remap_page_range failed.\n");
 913 +           return -EAGAIN;
 914 +       }
 915 +    }
 916 +#endif
 917 +
 918 +#if 1
 919 +    vma_start = vma->vm_start;
 920 +    size = vma->vm_end - vma->vm_start;
 921 +    while (size > 0) {
 922 +       vram_area_t *va = NULL;
 923 +       int aoff, alen;
 924 +
 925 +       for (i = 0; i < MAX_VRAM_AREAS; ++i) {
 926 +           va = &vram_areas[i];
 927 +           if (va->offset <= offset && offset < va->offset + (va->end_phys - va->start_phys))
 928 +               break;
 929 +       }
 930 +       if (i == MAX_VRAM_AREAS) {
 931 +           return -EAGAIN;
 932 +       }
 933 +
 934 +       aoff = offset - va->offset;
 935 +       alen = va->end_phys - va->start_phys - aoff;
 936 +       if (alen > size)
 937 +           alen = size;
 938 +       PRINT_DEBUG("io_remap_page_range(0x%p, 0x%p, %d)\n", vma_start, va->start_phys + aoff, alen);
 939 +       if (io_remap_page_range(vma_start, va->start_phys + aoff, alen, vma->vm_page_prot)) {
 940 +           printk(DEVICE_NAME ":   io_remap_page_range failed.\n");
 941 +           return -EAGAIN;
 942 +       }
 943 +       vma_start += alen;
 944 +       size -= alen;
 945 +       offset += alen;
 946 +    }
 947 +
 948 +    printk(DEVICE_NAME ":   successed.\n");
 949 +    return 0;
 950 +#endif
 951 +}
 952 +
 953 +/* Module Declarations *************************** */
 954 +
 955 +
 956 +/* This structure will hold the functions to be called
 957 + * when a process does something to the device we
 958 + * created. Since a pointer to this structure is kept in
 959 + * the devices table, it can't be local to
 960 + * init_module. NULL is for unimplemented functions. */
 961 +struct file_operations fops = {
 962 +    ioctl : bvdd_ioctl,
 963 +    mmap : bvdd_mmap,
 964 +    open : bvdd_open,
 965 +    release : bvdd_release,
 966 +};
 967 +
 968 +
 969 +/* Initialize the module - Register the character device */
 970 +int init_module()
 971 +{
 972 +    int i, ret;
 973 +    unsigned long *p;
 974 +
 975 +    /* Register the character device (atleast try) */
 976 +    ret = register_chrdev(BVDD_MAJOR_NUM, DEVICE_NAME, &fops);
 977 +
 978 +    /* Negative values signify an error */
 979 +    if (ret < 0) {
 980 +       printk (DEVICE_NAME ": Registering the device failed with %d\n", ret);
 981 +       return ret;
 982 +    }
 983 +
 984 +    printk (DEVICE_NAME ": Registeration is a success. \n");
 985 +
 986 +    /* TODO */
 987 +/*     vram_sharpsl_pxafb_phys = ((descriptor_t *)__phys_to_virt(FDADR0))->FSADR; */
 988 +    vram_sharpsl_pxafb_phys = (dma_addr_t)0xA3E00000UL;
 989 +
 990 +#if 0
 991 +    p = offset2phys_map;
 992 +    for (i = 0; i < ((256 * 1024) >> PAGE_SHIFT); ++i) {
 993 +       *p++ = SRAM_BASE_PHYS + (i << PAGE_SHIFT);
 994 +    }
 995 +    for (i = 0; i < ((PAGE_ALIGN(640 * 480 * 2)) >> PAGE_SHIFT); ++i) {
 996 +       *p++ = vram_sharpsl_pxafb_phys + (i << PAGE_SHIFT);
 997 +    }
 998 +#endif
 999 +
1000 +    memset(vram_areas, 0, sizeof(vram_areas));
1001 +    vram_areas[0].start_phys = vram_sharpsl_pxafb_phys;
1002 +    vram_areas[0].start_virt = (void *)__phys_to_virt(vram_sharpsl_pxafb_phys);
1003 +    vram_areas[0].end_phys = vram_areas[0].start_phys + PAGE_ALIGN(480 * 640 * 2);
1004 +    vram_areas[0].offset = 0;
1005 +    vram_areas[1].start_phys = SRAM_BASE_PHYS;
1006 +    vram_areas[1].start_virt = (void *)SRAM_BASE;
1007 +    vram_areas[1].end_phys = vram_areas[1].start_phys + 256 * 1024;
1008 +    vram_areas[1].offset = PAGE_ALIGN(480 * 640 * 2);
1009 +
1010 +    return 0;
1011 +}
1012 +
1013 +
1014 +/* Cleanup - unregister the appropriate file from /proc */
1015 +void cleanup_module()
1016 +{
1017 +    int ret;
1018 +
1019 +    /* Unregister the device */
1020 +    ret = unregister_chrdev(BVDD_MAJOR_NUM, DEVICE_NAME);
1021 +
1022 +    /* If there's an error, report it */
1023 +    if (ret < 0)
1024 +       printk(DEVICE_NAME ": Error in unregister_chrdev: %d\n", ret);
1025 +    printk (DEVICE_NAME ": Unregisteration is a success. \n");
1026 +}
1027 +
1028 +#if 1
1029 +//////////////////////////////////////////////
1030 +#include <linux/interrupt.h>
1031 +
1032 +/*
1033 + * This allocates one page of cache-coherent memory space and returns
1034 + * both the virtual and a "dma" address to that space.  It is not clear
1035 + * whether this could be called from an interrupt context or not.  For
1036 + * now, we expressly forbid it, especially as some of the stuff we do
1037 + * here is not interrupt context safe.
1038 + *
1039 + * We should allow this function to be called from interrupt context.
1040 + * However, we call ioremap, which needs to fiddle around with various
1041 + * things (like the vmlist_lock, and allocating page tables).  These
1042 + * things aren't interrupt safe (yet).
1043 + *
1044 + * Note that this does *not* zero the allocated area!
1045 + */
1046 +static void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle)
1047 +{
1048 +    return l_consistent_alloc2(gfp, size, dma_handle, L_PTE_CACHEABLE);
1049 +}
1050 +
1051 +static void *l_consistent_alloc2(int gfp, size_t size, dma_addr_t *dma_handle, int pte)
1052 +{
1053 +    struct page *page, *end, *free;
1054 +    unsigned long order;
1055 +    void *ret;
1056 +
1057 +    /* FIXME */
1058 +    if (in_interrupt())
1059 +       BUG();
1060 +
1061 +    size = PAGE_ALIGN(size);
1062 +    order = get_order(size);
1063 +
1064 +    page = alloc_pages(gfp, order);
1065 +    if (!page) {
1066 +       printk("size:%d, order:%d\n", size, order);
1067 +       goto no_page;
1068 +    }
1069 +
1070 +    *dma_handle = page_to_bus(page);
1071 +    //ret = __ioremap(page_to_pfn(page) << PAGE_SHIFT, size, 0);
1072 +    ret = __ioremap(page_to_pfn(page) << PAGE_SHIFT, size, pte);
1073 +    if (!ret) {
1074 +       goto no_remap;
1075 +    }
1076 +
1077 +#if 0 /* ioremap_does_flush_cache_all */
1078 +    {
1079 +       void *virt = page_address(page);
1080 +
1081 +       /*
1082 +        * we need to ensure that there are no cachelines in use, or
1083 +        * worse dirty in this area.  Really, we don't need to do
1084 +        * this since __ioremap does a flush_cache_all() anyway. --rmk
1085 +        */
1086 +       invalidate_dcache_range(virt, virt + size);
1087 +    }
1088 +#endif
1089 +
1090 +    /*
1091 +     * free wasted pages.  We skip the first page since we know
1092 +     * that it will have count = 1 and won't require freeing.
1093 +     * We also mark the pages in use as reserved so that
1094 +     * remap_page_range works.
1095 +     */
1096 +    free = page + (size >> PAGE_SHIFT);
1097 +    end  = page + (1 << order);
1098 +
1099 +    for (; page < end; page++) {
1100 +       set_page_count(page, 1);
1101 +       if (page >= free)
1102 +           __free_page(page);
1103 +       else
1104 +           SetPageReserved(page);
1105 +    }
1106 +    return ret;
1107 +
1108 + no_remap:
1109 +    __free_pages(page, order);
1110 + no_page:
1111 +    return NULL;
1112 +}
1113 +
1114 +/*
1115 + * free a page as defined by the above mapping.  We expressly forbid
1116 + * calling this from interrupt context.
1117 + */
1118 +static void consistent_free(void *vaddr, size_t size, dma_addr_t handle)
1119 +{
1120 +    struct page *page, *end;
1121 +
1122 +    if (in_interrupt())
1123 +       BUG();
1124 +
1125 +    /*
1126 +     * More messing around with the MM internals.  This is
1127 +     * sick, but then so is remap_page_range().
1128 +     */
1129 +    size = PAGE_ALIGN(size);
1130 +    page = virt_to_page(bus_to_virt(handle));
1131 +    end = page + (size >> PAGE_SHIFT);
1132 +
1133 +    for (; page < end; page++)
1134 +       ClearPageReserved(page);
1135 +
1136 +    __iounmap(vaddr);
1137 +}
1138 +
1139 +#endif
1140 +
1141 +/*
1142 +
1143 +document
1144 +
1145 +- Do not change resolution (VGA, QVGA) while bvdd device opened. (TODO)
1146 +- open()¤¹¤ë¤È¤¤Èclose()¤¹¤ë¤È¤¤Î²òÁüÅÙ¤¬Æ±¤¸¤Ç¤Ê¤¤¤È¤¤¤±¤Þ¤»¤ó¡£
1147 +  ¾õÂÖ¤¬°ã¤Ã¤¿¤È¤¤ÎÆ°ºî¤ÏÌ¤ÊÝ¾Ú¤Ç¤¹¡£
1148 +
1149 +
1150 +*/
1151 diff -Nur c3000_pre/linux/drivers/video/bvdd.h c3000_work/linux/drivers/video/bvdd.h
1152 --- c3000_pre/linux/drivers/video/bvdd.h        1970-01-01 09:00:00.000000000 +0900
1153 +++ c3000_work/linux/drivers/video/bvdd.h       2005-02-21 23:48:01.000000000 +0900
1154 @@ -0,0 +1,64 @@
1155 +/*  bulverded.h - bulverde(PXA27x) display driver
1156 +BulVerDD
1157 + */
1158 +
1159 +#ifndef CHARDEV_H
1160 +#define CHARDEV_H
1161 +
1162 +#include <linux/ioctl.h>
1163 +
1164 +#define BVDD_VRAM_OFFSET_PXAFB (0)
1165 +#define BVDD_VRAM_OFFSET_SRAM (480 * 640 * 2)
1166 +#define BVDD_VRAM_OFFSET_USER (BVDD_VRAM_OFFSET_SRAM + (256 * 1024))
1167 +
1168 +#define BVDD_FORMAT_RGB2 1     /* 2-bits/pixel [4 entry palette] */
1169 +#define BVDD_FORMAT_RGB4 2     /* 4-bits/pixel [16 entry palette] */
1170 +#define BVDD_FORMAT_RGB8 3     /* 8-bits/pixel [256 entry palette] */
1171 +#define BVDD_FORMAT_RGB16 4    /* 16-bits/pixel */
1172 +#define BVDD_FORMAT_RGB18 5    /* 18-bits/pixel, unpacked */
1173 +#define BVDD_FORMAT_RGB18P 6   /* 18-bits/pixel, packed */
1174 +#define BVDD_FORMAT_RGB19 7    /* 19-bits/pixel, unpacked */
1175 +#define BVDD_FORMAT_RGB19P 8   /* 19-bits/pixel, packed */
1176 +#define BVDD_FORMAT_RGB24 9    /* 24-bits/pixel */
1177 +#define BVDD_FORMAT_RGB25 10   /* 25-bits/pixel */
1178 +#define BVDD_FORMAT_YUV444P 17 /* YCbCr4:4:4 Packed */
1179 +#define BVDD_FORMAT_YUV444 18  /* YCbCr4:4:4 Planar */
1180 +#define BVDD_FORMAT_YUV422 19  /* YCbCr4:2:2 Planar */
1181 +#define BVDD_FORMAT_YUV420 20  /* YCbCr4:2:0 Planar */
1182 +
1183 +
1184 +typedef struct {
1185 +    unsigned char format;
1186 +    unsigned short width;
1187 +    unsigned short height;
1188 +    unsigned short x;
1189 +    unsigned short y;
1190 +    unsigned long offset;      /* aligned on a 16-byte boundary */
1191 +    unsigned long u_offset;    /* aligned on a 16-byte boundary */
1192 +    unsigned long v_offset;    /* aligned on a 16-byte boundary */
1193 +} bvdd_frame_t;
1194 +
1195 +/* The major device number. We can't rely on dynamic
1196 + * registration any more, because ioctls need to know
1197 + * it. */
1198 +#define BVDD_MAJOR_NUM 240
1199 +
1200 +/* Set the message of the device driver */
1201 +#define BVDD_IOCTL_SETUP_VRAM _IOR(BVDD_MAJOR_NUM, 0, uint32_t)
1202 +#define BVDD_IOCTL_SETUP_BASE_FRAME _IOR(BVDD_MAJOR_NUM, 1, bvdd_frame_t *)
1203 +#define BVDD_IOCTL_SETUP_OVERLAY1_FRAME _IOR(BVDD_MAJOR_NUM, 2, bvdd_frame_t *)
1204 +#define BVDD_IOCTL_SETUP_OVERLAY2_FRAME _IOR(BVDD_MAJOR_NUM, 3, bvdd_frame_t *)
1205 +#define BVDD_IOCTL_BRANCH_OVERLAY2_FRAME _IOR(BVDD_MAJOR_NUM, 6, bvdd_frame_t *)
1206 +#define BVDD_IOCTL_SET_IWMMXT_STATE _IOR(BVDD_MAJOR_NUM, 7, int)
1207 +#define BVDD_IOCTL_GET_CCCR _IOR(BVDD_MAJOR_NUM, 11, int *)
1208 +#define BVDD_IOCTL_SET_CCCR _IOR(BVDD_MAJOR_NUM, 12, int)
1209 +#define BVDD_IOCTL_GET_VCORE _IOR(BVDD_MAJOR_NUM, 13, int *)
1210 +#define BVDD_IOCTL_SET_VCORE _IOR(BVDD_MAJOR_NUM, 14, int)
1211 +
1212 +#define BVDD_IOCTL_DEBUG _IO(BVDD_MAJOR_NUM, 10)
1213 +
1214 +/* The name of the device file */
1215 +#define BVDD_DEVICE_FILE_NAME "bvdd"
1216 +
1217 +
1218 +#endif
1219 diff -Nur c3000_pre/linux/drivers/video/bvdd_p.h c3000_work/linux/drivers/video/bvdd_p.h
1220 --- c3000_pre/linux/drivers/video/bvdd_p.h      1970-01-01 09:00:00.000000000 +0900
1221 +++ c3000_work/linux/drivers/video/bvdd_p.h     2005-02-21 23:41:29.000000000 +0900
1222 @@ -0,0 +1,284 @@
1223 +#ifndef BVDD_P_INCLUDED
1224 +#define BVDD_P_INCLUDED
1225 +
1226 +#include <asm/hardware.h>
1227 +
1228 +#define REG_LCCR0      __REG(0x44000000) /* LCD Controller Control register 0 */
1229 +#define REG_LCCR1      __REG(0x44000004) /* LCD Controller Control register 1 */
1230 +#define REG_LCCR2      __REG(0x44000008) /* LCD Controller Control register 2 */
1231 +#define REG_LCCR3      __REG(0x4400000C) /* LCD Controller Control register 3 */
1232 +#define REG_LCCR4      __REG(0x44000010) /* LCD Controller Control register 4 */
1233 +#define REG_LCCR5      __REG(0x44000014) /* LCD Controller Control register 5 */
1234 +#define REG_FBR0       __REG(0x44000020)
1235 +#define REG_FBR1       __REG(0x44000024)
1236 +#define REG_FBR2       __REG(0x44000028)
1237 +#define REG_FBR3       __REG(0x4400002C)
1238 +#define REG_FBR4       __REG(0x44000030)
1239 +#define REG_LCSR1      __REG(0x44000034)
1240 +#define REG_LCSR0      __REG(0x44000038)
1241 +#define REG_LIIDR      __REG(0x4400003C)
1242 +#define REG_TRGBR      __REG(0x44000040)
1243 +#define REG_TCR                __REG(0x44000044)
1244 +#define REG_OVL1C1     __REG(0x44000050)
1245 +#define REG_OVL1C2     __REG(0x44000060)
1246 +#define REG_OVL2C1     __REG(0x44000070)
1247 +#define REG_OVL2C2     __REG(0x44000080)
1248 +#define REG_CCR                __REG(0x44000090)
1249 +#define REG_CMDCR      __REG(0x44000100)
1250 +#define REG_PRSR       __REG(0x44000104)
1251 +#define REG_FBR5       __REG(0x44000110)
1252 +#define REG_FBR6       __REG(0x44000114)
1253 +#define REG_FDADR0     __REG(0x44000200)
1254 +#define REG_FSADR0     __REG(0x44000204)
1255 +#define REG_FIDR0      __REG(0x44000208)
1256 +#define REG_LDCMD0     __REG(0x4400020C)
1257 +#define REG_FDADR1     __REG(0x44000210)
1258 +#define REG_FSADR1     __REG(0x44000214)
1259 +#define REG_FIDR1      __REG(0x44000218)
1260 +#define REG_LDCMD1     __REG(0x4400021C)
1261 +#define REG_FDADR2     __REG(0x44000220)
1262 +#define REG_FSADR2     __REG(0x44000224)
1263 +#define REG_FIDR2      __REG(0x44000228)
1264 +#define REG_LDCMD2     __REG(0x4400022C)
1265 +#define REG_FDADR3     __REG(0x44000230)
1266 +#define REG_FSADR3     __REG(0x44000234)
1267 +#define REG_FIDR3      __REG(0x44000238)
1268 +#define REG_LDCMD3     __REG(0x4400023C)
1269 +#define REG_FDADR4     __REG(0x44000240)
1270 +#define REG_FSADR4     __REG(0x44000244)
1271 +#define REG_FIDR4      __REG(0x44000248)
1272 +#define REG_LDCMD4     __REG(0x4400024C)
1273 +#define REG_FDADR5     __REG(0x44000250)
1274 +#define REG_FSADR5     __REG(0x44000254)
1275 +#define REG_FIDR5      __REG(0x44000258)
1276 +#define REG_LDCMD5     __REG(0x4400025C)
1277 +#define REG_FDADR6     __REG(0x44000260)
1278 +#define REG_FSADR6     __REG(0x44000264)
1279 +#define REG_FIDR6      __REG(0x44000268)
1280 +#define REG_LDCMD6     __REG(0x4400026C)
1281 +#define REG_LCDBSCNTR  __REG(0x48000054)
1282 +
1283 +typedef struct {
1284 +    unsigned long ENB          : 1; /* LCD Controller Enable */
1285 +    unsigned long CMS          : 1; /* Color/Monochrome Select */
1286 +    unsigned long SDS          : 1; /* Single-Scan/dual-scan Display Select */
1287 +    unsigned long LDM          : 1; /* LCD Disable Done Mask */
1288 +    unsigned long SOFM0                : 1; /* Start of Frame Mask for Channel 0 and Channel 1 (Dual Scan) */
1289 +    unsigned long IUM          : 1; /* Input FIFO Underrun Mask */
1290 +    unsigned long EOFM0                : 1; /* End of Frame Mask for Channel 0 and for Channel 1 (Dual Scan) */
1291 +    unsigned long PAS          : 1; /* Passive/Active Display Select */
1292 +    unsigned long reserved2    : 1;
1293 +    unsigned long DPD          : 1; /* Double-Pixel Data (DPD) Pin Mode */
1294 +    unsigned long DIS          : 1; /* LCD Disable */
1295 +    unsigned long QDM          : 1; /* LCD Quick Disable Mask */
1296 +    unsigned long PDD          : 8; /* Palette DMA Request Delay */
1297 +    unsigned long BSM0         : 1; /* Branch Status Mask */
1298 +    unsigned long OUM          : 1; /* Output FIFO Underrun Mask */
1299 +    unsigned long LCDT         : 1; /* LCD Panel Type */
1300 +    unsigned long RDSTM                : 1; /* LCD Read Status Interrupt Mask */
1301 +    unsigned long CMDIM                : 1; /* LCD Command Interrupt Mask */
1302 +    unsigned long OUC          : 1; /* Overlay Underlay Control Bit */
1303 +    unsigned long LDDALT       : 1; /* LDD Alternate Mapping Control Bit */
1304 +    unsigned long reserved1     : 5;
1305 +} LCCR0_t;
1306 +typedef union {
1307 +    LCCR0_t f;
1308 +    unsigned long val;
1309 +} LCCR0_u;
1310 +
1311 +typedef struct {
1312 +    unsigned long PPL          :10; /* Pixels per Line for the Base Frame */
1313 +    unsigned long HSW          : 6; /* Horizontal Sync Pulse Width */
1314 +    unsigned long ELW          : 8; /* End-of-Line Pixel Clock Wait Count */
1315 +    unsigned long BLW          : 8; /* Beginning-of-Line Pixel Clock Wait Count */
1316 +} LCCR1_t;
1317 +typedef union {
1318 +    LCCR1_t f;
1319 +    unsigned long val;
1320 +} LCCR1_u;
1321 +
1322 +typedef struct {
1323 +    unsigned long LPP          :10; /* Lines per Panel for the Base Frame */
1324 +    unsigned long VSW          : 6; /* Vertical Sync Pulse Width */
1325 +    unsigned long EFW          : 8; /* End-of-Frame Line Clock Wait Count */
1326 +    unsigned long BFW          : 8; /* Beginning-of-Frame Line Clock Wait Count */
1327 +} LCCR2_t;
1328 +typedef union {
1329 +    LCCR2_t f;
1330 +    unsigned long val;
1331 +} LCCR2_u;
1332 +
1333 +typedef struct {
1334 +    unsigned long PCD          : 8; /* Pixel Clock Divisor */
1335 +    unsigned long ACB          : 8; /* AC Bias Pin Frequency */
1336 +    unsigned long API          : 4; /* AC Bias Pin Transitions per Interrupt */
1337 +    unsigned long VSP          : 1; /* Vertical Sync Polarity */
1338 +    unsigned long HSP          : 1; /* Horizontal Sync Polarity */
1339 +    unsigned long PCP          : 1; /* Pixel Clock Polarity */
1340 +    unsigned long OEP          : 1; /* Output Enable Polarity */
1341 +    unsigned long BPP          : 3; /* Bits per Pixel */
1342 +    unsigned long DPC          : 1; /* Double Pixel Clock Mode */
1343 +    unsigned long reserved1    : 1;
1344 +    unsigned long BPP3         : 1; /* Bits per Pixel */
1345 +    unsigned long PDFOR                : 2; /* Pixel Data Format */
1346 +} LCCR3_t;
1347 +typedef union {
1348 +    LCCR3_t f;
1349 +    unsigned long val;
1350 +} LCCR3_u;
1351 +
1352 +typedef struct {
1353 +    unsigned long K1           : 3; /* Multiplication Constant for Red for Half Transparency */
1354 +    unsigned long K2           : 3; /* Multiplication Constant for Blue for Half Transparency */
1355 +    unsigned long K3           : 3; /* Multiplication Constant for Green for Half Transparency */
1356 +    unsigned long reserved2    : 6;
1357 +    unsigned long PAL_FOR      : 2; /* Palette Data Format */
1358 +    unsigned long reserved1    :12;
1359 +    unsigned long PCDDIV       : 1; /* PCD Divisor Selection */
1360 +} LCCR4_t;
1361 +typedef union {
1362 +    LCCR4_t f;
1363 +    unsigned long val;
1364 +} LCCR4_u;
1365 +
1366 +/* LCCR5 unused */
1367 +
1368 +typedef struct {
1369 +    unsigned long PPL1         :10; /* Pixels per Line for Overlay 1 Frame */
1370 +    unsigned long LPO1         :10; /* Number of Lines for Overlay 1 */
1371 +    unsigned long BPP1         : 4; /* Bits per Pixel for Overlay 1 */
1372 +    unsigned long reserved1    : 7;
1373 +    unsigned long O1EN         : 1; /* Enable bit for Overlay 1 */
1374 +} OVL1C1_t;
1375 +typedef union {
1376 +    OVL1C1_t f;
1377 +    unsigned long val;
1378 +} OVL1C1_u;
1379 +
1380 +typedef struct {
1381 +    unsigned long O1XPOS       :10; /* Horizontal Position of the Upper Left-Most Pixel of Overlay 1 Window */
1382 +    unsigned long O1YPOS       :10; /* Vertical Position of the Upper Left-Most Pixel of Overlay 1 Window */
1383 +    unsigned long reserved1    :12;
1384 +} OVL1C2_t;
1385 +typedef union {
1386 +    OVL1C2_t f;
1387 +    unsigned long val;
1388 +} OVL1C2_u;
1389 +
1390 +typedef struct {
1391 +    unsigned long PPL2         :10; /* Pixels per Line for Overlay 2 Frame */
1392 +    unsigned long LPO2         :10; /* Number of Lines for Overlay 2 Frame */
1393 +    unsigned long BPP2         : 4; /* Bits per Pixel for Overlay 2 */
1394 +    unsigned long reserved1    : 7;
1395 +    unsigned long O2EN         : 1; /* Overlay 2 Enable */
1396 +} OVL2C1_t;
1397 +typedef union {
1398 +    OVL2C1_t f;
1399 +    unsigned long val;
1400 +} OVL2C1_u;
1401 +
1402 +typedef struct {
1403 +    unsigned long O2XPOS       :10; /* Horizontal Position of the Upper Left Most Pixel of Overlay 2 */
1404 +    unsigned long O2YPOS       :10; /* Vertical Position of the Upper Left Most Pixel of Overlay 2 */
1405 +    unsigned long FOR          : 3; /* Format */
1406 +    unsigned long reserved1    : 9;
1407 +} OVL2C2_t;
1408 +typedef union {
1409 +    OVL2C2_t f;
1410 +    unsigned long val;
1411 +} OVL2C2_u;
1412 +
1413 +#undef BS0
1414 +typedef struct {
1415 +    unsigned long LDD          : 1; /* LCD Disable Done Flag */
1416 +    unsigned long SOF0         : 1; /* Start of Frame Status for Base */
1417 +    unsigned long BER          : 1; /* Bus Error Status */
1418 +    unsigned long ABC          : 1; /* AC Bias Count Status */
1419 +    unsigned long IU0          : 1; /* Input FIFO Underrun for Channel 0 */
1420 +    unsigned long IU1          : 1; /* Input FIFO Underrun for Channel 1 */
1421 +    unsigned long OU           : 1; /* Output FIFO Underrun */
1422 +    unsigned long QD           : 1; /* LCD Quick Disable Status */
1423 +    unsigned long EOF0         : 1; /* End of Frame Status for Base (Channel 0) */
1424 +    unsigned long BS0          : 1; /* Branch Status for Base */
1425 +    unsigned long SINT         : 1; /* Subsequent Interrupt Status */
1426 +    unsigned long RD_ST                : 1; /* Read Status */
1427 +    unsigned long CMD_INT      : 1; /* Command Interrupt Status */
1428 +    unsigned long reserved2    :15;
1429 +    unsigned long BER_CH       : 3; /* Bus Error Channel Number */
1430 +    unsigned long reserved1    : 1;
1431 +} LCSR0_t;
1432 +typedef union {
1433 +    LCSR0_t f;
1434 +    unsigned long val;
1435 +} LCSR0_u;
1436 +
1437 +#undef BS1
1438 +typedef struct {
1439 +    unsigned long SOF1         : 1; /* Start of Frame Status for Channel 1 */
1440 +    unsigned long SOF2         : 1; /* Start of Frame Status for Channel 2 */
1441 +    unsigned long SOF3         : 1; /* Start of Frame Status for Channel 3 */
1442 +    unsigned long SOF4         : 1; /* Start of Frame Status for Channel 4 */
1443 +    unsigned long SOF5         : 1; /* Start of Frame Status for Channel 5 */
1444 +    unsigned long SOF6         : 1; /* Start of Frame Status for Channel 6 */
1445 +    unsigned long reserved4    : 2;
1446 +    unsigned long EOF1         : 1; /* End of Frame Status for Channel 1 */
1447 +    unsigned long EOF2         : 1; /* End of Frame Status for Channel 2 */
1448 +    unsigned long EOF3         : 1; /* End of Frame Status for Channel 3 */
1449 +    unsigned long EOF4         : 1; /* End of Frame Status for Channel 4 */
1450 +    unsigned long EOF5         : 1; /* End of Frame Status for Channel 5 */
1451 +    unsigned long EOF6         : 1; /* End of Frame Status for Channel 6 */
1452 +    unsigned long reserved3    : 2;
1453 +    unsigned long BS1          : 1; /* Branch Status for Channel 1 (Command Register) */
1454 +    unsigned long BS2          : 1; /* Branch Status for Channel 2 (Command Register) */
1455 +    unsigned long BS3          : 1; /* Branch Status for Channel 3 (Command Register) */
1456 +    unsigned long BS4          : 1; /* Branch Status for Channel 4 (Command Register) */
1457 +    unsigned long BS5          : 1; /* Branch Status for Channel 5 (Command Register) */
1458 +    unsigned long BS6          : 1; /* Branch Status for Channel 6 (Command Register) */
1459 +    unsigned long reserved2    : 3;
1460 +    unsigned long IU2          : 1; /* Input FIFO Underrun for Channel 2 */
1461 +    unsigned long IU3          : 1; /* Input FIFO Underrun for Channel 3 */
1462 +    unsigned long IU4          : 1; /* Input FIFO Underrun for Channel 4 */
1463 +    unsigned long IU5          : 1; /* Input FIFO Underrun for Channel 5 */
1464 +    unsigned long IU6          : 1; /* Input FIFO Underrun for Channel 6 */
1465 +    unsigned long reserved1    : 2;
1466 +} LCSR1_t;
1467 +typedef union {
1468 +    LCSR1_t f;
1469 +    unsigned long val;
1470 +} LCSR1_u;
1471 +
1472 +/* CCR unused */
1473 +/* CMDCR unused */
1474 +/* TRGBR unused */
1475 +/* TCR unused */
1476 +
1477 +typedef struct {
1478 +    unsigned long LCDBS                : 4; /* LCD Buffer Strength */
1479 +    unsigned long reserved1    :28;
1480 +} LCDBSCNTR_t;
1481 +typedef union {
1482 +    LCDBSCNTR_t f;
1483 +    unsigned long val;
1484 +} LCDBSCNTR_u;
1485 +
1486 +typedef struct {
1487 +    LCCR0_u lccr0;
1488 +    LCCR1_u lccr1;
1489 +    LCCR2_u lccr2;
1490 +    LCCR3_u lccr3;
1491 +    LCCR4_u lccr4;
1492 +    OVL1C1_u ovl1c1;
1493 +    OVL1C2_u ovl1c2;
1494 +    OVL2C1_u ovl2c1;
1495 +    OVL2C2_u ovl2c2;
1496 +    unsigned long fdadr0;
1497 +    unsigned long fdadr1;
1498 +    unsigned long fdadr2;
1499 +    unsigned long fdadr3;
1500 +    unsigned long fdadr4;
1501 +    unsigned long fdadr5;
1502 +    unsigned long fdadr6;
1503 +    char cken20_intmem;
1504 +} lcdc_state_t;
1505 +
1506 +#endif /* BVDD_P_INCLUDED */