sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <sound/core.h>
  49 #include <sound/initval.h>
  50 #include "hda_codec.h"
  51
  52
  53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  55 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  56 static char *model[SNDRV_CARDS];
  57 static int position_fix[SNDRV_CARDS];
  58 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  59 static int single_cmd;
  60 static int enable_msi;
  61 static int bdl_pos_adj = 1;
  62
  63 module_param_array(index, int, NULL, 0444);
  64 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  65 module_param_array(id, charp, NULL, 0444);
  66 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  67 module_param_array(enable, bool, NULL, 0444);
  68 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  69 module_param_array(model, charp, NULL, 0444);
  70 MODULE_PARM_DESC(model, "Use the given board model.");
  71 module_param_array(position_fix, int, NULL, 0444);
  72 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  73                  "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
  74 module_param_array(probe_mask, int, NULL, 0444);
  75 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  76 module_param(single_cmd, bool, 0444);
  77 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  78                  "(for debugging only).");
  79 module_param(enable_msi, int, 0444);
  80 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  81 module_param(bdl_pos_adj, int, 0644);
  82 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset");
  83
  84 #ifdef CONFIG_SND_HDA_POWER_SAVE
  85 /* power_save option is defined in hda_codec.c */
  86
  87 /* reset the HD-audio controller in power save mode.
  88  * this may give more power-saving, but will take longer time to
  89  * wake up.
  90  */
  91 static int power_save_controller = 1;
  92 module_param(power_save_controller, bool, 0644);
  93 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
  94 #endif
  95
  96 MODULE_LICENSE("GPL");
  97 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  98                          "{Intel, ICH6M},"
  99                          "{Intel, ICH7},"
 100                          "{Intel, ESB2},"
 101                          "{Intel, ICH8},"
 102                          "{Intel, ICH9},"
 103                          "{Intel, ICH10},"
 104                          "{Intel, SCH},"
 105                          "{ATI, SB450},"
 106                          "{ATI, SB600},"
 107                          "{ATI, RS600},"
 108                          "{ATI, RS690},"
 109                          "{ATI, RS780},"
 110                          "{ATI, R600},"
 111                          "{ATI, RV630},"
 112                          "{ATI, RV610},"
 113                          "{ATI, RV670},"
 114                          "{ATI, RV635},"
 115                          "{ATI, RV620},"
 116                          "{ATI, RV770},"
 117                          "{VIA, VT8251},"
 118                          "{VIA, VT8237A},"
 119                          "{SiS, SIS966},"
 120                          "{ULI, M5461}}");
 121 MODULE_DESCRIPTION("Intel HDA driver");
 122
 123 #define SFX     "hda-intel: "
 124
 125
 126 /*
 127  * registers
 128  */
 129 #define ICH6_REG_GCAP                   0x00
 130 #define ICH6_REG_VMIN                   0x02
 131 #define ICH6_REG_VMAJ                   0x03
 132 #define ICH6_REG_OUTPAY                 0x04
 133 #define ICH6_REG_INPAY                  0x06
 134 #define ICH6_REG_GCTL                   0x08
 135 #define ICH6_REG_WAKEEN                 0x0c
 136 #define ICH6_REG_STATESTS               0x0e
 137 #define ICH6_REG_GSTS                   0x10
 138 #define ICH6_REG_INTCTL                 0x20
 139 #define ICH6_REG_INTSTS                 0x24
 140 #define ICH6_REG_WALCLK                 0x30
 141 #define ICH6_REG_SYNC                   0x34
 142 #define ICH6_REG_CORBLBASE              0x40
 143 #define ICH6_REG_CORBUBASE              0x44
 144 #define ICH6_REG_CORBWP                 0x48
 145 #define ICH6_REG_CORBRP                 0x4A
 146 #define ICH6_REG_CORBCTL                0x4c
 147 #define ICH6_REG_CORBSTS                0x4d
 148 #define ICH6_REG_CORBSIZE               0x4e
 149
 150 #define ICH6_REG_RIRBLBASE              0x50
 151 #define ICH6_REG_RIRBUBASE              0x54
 152 #define ICH6_REG_RIRBWP                 0x58
 153 #define ICH6_REG_RINTCNT                0x5a
 154 #define ICH6_REG_RIRBCTL                0x5c
 155 #define ICH6_REG_RIRBSTS                0x5d
 156 #define ICH6_REG_RIRBSIZE               0x5e
 157
 158 #define ICH6_REG_IC                     0x60
 159 #define ICH6_REG_IR                     0x64
 160 #define ICH6_REG_IRS                    0x68
 161 #define   ICH6_IRS_VALID        (1<<1)
 162 #define   ICH6_IRS_BUSY         (1<<0)
 163
 164 #define ICH6_REG_DPLBASE                0x70
 165 #define ICH6_REG_DPUBASE                0x74
 166 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 167
 168 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 169 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 170
 171 /* stream register offsets from stream base */
 172 #define ICH6_REG_SD_CTL                 0x00
 173 #define ICH6_REG_SD_STS                 0x03
 174 #define ICH6_REG_SD_LPIB                0x04
 175 #define ICH6_REG_SD_CBL                 0x08
 176 #define ICH6_REG_SD_LVI                 0x0c
 177 #define ICH6_REG_SD_FIFOW               0x0e
 178 #define ICH6_REG_SD_FIFOSIZE            0x10
 179 #define ICH6_REG_SD_FORMAT              0x12
 180 #define ICH6_REG_SD_BDLPL               0x18
 181 #define ICH6_REG_SD_BDLPU               0x1c
 182
 183 /* PCI space */
 184 #define ICH6_PCIREG_TCSEL       0x44
 185
 186 /*
 187  * other constants
 188  */
 189
 190 /* max number of SDs */
 191 /* ICH, ATI and VIA have 4 playback and 4 capture */
 192 #define ICH6_NUM_CAPTURE        4
 193 #define ICH6_NUM_PLAYBACK       4
 194
 195 /* ULI has 6 playback and 5 capture */
 196 #define ULI_NUM_CAPTURE         5
 197 #define ULI_NUM_PLAYBACK        6
 198
 199 /* ATI HDMI has 1 playback and 0 capture */
 200 #define ATIHDMI_NUM_CAPTURE     0
 201 #define ATIHDMI_NUM_PLAYBACK    1
 202
 203 /* TERA has 4 playback and 3 capture */
 204 #define TERA_NUM_CAPTURE        3
 205 #define TERA_NUM_PLAYBACK       4
 206
 207 /* this number is statically defined for simplicity */
 208 #define MAX_AZX_DEV             16
 209
 210 /* max number of fragments - we may use more if allocating more pages for BDL */
 211 #define BDL_SIZE                4096
 212 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 213 #define AZX_MAX_FRAG            32
 214 /* max buffer size - no h/w limit, you can increase as you like */
 215 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 216 /* max number of PCM devics per card */
 217 #define AZX_MAX_PCMS            8
 218
 219 /* RIRB int mask: overrun[2], response[0] */
 220 #define RIRB_INT_RESPONSE       0x01
 221 #define RIRB_INT_OVERRUN        0x04
 222 #define RIRB_INT_MASK           0x05
 223
 224 /* STATESTS int mask: SD2,SD1,SD0 */
 225 #define AZX_MAX_CODECS          3
 226 #define STATESTS_INT_MASK       0x07
 227
 228 /* SD_CTL bits */
 229 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 230 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 231 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 232 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 233 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 234 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 235 #define SD_CTL_STREAM_TAG_SHIFT 20
 236
 237 /* SD_CTL and SD_STS */
 238 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 239 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 240 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 241 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 242                                  SD_INT_COMPLETE)
 243
 244 /* SD_STS */
 245 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 246
 247 /* INTCTL and INTSTS */
 248 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 249 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 250 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 251
 252 /* GCTL unsolicited response enable bit */
 253 #define ICH6_GCTL_UREN          (1<<8)
 254
 255 /* GCTL reset bit */
 256 #define ICH6_GCTL_RESET         (1<<0)
 257
 258 /* CORB/RIRB control, read/write pointer */
 259 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 260 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 261 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 262 /* below are so far hardcoded - should read registers in future */
 263 #define ICH6_MAX_CORB_ENTRIES   256
 264 #define ICH6_MAX_RIRB_ENTRIES   256
 265
 266 /* position fix mode */
 267 enum {
 268         POS_FIX_AUTO,
 269         POS_FIX_NONE,
 270         POS_FIX_POSBUF,
 271         POS_FIX_FIFO,
 272 };
 273
 274 /* Defines for ATI HD Audio support in SB450 south bridge */
 275 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 276 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 277
 278 /* Defines for Nvidia HDA support */
 279 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 280 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 281
 282 /* Defines for Intel SCH HDA snoop control */
 283 #define INTEL_SCH_HDA_DEVC      0x78
 284 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 285
 286
 287 /*
 288  */
 289
 290 struct azx_dev {
 291         struct snd_dma_buffer bdl; /* BDL buffer */
 292         u32 *posbuf;            /* position buffer pointer */
 293
 294         unsigned int bufsize;   /* size of the play buffer in bytes */
 295         unsigned int period_bytes; /* size of the period in bytes */
 296         unsigned int frags;     /* number for period in the play buffer */
 297         unsigned int fifo_size; /* FIFO size */
 298
 299         void __iomem *sd_addr;  /* stream descriptor pointer */
 300
 301         u32 sd_int_sta_mask;    /* stream int status mask */
 302
 303         /* pcm support */
 304         struct snd_pcm_substream *substream;    /* assigned substream,
 305                                                  * set in PCM open
 306                                                  */
 307         unsigned int format_val;        /* format value to be set in the
 308                                          * controller and the codec
 309                                          */
 310         unsigned char stream_tag;       /* assigned stream */
 311         unsigned char index;            /* stream index */
 312
 313         unsigned int opened :1;
 314         unsigned int running :1;
 315         unsigned int irq_pending :1;
 316         unsigned int irq_ignore :1;
 317 };
 318
 319 /* CORB/RIRB */
 320 struct azx_rb {
 321         u32 *buf;               /* CORB/RIRB buffer
 322                                  * Each CORB entry is 4byte, RIRB is 8byte
 323                                  */
 324         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 325         /* for RIRB */
 326         unsigned short rp, wp;  /* read/write pointers */
 327         int cmds;               /* number of pending requests */
 328         u32 res;                /* last read value */
 329 };
 330
 331 struct azx {
 332         struct snd_card *card;
 333         struct pci_dev *pci;
 334
 335         /* chip type specific */
 336         int driver_type;
 337         int playback_streams;
 338         int playback_index_offset;
 339         int capture_streams;
 340         int capture_index_offset;
 341         int num_streams;
 342
 343         /* pci resources */
 344         unsigned long addr;
 345         void __iomem *remap_addr;
 346         int irq;
 347
 348         /* locks */
 349         spinlock_t reg_lock;
 350         struct mutex open_mutex;
 351
 352         /* streams (x num_streams) */
 353         struct azx_dev *azx_dev;
 354
 355         /* PCM */
 356         struct snd_pcm *pcm[AZX_MAX_PCMS];
 357
 358         /* HD codec */
 359         unsigned short codec_mask;
 360         struct hda_bus *bus;
 361
 362         /* CORB/RIRB */
 363         struct azx_rb corb;
 364         struct azx_rb rirb;
 365
 366         /* CORB/RIRB and position buffers */
 367         struct snd_dma_buffer rb;
 368         struct snd_dma_buffer posbuf;
 369
 370         /* flags */
 371         int position_fix;
 372         unsigned int running :1;
 373         unsigned int initialized :1;
 374         unsigned int single_cmd :1;
 375         unsigned int polling_mode :1;
 376         unsigned int msi :1;
 377
 378         /* for debugging */
 379         unsigned int last_cmd;  /* last issued command (to sync) */
 380
 381         /* for pending irqs */
 382         struct work_struct irq_pending_work;
 383 };
 384
 385 /* driver types */
 386 enum {
 387         AZX_DRIVER_ICH,
 388         AZX_DRIVER_SCH,
 389         AZX_DRIVER_ATI,
 390         AZX_DRIVER_ATIHDMI,
 391         AZX_DRIVER_VIA,
 392         AZX_DRIVER_SIS,
 393         AZX_DRIVER_ULI,
 394         AZX_DRIVER_NVIDIA,
 395         AZX_DRIVER_TERA,
 396 };
 397
 398 static char *driver_short_names[] __devinitdata = {
 399         [AZX_DRIVER_ICH] = "HDA Intel",
 400         [AZX_DRIVER_SCH] = "HDA Intel MID",
 401         [AZX_DRIVER_ATI] = "HDA ATI SB",
 402         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 403         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 404         [AZX_DRIVER_SIS] = "HDA SIS966",
 405         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 406         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 407         [AZX_DRIVER_TERA] = "HDA Teradici",
 408 };
 409
 410 /*
 411  * macros for easy use
 412  */
 413 #define azx_writel(chip,reg,value) \
 414         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 415 #define azx_readl(chip,reg) \
 416         readl((chip)->remap_addr + ICH6_REG_##reg)
 417 #define azx_writew(chip,reg,value) \
 418         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 419 #define azx_readw(chip,reg) \
 420         readw((chip)->remap_addr + ICH6_REG_##reg)
 421 #define azx_writeb(chip,reg,value) \
 422         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 423 #define azx_readb(chip,reg) \
 424         readb((chip)->remap_addr + ICH6_REG_##reg)
 425
 426 #define azx_sd_writel(dev,reg,value) \
 427         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 428 #define azx_sd_readl(dev,reg) \
 429         readl((dev)->sd_addr + ICH6_REG_##reg)
 430 #define azx_sd_writew(dev,reg,value) \
 431         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 432 #define azx_sd_readw(dev,reg) \
 433         readw((dev)->sd_addr + ICH6_REG_##reg)
 434 #define azx_sd_writeb(dev,reg,value) \
 435         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 436 #define azx_sd_readb(dev,reg) \
 437         readb((dev)->sd_addr + ICH6_REG_##reg)
 438
 439 /* for pcm support */
 440 #define get_azx_dev(substream) (substream->runtime->private_data)
 441
 442 /* Get the upper 32bit of the given dma_addr_t
 443  * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
 444  */
 445 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
 446
 447 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 448
 449 /*
 450  * Interface for HD codec
 451  */
 452
 453 /*
 454  * CORB / RIRB interface
 455  */
 456 static int azx_alloc_cmd_io(struct azx *chip)
 457 {
 458         int err;
 459
 460         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 461         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 462                                   snd_dma_pci_data(chip->pci),
 463                                   PAGE_SIZE, &chip->rb);
 464         if (err < 0) {
 465                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 466                 return err;
 467         }
 468         return 0;
 469 }
 470
 471 static void azx_init_cmd_io(struct azx *chip)
 472 {
 473         /* CORB set up */
 474         chip->corb.addr = chip->rb.addr;
 475         chip->corb.buf = (u32 *)chip->rb.area;
 476         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 477         azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
 478
 479         /* set the corb size to 256 entries (ULI requires explicitly) */
 480         azx_writeb(chip, CORBSIZE, 0x02);
 481         /* set the corb write pointer to 0 */
 482         azx_writew(chip, CORBWP, 0);
 483         /* reset the corb hw read pointer */
 484         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 485         /* enable corb dma */
 486         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 487
 488         /* RIRB set up */
 489         chip->rirb.addr = chip->rb.addr + 2048;
 490         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 491         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 492         azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
 493
 494         /* set the rirb size to 256 entries (ULI requires explicitly) */
 495         azx_writeb(chip, RIRBSIZE, 0x02);
 496         /* reset the rirb hw write pointer */
 497         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 498         /* set N=1, get RIRB response interrupt for new entry */
 499         azx_writew(chip, RINTCNT, 1);
 500         /* enable rirb dma and response irq */
 501         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 502         chip->rirb.rp = chip->rirb.cmds = 0;
 503 }
 504
 505 static void azx_free_cmd_io(struct azx *chip)
 506 {
 507         /* disable ringbuffer DMAs */
 508         azx_writeb(chip, RIRBCTL, 0);
 509         azx_writeb(chip, CORBCTL, 0);
 510 }
 511
 512 /* send a command */
 513 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
 514 {
 515         struct azx *chip = codec->bus->private_data;
 516         unsigned int wp;
 517
 518         /* add command to corb */
 519         wp = azx_readb(chip, CORBWP);
 520         wp++;
 521         wp %= ICH6_MAX_CORB_ENTRIES;
 522
 523         spin_lock_irq(&chip->reg_lock);
 524         chip->rirb.cmds++;
 525         chip->corb.buf[wp] = cpu_to_le32(val);
 526         azx_writel(chip, CORBWP, wp);
 527         spin_unlock_irq(&chip->reg_lock);
 528
 529         return 0;
 530 }
 531
 532 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 533
 534 /* retrieve RIRB entry - called from interrupt handler */
 535 static void azx_update_rirb(struct azx *chip)
 536 {
 537         unsigned int rp, wp;
 538         u32 res, res_ex;
 539
 540         wp = azx_readb(chip, RIRBWP);
 541         if (wp == chip->rirb.wp)
 542                 return;
 543         chip->rirb.wp = wp;
 544
 545         while (chip->rirb.rp != wp) {
 546                 chip->rirb.rp++;
 547                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 548
 549                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 550                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 551                 res = le32_to_cpu(chip->rirb.buf[rp]);
 552                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 553                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 554                 else if (chip->rirb.cmds) {
 555                         chip->rirb.res = res;
 556                         smp_wmb();
 557                         chip->rirb.cmds--;
 558                 }
 559         }
 560 }
 561
 562 /* receive a response */
 563 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
 564 {
 565         struct azx *chip = codec->bus->private_data;
 566         unsigned long timeout;
 567
 568  again:
 569         timeout = jiffies + msecs_to_jiffies(1000);
 570         for (;;) {
 571                 if (chip->polling_mode) {
 572                         spin_lock_irq(&chip->reg_lock);
 573                         azx_update_rirb(chip);
 574                         spin_unlock_irq(&chip->reg_lock);
 575                 }
 576                 if (!chip->rirb.cmds) {
 577                         smp_rmb();
 578                         return chip->rirb.res; /* the last value */
 579                 }
 580                 if (time_after(jiffies, timeout))
 581                         break;
 582                 if (codec->bus->needs_damn_long_delay)
 583                         msleep(2); /* temporary workaround */
 584                 else {
 585                         udelay(10);
 586                         cond_resched();
 587                 }
 588         }
 589
 590         if (chip->msi) {
 591                 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
 592                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 593                 free_irq(chip->irq, chip);
 594                 chip->irq = -1;
 595                 pci_disable_msi(chip->pci);
 596                 chip->msi = 0;
 597                 if (azx_acquire_irq(chip, 1) < 0)
 598                         return -1;
 599                 goto again;
 600         }
 601
 602         if (!chip->polling_mode) {
 603                 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
 604                            "switching to polling mode: last cmd=0x%08x\n",
 605                            chip->last_cmd);
 606                 chip->polling_mode = 1;
 607                 goto again;
 608         }
 609
 610         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 611                    "switching to single_cmd mode: last cmd=0x%08x\n",
 612                    chip->last_cmd);
 613         chip->rirb.rp = azx_readb(chip, RIRBWP);
 614         chip->rirb.cmds = 0;
 615         /* switch to single_cmd mode */
 616         chip->single_cmd = 1;
 617         azx_free_cmd_io(chip);
 618         return -1;
 619 }
 620
 621 /*
 622  * Use the single immediate command instead of CORB/RIRB for simplicity
 623  *
 624  * Note: according to Intel, this is not preferred use.  The command was
 625  *       intended for the BIOS only, and may get confused with unsolicited
 626  *       responses.  So, we shouldn't use it for normal operation from the
 627  *       driver.
 628  *       I left the codes, however, for debugging/testing purposes.
 629  */
 630
 631 /* send a command */
 632 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
 633 {
 634         struct azx *chip = codec->bus->private_data;
 635         int timeout = 50;
 636
 637         while (timeout--) {
 638                 /* check ICB busy bit */
 639                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 640                         /* Clear IRV valid bit */
 641                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 642                                    ICH6_IRS_VALID);
 643                         azx_writel(chip, IC, val);
 644                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 645                                    ICH6_IRS_BUSY);
 646                         return 0;
 647                 }
 648                 udelay(1);
 649         }
 650         if (printk_ratelimit())
 651                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 652                            azx_readw(chip, IRS), val);
 653         return -EIO;
 654 }
 655
 656 /* receive a response */
 657 static unsigned int azx_single_get_response(struct hda_codec *codec)
 658 {
 659         struct azx *chip = codec->bus->private_data;
 660         int timeout = 50;
 661
 662         while (timeout--) {
 663                 /* check IRV busy bit */
 664                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 665                         return azx_readl(chip, IR);
 666                 udelay(1);
 667         }
 668         if (printk_ratelimit())
 669                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 670                            azx_readw(chip, IRS));
 671         return (unsigned int)-1;
 672 }
 673
 674 /*
 675  * The below are the main callbacks from hda_codec.
 676  *
 677  * They are just the skeleton to call sub-callbacks according to the
 678  * current setting of chip->single_cmd.
 679  */
 680
 681 /* send a command */
 682 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
 683                         int direct, unsigned int verb,
 684                         unsigned int para)
 685 {
 686         struct azx *chip = codec->bus->private_data;
 687         u32 val;
 688
 689         val = (u32)(codec->addr & 0x0f) << 28;
 690         val |= (u32)direct << 27;
 691         val |= (u32)nid << 20;
 692         val |= verb << 8;
 693         val |= para;
 694         chip->last_cmd = val;
 695
 696         if (chip->single_cmd)
 697                 return azx_single_send_cmd(codec, val);
 698         else
 699                 return azx_corb_send_cmd(codec, val);
 700 }
 701
 702 /* get a response */
 703 static unsigned int azx_get_response(struct hda_codec *codec)
 704 {
 705         struct azx *chip = codec->bus->private_data;
 706         if (chip->single_cmd)
 707                 return azx_single_get_response(codec);
 708         else
 709                 return azx_rirb_get_response(codec);
 710 }
 711
 712 #ifdef CONFIG_SND_HDA_POWER_SAVE
 713 static void azx_power_notify(struct hda_codec *codec);
 714 #endif
 715
 716 /* reset codec link */
 717 static int azx_reset(struct azx *chip)
 718 {
 719         int count;
 720
 721         /* clear STATESTS */
 722         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 723
 724         /* reset controller */
 725         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 726
 727         count = 50;
 728         while (azx_readb(chip, GCTL) && --count)
 729                 msleep(1);
 730
 731         /* delay for >= 100us for codec PLL to settle per spec
 732          * Rev 0.9 section 5.5.1
 733          */
 734         msleep(1);
 735
 736         /* Bring controller out of reset */
 737         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 738
 739         count = 50;
 740         while (!azx_readb(chip, GCTL) && --count)
 741                 msleep(1);
 742
 743         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 744         msleep(1);
 745
 746         /* check to see if controller is ready */
 747         if (!azx_readb(chip, GCTL)) {
 748                 snd_printd("azx_reset: controller not ready!\n");
 749                 return -EBUSY;
 750         }
 751
 752         /* Accept unsolicited responses */
 753         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
 754
 755         /* detect codecs */
 756         if (!chip->codec_mask) {
 757                 chip->codec_mask = azx_readw(chip, STATESTS);
 758                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 759         }
 760
 761         return 0;
 762 }
 763
 764
 765 /*
 766  * Lowlevel interface
 767  */
 768
 769 /* enable interrupts */
 770 static void azx_int_enable(struct azx *chip)
 771 {
 772         /* enable controller CIE and GIE */
 773         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 774                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 775 }
 776
 777 /* disable interrupts */
 778 static void azx_int_disable(struct azx *chip)
 779 {
 780         int i;
 781
 782         /* disable interrupts in stream descriptor */
 783         for (i = 0; i < chip->num_streams; i++) {
 784                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 785                 azx_sd_writeb(azx_dev, SD_CTL,
 786                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 787         }
 788
 789         /* disable SIE for all streams */
 790         azx_writeb(chip, INTCTL, 0);
 791
 792         /* disable controller CIE and GIE */
 793         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 794                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 795 }
 796
 797 /* clear interrupts */
 798 static void azx_int_clear(struct azx *chip)
 799 {
 800         int i;
 801
 802         /* clear stream status */
 803         for (i = 0; i < chip->num_streams; i++) {
 804                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 805                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 806         }
 807
 808         /* clear STATESTS */
 809         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 810
 811         /* clear rirb status */
 812         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 813
 814         /* clear int status */
 815         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 816 }
 817
 818 /* start a stream */
 819 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 820 {
 821         /* enable SIE */
 822         azx_writeb(chip, INTCTL,
 823                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 824         /* set DMA start and interrupt mask */
 825         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 826                       SD_CTL_DMA_START | SD_INT_MASK);
 827 }
 828
 829 /* stop a stream */
 830 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 831 {
 832         /* stop DMA */
 833         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 834                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 835         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 836         /* disable SIE */
 837         azx_writeb(chip, INTCTL,
 838                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 839 }
 840
 841
 842 /*
 843  * reset and start the controller registers
 844  */
 845 static void azx_init_chip(struct azx *chip)
 846 {
 847         if (chip->initialized)
 848                 return;
 849
 850         /* reset controller */
 851         azx_reset(chip);
 852
 853         /* initialize interrupts */
 854         azx_int_clear(chip);
 855         azx_int_enable(chip);
 856
 857         /* initialize the codec command I/O */
 858         if (!chip->single_cmd)
 859                 azx_init_cmd_io(chip);
 860
 861         /* program the position buffer */
 862         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 863         azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
 864
 865         chip->initialized = 1;
 866 }
 867
 868 /*
 869  * initialize the PCI registers
 870  */
 871 /* update bits in a PCI register byte */
 872 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 873                             unsigned char mask, unsigned char val)
 874 {
 875         unsigned char data;
 876
 877         pci_read_config_byte(pci, reg, &data);
 878         data &= ~mask;
 879         data |= (val & mask);
 880         pci_write_config_byte(pci, reg, data);
 881 }
 882
 883 static void azx_init_pci(struct azx *chip)
 884 {
 885         unsigned short snoop;
 886
 887         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 888          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 889          * Ensuring these bits are 0 clears playback static on some HD Audio
 890          * codecs
 891          */
 892         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 893
 894         switch (chip->driver_type) {
 895         case AZX_DRIVER_ATI:
 896                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
 897                 update_pci_byte(chip->pci,
 898                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 899                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 900                 break;
 901         case AZX_DRIVER_NVIDIA:
 902                 /* For NVIDIA HDA, enable snoop */
 903                 update_pci_byte(chip->pci,
 904                                 NVIDIA_HDA_TRANSREG_ADDR,
 905                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 906                 break;
 907         case AZX_DRIVER_SCH:
 908                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 909                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
 910                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
 911                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
 912                         pci_read_config_word(chip->pci,
 913                                 INTEL_SCH_HDA_DEVC, &snoop);
 914                         snd_printdd("HDA snoop disabled, enabling ... %s\n",\
 915                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
 916                                 ? "Failed" : "OK");
 917                 }
 918                 break;
 919
 920         }
 921 }
 922
 923
 924 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 925
 926 /*
 927  * interrupt handler
 928  */
 929 static irqreturn_t azx_interrupt(int irq, void *dev_id)
 930 {
 931         struct azx *chip = dev_id;
 932         struct azx_dev *azx_dev;
 933         u32 status;
 934         int i;
 935
 936         spin_lock(&chip->reg_lock);
 937
 938         status = azx_readl(chip, INTSTS);
 939         if (status == 0) {
 940                 spin_unlock(&chip->reg_lock);
 941                 return IRQ_NONE;
 942         }
 943
 944         for (i = 0; i < chip->num_streams; i++) {
 945                 azx_dev = &chip->azx_dev[i];
 946                 if (status & azx_dev->sd_int_sta_mask) {
 947                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 948                         if (!azx_dev->substream || !azx_dev->running)
 949                                 continue;
 950                         /* ignore the first dummy IRQ (due to pos_adj) */
 951                         if (azx_dev->irq_ignore) {
 952                                 azx_dev->irq_ignore = 0;
 953                                 continue;
 954                         }
 955                         /* check whether this IRQ is really acceptable */
 956                         if (azx_position_ok(chip, azx_dev)) {
 957                                 azx_dev->irq_pending = 0;
 958                                 spin_unlock(&chip->reg_lock);
 959                                 snd_pcm_period_elapsed(azx_dev->substream);
 960                                 spin_lock(&chip->reg_lock);
 961                         } else {
 962                                 /* bogus IRQ, process it later */
 963                                 azx_dev->irq_pending = 1;
 964                                 schedule_work(&chip->irq_pending_work);
 965                         }
 966                 }
 967         }
 968
 969         /* clear rirb int */
 970         status = azx_readb(chip, RIRBSTS);
 971         if (status & RIRB_INT_MASK) {
 972                 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
 973                         azx_update_rirb(chip);
 974                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 975         }
 976
 977 #if 0
 978         /* clear state status int */
 979         if (azx_readb(chip, STATESTS) & 0x04)
 980                 azx_writeb(chip, STATESTS, 0x04);
 981 #endif
 982         spin_unlock(&chip->reg_lock);
 983
 984         return IRQ_HANDLED;
 985 }
 986
 987
 988 /*
 989  * set up a BDL entry
 990  */
 991 static int setup_bdle(struct snd_pcm_substream *substream,
 992                       struct azx_dev *azx_dev, u32 **bdlp,
 993                       int ofs, int size, int with_ioc)
 994 {
 995         struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
 996         u32 *bdl = *bdlp;
 997
 998         while (size > 0) {
 999                 dma_addr_t addr;
1000                 int chunk;
1001
1002                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1003                         return -EINVAL;
1004
1005                 addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs);
1006                 /* program the address field of the BDL entry */
1007                 bdl[0] = cpu_to_le32((u32)addr);
1008                 bdl[1] = cpu_to_le32(upper_32bit(addr));
1009                 /* program the size field of the BDL entry */
1010                 chunk = PAGE_SIZE - (ofs % PAGE_SIZE);
1011                 if (size < chunk)
1012                         chunk = size;
1013                 bdl[2] = cpu_to_le32(chunk);
1014                 /* program the IOC to enable interrupt
1015                  * only when the whole fragment is processed
1016                  */
1017                 size -= chunk;
1018                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1019                 bdl += 4;
1020                 azx_dev->frags++;
1021                 ofs += chunk;
1022         }
1023         *bdlp = bdl;
1024         return ofs;
1025 }
1026
1027 /*
1028  * set up BDL entries
1029  */
1030 static int azx_setup_periods(struct snd_pcm_substream *substream,
1031                              struct azx_dev *azx_dev)
1032 {
1033         u32 *bdl;
1034         int i, ofs, periods, period_bytes;
1035         int pos_adj = 0;
1036
1037         /* reset BDL address */
1038         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1039         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1040
1041         period_bytes = snd_pcm_lib_period_bytes(substream);
1042         azx_dev->period_bytes = period_bytes;
1043         periods = azx_dev->bufsize / period_bytes;
1044
1045         /* program the initial BDL entries */
1046         bdl = (u32 *)azx_dev->bdl.area;
1047         ofs = 0;
1048         azx_dev->frags = 0;
1049         azx_dev->irq_ignore = 0;
1050         if (bdl_pos_adj > 0) {
1051                 struct snd_pcm_runtime *runtime = substream->runtime;
1052                 pos_adj = (bdl_pos_adj * runtime->rate + 47999) / 48000;
1053                 if (!pos_adj)
1054                         pos_adj = 1;
1055                 pos_adj = frames_to_bytes(runtime, pos_adj);
1056                 if (pos_adj >= period_bytes) {
1057                         snd_printk(KERN_WARNING "Too big adjustment %d\n",
1058                                    bdl_pos_adj);
1059                         pos_adj = 0;
1060                 } else {
1061                         ofs = setup_bdle(substream, azx_dev,
1062                                          &bdl, ofs, pos_adj, 1);
1063                         if (ofs < 0)
1064                                 goto error;
1065                         azx_dev->irq_ignore = 1;
1066                 }
1067         }
1068         for (i = 0; i < periods; i++) {
1069                 if (i == periods - 1 && pos_adj)
1070                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1071                                          period_bytes - pos_adj, 0);
1072                 else
1073                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1074                                          period_bytes, 1);
1075                 if (ofs < 0)
1076                         goto error;
1077         }
1078         return 0;
1079
1080  error:
1081         snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1082                    azx_dev->bufsize, period_bytes);
1083         /* reset */
1084         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1085         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1086         return -EINVAL;
1087 }
1088
1089 /*
1090  * set up the SD for streaming
1091  */
1092 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1093 {
1094         unsigned char val;
1095         int timeout;
1096
1097         /* make sure the run bit is zero for SD */
1098         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1099                       ~SD_CTL_DMA_START);
1100         /* reset stream */
1101         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1102                       SD_CTL_STREAM_RESET);
1103         udelay(3);
1104         timeout = 300;
1105         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1106                --timeout)
1107                 ;
1108         val &= ~SD_CTL_STREAM_RESET;
1109         azx_sd_writeb(azx_dev, SD_CTL, val);
1110         udelay(3);
1111
1112         timeout = 300;
1113         /* waiting for hardware to report that the stream is out of reset */
1114         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1115                --timeout)
1116                 ;
1117
1118         /* program the stream_tag */
1119         azx_sd_writel(azx_dev, SD_CTL,
1120                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1121                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1122
1123         /* program the length of samples in cyclic buffer */
1124         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1125
1126         /* program the stream format */
1127         /* this value needs to be the same as the one programmed */
1128         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1129
1130         /* program the stream LVI (last valid index) of the BDL */
1131         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1132
1133         /* program the BDL address */
1134         /* lower BDL address */
1135         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1136         /* upper BDL address */
1137         azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl.addr));
1138
1139         /* enable the position buffer */
1140         if (chip->position_fix == POS_FIX_POSBUF ||
1141             chip->position_fix == POS_FIX_AUTO) {
1142                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1143                         azx_writel(chip, DPLBASE,
1144                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1145         }
1146
1147         /* set the interrupt enable bits in the descriptor control register */
1148         azx_sd_writel(azx_dev, SD_CTL,
1149                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1150
1151         return 0;
1152 }
1153
1154
1155 /*
1156  * Codec initialization
1157  */
1158
1159 static unsigned int azx_max_codecs[] __devinitdata = {
1160         [AZX_DRIVER_ICH] = 4,           /* Some ICH9 boards use SD3 */
1161         [AZX_DRIVER_SCH] = 3,
1162         [AZX_DRIVER_ATI] = 4,
1163         [AZX_DRIVER_ATIHDMI] = 4,
1164         [AZX_DRIVER_VIA] = 3,           /* FIXME: correct? */
1165         [AZX_DRIVER_SIS] = 3,           /* FIXME: correct? */
1166         [AZX_DRIVER_ULI] = 3,           /* FIXME: correct? */
1167         [AZX_DRIVER_NVIDIA] = 3,        /* FIXME: correct? */
1168         [AZX_DRIVER_TERA] = 1,
1169 };
1170
1171 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1172                                       unsigned int codec_probe_mask)
1173 {
1174         struct hda_bus_template bus_temp;
1175         int c, codecs, audio_codecs, err;
1176
1177         memset(&bus_temp, 0, sizeof(bus_temp));
1178         bus_temp.private_data = chip;
1179         bus_temp.modelname = model;
1180         bus_temp.pci = chip->pci;
1181         bus_temp.ops.command = azx_send_cmd;
1182         bus_temp.ops.get_response = azx_get_response;
1183 #ifdef CONFIG_SND_HDA_POWER_SAVE
1184         bus_temp.ops.pm_notify = azx_power_notify;
1185 #endif
1186
1187         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1188         if (err < 0)
1189                 return err;
1190
1191         codecs = audio_codecs = 0;
1192         for (c = 0; c < AZX_MAX_CODECS; c++) {
1193                 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1194                         struct hda_codec *codec;
1195                         err = snd_hda_codec_new(chip->bus, c, &codec);
1196                         if (err < 0)
1197                                 continue;
1198                         codecs++;
1199                         if (codec->afg)
1200                                 audio_codecs++;
1201                 }
1202         }
1203         if (!audio_codecs) {
1204                 /* probe additional slots if no codec is found */
1205                 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1206                         if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1207                                 err = snd_hda_codec_new(chip->bus, c, NULL);
1208                                 if (err < 0)
1209                                         continue;
1210                                 codecs++;
1211                         }
1212                 }
1213         }
1214         if (!codecs) {
1215                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1216                 return -ENXIO;
1217         }
1218
1219         return 0;
1220 }
1221
1222
1223 /*
1224  * PCM support
1225  */
1226
1227 /* assign a stream for the PCM */
1228 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1229 {
1230         int dev, i, nums;
1231         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1232                 dev = chip->playback_index_offset;
1233                 nums = chip->playback_streams;
1234         } else {
1235                 dev = chip->capture_index_offset;
1236                 nums = chip->capture_streams;
1237         }
1238         for (i = 0; i < nums; i++, dev++)
1239                 if (!chip->azx_dev[dev].opened) {
1240                         chip->azx_dev[dev].opened = 1;
1241                         return &chip->azx_dev[dev];
1242                 }
1243         return NULL;
1244 }
1245
1246 /* release the assigned stream */
1247 static inline void azx_release_device(struct azx_dev *azx_dev)
1248 {
1249         azx_dev->opened = 0;
1250 }
1251
1252 static struct snd_pcm_hardware azx_pcm_hw = {
1253         .info =                 (SNDRV_PCM_INFO_MMAP |
1254                                  SNDRV_PCM_INFO_INTERLEAVED |
1255                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1256                                  SNDRV_PCM_INFO_MMAP_VALID |
1257                                  /* No full-resume yet implemented */
1258                                  /* SNDRV_PCM_INFO_RESUME |*/
1259                                  SNDRV_PCM_INFO_PAUSE |
1260                                  SNDRV_PCM_INFO_SYNC_START),
1261         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1262         .rates =                SNDRV_PCM_RATE_48000,
1263         .rate_min =             48000,
1264         .rate_max =             48000,
1265         .channels_min =         2,
1266         .channels_max =         2,
1267         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1268         .period_bytes_min =     128,
1269         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1270         .periods_min =          2,
1271         .periods_max =          AZX_MAX_FRAG,
1272         .fifo_size =            0,
1273 };
1274
1275 struct azx_pcm {
1276         struct azx *chip;
1277         struct hda_codec *codec;
1278         struct hda_pcm_stream *hinfo[2];
1279 };
1280
1281 static int azx_pcm_open(struct snd_pcm_substream *substream)
1282 {
1283         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1284         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1285         struct azx *chip = apcm->chip;
1286         struct azx_dev *azx_dev;
1287         struct snd_pcm_runtime *runtime = substream->runtime;
1288         unsigned long flags;
1289         int err;
1290
1291         mutex_lock(&chip->open_mutex);
1292         azx_dev = azx_assign_device(chip, substream->stream);
1293         if (azx_dev == NULL) {
1294                 mutex_unlock(&chip->open_mutex);
1295                 return -EBUSY;
1296         }
1297         runtime->hw = azx_pcm_hw;
1298         runtime->hw.channels_min = hinfo->channels_min;
1299         runtime->hw.channels_max = hinfo->channels_max;
1300         runtime->hw.formats = hinfo->formats;
1301         runtime->hw.rates = hinfo->rates;
1302         snd_pcm_limit_hw_rates(runtime);
1303         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1304         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1305                                    128);
1306         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1307                                    128);
1308         snd_hda_power_up(apcm->codec);
1309         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1310         if (err < 0) {
1311                 azx_release_device(azx_dev);
1312                 snd_hda_power_down(apcm->codec);
1313                 mutex_unlock(&chip->open_mutex);
1314                 return err;
1315         }
1316         spin_lock_irqsave(&chip->reg_lock, flags);
1317         azx_dev->substream = substream;
1318         azx_dev->running = 0;
1319         spin_unlock_irqrestore(&chip->reg_lock, flags);
1320
1321         runtime->private_data = azx_dev;
1322         snd_pcm_set_sync(substream);
1323         mutex_unlock(&chip->open_mutex);
1324         return 0;
1325 }
1326
1327 static int azx_pcm_close(struct snd_pcm_substream *substream)
1328 {
1329         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1330         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1331         struct azx *chip = apcm->chip;
1332         struct azx_dev *azx_dev = get_azx_dev(substream);
1333         unsigned long flags;
1334
1335         mutex_lock(&chip->open_mutex);
1336         spin_lock_irqsave(&chip->reg_lock, flags);
1337         azx_dev->substream = NULL;
1338         azx_dev->running = 0;
1339         spin_unlock_irqrestore(&chip->reg_lock, flags);
1340         azx_release_device(azx_dev);
1341         hinfo->ops.close(hinfo, apcm->codec, substream);
1342         snd_hda_power_down(apcm->codec);
1343         mutex_unlock(&chip->open_mutex);
1344         return 0;
1345 }
1346
1347 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1348                              struct snd_pcm_hw_params *hw_params)
1349 {
1350         return snd_pcm_lib_malloc_pages(substream,
1351                                         params_buffer_bytes(hw_params));
1352 }
1353
1354 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1355 {
1356         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1357         struct azx_dev *azx_dev = get_azx_dev(substream);
1358         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1359
1360         /* reset BDL address */
1361         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1362         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1363         azx_sd_writel(azx_dev, SD_CTL, 0);
1364
1365         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1366
1367         return snd_pcm_lib_free_pages(substream);
1368 }
1369
1370 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1371 {
1372         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1373         struct azx *chip = apcm->chip;
1374         struct azx_dev *azx_dev = get_azx_dev(substream);
1375         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1376         struct snd_pcm_runtime *runtime = substream->runtime;
1377
1378         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1379         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1380                                                          runtime->channels,
1381                                                          runtime->format,
1382                                                          hinfo->maxbps);
1383         if (!azx_dev->format_val) {
1384                 snd_printk(KERN_ERR SFX
1385                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1386                            runtime->rate, runtime->channels, runtime->format);
1387                 return -EINVAL;
1388         }
1389
1390         snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1391                     azx_dev->bufsize, azx_dev->format_val);
1392         if (azx_setup_periods(substream, azx_dev) < 0)
1393                 return -EINVAL;
1394         azx_setup_controller(chip, azx_dev);
1395         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1396                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1397         else
1398                 azx_dev->fifo_size = 0;
1399
1400         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1401                                   azx_dev->format_val, substream);
1402 }
1403
1404 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1405 {
1406         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1407         struct azx *chip = apcm->chip;
1408         struct azx_dev *azx_dev;
1409         struct snd_pcm_substream *s;
1410         int start, nsync = 0, sbits = 0;
1411         int nwait, timeout;
1412
1413         switch (cmd) {
1414         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1415         case SNDRV_PCM_TRIGGER_RESUME:
1416         case SNDRV_PCM_TRIGGER_START:
1417                 start = 1;
1418                 break;
1419         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1420         case SNDRV_PCM_TRIGGER_SUSPEND:
1421         case SNDRV_PCM_TRIGGER_STOP:
1422                 start = 0;
1423                 break;
1424         default:
1425                 return -EINVAL;
1426         }
1427
1428         snd_pcm_group_for_each_entry(s, substream) {
1429                 if (s->pcm->card != substream->pcm->card)
1430                         continue;
1431                 azx_dev = get_azx_dev(s);
1432                 sbits |= 1 << azx_dev->index;
1433                 nsync++;
1434                 snd_pcm_trigger_done(s, substream);
1435         }
1436
1437         spin_lock(&chip->reg_lock);
1438         if (nsync > 1) {
1439                 /* first, set SYNC bits of corresponding streams */
1440                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1441         }
1442         snd_pcm_group_for_each_entry(s, substream) {
1443                 if (s->pcm->card != substream->pcm->card)
1444                         continue;
1445                 azx_dev = get_azx_dev(s);
1446                 if (start)
1447                         azx_stream_start(chip, azx_dev);
1448                 else
1449                         azx_stream_stop(chip, azx_dev);
1450                 azx_dev->running = start;
1451         }
1452         spin_unlock(&chip->reg_lock);
1453         if (start) {
1454                 if (nsync == 1)
1455                         return 0;
1456                 /* wait until all FIFOs get ready */
1457                 for (timeout = 5000; timeout; timeout--) {
1458                         nwait = 0;
1459                         snd_pcm_group_for_each_entry(s, substream) {
1460                                 if (s->pcm->card != substream->pcm->card)
1461                                         continue;
1462                                 azx_dev = get_azx_dev(s);
1463                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1464                                       SD_STS_FIFO_READY))
1465                                         nwait++;
1466                         }
1467                         if (!nwait)
1468                                 break;
1469                         cpu_relax();
1470                 }
1471         } else {
1472                 /* wait until all RUN bits are cleared */
1473                 for (timeout = 5000; timeout; timeout--) {
1474                         nwait = 0;
1475                         snd_pcm_group_for_each_entry(s, substream) {
1476                                 if (s->pcm->card != substream->pcm->card)
1477                                         continue;
1478                                 azx_dev = get_azx_dev(s);
1479                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1480                                     SD_CTL_DMA_START)
1481                                         nwait++;
1482                         }
1483                         if (!nwait)
1484                                 break;
1485                         cpu_relax();
1486                 }
1487         }
1488         if (nsync > 1) {
1489                 spin_lock(&chip->reg_lock);
1490                 /* reset SYNC bits */
1491                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1492                 spin_unlock(&chip->reg_lock);
1493         }
1494         return 0;
1495 }
1496
1497 static unsigned int azx_get_position(struct azx *chip,
1498                                      struct azx_dev *azx_dev)
1499 {
1500         unsigned int pos;
1501
1502         if (chip->position_fix == POS_FIX_POSBUF ||
1503             chip->position_fix == POS_FIX_AUTO) {
1504                 /* use the position buffer */
1505                 pos = le32_to_cpu(*azx_dev->posbuf);
1506         } else {
1507                 /* read LPIB */
1508                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1509                 if (chip->position_fix == POS_FIX_FIFO)
1510                         pos += azx_dev->fifo_size;
1511         }
1512         if (pos >= azx_dev->bufsize)
1513                 pos = 0;
1514         return pos;
1515 }
1516
1517 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1518 {
1519         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1520         struct azx *chip = apcm->chip;
1521         struct azx_dev *azx_dev = get_azx_dev(substream);
1522         return bytes_to_frames(substream->runtime,
1523                                azx_get_position(chip, azx_dev));
1524 }
1525
1526 /*
1527  * Check whether the current DMA position is acceptable for updating
1528  * periods.  Returns non-zero if it's OK.
1529  *
1530  * Many HD-audio controllers appear pretty inaccurate about
1531  * the update-IRQ timing.  The IRQ is issued before actually the
1532  * data is processed.  So, we need to process it afterwords in a
1533  * workqueue.
1534  */
1535 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1536 {
1537         unsigned int pos;
1538
1539         pos = azx_get_position(chip, azx_dev);
1540         if (chip->position_fix == POS_FIX_AUTO) {
1541                 if (!pos) {
1542                         printk(KERN_WARNING
1543                                "hda-intel: Invalid position buffer, "
1544                                "using LPIB read method instead.\n");
1545                         chip->position_fix = POS_FIX_NONE;
1546                         pos = azx_get_position(chip, azx_dev);
1547                 } else
1548                         chip->position_fix = POS_FIX_POSBUF;
1549         }
1550
1551         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1552                 return 0; /* NG - it's below the period boundary */
1553         return 1; /* OK, it's fine */
1554 }
1555
1556 /*
1557  * The work for pending PCM period updates.
1558  */
1559 static void azx_irq_pending_work(struct work_struct *work)
1560 {
1561         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1562         int i, pending;
1563
1564         for (;;) {
1565                 pending = 0;
1566                 spin_lock_irq(&chip->reg_lock);
1567                 for (i = 0; i < chip->num_streams; i++) {
1568                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1569                         if (!azx_dev->irq_pending ||
1570                             !azx_dev->substream ||
1571                             !azx_dev->running)
1572                                 continue;
1573                         if (azx_position_ok(chip, azx_dev)) {
1574                                 azx_dev->irq_pending = 0;
1575                                 spin_unlock(&chip->reg_lock);
1576                                 snd_pcm_period_elapsed(azx_dev->substream);
1577                                 spin_lock(&chip->reg_lock);
1578                         } else
1579                                 pending++;
1580                 }
1581                 spin_unlock_irq(&chip->reg_lock);
1582                 if (!pending)
1583                         return;
1584                 cond_resched();
1585         }
1586 }
1587
1588 /* clear irq_pending flags and assure no on-going workq */
1589 static void azx_clear_irq_pending(struct azx *chip)
1590 {
1591         int i;
1592
1593         spin_lock_irq(&chip->reg_lock);
1594         for (i = 0; i < chip->num_streams; i++)
1595                 chip->azx_dev[i].irq_pending = 0;
1596         spin_unlock_irq(&chip->reg_lock);
1597         flush_scheduled_work();
1598 }
1599
1600 static struct snd_pcm_ops azx_pcm_ops = {
1601         .open = azx_pcm_open,
1602         .close = azx_pcm_close,
1603         .ioctl = snd_pcm_lib_ioctl,
1604         .hw_params = azx_pcm_hw_params,
1605         .hw_free = azx_pcm_hw_free,
1606         .prepare = azx_pcm_prepare,
1607         .trigger = azx_pcm_trigger,
1608         .pointer = azx_pcm_pointer,
1609         .page = snd_pcm_sgbuf_ops_page,
1610 };
1611
1612 static void azx_pcm_free(struct snd_pcm *pcm)
1613 {
1614         kfree(pcm->private_data);
1615 }
1616
1617 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1618                                       struct hda_pcm *cpcm)
1619 {
1620         int err;
1621         struct snd_pcm *pcm;
1622         struct azx_pcm *apcm;
1623
1624         /* if no substreams are defined for both playback and capture,
1625          * it's just a placeholder.  ignore it.
1626          */
1627         if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1628                 return 0;
1629
1630         snd_assert(cpcm->name, return -EINVAL);
1631
1632         err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1633                           cpcm->stream[0].substreams,
1634                           cpcm->stream[1].substreams,
1635                           &pcm);
1636         if (err < 0)
1637                 return err;
1638         strcpy(pcm->name, cpcm->name);
1639         apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1640         if (apcm == NULL)
1641                 return -ENOMEM;
1642         apcm->chip = chip;
1643         apcm->codec = codec;
1644         apcm->hinfo[0] = &cpcm->stream[0];
1645         apcm->hinfo[1] = &cpcm->stream[1];
1646         pcm->private_data = apcm;
1647         pcm->private_free = azx_pcm_free;
1648         if (cpcm->stream[0].substreams)
1649                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1650         if (cpcm->stream[1].substreams)
1651                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1652         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1653                                               snd_dma_pci_data(chip->pci),
1654                                               1024 * 64, 1024 * 1024);
1655         chip->pcm[cpcm->device] = pcm;
1656         return 0;
1657 }
1658
1659 static int __devinit azx_pcm_create(struct azx *chip)
1660 {
1661         static const char *dev_name[HDA_PCM_NTYPES] = {
1662                 "Audio", "SPDIF", "HDMI", "Modem"
1663         };
1664         /* starting device index for each PCM type */
1665         static int dev_idx[HDA_PCM_NTYPES] = {
1666                 [HDA_PCM_TYPE_AUDIO] = 0,
1667                 [HDA_PCM_TYPE_SPDIF] = 1,
1668                 [HDA_PCM_TYPE_HDMI] = 3,
1669                 [HDA_PCM_TYPE_MODEM] = 6
1670         };
1671         /* normal audio device indices; not linear to keep compatibility */
1672         static int audio_idx[4] = { 0, 2, 4, 5 };
1673         struct hda_codec *codec;
1674         int c, err;
1675         int num_devs[HDA_PCM_NTYPES];
1676
1677         err = snd_hda_build_pcms(chip->bus);
1678         if (err < 0)
1679                 return err;
1680
1681         /* create audio PCMs */
1682         memset(num_devs, 0, sizeof(num_devs));
1683         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1684                 for (c = 0; c < codec->num_pcms; c++) {
1685                         struct hda_pcm *cpcm = &codec->pcm_info[c];
1686                         int type = cpcm->pcm_type;
1687                         switch (type) {
1688                         case HDA_PCM_TYPE_AUDIO:
1689                                 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1690                                         snd_printk(KERN_WARNING
1691                                                    "Too many audio devices\n");
1692                                         continue;
1693                                 }
1694                                 cpcm->device = audio_idx[num_devs[type]];
1695                                 break;
1696                         case HDA_PCM_TYPE_SPDIF:
1697                         case HDA_PCM_TYPE_HDMI:
1698                         case HDA_PCM_TYPE_MODEM:
1699                                 if (num_devs[type]) {
1700                                         snd_printk(KERN_WARNING
1701                                                    "%s already defined\n",
1702                                                    dev_name[type]);
1703                                         continue;
1704                                 }
1705                                 cpcm->device = dev_idx[type];
1706                                 break;
1707                         default:
1708                                 snd_printk(KERN_WARNING
1709                                            "Invalid PCM type %d\n", type);
1710                                 continue;
1711                         }
1712                         num_devs[type]++;
1713                         err = create_codec_pcm(chip, codec, cpcm);
1714                         if (err < 0)
1715                                 return err;
1716                 }
1717         }
1718         return 0;
1719 }
1720
1721 /*
1722  * mixer creation - all stuff is implemented in hda module
1723  */
1724 static int __devinit azx_mixer_create(struct azx *chip)
1725 {
1726         return snd_hda_build_controls(chip->bus);
1727 }
1728
1729
1730 /*
1731  * initialize SD streams
1732  */
1733 static int __devinit azx_init_stream(struct azx *chip)
1734 {
1735         int i;
1736
1737         /* initialize each stream (aka device)
1738          * assign the starting bdl address to each stream (device)
1739          * and initialize
1740          */
1741         for (i = 0; i < chip->num_streams; i++) {
1742                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1743                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1744                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1745                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1746                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1747                 azx_dev->sd_int_sta_mask = 1 << i;
1748                 /* stream tag: must be non-zero and unique */
1749                 azx_dev->index = i;
1750                 azx_dev->stream_tag = i + 1;
1751         }
1752
1753         return 0;
1754 }
1755
1756 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1757 {
1758         if (request_irq(chip->pci->irq, azx_interrupt,
1759                         chip->msi ? 0 : IRQF_SHARED,
1760                         "HDA Intel", chip)) {
1761                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1762                        "disabling device\n", chip->pci->irq);
1763                 if (do_disconnect)
1764                         snd_card_disconnect(chip->card);
1765                 return -1;
1766         }
1767         chip->irq = chip->pci->irq;
1768         pci_intx(chip->pci, !chip->msi);
1769         return 0;
1770 }
1771
1772
1773 static void azx_stop_chip(struct azx *chip)
1774 {
1775         if (!chip->initialized)
1776                 return;
1777
1778         /* disable interrupts */
1779         azx_int_disable(chip);
1780         azx_int_clear(chip);
1781
1782         /* disable CORB/RIRB */
1783         azx_free_cmd_io(chip);
1784
1785         /* disable position buffer */
1786         azx_writel(chip, DPLBASE, 0);
1787         azx_writel(chip, DPUBASE, 0);
1788
1789         chip->initialized = 0;
1790 }
1791
1792 #ifdef CONFIG_SND_HDA_POWER_SAVE
1793 /* power-up/down the controller */
1794 static void azx_power_notify(struct hda_codec *codec)
1795 {
1796         struct azx *chip = codec->bus->private_data;
1797         struct hda_codec *c;
1798         int power_on = 0;
1799
1800         list_for_each_entry(c, &codec->bus->codec_list, list) {
1801                 if (c->power_on) {
1802                         power_on = 1;
1803                         break;
1804                 }
1805         }
1806         if (power_on)
1807                 azx_init_chip(chip);
1808         else if (chip->running && power_save_controller)
1809                 azx_stop_chip(chip);
1810 }
1811 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1812
1813 #ifdef CONFIG_PM
1814 /*
1815  * power management
1816  */
1817 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1818 {
1819         struct snd_card *card = pci_get_drvdata(pci);
1820         struct azx *chip = card->private_data;
1821         int i;
1822
1823         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1824         azx_clear_irq_pending(chip);
1825         for (i = 0; i < AZX_MAX_PCMS; i++)
1826                 snd_pcm_suspend_all(chip->pcm[i]);
1827         if (chip->initialized)
1828                 snd_hda_suspend(chip->bus, state);
1829         azx_stop_chip(chip);
1830         if (chip->irq >= 0) {
1831                 free_irq(chip->irq, chip);
1832                 chip->irq = -1;
1833         }
1834         if (chip->msi)
1835                 pci_disable_msi(chip->pci);
1836         pci_disable_device(pci);
1837         pci_save_state(pci);
1838         pci_set_power_state(pci, pci_choose_state(pci, state));
1839         return 0;
1840 }
1841
1842 static int azx_resume(struct pci_dev *pci)
1843 {
1844         struct snd_card *card = pci_get_drvdata(pci);
1845         struct azx *chip = card->private_data;
1846
1847         pci_set_power_state(pci, PCI_D0);
1848         pci_restore_state(pci);
1849         if (pci_enable_device(pci) < 0) {
1850                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1851                        "disabling device\n");
1852                 snd_card_disconnect(card);
1853                 return -EIO;
1854         }
1855         pci_set_master(pci);
1856         if (chip->msi)
1857                 if (pci_enable_msi(pci) < 0)
1858                         chip->msi = 0;
1859         if (azx_acquire_irq(chip, 1) < 0)
1860                 return -EIO;
1861         azx_init_pci(chip);
1862
1863         if (snd_hda_codecs_inuse(chip->bus))
1864                 azx_init_chip(chip);
1865
1866         snd_hda_resume(chip->bus);
1867         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1868         return 0;
1869 }
1870 #endif /* CONFIG_PM */
1871
1872
1873 /*
1874  * destructor
1875  */
1876 static int azx_free(struct azx *chip)
1877 {
1878         int i;
1879
1880         if (chip->initialized) {
1881                 azx_clear_irq_pending(chip);
1882                 for (i = 0; i < chip->num_streams; i++)
1883                         azx_stream_stop(chip, &chip->azx_dev[i]);
1884                 azx_stop_chip(chip);
1885         }
1886
1887         if (chip->irq >= 0)
1888                 free_irq(chip->irq, (void*)chip);
1889         if (chip->msi)
1890                 pci_disable_msi(chip->pci);
1891         if (chip->remap_addr)
1892                 iounmap(chip->remap_addr);
1893
1894         if (chip->azx_dev) {
1895                 for (i = 0; i < chip->num_streams; i++)
1896                         if (chip->azx_dev[i].bdl.area)
1897                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1898         }
1899         if (chip->rb.area)
1900                 snd_dma_free_pages(&chip->rb);
1901         if (chip->posbuf.area)
1902                 snd_dma_free_pages(&chip->posbuf);
1903         pci_release_regions(chip->pci);
1904         pci_disable_device(chip->pci);
1905         kfree(chip->azx_dev);
1906         kfree(chip);
1907
1908         return 0;
1909 }
1910
1911 static int azx_dev_free(struct snd_device *device)
1912 {
1913         return azx_free(device->device_data);
1914 }
1915
1916 /*
1917  * white/black-listing for position_fix
1918  */
1919 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1920         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1921         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1922         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_NONE),
1923         {}
1924 };
1925
1926 static int __devinit check_position_fix(struct azx *chip, int fix)
1927 {
1928         const struct snd_pci_quirk *q;
1929
1930         if (fix == POS_FIX_AUTO) {
1931                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1932                 if (q) {
1933                         printk(KERN_INFO
1934                                     "hda_intel: position_fix set to %d "
1935                                     "for device %04x:%04x\n",
1936                                     q->value, q->subvendor, q->subdevice);
1937                         return q->value;
1938                 }
1939         }
1940         return fix;
1941 }
1942
1943 /*
1944  * black-lists for probe_mask
1945  */
1946 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1947         /* Thinkpad often breaks the controller communication when accessing
1948          * to the non-working (or non-existing) modem codec slot.
1949          */
1950         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1951         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1952         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1953         {}
1954 };
1955
1956 static void __devinit check_probe_mask(struct azx *chip, int dev)
1957 {
1958         const struct snd_pci_quirk *q;
1959
1960         if (probe_mask[dev] == -1) {
1961                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1962                 if (q) {
1963                         printk(KERN_INFO
1964                                "hda_intel: probe_mask set to 0x%x "
1965                                "for device %04x:%04x\n",
1966                                q->value, q->subvendor, q->subdevice);
1967                         probe_mask[dev] = q->value;
1968                 }
1969         }
1970 }
1971
1972
1973 /*
1974  * constructor
1975  */
1976 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1977                                 int dev, int driver_type,
1978                                 struct azx **rchip)
1979 {
1980         struct azx *chip;
1981         int i, err;
1982         unsigned short gcap;
1983         static struct snd_device_ops ops = {
1984                 .dev_free = azx_dev_free,
1985         };
1986
1987         *rchip = NULL;
1988
1989         err = pci_enable_device(pci);
1990         if (err < 0)
1991                 return err;
1992
1993         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1994         if (!chip) {
1995                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1996                 pci_disable_device(pci);
1997                 return -ENOMEM;
1998         }
1999
2000         spin_lock_init(&chip->reg_lock);
2001         mutex_init(&chip->open_mutex);
2002         chip->card = card;
2003         chip->pci = pci;
2004         chip->irq = -1;
2005         chip->driver_type = driver_type;
2006         chip->msi = enable_msi;
2007         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2008
2009         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2010         check_probe_mask(chip, dev);
2011
2012         chip->single_cmd = single_cmd;
2013
2014 #if BITS_PER_LONG != 64
2015         /* Fix up base address on ULI M5461 */
2016         if (chip->driver_type == AZX_DRIVER_ULI) {
2017                 u16 tmp3;
2018                 pci_read_config_word(pci, 0x40, &tmp3);
2019                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2020                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2021         }
2022 #endif
2023
2024         err = pci_request_regions(pci, "ICH HD audio");
2025         if (err < 0) {
2026                 kfree(chip);
2027                 pci_disable_device(pci);
2028                 return err;
2029         }
2030
2031         chip->addr = pci_resource_start(pci, 0);
2032         chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
2033         if (chip->remap_addr == NULL) {
2034                 snd_printk(KERN_ERR SFX "ioremap error\n");
2035                 err = -ENXIO;
2036                 goto errout;
2037         }
2038
2039         if (chip->msi)
2040                 if (pci_enable_msi(pci) < 0)
2041                         chip->msi = 0;
2042
2043         if (azx_acquire_irq(chip, 0) < 0) {
2044                 err = -EBUSY;
2045                 goto errout;
2046         }
2047
2048         pci_set_master(pci);
2049         synchronize_irq(chip->irq);
2050
2051         gcap = azx_readw(chip, GCAP);
2052         snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2053
2054         /* allow 64bit DMA address if supported by H/W */
2055         if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2056                 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2057
2058         /* read number of streams from GCAP register instead of using
2059          * hardcoded value
2060          */
2061         chip->capture_streams = (gcap >> 8) & 0x0f;
2062         chip->playback_streams = (gcap >> 12) & 0x0f;
2063         if (!chip->playback_streams && !chip->capture_streams) {
2064                 /* gcap didn't give any info, switching to old method */
2065
2066                 switch (chip->driver_type) {
2067                 case AZX_DRIVER_ULI:
2068                         chip->playback_streams = ULI_NUM_PLAYBACK;
2069                         chip->capture_streams = ULI_NUM_CAPTURE;
2070                         break;
2071                 case AZX_DRIVER_ATIHDMI:
2072                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2073                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2074                         break;
2075                 default:
2076                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2077                         chip->capture_streams = ICH6_NUM_CAPTURE;
2078                         break;
2079                 }
2080         }
2081         chip->capture_index_offset = 0;
2082         chip->playback_index_offset = chip->capture_streams;
2083         chip->num_streams = chip->playback_streams + chip->capture_streams;
2084         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2085                                 GFP_KERNEL);
2086         if (!chip->azx_dev) {
2087                 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2088                 goto errout;
2089         }
2090
2091         for (i = 0; i < chip->num_streams; i++) {
2092                 /* allocate memory for the BDL for each stream */
2093                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2094                                           snd_dma_pci_data(chip->pci),
2095                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2096                 if (err < 0) {
2097                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2098                         goto errout;
2099                 }
2100         }
2101         /* allocate memory for the position buffer */
2102         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2103                                   snd_dma_pci_data(chip->pci),
2104                                   chip->num_streams * 8, &chip->posbuf);
2105         if (err < 0) {
2106                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2107                 goto errout;
2108         }
2109         /* allocate CORB/RIRB */
2110         if (!chip->single_cmd) {
2111                 err = azx_alloc_cmd_io(chip);
2112                 if (err < 0)
2113                         goto errout;
2114         }
2115
2116         /* initialize streams */
2117         azx_init_stream(chip);
2118
2119         /* initialize chip */
2120         azx_init_pci(chip);
2121         azx_init_chip(chip);
2122
2123         /* codec detection */
2124         if (!chip->codec_mask) {
2125                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2126                 err = -ENODEV;
2127                 goto errout;
2128         }
2129
2130         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2131         if (err <0) {
2132                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2133                 goto errout;
2134         }
2135
2136         strcpy(card->driver, "HDA-Intel");
2137         strcpy(card->shortname, driver_short_names[chip->driver_type]);
2138         sprintf(card->longname, "%s at 0x%lx irq %i",
2139                 card->shortname, chip->addr, chip->irq);
2140
2141         *rchip = chip;
2142         return 0;
2143
2144  errout:
2145         azx_free(chip);
2146         return err;
2147 }
2148
2149 static void power_down_all_codecs(struct azx *chip)
2150 {
2151 #ifdef CONFIG_SND_HDA_POWER_SAVE
2152         /* The codecs were powered up in snd_hda_codec_new().
2153          * Now all initialization done, so turn them down if possible
2154          */
2155         struct hda_codec *codec;
2156         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2157                 snd_hda_power_down(codec);
2158         }
2159 #endif
2160 }
2161
2162 static int __devinit azx_probe(struct pci_dev *pci,
2163                                const struct pci_device_id *pci_id)
2164 {
2165         static int dev;
2166         struct snd_card *card;
2167         struct azx *chip;
2168         int err;
2169
2170         if (dev >= SNDRV_CARDS)
2171                 return -ENODEV;
2172         if (!enable[dev]) {
2173                 dev++;
2174                 return -ENOENT;
2175         }
2176
2177         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2178         if (!card) {
2179                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2180                 return -ENOMEM;
2181         }
2182
2183         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2184         if (err < 0) {
2185                 snd_card_free(card);
2186                 return err;
2187         }
2188         card->private_data = chip;
2189
2190         /* create codec instances */
2191         err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2192         if (err < 0) {
2193                 snd_card_free(card);
2194                 return err;
2195         }
2196
2197         /* create PCM streams */
2198         err = azx_pcm_create(chip);
2199         if (err < 0) {
2200                 snd_card_free(card);
2201                 return err;
2202         }
2203
2204         /* create mixer controls */
2205         err = azx_mixer_create(chip);
2206         if (err < 0) {
2207                 snd_card_free(card);
2208                 return err;
2209         }
2210
2211         snd_card_set_dev(card, &pci->dev);
2212
2213         err = snd_card_register(card);
2214         if (err < 0) {
2215                 snd_card_free(card);
2216                 return err;
2217         }
2218
2219         pci_set_drvdata(pci, card);
2220         chip->running = 1;
2221         power_down_all_codecs(chip);
2222
2223         dev++;
2224         return err;
2225 }
2226
2227 static void __devexit azx_remove(struct pci_dev *pci)
2228 {
2229         snd_card_free(pci_get_drvdata(pci));
2230         pci_set_drvdata(pci, NULL);
2231 }
2232
2233 /* PCI IDs */
2234 static struct pci_device_id azx_ids[] = {
2235         /* ICH 6..10 */
2236         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2237         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2238         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2239         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2240         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2241         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2242         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2243         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2244         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2245         /* SCH */
2246         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2247         /* ATI SB 450/600 */
2248         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2249         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2250         /* ATI HDMI */
2251         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2252         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2253         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2254         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2255         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2256         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2257         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2258         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2259         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2260         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2261         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2262         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2263         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2264         /* VIA VT8251/VT8237A */
2265         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2266         /* SIS966 */
2267         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2268         /* ULI M5461 */
2269         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2270         /* NVIDIA MCP */
2271         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2272         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2273         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2274         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2275         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2276         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2277         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2278         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2279         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2280         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2281         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2282         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2283         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2284         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2285         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2286         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2287         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2288         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2289         { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2290         { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2291         { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2292         { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2293         /* Teradici */
2294         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2295         { 0, }
2296 };
2297 MODULE_DEVICE_TABLE(pci, azx_ids);
2298
2299 /* pci_driver definition */
2300 static struct pci_driver driver = {
2301         .name = "HDA Intel",
2302         .id_table = azx_ids,
2303         .probe = azx_probe,
2304         .remove = __devexit_p(azx_remove),
2305 #ifdef CONFIG_PM
2306         .suspend = azx_suspend,
2307         .resume = azx_resume,
2308 #endif
2309 };
2310
2311 static int __init alsa_card_azx_init(void)
2312 {
2313         return pci_register_driver(&driver);
2314 }
2315
2316 static void __exit alsa_card_azx_exit(void)
2317 {
2318         pci_unregister_driver(&driver);
2319 }
2320
2321 module_init(alsa_card_azx_init)
2322 module_exit(alsa_card_azx_exit)