2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@ru.mvista.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_set_endpoint(codec, "MONO_LOUT", 0), etc.
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
49 #include "tlv320aic3x.h"
51 #define AUDIO_NAME "aic3x"
52 #define AIC3X_VERSION "0.2"
54 /* codec private data */
61 * AIC3X register cache
62 * We can't read the AIC3X register space when we are
63 * using 2 wire for device control, so we cache them instead.
64 * There is no point in caching the reset register
66 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
67 0x00, 0x00, 0x00, 0x10, /* 0 */
68 0x04, 0x00, 0x00, 0x00, /* 4 */
69 0x00, 0x00, 0x00, 0x01, /* 8 */
70 0x00, 0x00, 0x00, 0x80, /* 12 */
71 0x80, 0xff, 0xff, 0x78, /* 16 */
72 0x78, 0x78, 0x78, 0x78, /* 20 */
73 0x78, 0x00, 0x00, 0xfe, /* 24 */
74 0x00, 0x00, 0xfe, 0x00, /* 28 */
75 0x18, 0x18, 0x00, 0x00, /* 32 */
76 0x00, 0x00, 0x00, 0x00, /* 36 */
77 0x00, 0x00, 0x00, 0x80, /* 40 */
78 0x80, 0x00, 0x00, 0x00, /* 44 */
79 0x00, 0x00, 0x00, 0x04, /* 48 */
80 0x00, 0x00, 0x00, 0x00, /* 52 */
81 0x00, 0x00, 0x04, 0x00, /* 56 */
82 0x00, 0x00, 0x00, 0x00, /* 60 */
83 0x00, 0x04, 0x00, 0x00, /* 64 */
84 0x00, 0x00, 0x00, 0x00, /* 68 */
85 0x04, 0x00, 0x00, 0x00, /* 72 */
86 0x00, 0x00, 0x00, 0x00, /* 76 */
87 0x00, 0x00, 0x00, 0x00, /* 80 */
88 0x00, 0x00, 0x00, 0x00, /* 84 */
89 0x00, 0x00, 0x00, 0x00, /* 88 */
90 0x00, 0x00, 0x00, 0x00, /* 92 */
91 0x00, 0x00, 0x00, 0x00, /* 96 */
92 0x00, 0x00, 0x02, /* 100 */
96 * read aic3x register cache
98 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
101 u8 *cache = codec->reg_cache;
102 if (reg >= AIC3X_CACHEREGNUM)
108 * write aic3x register cache
110 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
113 u8 *cache = codec->reg_cache;
114 if (reg >= AIC3X_CACHEREGNUM)
120 * write to the aic3x register space
122 static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
128 * D15..D8 aic3x register offset
129 * D7...D0 register data
131 data[0] = reg & 0xff;
132 data[1] = value & 0xff;
134 aic3x_write_reg_cache(codec, data[0], data[1]);
135 if (codec->hw_write(codec->control_data, data, 2) == 2)
142 * read from the aic3x register space
144 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
148 if (codec->hw_read(codec->control_data, value, 1) != 1)
151 aic3x_write_reg_cache(codec, reg, *value);
155 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
156 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
157 .info = snd_soc_info_volsw, \
158 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
159 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
162 * All input lines are connected when !0xf and disconnected with 0xf bit field,
163 * so we have to use specific dapm_put call for input mixer
165 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
166 struct snd_ctl_elem_value *ucontrol)
168 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
169 int reg = kcontrol->private_value & 0xff;
170 int shift = (kcontrol->private_value >> 8) & 0x0f;
171 int mask = (kcontrol->private_value >> 16) & 0xff;
172 int invert = (kcontrol->private_value >> 24) & 0x01;
173 unsigned short val, val_mask;
175 struct snd_soc_dapm_path *path;
178 val = (ucontrol->value.integer.value[0] & mask);
186 val_mask = mask << shift;
189 mutex_lock(&widget->codec->mutex);
191 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
192 /* find dapm widget path assoc with kcontrol */
193 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
194 if (path->kcontrol != kcontrol)
197 /* found, now check type */
201 path->connect = invert ? 0 : 1;
203 /* old connection must be powered down */
204 path->connect = invert ? 1 : 0;
209 snd_soc_dapm_sync_endpoints(widget->codec);
212 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
214 mutex_unlock(&widget->codec->mutex);
218 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
219 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
220 static const char *aic3x_left_hpcom_mux[] =
221 { "differential of HPLOUT", "constant VCM", "single-ended" };
222 static const char *aic3x_right_hpcom_mux[] =
223 { "differential of HPROUT", "constant VCM", "single-ended",
224 "differential of HPLCOM", "external feedback" };
225 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
229 #define LHPCOM_ENUM 2
230 #define RHPCOM_ENUM 3
231 #define LINE1L_ENUM 4
232 #define LINE1R_ENUM 5
233 #define LINE2L_ENUM 6
234 #define LINE2R_ENUM 7
236 static const struct soc_enum aic3x_enum[] = {
237 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
238 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
239 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
240 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
241 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
242 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
243 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
244 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
247 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
249 SOC_DOUBLE_R("PCM Playback Volume", LDAC_VOL, RDAC_VOL, 0, 0x7f, 1),
251 SOC_DOUBLE_R("Line DAC Playback Volume", DACL1_2_LLOPM_VOL,
252 DACR1_2_RLOPM_VOL, 0, 0x7f, 1),
253 SOC_DOUBLE_R("Line DAC Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
255 SOC_DOUBLE_R("Line PGA Bypass Playback Volume", PGAL_2_LLOPM_VOL,
256 PGAR_2_RLOPM_VOL, 0, 0x7f, 1),
257 SOC_DOUBLE_R("Line Line2 Bypass Playback Volume", LINE2L_2_LLOPM_VOL,
258 LINE2R_2_RLOPM_VOL, 0, 0x7f, 1),
260 SOC_DOUBLE_R("Mono DAC Playback Volume", DACL1_2_MONOLOPM_VOL,
261 DACR1_2_MONOLOPM_VOL, 0, 0x7f, 1),
262 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
263 SOC_DOUBLE_R("Mono PGA Bypass Playback Volume", PGAL_2_MONOLOPM_VOL,
264 PGAR_2_MONOLOPM_VOL, 0, 0x7f, 1),
265 SOC_DOUBLE_R("Mono Line2 Bypass Playback Volume", LINE2L_2_MONOLOPM_VOL,
266 LINE2R_2_MONOLOPM_VOL, 0, 0x7f, 1),
268 SOC_DOUBLE_R("HP DAC Playback Volume", DACL1_2_HPLOUT_VOL,
269 DACR1_2_HPROUT_VOL, 0, 0x7f, 1),
270 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
272 SOC_DOUBLE_R("HP PGA Bypass Playback Volume", PGAL_2_HPLOUT_VOL,
273 PGAR_2_HPROUT_VOL, 0, 0x7f, 1),
274 SOC_DOUBLE_R("HP Line2 Bypass Playback Volume", LINE2L_2_HPLOUT_VOL,
275 LINE2R_2_HPROUT_VOL, 0, 0x7f, 1),
277 SOC_DOUBLE_R("HPCOM DAC Playback Volume", DACL1_2_HPLCOM_VOL,
278 DACR1_2_HPRCOM_VOL, 0, 0x7f, 1),
279 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
281 SOC_DOUBLE_R("HPCOM PGA Bypass Playback Volume", PGAL_2_HPLCOM_VOL,
282 PGAR_2_HPRCOM_VOL, 0, 0x7f, 1),
283 SOC_DOUBLE_R("HPCOM Line2 Bypass Playback Volume", LINE2L_2_HPLCOM_VOL,
284 LINE2R_2_HPRCOM_VOL, 0, 0x7f, 1),
287 * Note: enable Automatic input Gain Controller with care. It can
288 * adjust PGA to max value when ADC is on and will never go back.
290 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
293 SOC_DOUBLE_R("PGA Capture Volume", LADC_VOL, RADC_VOL, 0, 0x7f, 0),
294 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
297 /* add non dapm controls */
298 static int aic3x_add_controls(struct snd_soc_codec *codec)
302 for (i = 0; i < ARRAY_SIZE(aic3x_snd_controls); i++) {
303 err = snd_ctl_add(codec->card,
304 snd_soc_cnew(&aic3x_snd_controls[i],
314 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
315 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
318 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
319 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
322 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
323 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
325 /* Right HPCOM Mux */
326 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
327 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
329 /* Left DAC_L1 Mixer */
330 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
331 SOC_DAPM_SINGLE("Line Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
332 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
333 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
334 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
337 /* Right DAC_R1 Mixer */
338 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
339 SOC_DAPM_SINGLE("Line Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
340 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
341 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
342 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
346 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
347 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
348 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
349 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
352 /* Right PGA Mixer */
353 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
354 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
355 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
356 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
360 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
361 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
363 /* Right Line1 Mux */
364 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
365 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
368 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
369 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
371 /* Right Line2 Mux */
372 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
373 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
375 /* Left PGA Bypass Mixer */
376 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
377 SOC_DAPM_SINGLE("Line Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
378 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
379 SOC_DAPM_SINGLE("HP Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
380 SOC_DAPM_SINGLE("HPCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
383 /* Right PGA Bypass Mixer */
384 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
385 SOC_DAPM_SINGLE("Line Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
386 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
387 SOC_DAPM_SINGLE("HP Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
388 SOC_DAPM_SINGLE("HPCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
391 /* Left Line2 Bypass Mixer */
392 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
393 SOC_DAPM_SINGLE("Line Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
394 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
395 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
396 SOC_DAPM_SINGLE("HPCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
399 /* Right Line2 Bypass Mixer */
400 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
401 SOC_DAPM_SINGLE("Line Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
402 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
403 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
404 SOC_DAPM_SINGLE("HPCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
407 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
408 /* Left DAC to Left Outputs */
409 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
410 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
411 &aic3x_left_dac_mux_controls),
412 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
413 &aic3x_left_dac_mixer_controls[0],
414 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
415 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
416 &aic3x_left_hpcom_mux_controls),
417 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
418 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
419 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
421 /* Right DAC to Right Outputs */
422 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
423 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
424 &aic3x_right_dac_mux_controls),
425 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
426 &aic3x_right_dac_mixer_controls[0],
427 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
428 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
429 &aic3x_right_hpcom_mux_controls),
430 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
431 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
432 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
435 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
437 /* Left Inputs to Left ADC */
438 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
439 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
440 &aic3x_left_pga_mixer_controls[0],
441 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
442 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
443 &aic3x_left_line1_mux_controls),
444 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
445 &aic3x_left_line2_mux_controls),
447 /* Right Inputs to Right ADC */
448 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
449 LINE1R_2_RADC_CTRL, 2, 0),
450 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
451 &aic3x_right_pga_mixer_controls[0],
452 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
453 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
454 &aic3x_right_line1_mux_controls),
455 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
456 &aic3x_right_line2_mux_controls),
459 * Not a real mic bias widget but similar function. This is for dynamic
460 * control of GPIO1 digital mic modulator clock output function when
463 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
464 AIC3X_GPIO1_REG, 4, 0xf,
465 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
466 AIC3X_GPIO1_FUNC_DISABLED),
469 * Also similar function like mic bias. Selects digital mic with
470 * configurable oversampling rate instead of ADC converter.
472 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
473 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
474 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
475 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
476 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
477 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
480 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
481 MICBIAS_CTRL, 6, 3, 1, 0),
482 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
483 MICBIAS_CTRL, 6, 3, 2, 0),
484 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
485 MICBIAS_CTRL, 6, 3, 3, 0),
487 /* Left PGA to Left Output bypass */
488 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
489 &aic3x_left_pga_bp_mixer_controls[0],
490 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
492 /* Right PGA to Right Output bypass */
493 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
494 &aic3x_right_pga_bp_mixer_controls[0],
495 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
497 /* Left Line2 to Left Output bypass */
498 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
499 &aic3x_left_line2_bp_mixer_controls[0],
500 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
502 /* Right Line2 to Right Output bypass */
503 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
504 &aic3x_right_line2_bp_mixer_controls[0],
505 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
507 SND_SOC_DAPM_OUTPUT("LLOUT"),
508 SND_SOC_DAPM_OUTPUT("RLOUT"),
509 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
510 SND_SOC_DAPM_OUTPUT("HPLOUT"),
511 SND_SOC_DAPM_OUTPUT("HPROUT"),
512 SND_SOC_DAPM_OUTPUT("HPLCOM"),
513 SND_SOC_DAPM_OUTPUT("HPRCOM"),
515 SND_SOC_DAPM_INPUT("MIC3L"),
516 SND_SOC_DAPM_INPUT("MIC3R"),
517 SND_SOC_DAPM_INPUT("LINE1L"),
518 SND_SOC_DAPM_INPUT("LINE1R"),
519 SND_SOC_DAPM_INPUT("LINE2L"),
520 SND_SOC_DAPM_INPUT("LINE2R"),
523 static const struct snd_soc_dapm_route intercon[] = {
525 {"Left DAC Mux", "DAC_L1", "Left DAC"},
526 {"Left DAC Mux", "DAC_L2", "Left DAC"},
527 {"Left DAC Mux", "DAC_L3", "Left DAC"},
529 {"Left DAC_L1 Mixer", "Line Switch", "Left DAC Mux"},
530 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
531 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
532 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
533 {"Left Line Out", NULL, "Left DAC Mux"},
534 {"Left HP Out", NULL, "Left DAC Mux"},
536 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
537 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
538 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
540 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
541 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
542 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
543 {"Left HP Com", NULL, "Left HPCOM Mux"},
545 {"LLOUT", NULL, "Left Line Out"},
546 {"LLOUT", NULL, "Left Line Out"},
547 {"HPLOUT", NULL, "Left HP Out"},
548 {"HPLCOM", NULL, "Left HP Com"},
551 {"Right DAC Mux", "DAC_R1", "Right DAC"},
552 {"Right DAC Mux", "DAC_R2", "Right DAC"},
553 {"Right DAC Mux", "DAC_R3", "Right DAC"},
555 {"Right DAC_R1 Mixer", "Line Switch", "Right DAC Mux"},
556 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
557 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
558 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
559 {"Right Line Out", NULL, "Right DAC Mux"},
560 {"Right HP Out", NULL, "Right DAC Mux"},
562 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
563 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
564 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
565 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
566 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
568 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
569 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
570 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
571 {"Right HP Com", NULL, "Right HPCOM Mux"},
573 {"RLOUT", NULL, "Right Line Out"},
574 {"RLOUT", NULL, "Right Line Out"},
575 {"HPROUT", NULL, "Right HP Out"},
576 {"HPRCOM", NULL, "Right HP Com"},
579 {"MONO_LOUT", NULL, "Mono Out"},
580 {"MONO_LOUT", NULL, "Mono Out"},
583 {"Left Line1L Mux", "single-ended", "LINE1L"},
584 {"Left Line1L Mux", "differential", "LINE1L"},
586 {"Left Line2L Mux", "single-ended", "LINE2L"},
587 {"Left Line2L Mux", "differential", "LINE2L"},
589 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
590 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
591 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
593 {"Left ADC", NULL, "Left PGA Mixer"},
594 {"Left ADC", NULL, "GPIO1 dmic modclk"},
597 {"Right Line1R Mux", "single-ended", "LINE1R"},
598 {"Right Line1R Mux", "differential", "LINE1R"},
600 {"Right Line2R Mux", "single-ended", "LINE2R"},
601 {"Right Line2R Mux", "differential", "LINE2R"},
603 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
604 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
605 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
607 {"Right ADC", NULL, "Right PGA Mixer"},
608 {"Right ADC", NULL, "GPIO1 dmic modclk"},
610 /* Left PGA Bypass */
611 {"Left PGA Bypass Mixer", "Line Switch", "Left PGA Mixer"},
612 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
613 {"Left PGA Bypass Mixer", "HP Switch", "Left PGA Mixer"},
614 {"Left PGA Bypass Mixer", "HPCOM Switch", "Left PGA Mixer"},
616 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
617 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
618 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
620 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
621 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
622 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
624 /* Right PGA Bypass */
625 {"Right PGA Bypass Mixer", "Line Switch", "Right PGA Mixer"},
626 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
627 {"Right PGA Bypass Mixer", "HP Switch", "Right PGA Mixer"},
628 {"Right PGA Bypass Mixer", "HPCOM Switch", "Right PGA Mixer"},
630 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
631 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
632 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
633 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
634 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
636 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
637 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
638 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
640 /* Left Line2 Bypass */
641 {"Left Line2 Bypass Mixer", "Line Switch", "Left Line2L Mux"},
642 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
643 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
644 {"Left Line2 Bypass Mixer", "HPCOM Switch", "Left Line2L Mux"},
646 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
647 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
648 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
650 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
651 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
652 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
654 /* Right Line2 Bypass */
655 {"Right Line2 Bypass Mixer", "Line Switch", "Right Line2R Mux"},
656 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
657 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
658 {"Right Line2 Bypass Mixer", "HPCOM Switch", "Right Line2R Mux"},
660 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
661 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
662 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
663 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
664 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
666 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
667 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
668 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
671 * Logical path between digital mic enable and GPIO1 modulator clock
674 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
675 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
676 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
679 static int aic3x_add_widgets(struct snd_soc_codec *codec)
681 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
682 ARRAY_SIZE(aic3x_dapm_widgets));
684 /* set up audio path interconnects */
685 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
687 snd_soc_dapm_new_widgets(codec);
691 static int aic3x_hw_params(struct snd_pcm_substream *substream,
692 struct snd_pcm_hw_params *params)
694 struct snd_soc_pcm_runtime *rtd = substream->private_data;
695 struct snd_soc_device *socdev = rtd->socdev;
696 struct snd_soc_codec *codec = socdev->codec;
697 struct aic3x_priv *aic3x = codec->private_data;
698 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
699 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
702 /* select data word length */
704 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
705 switch (params_format(params)) {
706 case SNDRV_PCM_FORMAT_S16_LE:
708 case SNDRV_PCM_FORMAT_S20_3LE:
711 case SNDRV_PCM_FORMAT_S24_LE:
714 case SNDRV_PCM_FORMAT_S32_LE:
718 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
720 /* Fsref can be 44100 or 48000 */
721 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
723 /* Try to find a value for Q which allows us to bypass the PLL and
724 * generate CODEC_CLK directly. */
725 for (pll_q = 2; pll_q < 18; pll_q++)
726 if (aic3x->sysclk / (128 * pll_q) == fsref) {
733 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
734 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
736 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
738 /* Route Left DAC to left channel input and
739 * right DAC to right channel input */
740 data = (LDAC2LCH | RDAC2RCH);
741 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
742 if (params_rate(params) >= 64000)
743 data |= DUAL_RATE_MODE;
744 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
746 /* codec sample rate select */
747 data = (fsref * 20) / params_rate(params);
748 if (params_rate(params) < 64000)
753 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
759 * find an apropriate setup for j, d, r and p by iterating over
760 * p and r - j and d are calculated for each fraction.
761 * Up to 128 values are probed, the closest one wins the game.
762 * The sysclk is divided by 1000 to prevent integer overflows.
764 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
766 for (r = 1; r <= 16; r++)
767 for (p = 1; p <= 8; p++) {
768 int clk, tmp = (codec_clk * pll_r * 10) / pll_p;
775 if (d != 0 && aic3x->sysclk < 10000000)
778 /* This is actually 1000 * ((j + (d/10000)) * r) / p
779 * The term had to be converted to get rid of the
780 * division by 10000 */
781 clk = ((10000 * j * r) + (d * r)) / (10 * p);
783 /* check whether this values get closer than the best
784 * ones we had before */
785 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
786 pll_j = j; pll_d = d; pll_r = r; pll_p = p;
790 /* Early exit for exact matches */
791 if (clk == codec_clk)
796 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
800 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
801 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
802 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
803 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
804 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
805 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
806 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
811 static int aic3x_mute(struct snd_soc_codec_dai *dai, int mute)
813 struct snd_soc_codec *codec = dai->codec;
814 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
815 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
818 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
819 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
821 aic3x_write(codec, LDAC_VOL, ldac_reg);
822 aic3x_write(codec, RDAC_VOL, rdac_reg);
828 static int aic3x_set_dai_sysclk(struct snd_soc_codec_dai *codec_dai,
829 int clk_id, unsigned int freq, int dir)
831 struct snd_soc_codec *codec = codec_dai->codec;
832 struct aic3x_priv *aic3x = codec->private_data;
834 aic3x->sysclk = freq;
838 static int aic3x_set_dai_fmt(struct snd_soc_codec_dai *codec_dai,
841 struct snd_soc_codec *codec = codec_dai->codec;
842 struct aic3x_priv *aic3x = codec->private_data;
843 u8 iface_areg, iface_breg;
845 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
846 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
848 /* set master/slave audio interface */
849 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
850 case SND_SOC_DAIFMT_CBM_CFM:
852 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
854 case SND_SOC_DAIFMT_CBS_CFS:
861 /* interface format */
862 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
863 case SND_SOC_DAIFMT_I2S:
865 case SND_SOC_DAIFMT_DSP_A:
866 iface_breg |= (0x01 << 6);
868 case SND_SOC_DAIFMT_RIGHT_J:
869 iface_breg |= (0x02 << 6);
871 case SND_SOC_DAIFMT_LEFT_J:
872 iface_breg |= (0x03 << 6);
879 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
880 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
885 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
886 enum snd_soc_bias_level level)
888 struct aic3x_priv *aic3x = codec->private_data;
892 case SND_SOC_BIAS_ON:
893 /* all power is driven by DAPM system */
896 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
897 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
901 case SND_SOC_BIAS_PREPARE:
903 case SND_SOC_BIAS_STANDBY:
905 * all power is driven by DAPM system,
906 * so output power is safe if bypass was set
910 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
911 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
915 case SND_SOC_BIAS_OFF:
916 /* force all power off */
917 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
918 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
919 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
920 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
922 reg = aic3x_read_reg_cache(codec, DAC_PWR);
923 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
925 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
926 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
927 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
928 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
930 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
931 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
932 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
933 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
935 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
936 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
938 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
939 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
940 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
941 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
945 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
946 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
951 codec->bias_level = level;
956 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
958 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
959 u8 bit = gpio ? 3: 0;
960 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
961 aic3x_write(codec, reg, val | (!!state << bit));
963 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
965 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
967 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
968 u8 val, bit = gpio ? 2: 1;
970 aic3x_read(codec, reg, &val);
971 return (val >> bit) & 1;
973 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
975 int aic3x_headset_detected(struct snd_soc_codec *codec)
978 aic3x_read(codec, AIC3X_RT_IRQ_FLAGS_REG, &val);
979 return (val >> 2) & 1;
981 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
983 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
984 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
985 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
987 struct snd_soc_codec_dai aic3x_dai = {
990 .stream_name = "Playback",
993 .rates = AIC3X_RATES,
994 .formats = AIC3X_FORMATS,},
996 .stream_name = "Capture",
999 .rates = AIC3X_RATES,
1000 .formats = AIC3X_FORMATS,},
1002 .hw_params = aic3x_hw_params,
1005 .digital_mute = aic3x_mute,
1006 .set_sysclk = aic3x_set_dai_sysclk,
1007 .set_fmt = aic3x_set_dai_fmt,
1010 EXPORT_SYMBOL_GPL(aic3x_dai);
1012 static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
1014 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1015 struct snd_soc_codec *codec = socdev->codec;
1017 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1022 static int aic3x_resume(struct platform_device *pdev)
1024 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1025 struct snd_soc_codec *codec = socdev->codec;
1028 u8 *cache = codec->reg_cache;
1030 /* Sync reg_cache with the hardware */
1031 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1034 codec->hw_write(codec->control_data, data, 2);
1037 aic3x_set_bias_level(codec, codec->suspend_bias_level);
1043 * initialise the AIC3X driver
1044 * register the mixer and dsp interfaces with the kernel
1046 static int aic3x_init(struct snd_soc_device *socdev)
1048 struct snd_soc_codec *codec = socdev->codec;
1049 struct aic3x_setup_data *setup = socdev->codec_data;
1052 codec->name = "aic3x";
1053 codec->owner = THIS_MODULE;
1054 codec->read = aic3x_read_reg_cache;
1055 codec->write = aic3x_write;
1056 codec->set_bias_level = aic3x_set_bias_level;
1057 codec->dai = &aic3x_dai;
1059 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
1060 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1061 if (codec->reg_cache == NULL)
1064 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1065 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1068 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1070 printk(KERN_ERR "aic3x: failed to create pcms\n");
1074 /* DAC default volume and mute */
1075 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1076 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1078 /* DAC to HP default volume and route to Output mixer */
1079 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1080 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1081 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1082 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1083 /* DAC to Line Out default volume and route to Output mixer */
1084 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1085 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1086 /* DAC to Mono Line Out default volume and route to Output mixer */
1087 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1088 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1090 /* unmute all outputs */
1091 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1092 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1093 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1094 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1095 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1096 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1097 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1098 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1099 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1100 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1101 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1102 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1103 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1104 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1106 /* ADC default volume and unmute */
1107 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1108 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1109 /* By default route Line1 to ADC PGA mixer */
1110 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1111 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1113 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1114 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1115 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1116 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1117 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1118 /* PGA to Line Out default volume, disconnect from Output Mixer */
1119 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1120 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1121 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1122 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1123 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1125 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1126 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1127 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1128 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1129 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1130 /* Line2 Line Out default volume, disconnect from Output Mixer */
1131 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1132 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1133 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1134 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1135 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1137 /* off, with power on */
1138 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1140 /* setup GPIO functions */
1141 aic3x_write(codec, AIC3X_GPIO1_REG, (setup->gpio_func[0] & 0xf) << 4);
1142 aic3x_write(codec, AIC3X_GPIO2_REG, (setup->gpio_func[1] & 0xf) << 4);
1144 aic3x_add_controls(codec);
1145 aic3x_add_widgets(codec);
1146 ret = snd_soc_register_card(socdev);
1148 printk(KERN_ERR "aic3x: failed to register card\n");
1155 snd_soc_free_pcms(socdev);
1156 snd_soc_dapm_free(socdev);
1158 kfree(codec->reg_cache);
1162 static struct snd_soc_device *aic3x_socdev;
1164 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1166 * AIC3X 2 wire address can be up to 4 devices with device addresses
1167 * 0x18, 0x19, 0x1A, 0x1B
1169 static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END };
1171 /* Magic definition of all other variables and things */
1174 static struct i2c_driver aic3x_i2c_driver;
1175 static struct i2c_client client_template;
1178 * If the i2c layer weren't so broken, we could pass this kind of data
1181 static int aic3x_codec_probe(struct i2c_adapter *adap, int addr, int kind)
1183 struct snd_soc_device *socdev = aic3x_socdev;
1184 struct aic3x_setup_data *setup = socdev->codec_data;
1185 struct snd_soc_codec *codec = socdev->codec;
1186 struct i2c_client *i2c;
1189 if (addr != setup->i2c_address)
1192 client_template.adapter = adap;
1193 client_template.addr = addr;
1195 i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL);
1200 i2c_set_clientdata(i2c, codec);
1201 codec->control_data = i2c;
1203 ret = i2c_attach_client(i2c);
1205 printk(KERN_ERR "aic3x: failed to attach codec at addr %x\n",
1210 ret = aic3x_init(socdev);
1212 printk(KERN_ERR "aic3x: failed to initialise AIC3X\n");
1223 static int aic3x_i2c_detach(struct i2c_client *client)
1225 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1226 i2c_detach_client(client);
1227 kfree(codec->reg_cache);
1232 static int aic3x_i2c_attach(struct i2c_adapter *adap)
1234 return i2c_probe(adap, &addr_data, aic3x_codec_probe);
1237 /* machine i2c codec control layer */
1238 static struct i2c_driver aic3x_i2c_driver = {
1240 .name = "aic3x I2C Codec",
1241 .owner = THIS_MODULE,
1243 .attach_adapter = aic3x_i2c_attach,
1244 .detach_client = aic3x_i2c_detach,
1247 static struct i2c_client client_template = {
1249 .driver = &aic3x_i2c_driver,
1252 static int aic3x_i2c_read(struct i2c_client *client, u8 *value, int len)
1254 value[0] = i2c_smbus_read_byte_data(client, value[0]);
1259 static int aic3x_probe(struct platform_device *pdev)
1261 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1262 struct aic3x_setup_data *setup;
1263 struct snd_soc_codec *codec;
1264 struct aic3x_priv *aic3x;
1267 printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION);
1269 setup = socdev->codec_data;
1270 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1274 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1275 if (aic3x == NULL) {
1280 codec->private_data = aic3x;
1281 socdev->codec = codec;
1282 mutex_init(&codec->mutex);
1283 INIT_LIST_HEAD(&codec->dapm_widgets);
1284 INIT_LIST_HEAD(&codec->dapm_paths);
1286 aic3x_socdev = socdev;
1287 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1288 if (setup->i2c_address) {
1289 normal_i2c[0] = setup->i2c_address;
1290 codec->hw_write = (hw_write_t) i2c_master_send;
1291 codec->hw_read = (hw_read_t) aic3x_i2c_read;
1292 ret = i2c_add_driver(&aic3x_i2c_driver);
1294 printk(KERN_ERR "can't add i2c driver");
1297 /* Add other interfaces here */
1302 static int aic3x_remove(struct platform_device *pdev)
1304 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1305 struct snd_soc_codec *codec = socdev->codec;
1307 /* power down chip */
1308 if (codec->control_data)
1309 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1311 snd_soc_free_pcms(socdev);
1312 snd_soc_dapm_free(socdev);
1313 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1314 i2c_del_driver(&aic3x_i2c_driver);
1316 kfree(codec->private_data);
1322 struct snd_soc_codec_device soc_codec_dev_aic3x = {
1323 .probe = aic3x_probe,
1324 .remove = aic3x_remove,
1325 .suspend = aic3x_suspend,
1326 .resume = aic3x_resume,
1328 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1330 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1331 MODULE_AUTHOR("Vladimir Barinov");
1332 MODULE_LICENSE("GPL");