2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
4 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/device.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/initval.h>
31 #include <sound/soc.h>
33 #include <mach/control.h>
35 #include <mach/mcbsp.h>
36 #include "omap-mcbsp.h"
39 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
41 struct omap_mcbsp_data {
43 struct omap_mcbsp_reg_cfg regs;
46 * Flags indicating is the bus already activated and configured by
53 #define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
55 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
58 * Stream DMA parameters. DMA request line and port address are set runtime
59 * since they are different between OMAP1 and later OMAPs
61 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
63 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
64 static const int omap1_dma_reqs[][2] = {
65 { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
66 { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
67 { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
69 static const unsigned long omap1_mcbsp_port[][2] = {
70 { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
71 OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
72 { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
73 OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
74 { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
75 OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
78 static const int omap1_dma_reqs[][2] = {};
79 static const unsigned long omap1_mcbsp_port[][2] = {};
82 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
83 static const int omap24xx_dma_reqs[][2] = {
84 { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
85 { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
86 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
87 { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
88 { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
89 { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
93 static const int omap24xx_dma_reqs[][2] = {};
96 #if defined(CONFIG_ARCH_OMAP2420)
97 static const unsigned long omap2420_mcbsp_port[][2] = {
98 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
99 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
100 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
101 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
104 static const unsigned long omap2420_mcbsp_port[][2] = {};
107 #if defined(CONFIG_ARCH_OMAP2430)
108 static const unsigned long omap2430_mcbsp_port[][2] = {
109 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
110 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
111 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
112 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
113 { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
114 OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
115 { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
116 OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
117 { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
118 OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
121 static const unsigned long omap2430_mcbsp_port[][2] = {};
124 #if defined(CONFIG_ARCH_OMAP34XX)
125 static const unsigned long omap34xx_mcbsp_port[][2] = {
126 { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
127 OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
128 { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
129 OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
130 { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
131 OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
132 { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
133 OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
134 { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
135 OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
138 static const unsigned long omap34xx_mcbsp_port[][2] = {};
141 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
142 struct snd_soc_dai *dai)
144 struct snd_soc_pcm_runtime *rtd = substream->private_data;
145 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
146 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
149 if (!cpu_dai->active)
150 err = omap_mcbsp_request(mcbsp_data->bus_id);
155 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
156 struct snd_soc_dai *dai)
158 struct snd_soc_pcm_runtime *rtd = substream->private_data;
159 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
160 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
162 if (!cpu_dai->active) {
163 omap_mcbsp_free(mcbsp_data->bus_id);
164 mcbsp_data->configured = 0;
168 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
169 struct snd_soc_dai *dai)
171 struct snd_soc_pcm_runtime *rtd = substream->private_data;
172 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
173 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
177 case SNDRV_PCM_TRIGGER_START:
178 case SNDRV_PCM_TRIGGER_RESUME:
179 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
180 if (!mcbsp_data->active++)
181 omap_mcbsp_start(mcbsp_data->bus_id);
184 case SNDRV_PCM_TRIGGER_STOP:
185 case SNDRV_PCM_TRIGGER_SUSPEND:
186 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
187 if (!--mcbsp_data->active)
188 omap_mcbsp_stop(mcbsp_data->bus_id);
197 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
198 struct snd_pcm_hw_params *params,
199 struct snd_soc_dai *dai)
201 struct snd_soc_pcm_runtime *rtd = substream->private_data;
202 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
203 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
204 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
205 int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
209 if (cpu_class_is_omap1()) {
210 dma = omap1_dma_reqs[bus_id][substream->stream];
211 port = omap1_mcbsp_port[bus_id][substream->stream];
212 } else if (cpu_is_omap2420()) {
213 dma = omap24xx_dma_reqs[bus_id][substream->stream];
214 port = omap2420_mcbsp_port[bus_id][substream->stream];
215 } else if (cpu_is_omap2430()) {
216 dma = omap24xx_dma_reqs[bus_id][substream->stream];
217 port = omap2430_mcbsp_port[bus_id][substream->stream];
218 } else if (cpu_is_omap343x()) {
219 dma = omap24xx_dma_reqs[bus_id][substream->stream];
220 port = omap34xx_mcbsp_port[bus_id][substream->stream];
224 omap_mcbsp_dai_dma_params[id][substream->stream].name =
225 substream->stream ? "Audio Capture" : "Audio Playback";
226 omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
227 omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
228 cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
230 if (mcbsp_data->configured) {
231 /* McBSP already configured by another stream */
235 switch (params_channels(params)) {
237 /* Set 1 word per (McBPSP) frame and use dual-phase frames */
238 regs->rcr2 |= RFRLEN2(1 - 1) | RPHASE;
239 regs->rcr1 |= RFRLEN1(1 - 1);
240 regs->xcr2 |= XFRLEN2(1 - 1) | XPHASE;
241 regs->xcr1 |= XFRLEN1(1 - 1);
244 /* Unsupported number of channels */
248 switch (params_format(params)) {
249 case SNDRV_PCM_FORMAT_S16_LE:
250 /* Set word lengths */
252 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
253 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
254 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
255 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
258 /* Unsupported PCM format */
262 /* Set FS period and length in terms of bit clock periods */
263 switch (mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
264 case SND_SOC_DAIFMT_I2S:
265 regs->srgr2 |= FPER(wlen * 2 - 1);
266 regs->srgr1 |= FWID(wlen - 1);
268 case SND_SOC_DAIFMT_DSP_A:
269 regs->srgr2 |= FPER(wlen * 2 - 1);
270 regs->srgr1 |= FWID(wlen * 2 - 2);
274 omap_mcbsp_config(bus_id, &mcbsp_data->regs);
275 mcbsp_data->configured = 1;
281 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
282 * cache is initialized here
284 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
287 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
288 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
290 if (mcbsp_data->configured)
293 mcbsp_data->fmt = fmt;
294 memset(regs, 0, sizeof(*regs));
295 /* Generic McBSP register settings */
296 regs->spcr2 |= XINTM(3) | FREE;
297 regs->spcr1 |= RINTM(3);
301 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
302 case SND_SOC_DAIFMT_I2S:
303 /* 1-bit data delay */
304 regs->rcr2 |= RDATDLY(1);
305 regs->xcr2 |= XDATDLY(1);
307 case SND_SOC_DAIFMT_DSP_A:
308 /* 0-bit data delay */
309 regs->rcr2 |= RDATDLY(0);
310 regs->xcr2 |= XDATDLY(0);
313 /* Unsupported data format */
317 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
318 case SND_SOC_DAIFMT_CBS_CFS:
319 /* McBSP master. Set FS and bit clocks as outputs */
320 regs->pcr0 |= FSXM | FSRM |
322 /* Sample rate generator drives the FS */
325 case SND_SOC_DAIFMT_CBM_CFM:
329 /* Unsupported master/slave configuration */
333 /* Set bit clock (CLKX/CLKR) and FS polarities */
334 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
335 case SND_SOC_DAIFMT_NB_NF:
338 * FS active low. TX data driven on falling edge of bit clock
339 * and RX data sampled on rising edge of bit clock.
341 regs->pcr0 |= FSXP | FSRP |
344 case SND_SOC_DAIFMT_NB_IF:
345 regs->pcr0 |= CLKXP | CLKRP;
347 case SND_SOC_DAIFMT_IB_NF:
348 regs->pcr0 |= FSXP | FSRP;
350 case SND_SOC_DAIFMT_IB_IF:
359 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
362 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
363 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
365 if (div_id != OMAP_MCBSP_CLKGDV)
368 regs->srgr1 |= CLKGDV(div - 1);
373 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
377 u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
379 if (cpu_class_is_omap1()) {
380 /* OMAP1's can use only external source clock */
381 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
387 if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
390 if (cpu_is_omap343x())
391 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
393 switch (mcbsp_data->bus_id) {
395 reg = OMAP2_CONTROL_DEVCONF0;
399 reg = OMAP2_CONTROL_DEVCONF0;
418 if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
419 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
421 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
426 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
427 int clk_id, unsigned int freq,
430 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
431 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
435 case OMAP_MCBSP_SYSCLK_CLK:
436 regs->srgr2 |= CLKSM;
438 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
439 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
440 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
443 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
444 regs->srgr2 |= CLKSM;
445 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
446 regs->pcr0 |= SCLKME;
455 #define OMAP_MCBSP_DAI_BUILDER(link_id) \
457 .name = "omap-mcbsp-dai-"#link_id, \
459 .type = SND_SOC_DAI_I2S, \
463 .rates = OMAP_MCBSP_RATES, \
464 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
469 .rates = OMAP_MCBSP_RATES, \
470 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
473 .startup = omap_mcbsp_dai_startup, \
474 .shutdown = omap_mcbsp_dai_shutdown, \
475 .trigger = omap_mcbsp_dai_trigger, \
476 .hw_params = omap_mcbsp_dai_hw_params, \
477 .set_fmt = omap_mcbsp_dai_set_dai_fmt, \
478 .set_clkdiv = omap_mcbsp_dai_set_clkdiv, \
479 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk, \
481 .private_data = &mcbsp_data[(link_id)].bus_id, \
484 struct snd_soc_dai omap_mcbsp_dai[] = {
485 OMAP_MCBSP_DAI_BUILDER(0),
486 OMAP_MCBSP_DAI_BUILDER(1),
488 OMAP_MCBSP_DAI_BUILDER(2),
491 OMAP_MCBSP_DAI_BUILDER(3),
492 OMAP_MCBSP_DAI_BUILDER(4),
496 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
498 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
499 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
500 MODULE_LICENSE("GPL");