Merge branch 'topic/atmel' into for-linus

[linux-2.6-omap-h63xx.git] / arch / mips / Kconfig

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5f149b030c0f9fc7949793c6d8591d4bf0fd0450..206cb7953b0cb21360cb331cae3069ac49e8ce38 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -238,21 +238,12 @@ config MIPS_SIM
          This option enables support for MIPS Technologies MIPSsim software
          emulator.
 
          This option enables support for MIPS Technologies MIPSsim software
          emulator.
 

-config MARKEINS
-       bool "NEC EMMA2RH Mark-eins"
-       select CEVT_R4K
-       select CSRC_R4K
-       select DMA_NONCOHERENT
+config NEC_MARKEINS
+       bool "NEC EMMA2RH Mark-eins board"
+       select SOC_EMMA2RH

        select HW_HAS_PCI
        select HW_HAS_PCI

-       select IRQ_CPU
-       select SWAP_IO_SPACE
-       select SYS_SUPPORTS_32BIT_KERNEL
-       select SYS_SUPPORTS_BIG_ENDIAN
-       select SYS_SUPPORTS_LITTLE_ENDIAN
-       select SYS_HAS_CPU_R5000

        help
        help

-         This enables support for the R5432-based NEC Mark-eins
-         boards with R5500 CPU.
+         This enables support for the NEC Electronics Mark-eins boards.

 
 config MACH_VR41XX
        bool "NEC VR4100 series based machines"
 
 config MACH_VR41XX
        bool "NEC VR4100 series based machines"


@@ -261,6 +252,19 @@ config MACH_VR41XX
        select SYS_HAS_CPU_VR41XX
        select GENERIC_HARDIRQS_NO__DO_IRQ
 
        select SYS_HAS_CPU_VR41XX
        select GENERIC_HARDIRQS_NO__DO_IRQ
 

+config NXP_STB220
+       bool "NXP STB220 board"
+       select SOC_PNX833X
+       help
+        Support for NXP Semiconductors STB220 Development Board.
+
+config NXP_STB225
+       bool "NXP 225 board"
+       select SOC_PNX833X
+       select SOC_PNX8335
+       help
+        Support for NXP Semiconductors STB225 Development Board.
+

 config PNX8550_JBS
        bool "NXP PNX8550 based JBS board"
        select PNX8550
 config PNX8550_JBS
        bool "NXP PNX8550 based JBS board"
        select PNX8550


@@ -327,7 +331,6 @@ config SGI_IP22
        select IP22_CPU_SCACHE
        select IRQ_CPU
        select GENERIC_ISA_DMA_SUPPORT_BROKEN
        select IP22_CPU_SCACHE
        select IRQ_CPU
        select GENERIC_ISA_DMA_SUPPORT_BROKEN

-       select SGI_HAS_DS1286

        select SGI_HAS_I8042
        select SGI_HAS_INDYDOG
        select SGI_HAS_HAL2
        select SGI_HAS_I8042
        select SGI_HAS_INDYDOG
        select SGI_HAS_HAL2


@@ -352,7 +355,7 @@ config SGI_IP27
        select ARC64
        select BOOT_ELF64
        select DEFAULT_SGI_PARTITION
        select ARC64
        select BOOT_ELF64
        select DEFAULT_SGI_PARTITION

-       select DMA_IP27
+       select DMA_COHERENT

        select SYS_HAS_EARLY_PRINTK
        select HW_HAS_PCI
        select NR_CPUS_DEFAULT_64
        select SYS_HAS_EARLY_PRINTK
        select HW_HAS_PCI
        select NR_CPUS_DEFAULT_64


@@ -382,7 +385,6 @@ config SGI_IP28
        select HW_HAS_EISA
        select I8253
        select I8259
        select HW_HAS_EISA
        select I8253
        select I8259

-       select SGI_HAS_DS1286

        select SGI_HAS_I8042
        select SGI_HAS_INDYDOG
        select SGI_HAS_HAL2
        select SGI_HAS_I8042
        select SGI_HAS_INDYDOG
        select SGI_HAS_HAL2


@@ -597,6 +599,44 @@ config WR_PPMC
          This enables support for the Wind River MIPS32 4KC PPMC evaluation
          board, which is based on GT64120 bridge chip.
 
          This enables support for the Wind River MIPS32 4KC PPMC evaluation
          board, which is based on GT64120 bridge chip.
 

+config CAVIUM_OCTEON_SIMULATOR
+       bool "Support for the Cavium Networks Octeon Simulator"
+       select CEVT_R4K
+       select 64BIT_PHYS_ADDR
+       select DMA_COHERENT
+       select SYS_SUPPORTS_64BIT_KERNEL
+       select SYS_SUPPORTS_BIG_ENDIAN
+       select SYS_SUPPORTS_HIGHMEM
+       select SYS_HAS_CPU_CAVIUM_OCTEON
+       help
+         The Octeon simulator is software performance model of the Cavium
+         Octeon Processor. It supports simulating Octeon processors on x86
+         hardware.
+
+config CAVIUM_OCTEON_REFERENCE_BOARD
+       bool "Support for the Cavium Networks Octeon reference board"
+       select CEVT_R4K
+       select 64BIT_PHYS_ADDR
+       select DMA_COHERENT
+       select SYS_SUPPORTS_64BIT_KERNEL
+       select SYS_SUPPORTS_BIG_ENDIAN
+       select SYS_SUPPORTS_HIGHMEM
+       select SYS_HAS_EARLY_PRINTK
+       select SYS_HAS_CPU_CAVIUM_OCTEON
+       select SWAP_IO_SPACE
+       help
+         This option supports all of the Octeon reference boards from Cavium
+         Networks. It builds a kernel that dynamically determines the Octeon
+         CPU type and supports all known board reference implementations.
+         Some of the supported boards are:
+               EBT3000
+               EBH3000
+               EBH3100
+               Thunder
+               Kodama
+               Hikari
+         Say Y here for most Octeon reference boards.
+

 endchoice
 
 source "arch/mips/alchemy/Kconfig"
 endchoice
 
 source "arch/mips/alchemy/Kconfig"


@@ -608,6 +648,7 @@ source "arch/mips/sgi-ip27/Kconfig"
 source "arch/mips/sibyte/Kconfig"
 source "arch/mips/txx9/Kconfig"
 source "arch/mips/vr41xx/Kconfig"
 source "arch/mips/sibyte/Kconfig"
 source "arch/mips/txx9/Kconfig"
 source "arch/mips/vr41xx/Kconfig"

+source "arch/mips/cavium-octeon/Kconfig"

 
 endmenu
 
 
 endmenu
 


@@ -654,7 +695,7 @@ config GENERIC_CMOS_UPDATE
        bool
        default y
 
        bool
        default y
 

-config SCHED_NO_NO_OMIT_FRAME_POINTER
+config SCHED_OMIT_FRAME_POINTER

        bool
        default y
 
        bool
        default y
 


@@ -683,7 +724,11 @@ config CEVT_DS1287
 config CEVT_GT641XX
        bool
 
 config CEVT_GT641XX
        bool
 

+config CEVT_R4K_LIB
+       bool
+

 config CEVT_R4K
 config CEVT_R4K

+       select CEVT_R4K_LIB

        bool
 
 config CEVT_SB1250
        bool
 
 config CEVT_SB1250


@@ -698,7 +743,11 @@ config CSRC_BCM1480
 config CSRC_IOASIC
        bool
 
 config CSRC_IOASIC
        bool
 

+config CSRC_R4K_LIB
+       bool
+

 config CSRC_R4K
 config CSRC_R4K

+       select CSRC_R4K_LIB

        bool
 
 config CSRC_SB1250
        bool
 
 config CSRC_SB1250


@@ -715,9 +764,6 @@ config CFE
 config DMA_COHERENT
        bool
 
 config DMA_COHERENT
        bool
 

-config DMA_IP27
-       bool
-

 config DMA_NONCOHERENT
        bool
        select DMA_NEED_PCI_MAP_STATE
 config DMA_NONCOHERENT
        bool
        select DMA_NEED_PCI_MAP_STATE


@@ -836,6 +882,9 @@ config IRQ_GT641XX
 config IRQ_GIC
        bool
 
 config IRQ_GIC
        bool
 

+config IRQ_CPU_OCTEON
+       bool
+

 config MIPS_BOARDS_GEN
        bool
 
 config MIPS_BOARDS_GEN
        bool
 


@@ -849,6 +898,36 @@ config MIPS_RM9122
        bool
        select SERIAL_RM9000
 
        bool
        select SERIAL_RM9000
 

+config SOC_EMMA2RH
+       bool
+       select CEVT_R4K
+       select CSRC_R4K
+       select DMA_NONCOHERENT
+       select IRQ_CPU
+       select SWAP_IO_SPACE
+       select SYS_HAS_CPU_R5500
+       select SYS_SUPPORTS_32BIT_KERNEL
+       select SYS_SUPPORTS_64BIT_KERNEL
+       select SYS_SUPPORTS_BIG_ENDIAN
+
+config SOC_PNX833X
+       bool
+       select CEVT_R4K
+       select CSRC_R4K
+       select IRQ_CPU
+       select DMA_NONCOHERENT
+       select SYS_HAS_CPU_MIPS32_R2
+       select SYS_SUPPORTS_32BIT_KERNEL
+       select SYS_SUPPORTS_LITTLE_ENDIAN
+       select SYS_SUPPORTS_BIG_ENDIAN
+       select GENERIC_HARDIRQS_NO__DO_IRQ
+       select GENERIC_GPIO
+       select CPU_MIPSR2_IRQ_VI
+
+config SOC_PNX8335
+       bool
+       select SOC_PNX833X
+

 config PNX8550
        bool
        select SOC_PNX8550
 config PNX8550
        bool
        select SOC_PNX8550


@@ -866,17 +945,9 @@ config SOC_PNX8550
 config SWAP_IO_SPACE
        bool
 
 config SWAP_IO_SPACE
        bool
 

-config EMMA2RH
-       bool
-       depends on MARKEINS
-       default y
-

 config SERIAL_RM9000
        bool
 
 config SERIAL_RM9000
        bool
 

-config SGI_HAS_DS1286
-       bool
-

 config SGI_HAS_INDYDOG
        bool
 
 config SGI_HAS_INDYDOG
        bool
 


@@ -910,7 +981,7 @@ config BOOT_ELF32
 config MIPS_L1_CACHE_SHIFT
        int
        default "4" if MACH_DECSTATION || MIKROTIK_RB532
 config MIPS_L1_CACHE_SHIFT
        int
        default "4" if MACH_DECSTATION || MIKROTIK_RB532

-       default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM
+       default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON

        default "4" if PMC_MSP4200_EVAL
        default "5"
 
        default "4" if PMC_MSP4200_EVAL
        default "5"
 


@@ -1092,6 +1163,16 @@ config CPU_R5432
        select CPU_SUPPORTS_32BIT_KERNEL
        select CPU_SUPPORTS_64BIT_KERNEL
 
        select CPU_SUPPORTS_32BIT_KERNEL
        select CPU_SUPPORTS_64BIT_KERNEL
 

+config CPU_R5500
+       bool "R5500"
+       depends on SYS_HAS_CPU_R5500
+       select CPU_HAS_LLSC
+       select CPU_SUPPORTS_32BIT_KERNEL
+       select CPU_SUPPORTS_64BIT_KERNEL
+       help
+         NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
+         instruction set.
+

 config CPU_R6000
        bool "R6000"
        depends on EXPERIMENTAL
 config CPU_R6000
        bool "R6000"
        depends on EXPERIMENTAL


@@ -1161,6 +1242,24 @@ config CPU_SB1
        select CPU_SUPPORTS_HIGHMEM
        select WEAK_ORDERING
 
        select CPU_SUPPORTS_HIGHMEM
        select WEAK_ORDERING
 

+config CPU_CAVIUM_OCTEON
+       bool "Cavium Octeon processor"
+       depends on SYS_HAS_CPU_CAVIUM_OCTEON
+       select IRQ_CPU
+       select IRQ_CPU_OCTEON
+       select CPU_HAS_PREFETCH
+       select CPU_SUPPORTS_64BIT_KERNEL
+       select SYS_SUPPORTS_SMP
+       select NR_CPUS_DEFAULT_16
+       select WEAK_ORDERING
+       select WEAK_REORDERING_BEYOND_LLSC
+       select CPU_SUPPORTS_HIGHMEM
+       help
+         The Cavium Octeon processor is a highly integrated chip containing
+         many ethernet hardware widgets for networking tasks. The processor
+         can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
+         Full details can be found at http://www.caviumnetworks.com.
+

 endchoice
 
 config SYS_HAS_CPU_LOONGSON2
 endchoice
 
 config SYS_HAS_CPU_LOONGSON2


@@ -1202,6 +1301,9 @@ config SYS_HAS_CPU_R5000
 config SYS_HAS_CPU_R5432
        bool
 
 config SYS_HAS_CPU_R5432
        bool
 

+config SYS_HAS_CPU_R5500
+       bool
+

 config SYS_HAS_CPU_R6000
        bool
 
 config SYS_HAS_CPU_R6000
        bool
 


@@ -1223,6 +1325,9 @@ config SYS_HAS_CPU_RM9000
 config SYS_HAS_CPU_SB1
        bool
 
 config SYS_HAS_CPU_SB1
        bool
 

+config SYS_HAS_CPU_CAVIUM_OCTEON
+       bool
+

 #
 # CPU may reorder R->R, R->W, W->R, W->W
 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
 #
 # CPU may reorder R->R, R->W, W->R, W->W
 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC


@@ -1258,7 +1363,7 @@ config CPU_MIPSR1
 
 config CPU_MIPSR2
        bool
 
 config CPU_MIPSR2
        bool

-       default y if CPU_MIPS32_R2 || CPU_MIPS64_R2
+       default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON

 
 config SYS_SUPPORTS_32BIT_KERNEL
        bool
 
 config SYS_SUPPORTS_32BIT_KERNEL
        bool


@@ -1274,7 +1379,7 @@ config CPU_SUPPORTS_64BIT_KERNEL
 #
 config HARDWARE_WATCHPOINTS
        bool
 #
 config HARDWARE_WATCHPOINTS
        bool

-       default y if CPU_MIPS32 || CPU_MIPS64
+       default y if CPU_MIPSR1 || CPU_MIPSR2

 
 menu "Kernel type"
 
 
 menu "Kernel type"
 


@@ -1296,6 +1401,7 @@ config 32BIT
 config 64BIT
        bool "64-bit kernel"
        depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
 config 64BIT
        bool "64-bit kernel"
        depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL

+       select HAVE_SYSCALL_WRAPPERS

        help
          Select this option if you want to build a 64-bit kernel.
 
        help
          Select this option if you want to build a 64-bit kernel.