Merge master.kernel.org:/home/rmk/linux-2.6-arm

[linux-2.6-omap-h63xx.git] / arch / mips / Kconfig

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a5255e7c79e004001a8f55c82e33d964198b403f..600eef3f3ac7db71dc165946e657da08ee79a9ac 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -351,7 +351,7 @@ config SGI_IP27
        select ARC64
        select BOOT_ELF64
        select DEFAULT_SGI_PARTITION
        select ARC64
        select BOOT_ELF64
        select DEFAULT_SGI_PARTITION

-       select DMA_IP27
+       select DMA_COHERENT

        select SYS_HAS_EARLY_PRINTK
        select HW_HAS_PCI
        select NR_CPUS_DEFAULT_64
        select SYS_HAS_EARLY_PRINTK
        select HW_HAS_PCI
        select NR_CPUS_DEFAULT_64


@@ -595,6 +595,44 @@ config WR_PPMC
          This enables support for the Wind River MIPS32 4KC PPMC evaluation
          board, which is based on GT64120 bridge chip.
 
          This enables support for the Wind River MIPS32 4KC PPMC evaluation
          board, which is based on GT64120 bridge chip.
 

+config CAVIUM_OCTEON_SIMULATOR
+       bool "Support for the Cavium Networks Octeon Simulator"
+       select CEVT_R4K
+       select 64BIT_PHYS_ADDR
+       select DMA_COHERENT
+       select SYS_SUPPORTS_64BIT_KERNEL
+       select SYS_SUPPORTS_BIG_ENDIAN
+       select SYS_SUPPORTS_HIGHMEM
+       select CPU_CAVIUM_OCTEON
+       help
+         The Octeon simulator is software performance model of the Cavium
+         Octeon Processor. It supports simulating Octeon processors on x86
+         hardware.
+
+config CAVIUM_OCTEON_REFERENCE_BOARD
+       bool "Support for the Cavium Networks Octeon reference board"
+       select CEVT_R4K
+       select 64BIT_PHYS_ADDR
+       select DMA_COHERENT
+       select SYS_SUPPORTS_64BIT_KERNEL
+       select SYS_SUPPORTS_BIG_ENDIAN
+       select SYS_SUPPORTS_HIGHMEM
+       select SYS_HAS_EARLY_PRINTK
+       select CPU_CAVIUM_OCTEON
+       select SWAP_IO_SPACE
+       help
+         This option supports all of the Octeon reference boards from Cavium
+         Networks. It builds a kernel that dynamically determines the Octeon
+         CPU type and supports all known board reference implementations.
+         Some of the supported boards are:
+               EBT3000
+               EBH3000
+               EBH3100
+               Thunder
+               Kodama
+               Hikari
+         Say Y here for most Octeon reference boards.
+

 endchoice
 
 source "arch/mips/alchemy/Kconfig"
 endchoice
 
 source "arch/mips/alchemy/Kconfig"


@@ -607,6 +645,7 @@ source "arch/mips/sgi-ip27/Kconfig"
 source "arch/mips/sibyte/Kconfig"
 source "arch/mips/txx9/Kconfig"
 source "arch/mips/vr41xx/Kconfig"
 source "arch/mips/sibyte/Kconfig"
 source "arch/mips/txx9/Kconfig"
 source "arch/mips/vr41xx/Kconfig"

+source "arch/mips/cavium-octeon/Kconfig"

 
 endmenu
 
 
 endmenu
 


@@ -682,7 +721,11 @@ config CEVT_DS1287
 config CEVT_GT641XX
        bool
 
 config CEVT_GT641XX
        bool
 

+config CEVT_R4K_LIB
+       bool
+

 config CEVT_R4K
 config CEVT_R4K

+       select CEVT_R4K_LIB

        bool
 
 config CEVT_SB1250
        bool
 
 config CEVT_SB1250


@@ -697,7 +740,11 @@ config CSRC_BCM1480
 config CSRC_IOASIC
        bool
 
 config CSRC_IOASIC
        bool
 

+config CSRC_R4K_LIB
+       bool
+

 config CSRC_R4K
 config CSRC_R4K

+       select CSRC_R4K_LIB

        bool
 
 config CSRC_SB1250
        bool
 
 config CSRC_SB1250


@@ -714,9 +761,6 @@ config CFE
 config DMA_COHERENT
        bool
 
 config DMA_COHERENT
        bool
 

-config DMA_IP27
-       bool
-

 config DMA_NONCOHERENT
        bool
        select DMA_NEED_PCI_MAP_STATE
 config DMA_NONCOHERENT
        bool
        select DMA_NEED_PCI_MAP_STATE


@@ -835,6 +879,9 @@ config IRQ_GT641XX
 config IRQ_GIC
        bool
 
 config IRQ_GIC
        bool
 

+config IRQ_CPU_OCTEON
+       bool
+

 config MIPS_BOARDS_GEN
        bool
 
 config MIPS_BOARDS_GEN
        bool
 


@@ -924,7 +971,7 @@ config BOOT_ELF32
 config MIPS_L1_CACHE_SHIFT
        int
        default "4" if MACH_DECSTATION || MIKROTIK_RB532
 config MIPS_L1_CACHE_SHIFT
        int
        default "4" if MACH_DECSTATION || MIKROTIK_RB532

-       default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM
+       default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON

        default "4" if PMC_MSP4200_EVAL
        default "5"
 
        default "4" if PMC_MSP4200_EVAL
        default "5"
 


@@ -1185,6 +1232,23 @@ config CPU_SB1
        select CPU_SUPPORTS_HIGHMEM
        select WEAK_ORDERING
 
        select CPU_SUPPORTS_HIGHMEM
        select WEAK_ORDERING
 

+config CPU_CAVIUM_OCTEON
+       bool "Cavium Octeon processor"
+       select IRQ_CPU
+       select IRQ_CPU_OCTEON
+       select CPU_HAS_PREFETCH
+       select CPU_SUPPORTS_64BIT_KERNEL
+       select SYS_SUPPORTS_SMP
+       select NR_CPUS_DEFAULT_16
+       select WEAK_ORDERING
+       select WEAK_REORDERING_BEYOND_LLSC
+       select CPU_SUPPORTS_HIGHMEM
+       help
+         The Cavium Octeon processor is a highly integrated chip containing
+         many ethernet hardware widgets for networking tasks. The processor
+         can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
+         Full details can be found at http://www.caviumnetworks.com.
+

 endchoice
 
 config SYS_HAS_CPU_LOONGSON2
 endchoice
 
 config SYS_HAS_CPU_LOONGSON2


@@ -1285,7 +1349,7 @@ config CPU_MIPSR1
 
 config CPU_MIPSR2
        bool
 
 config CPU_MIPSR2
        bool

-       default y if CPU_MIPS32_R2 || CPU_MIPS64_R2
+       default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON

 
 config SYS_SUPPORTS_32BIT_KERNEL
        bool
 
 config SYS_SUPPORTS_32BIT_KERNEL
        bool


@@ -1301,7 +1365,7 @@ config CPU_SUPPORTS_64BIT_KERNEL
 #
 config HARDWARE_WATCHPOINTS
        bool
 #
 config HARDWARE_WATCHPOINTS
        bool

-       default y if CPU_MIPS32 || CPU_MIPS64
+       default y if CPU_MIPSR1 || CPU_MIPSR2

 
 menu "Kernel type"
 
 
 menu "Kernel type"