+int cx88_start_audio_dma(struct cx88_core *core)
+{
+ /* setup fifo + format */
+ cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], 128, 0);
+ cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], 128, 0);
+
+ cx_write(MO_AUDD_LNGTH, 128); /* fifo bpl size */
+ cx_write(MO_AUDR_LNGTH, 128); /* fifo bpl size */
+
+ /* start dma */
+ cx_write(MO_AUD_DMACNTRL, 0x0003); /* Up and Down fifo enable */
+
+ return 0;
+}
+
+int cx88_stop_audio_dma(struct cx88_core *core)
+{
+ /* stop dma */
+ cx_write(MO_AUD_DMACNTRL, 0x0000);
+
+ return 0;
+}
+