OMAP: Fix dpll4_m4_ck clk_set_rate()

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock34xx.h

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 1c2b49f32747d72acdb63ba75e248240c520aeec..5357507c413473b1d72199fbfb9f74ee69819b21 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -825,6 +825,8 @@ static struct clk dpll4_m4_ck = {
                                PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll4_clkdm" },
        .recalc         = &omap2_clksel_recalc,
+       .set_rate       = &omap2_clksel_set_rate,
+       .round_rate     = &omap2_clksel_round_rate,
 };
 
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
@@ -879,8 +881,6 @@ static struct clk dpll4_m6_ck = {
                                PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll4_clkdm" },
        .recalc         = &omap2_clksel_recalc,
-       .set_rate       = &omap2_clksel_set_rate,
-       .round_rate     = &omap2_clksel_round_rate,
 };
 
 /* The PWRDN bit is apparently only available on 3430ES2 and above */