Merge omap tree

[linux-2.6-omap-h63xx.git] / arch / arm / mm / proc-arm926.S

diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 7d042dc20c47a77855b258457478e1d0dceb8c96..ce246dd7b407c6e9458069775aaea5a6245c313f 100644 (file)
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -3,6 +3,7 @@
  *
  *  Copyright (C) 1999-2001 ARM Limited
  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *  hacked for non-paged-MM by Hyok S. Choi, 2003.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -28,9 +29,9 @@
 #include <linux/config.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
-#include <asm/hardware.h>
 #include <asm/page.h>
 #include <asm/ptrace.h>
 #include "proc-macros.S"
@@ -85,7 +86,9 @@ ENTRY(cpu_arm926_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
+#ifdef CONFIG_MMU
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
+#endif
        mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
        bic     ip, ip, #0x000f                 @ ............wcam
        bic     ip, ip, #0x1100                 @ ...i...s........
@@ -329,6 +332,7 @@ ENTRY(cpu_arm926_dcache_clean_area)
  */
        .align  5
 ENTRY(cpu_arm926_switch_mm)
+#ifdef CONFIG_MMU
        mov     ip, #0
 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
        mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
@@ -341,6 +345,7 @@ ENTRY(cpu_arm926_switch_mm)
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
        mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
+#endif
        mov     pc, lr
 
 /*
@@ -350,6 +355,7 @@ ENTRY(cpu_arm926_switch_mm)
  */
        .align  5
 ENTRY(cpu_arm926_set_pte)
+#ifdef CONFIG_MMU
        str     r1, [r0], #-2048                @ linux version
 
        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -378,6 +384,7 @@ ENTRY(cpu_arm926_set_pte)
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 #endif
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+#endif
        mov     pc, lr
 
        __INIT
@@ -387,7 +394,9 @@ __arm926_setup:
        mov     r0, #0
        mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
+#ifdef CONFIG_MMU
        mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
+#endif
 
 
 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -451,22 +460,7 @@ cpu_elf_name:
 
        .type   cpu_arm926_name, #object
 cpu_arm926_name:
-       .ascii  "ARM926EJ-S"
-#ifndef CONFIG_CPU_ICACHE_DISABLE
-       .ascii  "i"
-#endif
-#ifndef CONFIG_CPU_DCACHE_DISABLE
-       .ascii  "d"
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-       .ascii  "(wt)"
-#else
-       .ascii  "(wb)"
-#endif
-#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
-       .ascii  "RR"
-#endif
-#endif
-       .ascii  "\0"
+       .asciz  "ARM926EJ-S"
        .size   cpu_arm926_name, . - cpu_arm926_name
 
        .align