Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-rc-fixes-2.6

[linux-2.6-omap-h63xx.git] / arch / arm / mm / proc-feroceon.S

diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 61a5025bf0329ba807d9f22fb99184218716b2a2..f2e5884c513a05f0b0905a9f5c3ee023a8c702f7 100644 (file)
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -79,6 +79,13 @@ ENTRY(cpu_feroceon_proc_fin)
        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
        msr     cpsr_c, ip
        bl      feroceon_flush_kern_cache_all
+
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+       mov     r0, #0
+       mcr     p15, 1, r0, c15, c9, 0          @ clean L2
+       mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+#endif
+
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
@@ -237,6 +244,20 @@ ENTRY(feroceon_flush_kern_dcache_page)
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
 
+       .align  5
+ENTRY(feroceon_range_flush_kern_dcache_page)
+       mrs     r2, cpsr
+       add     r1, r0, #PAGE_SZ - CACHE_DLINESIZE      @ top addr is inclusive
+       orr     r3, r2, #PSR_I_BIT
+       msr     cpsr_c, r3                      @ disable interrupts
+       mcr     p15, 5, r0, c15, c15, 0         @ D clean/inv range start
+       mcr     p15, 5, r1, c15, c15, 1         @ D clean/inv range top
+       msr     cpsr_c, r2                      @ restore interrupts
+       mov     r0, #0
+       mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+       mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+       mov     pc, lr
+
 /*
  *     dma_inv_range(start, end)
  *
@@ -253,10 +274,10 @@ ENTRY(feroceon_flush_kern_dcache_page)
        .align  5
 ENTRY(feroceon_dma_inv_range)
        tst     r0, #CACHE_DLINESIZE - 1
+       bic     r0, r0, #CACHE_DLINESIZE - 1
        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
        tst     r1, #CACHE_DLINESIZE - 1
        mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
-       bic     r0, r0, #CACHE_DLINESIZE - 1
 1:     mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
        add     r0, r0, #CACHE_DLINESIZE
        cmp     r0, r1
@@ -264,6 +285,22 @@ ENTRY(feroceon_dma_inv_range)
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
 
+       .align  5
+ENTRY(feroceon_range_dma_inv_range)
+       mrs     r2, cpsr
+       tst     r0, #CACHE_DLINESIZE - 1
+       mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
+       tst     r1, #CACHE_DLINESIZE - 1
+       mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
+       cmp     r1, r0
+       subne   r1, r1, #1                      @ top address is inclusive
+       orr     r3, r2, #PSR_I_BIT
+       msr     cpsr_c, r3                      @ disable interrupts
+       mcr     p15, 5, r0, c15, c14, 0         @ D inv range start
+       mcr     p15, 5, r1, c15, c14, 1         @ D inv range top
+       msr     cpsr_c, r2                      @ restore interrupts
+       mov     pc, lr
+
 /*
  *     dma_clean_range(start, end)
  *
@@ -284,6 +321,19 @@ ENTRY(feroceon_dma_clean_range)
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
 
+       .align  5
+ENTRY(feroceon_range_dma_clean_range)
+       mrs     r2, cpsr
+       cmp     r1, r0
+       subne   r1, r1, #1                      @ top address is inclusive
+       orr     r3, r2, #PSR_I_BIT
+       msr     cpsr_c, r3                      @ disable interrupts
+       mcr     p15, 5, r0, c15, c13, 0         @ D clean range start
+       mcr     p15, 5, r1, c15, c13, 1         @ D clean range top
+       msr     cpsr_c, r2                      @ restore interrupts
+       mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+       mov     pc, lr
+
 /*
  *     dma_flush_range(start, end)
  *
@@ -302,6 +352,19 @@ ENTRY(feroceon_dma_flush_range)
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
 
+       .align  5
+ENTRY(feroceon_range_dma_flush_range)
+       mrs     r2, cpsr
+       cmp     r1, r0
+       subne   r1, r1, #1                      @ top address is inclusive
+       orr     r3, r2, #PSR_I_BIT
+       msr     cpsr_c, r3                      @ disable interrupts
+       mcr     p15, 5, r0, c15, c15, 0         @ D clean/inv range start
+       mcr     p15, 5, r1, c15, c15, 1         @ D clean/inv range top
+       msr     cpsr_c, r2                      @ restore interrupts
+       mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+       mov     pc, lr
+
 ENTRY(feroceon_cache_fns)
        .long   feroceon_flush_kern_cache_all
        .long   feroceon_flush_user_cache_all
@@ -313,12 +376,33 @@ ENTRY(feroceon_cache_fns)
        .long   feroceon_dma_clean_range
        .long   feroceon_dma_flush_range
 
+ENTRY(feroceon_range_cache_fns)
+       .long   feroceon_flush_kern_cache_all
+       .long   feroceon_flush_user_cache_all
+       .long   feroceon_flush_user_cache_range
+       .long   feroceon_coherent_kern_range
+       .long   feroceon_coherent_user_range
+       .long   feroceon_range_flush_kern_dcache_page
+       .long   feroceon_range_dma_inv_range
+       .long   feroceon_range_dma_clean_range
+       .long   feroceon_range_dma_flush_range
+
        .align  5
 ENTRY(cpu_feroceon_dcache_clean_area)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+       mov     r2, r0
+       mov     r3, r1
+#endif
 1:     mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        add     r0, r0, #CACHE_DLINESIZE
        subs    r1, r1, #CACHE_DLINESIZE
        bhi     1b
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+1:     mcr     p15, 1, r2, c15, c9, 1          @ clean L2 entry
+       add     r2, r2, #CACHE_DLINESIZE
+       subs    r3, r3, #CACHE_DLINESIZE
+       bhi     1b
+#endif
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
 
@@ -382,6 +466,9 @@ ENTRY(cpu_feroceon_set_pte_ext)
        str     r2, [r0]                        @ hardware version
        mov     r0, r0
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+       mcr     p15, 1, r0, c15, c9, 1          @ clean L2 entry
+#endif
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 #endif
        mov     pc, lr
@@ -406,14 +493,15 @@ __feroceon_setup:
        .size   __feroceon_setup, . - __feroceon_setup
 
        /*
-        *  R
-        * .RVI ZFRS BLDP WCAM
-        * .011 0001 ..11 0101
+        *      B
+        *  R   P
+        * .RVI UFRS BLDP WCAM
+        * .011 .001 ..11 0101
         *
         */
        .type   feroceon_crval, #object
 feroceon_crval:
-       crval   clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
+       crval   clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
 
        __INITDATA
 
@@ -456,6 +544,16 @@ cpu_88fr531_name:
        .asciz  "Feroceon 88FR531-vd"
        .size   cpu_88fr531_name, . - cpu_88fr531_name
 
+       .type   cpu_88fr571_name, #object
+cpu_88fr571_name:
+       .asciz  "Feroceon 88FR571-vd"
+       .size   cpu_88fr571_name, . - cpu_88fr571_name
+
+       .type   cpu_88fr131_name, #object
+cpu_88fr131_name:
+       .asciz  "Feroceon 88FR131"
+       .size   cpu_88fr131_name, . - cpu_88fr131_name
+
        .align
 
        .section ".proc.info.init", #alloc, #execinstr
@@ -511,3 +609,53 @@ __88fr531_proc_info:
        .long   feroceon_user_fns
        .long   feroceon_cache_fns
        .size   __88fr531_proc_info, . - __88fr531_proc_info
+
+       .type   __88fr571_proc_info,#object
+__88fr571_proc_info:
+       .long   0x56155710
+       .long   0xfffffff0
+       .long   PMD_TYPE_SECT | \
+               PMD_SECT_BUFFERABLE | \
+               PMD_SECT_CACHEABLE | \
+               PMD_BIT4 | \
+               PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ
+       .long   PMD_TYPE_SECT | \
+               PMD_BIT4 | \
+               PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ
+       b       __feroceon_setup
+       .long   cpu_arch_name
+       .long   cpu_elf_name
+       .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+       .long   cpu_88fr571_name
+       .long   feroceon_processor_functions
+       .long   v4wbi_tlb_fns
+       .long   feroceon_user_fns
+       .long   feroceon_range_cache_fns
+       .size   __88fr571_proc_info, . - __88fr571_proc_info
+
+       .type   __88fr131_proc_info,#object
+__88fr131_proc_info:
+       .long   0x56251310
+       .long   0xfffffff0
+       .long   PMD_TYPE_SECT | \
+               PMD_SECT_BUFFERABLE | \
+               PMD_SECT_CACHEABLE | \
+               PMD_BIT4 | \
+               PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ
+       .long   PMD_TYPE_SECT | \
+               PMD_BIT4 | \
+               PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ
+       b       __feroceon_setup
+       .long   cpu_arch_name
+       .long   cpu_elf_name
+       .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+       .long   cpu_88fr131_name
+       .long   feroceon_processor_functions
+       .long   v4wbi_tlb_fns
+       .long   feroceon_user_fns
+       .long   feroceon_range_cache_fns
+       .size   __88fr131_proc_info, . - __88fr131_proc_info