Merge branch 'linus' of master.kernel.org:/pub/scm/linux/kernel/git/perex/alsa

[linux-2.6-omap-h63xx.git] / arch / arm / mm / proc-macros.S

diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 9137fe563599a1e7f17280c6ec383eef274e5626..b13150052a76bd6c5d6cc16b17a48d05978c16f8 100644 (file)
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -4,7 +4,7 @@
  *  VMA_VM_FLAGS
  *  VM_EXEC
  */
-#include <asm/constants.h>
+#include <asm/asm-offsets.h>
 #include <asm/thread_info.h>
 
 /*
@@ -49,3 +49,25 @@
        .macro  asid, rd, rn
        and     \rd, \rn, #255
        .endm
+
+       .macro  crval, clear, mmuset, ucset
+#ifdef CONFIG_MMU
+       .word   \clear
+       .word   \mmuset
+#else
+       .word   \clear
+       .word   \ucset
+#endif
+       .endm
+
+/*
+ * cache_line_size - get the cache line size from the CSIDR register
+ * (available on ARMv7+). It assumes that the CSSR register was configured
+ * to access the L1 data cache CSIDR.
+ */
+       .macro  dcache_line_size, reg, tmp
+       mrc     p15, 1, \tmp, c0, c0, 0         @ read CSIDR
+       and     \tmp, \tmp, #7                  @ cache line size encoding
+       mov     \reg, #16                       @ size offset
+       mov     \reg, \reg, lsl \tmp            @ actual cache line size
+       .endm