Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6

[linux-2.6-omap-h63xx.git] / arch / arm / mm / proc-xsc3.S

diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index ad1ce5a89221c6190d736192417ce4c42f71c5e2..04dc8b65401b4890b6ebc67eaac43f2c11d09169 100644 (file)
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -27,7 +27,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <mach/hardware.h>
 #include <asm/pgtable.h>
 #include <asm/pgtable-hwdef.h>
@@ -345,18 +345,36 @@ ENTRY(cpu_xsc3_switch_mm)
  * cpu_xsc3_set_pte_ext(ptep, pte, ext)
  *
  * Set a PTE and flush it out
- *
  */
+cpu_xsc3_mt_table:
+       .long   0x00                                            @ L_PTE_MT_UNCACHED
+       .long   PTE_EXT_TEX(1)                                  @ L_PTE_MT_BUFFERABLE
+       .long   PTE_CACHEABLE                                   @ L_PTE_MT_WRITETHROUGH
+       .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_WRITEBACK
+       .long   PTE_EXT_TEX(1) | PTE_BUFFERABLE                 @ L_PTE_MT_DEV_SHARED
+       .long   0x00                                            @ unused
+       .long   0x00                                            @ L_PTE_MT_MINICACHE (not present)
+       .long   PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?)
+       .long   0x00                                            @ unused
+       .long   PTE_EXT_TEX(1)                                  @ L_PTE_MT_DEV_WC
+       .long   0x00                                            @ unused
+       .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_DEV_CACHED
+       .long   PTE_EXT_TEX(2)                                  @ L_PTE_MT_DEV_NONSHARED
+       .long   0x00                                            @ unused
+       .long   0x00                                            @ unused
+       .long   0x00                                            @ unused
+
        .align  5
 ENTRY(cpu_xsc3_set_pte_ext)
        xscale_set_pte_ext_prologue
 
-       @ If it's cacheable, it needs to be in L2 also.
-       tst     r1, #L_PTE_CACHEABLE
-       orrne   r2, r2, #PTE_EXT_TEX(0x5)
-
        tst     r1, #L_PTE_SHARED               @ shared?
-       orrne   r2, r2, #0x200
+       and     r1, r1, #L_PTE_MT_MASK
+       adr     ip, cpu_xsc3_mt_table
+       ldr     ip, [ip, r1]
+       orrne   r2, r2, #PTE_EXT_COHERENT       @ interlock: mask in coherent bit
+       bic     r2, r2, #0x0c                   @ clear old C,B bits
+       orr     r2, r2, ip
 
        xscale_set_pte_ext_epilogue
        mov     pc, lr