Merge branch 'linus' into core/rodata

[linux-2.6-omap-h63xx.git] / arch / blackfin / lib / outs.S

diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S
index f8c876fe8930b7dccf1be5653090a70c271857fc..4685b7aa00806a7722083e0a117184082ddf5cef 100644 (file)
--- a/arch/blackfin/lib/outs.S
+++ b/arch/blackfin/lib/outs.S
@@ -7,7 +7,7 @@
  * Description:  Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
  *
  * Modified:     Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
- *               Copyright 2004-2006 Analog Devices Inc.
+ *               Copyright 2004-2008 Analog Devices Inc.
  *
  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  *
@@ -40,6 +40,7 @@ ENTRY(_outsl)
 .Llong_loop_s: R0 = [P1++];
 .Llong_loop_e: [P0] = R0;
        RTS;
+ENDPROC(_outsl)
 
 ENTRY(_outsw)
        P0 = R0;        /* P0 = port */
@@ -50,6 +51,7 @@ ENTRY(_outsw)
 .Lword_loop_s: R0 = W[P1++];
 .Lword_loop_e: W[P0] = R0;
        RTS;
+ENDPROC(_outsw)
 
 ENTRY(_outsb)
        P0 = R0;        /* P0 = port */
@@ -60,3 +62,18 @@ ENTRY(_outsb)
 .Lbyte_loop_s: R0 = B[P1++];
 .Lbyte_loop_e: B[P0] = R0;
        RTS;
+ENDPROC(_outsb)
+
+ENTRY(_outsw_8)
+       P0 = R0;        /* P0 = port */
+       P1 = R1;        /* P1 = address */
+       P2 = R2;        /* P2 = count */
+
+       LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
+.Lword8_loop_s: R1 = B[P1++];
+               R0 = B[P1++];
+               R0 = R0 << 8;
+               R0 = R0 + R1;
+.Lword8_loop_e: W[P0] = R0;
+       RTS;
+ENDPROC(_outsw_8)