Pull ec into release branch

[linux-2.6-omap-h63xx.git] / arch / i386 / pci / pci.h

diff --git a/arch/i386/pci/pci.h b/arch/i386/pci/pci.h
index e58bae2076ad50b96a0e2fb78493e198e44816ec..8c66f275756f9f9ac4dc0d1177b396307fb3a7fc 100644 (file)
--- a/arch/i386/pci/pci.h
+++ b/arch/i386/pci/pci.h
@@ -104,3 +104,46 @@ extern DECLARE_BITMAP(pci_mmcfg_fallback_slots, 32*PCI_MMCFG_MAX_CHECK_BUS);
 extern int __init pci_mmcfg_arch_reachable(unsigned int seg, unsigned int bus,
                                           unsigned int devfn);
 extern int __init pci_mmcfg_arch_init(void);
+
+/*
+ * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
+ * on their northbrige except through the * %eax register. As such, you MUST
+ * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
+ * accessor functions.
+ * In fact just use pci_config_*, nothing else please.
+ */
+static inline unsigned char mmio_config_readb(void __iomem *pos)
+{
+       u8 val;
+       asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
+       return val;
+}
+
+static inline unsigned short mmio_config_readw(void __iomem *pos)
+{
+       u16 val;
+       asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
+       return val;
+}
+
+static inline unsigned int mmio_config_readl(void __iomem *pos)
+{
+       u32 val;
+       asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
+       return val;
+}
+
+static inline void mmio_config_writeb(void __iomem *pos, u8 val)
+{
+       asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
+}
+
+static inline void mmio_config_writew(void __iomem *pos, u16 val)
+{
+       asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
+}
+
+static inline void mmio_config_writel(void __iomem *pos, u32 val)
+{
+       asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");
+}