[PATCH] node hotplug: register cpu: remove node struct

[linux-2.6-omap-h63xx.git] / arch / mips / kernel / entry.S

diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index be0354a14e262ba2364e11bb3c117e2cf084a966..a9c6de1b954257e8e30e73518009f7cf3d1444ae 100644 (file)
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -17,6 +17,9 @@
 #include <asm/isadep.h>
 #include <asm/thread_info.h>
 #include <asm/war.h>
+#ifdef CONFIG_MIPS_MT_SMTC
+#include <asm/mipsmtregs.h>
+#endif
 
 #ifdef CONFIG_PREEMPT
        .macro  preempt_stop
@@ -48,6 +51,7 @@ resume_userspace:
 
 #ifdef CONFIG_PREEMPT
 resume_kernel:
+       local_irq_disable
        lw      t0, TI_PRE_COUNT($28)
        bnez    t0, restore_all
 need_resched:
@@ -57,12 +61,7 @@ need_resched:
        LONG_L  t0, PT_STATUS(sp)               # Interrupts off?
        andi    t0, 1
        beqz    t0, restore_all
-       li      t0, PREEMPT_ACTIVE
-       sw      t0, TI_PRE_COUNT($28)
-       local_irq_enable
-       jal     schedule
-       sw      zero, TI_PRE_COUNT($28)
-       local_irq_disable
+       jal     preempt_schedule_irq
        b       need_resched
 #endif
 
@@ -79,6 +78,37 @@ FEXPORT(syscall_exit)
        bnez    t0, syscall_exit_work
 
 FEXPORT(restore_all)                   # restore full frame
+#ifdef CONFIG_MIPS_MT_SMTC
+/* Detect and execute deferred IPI "interrupts" */
+       move    a0,sp
+       jal     deferred_smtc_ipi
+/* Re-arm any temporarily masked interrupts not explicitly "acked" */
+       mfc0    v0, CP0_TCSTATUS
+       ori     v1, v0, TCSTATUS_IXMT
+       mtc0    v1, CP0_TCSTATUS
+       andi    v0, TCSTATUS_IXMT
+       ehb
+       mfc0    t0, CP0_TCCONTEXT
+       DMT     9                               # dmt t1
+       jal     mips_ihb
+       mfc0    t2, CP0_STATUS
+       andi    t3, t0, 0xff00
+       or      t2, t2, t3
+       mtc0    t2, CP0_STATUS
+       ehb
+       andi    t1, t1, VPECONTROL_TE
+       beqz    t1, 1f
+       EMT
+1:
+       mfc0    v1, CP0_TCSTATUS
+       /* We set IXMT above, XOR should clear it here */
+       xori    v1, v1, TCSTATUS_IXMT
+       or      v1, v0, v1
+       mtc0    v1, CP0_TCSTATUS
+       ehb
+       xor     t0, t0, t3
+       mtc0    t0, CP0_TCCONTEXT
+#endif /* CONFIG_MIPS_MT_SMTC */
        .set    noat
        RESTORE_TEMP
        RESTORE_AT
@@ -109,7 +139,7 @@ work_notifysig:                             # deal with pending signals and
        move    a0, sp
        li      a1, 0
        jal     do_notify_resume        # a2 already loaded
-       j       restore_all
+       j       resume_userspace
 
 FEXPORT(syscall_exit_work_partial)
        SAVE_STATIC
@@ -124,28 +154,17 @@ syscall_exit_work:
        jal     do_syscall_trace
        b       resume_userspace
 
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT)
+
 /*
- * Common spurious interrupt handler.
+ * MIPS32R2 Instruction Hazard Barrier - must be called
+ *
+ * For C code use the inline version named instruction_hazard().
  */
-LEAF(spurious_interrupt)
-       /*
-        * Someone tried to fool us by sending an interrupt but we
-        * couldn't find a cause for it.
-        */
-       PTR_LA  t1, irq_err_count
-#ifdef CONFIG_SMP
-1:     ll      t0, (t1)
-       addiu   t0, 1
-       sc      t0, (t1)
-#if R10000_LLSC_WAR
-       beqzl   t0, 1b
-#else
-       beqz    t0, 1b
-#endif
-#else
-       lw      t0, (t1)
-       addiu   t0, 1
-       sw      t0, (t1)
-#endif
-       j       ret_from_irq
-       END(spurious_interrupt)
+LEAF(mips_ihb)
+       .set    mips32r2
+       jr.hb   ra
+       nop
+       END(mips_ihb)
+
+#endif /* CONFIG_CPU_MIPSR2 or CONFIG_MIPS_MT */