Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6

[linux-2.6-omap-h63xx.git] / arch / mips / kernel / traps.c

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index fa500787152d2cfbc40ffc38075f7ee7545ea103..fcae6675297273839812a4977c329ee6cb9e5899 100644 (file)
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1100,59 +1100,6 @@ void *set_except_vector(int n, void *addr)
        return (void *)old_handler;
 }
 
-#ifdef CONFIG_CPU_MIPSR2_SRS
-/*
- * MIPSR2 shadow register set allocation
- * FIXME: SMP...
- */
-
-static struct shadow_registers {
-       /*
-        * Number of shadow register sets supported
-        */
-       unsigned long sr_supported;
-       /*
-        * Bitmap of allocated shadow registers
-        */
-       unsigned long sr_allocated;
-} shadow_registers;
-
-static void mips_srs_init(void)
-{
-       shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
-       printk(KERN_INFO "%ld MIPSR2 register sets available\n",
-              shadow_registers.sr_supported);
-       shadow_registers.sr_allocated = 1;      /* Set 0 used by kernel */
-}
-
-int mips_srs_max(void)
-{
-       return shadow_registers.sr_supported;
-}
-
-int mips_srs_alloc(void)
-{
-       struct shadow_registers *sr = &shadow_registers;
-       int set;
-
-again:
-       set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
-       if (set >= sr->sr_supported)
-               return -1;
-
-       if (test_and_set_bit(set, &sr->sr_allocated))
-               goto again;
-
-       return set;
-}
-
-void mips_srs_free(int set)
-{
-       struct shadow_registers *sr = &shadow_registers;
-
-       clear_bit(set, &sr->sr_allocated);
-}
-
 static asmlinkage void do_default_vi(void)
 {
        show_regs(get_irq_regs());
@@ -1163,6 +1110,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
 {
        unsigned long handler;
        unsigned long old_handler = vi_handlers[n];
+       int srssets = current_cpu_data.srsets;
        u32 *w;
        unsigned char *b;
 
@@ -1178,7 +1126,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
 
        b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
 
-       if (srs >= mips_srs_max())
+       if (srs >= srssets)
                panic("Shadow register set %d not supported", srs);
 
        if (cpu_has_veic) {
@@ -1186,7 +1134,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
                        board_bind_eic_interrupt(n, srs);
        } else if (cpu_has_vint) {
                /* SRSMap is only defined if shadow sets are implemented */
-               if (mips_srs_max() > 1)
+               if (srssets > 1)
                        change_c0_srsmap(0xf << n*4, srs << n*4);
        }
 
@@ -1253,14 +1201,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
        return set_vi_srs_handler(n, addr, 0);
 }
 
-#else
-
-static inline void mips_srs_init(void)
-{
-}
-
-#endif /* CONFIG_CPU_MIPSR2_SRS */
-
 /*
  * This is used by native signal handling
  */
@@ -1377,12 +1317,12 @@ void __init per_cpu_trap_init(void)
 #endif
        if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
                status_set |= ST0_XX;
+       if (cpu_has_dsp)
+               status_set |= ST0_MX;
+
        change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
                         status_set);
 
-       if (cpu_has_dsp)
-               set_c0_status(ST0_MX);
-
 #ifdef CONFIG_CPU_MIPSR2
        if (cpu_has_mips_r2) {
                unsigned int enable = 0x0000000f;
@@ -1503,8 +1443,6 @@ void __init trap_init(void)
        else
                ebase = CAC_BASE;
 
-       mips_srs_init();
-
        per_cpu_trap_init();
 
        /*