static inline void build_src_pref(int advance)
{
- if (!(load_offset & (cpu_dcache_line_size() - 1))) {
+ if (!(load_offset & (cpu_dcache_line_size() - 1)) && advance) {
union mips_instruction mi;
mi.i_format.opcode = pref_op;
static inline void build_dst_pref(int advance)
{
- if (!(store_offset & (cpu_dcache_line_size() - 1))) {
+ if (!(store_offset & (cpu_dcache_line_size() - 1)) && advance) {
union mips_instruction mi;
mi.i_format.opcode = pref_op;
if (cpu_has_prefetch) {
switch (current_cpu_data.cputype) {
+ case CPU_TX49XX:
+ /* TX49 supports only Pref_Load */
+ pref_offset_clear = 0;
+ pref_offset_copy = 0;
+ break;
+
case CPU_RM9000:
/*
* As a workaround for erratum G105 which make the
case CPU_R10000:
case CPU_R12000:
+ case CPU_R14000:
pref_src_mode = Pref_LoadStreamed;
pref_dst_mode = Pref_StoreStreamed;
break;