idx = read_c0_index();
ptep = pte_offset_map(pmdp, address);
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
write_c0_entrylo0(ptep->pte_high);
ptep++;
write_c0_entrylo1(ptep->pte_high);
* lifetime of the system
*/
-static int temp_tlb_entry __initdata;
+static int temp_tlb_entry __cpuinitdata;
__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
unsigned long entryhi, unsigned long pagemask)
return ret;
}
-static void __init probe_tlb(unsigned long config)
+static void __cpuinit probe_tlb(unsigned long config)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
unsigned int reg;
c->tlbsize = ((reg >> 25) & 0x3f) + 1;
}
-static int __initdata ntlb = 0;
+static int __cpuinitdata ntlb = 0;
static int __init set_ntlb(char *str)
{
get_option(&str, &ntlb);
__setup("ntlb=", set_ntlb);
-void __init tlb_init(void)
+void __cpuinit tlb_init(void)
{
unsigned int config = read_c0_config();
* - On R4600 1.7 the tlbp never hits for pages smaller than
* the value in the c0_pagemask register.
* - The entire mm handling assumes the c0_pagemask register to
- * be set for 4kb pages.
+ * be set to fixed-size pages.
*/
probe_tlb(config);
write_c0_pagemask(PM_DEFAULT_MASK);
int wired = current_cpu_data.tlbsize - ntlb;
write_c0_wired(wired);
write_c0_index(wired-1);
- printk ("Restricting TLB to %d entries\n", ntlb);
+ printk("Restricting TLB to %d entries\n", ntlb);
} else
printk("Ignoring invalid argument ntlb=%d\n", ntlb);
}