#define DCRN_CPC0_PLLMR 0xb0
#define DCRN_405_CPC0_CR0 0xb1
#define DCRN_405_CPC0_CR1 0xb2
+#define DCRN_405_CPC0_PSR 0xb4
+/* 405EP Clocking/Power Management/Chip Control regs */
+#define DCRN_CPC0_PLLMR0 0xf0
+#define DCRN_CPC0_PLLMR1 0xf4
+#define DCRN_CPC0_UCR 0xf5
/* 440GX Clock control etc */