Merge git://git.kernel.org/pub/scm/linux/kernel/git/steve/gfs2-2.6-nmw

[linux-2.6-omap-h63xx.git] / arch / s390 / kernel / head64.S

diff --git a/arch/s390/kernel/head64.S b/arch/s390/kernel/head64.S
index a87b1976d409e3b94a7972998379731d08bcab6a..1d06961e87b328ec1bb27eb019c660194fda58f3 100644 (file)
--- a/arch/s390/kernel/head64.S
+++ b/arch/s390/kernel/head64.S
@@ -125,73 +125,11 @@ startup_continue:
 # and create a kernel NSS if the SAVESYS= parm is defined
 #
        brasl   %r14,startup_init
-                                       # set program check new psw mask
-       mvc     __LC_PGM_NEW_PSW(8),.Lpcmsk-.LPG1(%r13)
-       larl    %r12,machine_flags
-#
-# find out if we have the MVPG instruction
-#
-       la      %r1,0f-.LPG1(%r13)      # set program check address
-       stg     %r1,__LC_PGM_NEW_PSW+8
-       sgr     %r0,%r0
-       lghi    %r1,0
-       lghi    %r2,0
-       mvpg    %r1,%r2                 # test MVPG instruction
-       oi      7(%r12),16              # set MVPG flag
-0:
-
-#
-# find out if the diag 0x44 works in 64 bit mode
-#
-       la      %r1,0f-.LPG1(%r13)      # set program check address
-       stg     %r1,__LC_PGM_NEW_PSW+8
-       diag    0,0,0x44                # test diag 0x44
-       oi      7(%r12),32              # set diag44 flag
-0:
-
-#
-# find out if we have the IDTE instruction
-#
-       la      %r1,0f-.LPG1(%r13)      # set program check address
-       stg     %r1,__LC_PGM_NEW_PSW+8
-       .long   0xb2b10000              # store facility list
-       tm      0xc8,0x08               # check bit for clearing-by-ASCE
-       bno     0f-.LPG1(%r13)
-       lhi     %r1,2094
-       lhi     %r2,0
-       .long   0xb98e2001
-       oi      7(%r12),0x80            # set IDTE flag
-0:
-
-#
-# find out if the diag 0x9c is available
-#
-       la      %r1,0f-.LPG1(%r13)      # set program check address
-       stg     %r1,__LC_PGM_NEW_PSW+8
-       stap    __LC_CPUID+4            # store cpu address
-       lh      %r1,__LC_CPUID+4
-       diag    %r1,0,0x9c              # test diag 0x9c
-       oi      6(%r12),1               # set diag9c flag
-0:
-
-#
-# find out if we have the MVCOS instruction
-#
-       la      %r1,0f-.LPG1(%r13)      # set program check address
-       stg     %r1,__LC_PGM_NEW_PSW+8
-       .short  0xc800                  # mvcos 0(%r0),0(%r0),%r0
-       .short  0x0000
-       .short  0x0000
-0:     tm      0x8f,0x13               # special-operation exception?
-       bno     1f-.LPG1(%r13)          # if yes, MVCOS is present
-       oi      6(%r12),2               # set MVCOS flag
-1:
-
        lpswe   .Lentry-.LPG1(13)       # jump to _stext in primary-space,
                                        # virtual and never return ...
        .align  16
 .Lentry:.quad  0x0000000180000000,_stext
-.Lctl: .quad   0x04b50002              # cr0: various things
+.Lctl: .quad   0x04350002              # cr0: various things
        .quad   0                       # cr1: primary space segment table
        .quad   .Lduct                  # cr2: dispatchable unit control table
        .quad   0                       # cr3: instruction authorization