u64 range_length;
} __attribute__((packed));
+static int __initdata amd_iommu_detected;
+
u16 amd_iommu_last_bdf;
struct list_head amd_iommu_unity_map;
unsigned amd_iommu_aperture_order = 26;
void __init iommu_enable(struct amd_iommu *iommu)
{
- u32 ctrl;
-
printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at ");
print_devid(iommu->devid, 0);
printk(" cap 0x%hx\n", iommu->cap_ptr);
iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
- ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
}
static u8 * __init iommu_map_mmio_space(u64 address)
return 0;
}
+ if (!amd_iommu_detected)
+ return -ENODEV;
+
/*
* First parse ACPI tables to find the largest Bus/Dev/Func
* we need to handle. Upon this information the shared data
if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
iommu_detected = 1;
+ amd_iommu_detected = 1;
#ifdef CONFIG_GART_IOMMU
gart_iommu_aperture_disabled = 1;
gart_iommu_aperture = 0;