Disable NMI watchdog by default properly

[linux-2.6-omap-h63xx.git] / arch / x86_64 / kernel / nmi.c

diff --git a/arch/x86_64/kernel/nmi.c b/arch/x86_64/kernel/nmi.c
index 27e95e7922c16e6f2d637f9b677927cc049b989e..82d9d85d52709c2322392a5e33e5768b0c8dc085 100644 (file)
--- a/arch/x86_64/kernel/nmi.c
+++ b/arch/x86_64/kernel/nmi.c
@@ -172,7 +172,7 @@ static __cpuinit inline int nmi_known_cpu(void)
 {
        switch (boot_cpu_data.x86_vendor) {
        case X86_VENDOR_AMD:
-               return boot_cpu_data.x86 == 15;
+               return boot_cpu_data.x86 == 15 || boot_cpu_data.x86 == 16;
        case X86_VENDOR_INTEL:
                if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
                        return 1;
@@ -187,12 +187,11 @@ void nmi_watchdog_default(void)
 {
        if (nmi_watchdog != NMI_DEFAULT)
                return;
-       if (nmi_known_cpu())
-               nmi_watchdog = NMI_LOCAL_APIC;
-       else
-               nmi_watchdog = NMI_IO_APIC;
+       nmi_watchdog = NMI_NONE;
 }
 
+static int endflag __initdata = 0;
+
 #ifdef CONFIG_SMP
 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
  * the CPU is idle. To make sure the NMI watchdog really ticks on all
@@ -200,7 +199,6 @@ void nmi_watchdog_default(void)
  */
 static __init void nmi_cpu_busy(void *data)
 {
-       volatile int *endflag = data;
        local_irq_enable_in_hardirq();
        /* Intentionally don't use cpu_relax here. This is
           to make sure that the performance counter really ticks,
@@ -208,14 +206,30 @@ static __init void nmi_cpu_busy(void *data)
           pause instruction. On a real HT machine this is fine because
           all other CPUs are busy with "useless" delay loops and don't
           care if they get somewhat less cycles. */
-       while (*endflag == 0)
-               barrier();
+       while (endflag == 0)
+               mb();
 }
 #endif
 
+static unsigned int adjust_for_32bit_ctr(unsigned int hz)
+{
+       unsigned int retval = hz;
+
+       /*
+        * On Intel CPUs with ARCH_PERFMON only 32 bits in the counter
+        * are writable, with higher bits sign extending from bit 31.
+        * So, we can only program the counter with 31 bit values and
+        * 32nd bit should be 1, for 33.. to be 1.
+        * Find the appropriate nmi_hz
+        */
+       if ((((u64)cpu_khz * 1000) / retval) > 0x7fffffffULL) {
+               retval = ((u64)cpu_khz * 1000) / 0x7fffffffUL + 1;
+       }
+       return retval;
+}
+
 int __init check_nmi_watchdog (void)
 {
-       volatile int endflag = 0;
        int *counts;
        int cpu;
 
@@ -256,6 +270,7 @@ int __init check_nmi_watchdog (void)
        if (!atomic_read(&nmi_active)) {
                kfree(counts);
                atomic_set(&nmi_active, -1);
+               endflag = 1;
                return -1;
        }
        endflag = 1;
@@ -267,17 +282,8 @@ int __init check_nmi_watchdog (void)
                struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 
                nmi_hz = 1;
-               /*
-                * On Intel CPUs with ARCH_PERFMON only 32 bits in the counter
-                * are writable, with higher bits sign extending from bit 31.
-                * So, we can only program the counter with 31 bit values and
-                * 32nd bit should be 1, for 33.. to be 1.
-                * Find the appropriate nmi_hz
-                */
-               if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0 &&
-                       ((u64)cpu_khz * 1000) > 0x7fffffffULL) {
-                       nmi_hz = ((u64)cpu_khz * 1000) / 0x7fffffffUL + 1;
-               }
+               if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0)
+                       nmi_hz = adjust_for_32bit_ctr(nmi_hz);
        }
 
        kfree(counts);
@@ -301,8 +307,6 @@ int __init setup_nmi_watchdog(char *str)
        if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
                return 0;
 
-       if ((nmi == NMI_LOCAL_APIC) && (nmi_known_cpu() == 0))
-               return 0;  /* no lapic support */
        nmi_watchdog = nmi;
        return 1;
 }
@@ -361,6 +365,33 @@ void enable_timer_nmi_watchdog(void)
        }
 }
 
+static void __acpi_nmi_disable(void *__unused)
+{
+       apic_write(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED);
+}
+
+/*
+ * Disable timer based NMIs on all CPUs:
+ */
+void acpi_nmi_disable(void)
+{
+       if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
+               on_each_cpu(__acpi_nmi_disable, NULL, 0, 1);
+}
+
+static void __acpi_nmi_enable(void *__unused)
+{
+       apic_write(APIC_LVT0, APIC_DM_NMI);
+}
+
+/*
+ * Enable timer based NMIs on all CPUs:
+ */
+void acpi_nmi_enable(void)
+{
+       if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
+               on_each_cpu(__acpi_nmi_enable, NULL, 0, 1);
+}
 #ifdef CONFIG_PM
 
 static int nmi_pm_active; /* nmi_active before suspend */
@@ -635,7 +666,9 @@ static int setup_intel_arch_watchdog(void)
 
        /* setup the timer */
        wrmsr(evntsel_msr, evntsel, 0);
-       wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
+
+       nmi_hz = adjust_for_32bit_ctr(nmi_hz);
+       wrmsr(perfctr_msr, (u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
 
        apic_write(APIC_LVTPC, APIC_DM_NMI);
        evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
@@ -856,15 +889,23 @@ int __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
                                dummy &= ~P4_CCCR_OVF;
                                wrmsrl(wd->cccr_msr, dummy);
                                apic_write(APIC_LVTPC, APIC_DM_NMI);
+                               /* start the cycle over again */
+                               wrmsrl(wd->perfctr_msr,
+                                      -((u64)cpu_khz * 1000 / nmi_hz));
                        } else if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
                                /*
                                 * ArchPerfom/Core Duo needs to re-unmask
                                 * the apic vector
                                 */
                                apic_write(APIC_LVTPC, APIC_DM_NMI);
+                               /* ARCH_PERFMON has 32 bit counter writes */
+                               wrmsr(wd->perfctr_msr,
+                                    (u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
+                       } else {
+                               /* start the cycle over again */
+                               wrmsrl(wd->perfctr_msr,
+                                      -((u64)cpu_khz * 1000 / nmi_hz));
                        }
-                       /* start the cycle over again */
-                       wrmsrl(wd->perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
                        rc = 1;
                } else  if (nmi_watchdog == NMI_IO_APIC) {
                        /* don't know how to accurately check for this.