#include <linux/delay.h>
#include <linux/poll.h>
#include <linux/dma-mapping.h>
+#include <linux/mm.h>
#include <asm/uaccess.h>
#include <asm/semaphore.h>
return -ENOMEM;
}
- memset(&ab->descriptor, 0, sizeof ab->descriptor);
+ memset(&ab->descriptor, 0, sizeof(ab->descriptor));
ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
DESCRIPTOR_STATUS |
DESCRIPTOR_BRANCH_ALWAYS);
dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
- ctx->last_buffer->descriptor.branch_address = ab_bus | 1;
+ ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
ctx->last_buffer->next = ab;
ctx->last_buffer = ab;
ctx->current_buffer = ab.next;
ctx->pointer = ctx->current_buffer->data;
- reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab.descriptor.branch_address);
+ return 0;
+}
+
+static void ar_context_run(struct ar_context *ctx)
+{
+ struct ar_buffer *ab = ctx->current_buffer;
+ dma_addr_t ab_bus;
+ size_t offset;
+
+ offset = offsetof(struct ar_buffer, data);
+ ab_bus = ab->descriptor.data_address - offset;
+
+ reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
flush_writes(ctx->ohci);
-
- return 0;
}
static void context_tasklet(unsigned long data)
while (last->branch_address != 0) {
address = le32_to_cpu(last->branch_address);
z = address & 0xf;
- d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d;
+ d = ctx->buffer + (address - ctx->buffer_bus) / sizeof(*d);
last = (z == 2) ? d : d + z - 1;
if (!ctx->callback(ctx, d, last))
* element so that head == tail means buffer full.
*/
- memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor);
+ memset(ctx->head_descriptor, 0, sizeof(*ctx->head_descriptor));
ctx->head_descriptor->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
ctx->head_descriptor++;
d = ctx->head_descriptor;
tail = ctx->tail_descriptor;
- end = ctx->buffer + ctx->buffer_size / sizeof(struct descriptor);
+ end = ctx->buffer + ctx->buffer_size / sizeof(*d);
if (d + z <= tail) {
goto has_space;
return NULL;
has_space:
- memset(d, 0, z * sizeof *d);
- *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
+ memset(d, 0, z * sizeof(*d));
+ *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
return d;
}
{
dma_addr_t d_bus;
- d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
+ d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
ctx->head_descriptor = d + z + extra;
ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
fw_notify("swap not done yet\n");
fw_fill_response(&response, packet->header,
- RCODE_COMPLETE, &lock_old, sizeof lock_old);
+ RCODE_COMPLETE, &lock_old, sizeof(lock_old));
out:
fw_core_handle_response(&ohci->card, &response);
}
event = reg_read(ohci, OHCI1394_IntEventClear);
- if (!event)
+ if (!event || !~event)
return IRQ_NONE;
reg_write(ohci, OHCI1394_IntEventClear, event);
return IRQ_HANDLED;
}
+static int software_reset(struct fw_ohci *ohci)
+{
+ int i;
+
+ reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
+
+ for (i = 0; i < OHCI_LOOP_COUNT; i++) {
+ if ((reg_read(ohci, OHCI1394_HCControlSet) &
+ OHCI1394_HCControl_softReset) == 0)
+ return 0;
+ msleep(1);
+ }
+
+ return -EBUSY;
+}
+
static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
{
struct fw_ohci *ohci = fw_ohci(card);
struct pci_dev *dev = to_pci_dev(card->device);
+ if (software_reset(ohci)) {
+ fw_error("Failed to reset ohci card.\n");
+ return -EBUSY;
+ }
+
+ /*
+ * Now enable LPS, which we need in order to start accessing
+ * most of the registers. In fact, on some cards (ALI M5251),
+ * accessing registers in the SClk domain without LPS enabled
+ * will lock up the machine. Wait 50msec to make sure we have
+ * full link enabled.
+ */
+ reg_write(ohci, OHCI1394_HCControlSet,
+ OHCI1394_HCControl_LPS |
+ OHCI1394_HCControl_postedWriteEnable);
+ flush_writes(ohci);
+ msleep(50);
+
+ reg_write(ohci, OHCI1394_HCControlClear,
+ OHCI1394_HCControl_noByteSwapData);
+
+ reg_write(ohci, OHCI1394_LinkControlSet,
+ OHCI1394_LinkControl_rcvSelfID |
+ OHCI1394_LinkControl_cycleTimerEnable |
+ OHCI1394_LinkControl_cycleMaster);
+
+ reg_write(ohci, OHCI1394_ATRetries,
+ OHCI1394_MAX_AT_REQ_RETRIES |
+ (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
+ (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
+
+ ar_context_run(&ohci->ar_request_ctx);
+ ar_context_run(&ohci->ar_response_ctx);
+
+ reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
+ reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
+ reg_write(ohci, OHCI1394_IntEventClear, ~0);
+ reg_write(ohci, OHCI1394_IntMaskClear, ~0);
+ reg_write(ohci, OHCI1394_IntMaskSet,
+ OHCI1394_selfIDComplete |
+ OHCI1394_RQPkt | OHCI1394_RSPkt |
+ OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
+ OHCI1394_isochRx | OHCI1394_isochTx |
+ OHCI1394_masterIntEnable |
+ OHCI1394_cycle64Seconds);
+
+ /* Activate link_on bit and contender bit in our self ID packets.*/
+ if (ohci_update_phy_reg(card, 4, 0,
+ PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
+ return -EIO;
+
/*
* When the link is not yet enabled, the atomic config rom
* update mechanism described below in ohci_set_config_rom()
regs = OHCI1394_IsoRcvContextBase(index);
ctx = &list[index];
- memset(ctx, 0, sizeof *ctx);
+ memset(ctx, 0, sizeof(*ctx));
ctx->header_length = 0;
ctx->header = (void *) __get_free_page(GFP_KERNEL);
if (ctx->header == NULL)
z += payload_z;
/* Get header size in number of descriptors. */
- header_z = DIV_ROUND_UP(p->header_length, sizeof *d);
+ header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
if (d == NULL)
if (p->header_length > 0) {
d[2].req_count = cpu_to_le16(p->header_length);
- d[2].data_address = cpu_to_le32(d_bus + z * sizeof *d);
+ d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
memcpy(&d[z], p->header, p->header_length);
}
header_size = packet_count * (ctx->base.header_size + 4);
/* Get header size in number of descriptors. */
- header_z = DIV_ROUND_UP(header_size, sizeof *d);
+ header_z = DIV_ROUND_UP(header_size, sizeof(*d));
page = payload >> PAGE_SHIFT;
offset = payload & ~PAGE_MASK;
rest = p->payload_length;
db->first_size = cpu_to_le16(ctx->base.header_size + 4);
db->first_req_count = cpu_to_le16(header_size);
db->first_res_count = db->first_req_count;
- db->first_buffer = cpu_to_le32(d_bus + sizeof *db);
+ db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
if (offset + rest < PAGE_SIZE)
length = rest;
.stop_iso = ohci_stop_iso,
};
-static int software_reset(struct fw_ohci *ohci)
-{
- int i;
-
- reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
-
- for (i = 0; i < OHCI_LOOP_COUNT; i++) {
- if ((reg_read(ohci, OHCI1394_HCControlSet) &
- OHCI1394_HCControl_softReset) == 0)
- return 0;
- msleep(1);
- }
-
- return -EBUSY;
-}
-
-enum {
- CLEANUP_SELF_ID,
- CLEANUP_REGISTERS,
- CLEANUP_IOMEM,
- CLEANUP_DISABLE,
- CLEANUP_PUT_CARD,
-};
-
-static int cleanup(struct fw_ohci *ohci, int stage, int code)
-{
- struct pci_dev *dev = to_pci_dev(ohci->card.device);
-
- switch (stage) {
- case CLEANUP_SELF_ID:
- dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
- ohci->self_id_cpu, ohci->self_id_bus);
- case CLEANUP_REGISTERS:
- kfree(ohci->it_context_list);
- kfree(ohci->ir_context_list);
- pci_iounmap(dev, ohci->registers);
- case CLEANUP_IOMEM:
- pci_release_region(dev, 0);
- case CLEANUP_DISABLE:
- pci_disable_device(dev);
- case CLEANUP_PUT_CARD:
- fw_card_put(&ohci->card);
- }
-
- return code;
-}
-
static int __devinit
pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
{
struct fw_ohci *ohci;
u32 bus_options, max_receive, link_speed;
u64 guid;
- int error_code;
+ int err;
size_t size;
- ohci = kzalloc(sizeof *ohci, GFP_KERNEL);
+ ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
if (ohci == NULL) {
fw_error("Could not malloc fw_ohci data.\n");
return -ENOMEM;
fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
- if (pci_enable_device(dev)) {
+ err = pci_enable_device(dev);
+ if (err) {
fw_error("Failed to enable OHCI hardware.\n");
- return cleanup(ohci, CLEANUP_PUT_CARD, -ENODEV);
+ goto fail_put_card;
}
pci_set_master(dev);
tasklet_init(&ohci->bus_reset_tasklet,
bus_reset_tasklet, (unsigned long)ohci);
- if (pci_request_region(dev, 0, ohci_driver_name)) {
+ err = pci_request_region(dev, 0, ohci_driver_name);
+ if (err) {
fw_error("MMIO resource unavailable\n");
- return cleanup(ohci, CLEANUP_DISABLE, -EBUSY);
+ goto fail_disable;
}
ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
if (ohci->registers == NULL) {
fw_error("Failed to remap registers\n");
- return cleanup(ohci, CLEANUP_IOMEM, -ENXIO);
+ err = -ENXIO;
+ goto fail_iomem;
}
- if (software_reset(ohci)) {
- fw_error("Failed to reset ohci card.\n");
- return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY);
- }
-
- /*
- * Now enable LPS, which we need in order to start accessing
- * most of the registers. In fact, on some cards (ALI M5251),
- * accessing registers in the SClk domain without LPS enabled
- * will lock up the machine. Wait 50msec to make sure we have
- * full link enabled.
- */
- reg_write(ohci, OHCI1394_HCControlSet,
- OHCI1394_HCControl_LPS |
- OHCI1394_HCControl_postedWriteEnable);
- flush_writes(ohci);
- msleep(50);
-
- reg_write(ohci, OHCI1394_HCControlClear,
- OHCI1394_HCControl_noByteSwapData);
-
- reg_write(ohci, OHCI1394_LinkControlSet,
- OHCI1394_LinkControl_rcvSelfID |
- OHCI1394_LinkControl_cycleTimerEnable |
- OHCI1394_LinkControl_cycleMaster);
-
ar_context_init(&ohci->ar_request_ctx, ohci,
OHCI1394_AsReqRcvContextControlSet);
context_init(&ohci->at_response_ctx, ohci, AT_BUFFER_SIZE,
OHCI1394_AsRspTrContextControlSet, handle_at_packet);
- reg_write(ohci, OHCI1394_ATRetries,
- OHCI1394_MAX_AT_REQ_RETRIES |
- (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
- (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
-
reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
fw_error("Out of memory for it/ir contexts.\n");
- return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
+ err = -ENOMEM;
+ goto fail_registers;
}
/* self-id dma buffer allocation */
GFP_KERNEL);
if (ohci->self_id_cpu == NULL) {
fw_error("Out of memory for self ID buffer.\n");
- return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
+ err = -ENOMEM;
+ goto fail_registers;
}
- reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
- reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
- reg_write(ohci, OHCI1394_IntEventClear, ~0);
- reg_write(ohci, OHCI1394_IntMaskClear, ~0);
- reg_write(ohci, OHCI1394_IntMaskSet,
- OHCI1394_selfIDComplete |
- OHCI1394_RQPkt | OHCI1394_RSPkt |
- OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
- OHCI1394_isochRx | OHCI1394_isochTx |
- OHCI1394_masterIntEnable |
- OHCI1394_cycle64Seconds);
-
bus_options = reg_read(ohci, OHCI1394_BusOptions);
max_receive = (bus_options >> 12) & 0xf;
link_speed = bus_options & 0x7;
guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
reg_read(ohci, OHCI1394_GUIDLo);
- error_code = fw_card_add(&ohci->card, max_receive, link_speed, guid);
- if (error_code < 0)
- return cleanup(ohci, CLEANUP_SELF_ID, error_code);
+ err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
+ if (err < 0)
+ goto fail_self_id;
ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
return 0;
+
+ fail_self_id:
+ dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
+ ohci->self_id_cpu, ohci->self_id_bus);
+ fail_registers:
+ kfree(ohci->it_context_list);
+ kfree(ohci->ir_context_list);
+ pci_iounmap(dev, ohci->registers);
+ fail_iomem:
+ pci_release_region(dev, 0);
+ fail_disable:
+ pci_disable_device(dev);
+ fail_put_card:
+ fw_card_put(&ohci->card);
+
+ return err;
}
static void pci_remove(struct pci_dev *dev)
software_reset(ohci);
free_irq(dev->irq, ohci);
- cleanup(ohci, CLEANUP_SELF_ID, 0);
+ dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
+ ohci->self_id_cpu, ohci->self_id_bus);
+ kfree(ohci->it_context_list);
+ kfree(ohci->ir_context_list);
+ pci_iounmap(dev, ohci->registers);
+ pci_release_region(dev, 0);
+ pci_disable_device(dev);
+ fw_card_put(&ohci->card);
fw_notify("Removed fw-ohci device.\n");
}
+#ifdef CONFIG_PM
+static int pci_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ struct fw_ohci *ohci = pci_get_drvdata(pdev);
+ int err;
+
+ software_reset(ohci);
+ free_irq(pdev->irq, ohci);
+ err = pci_save_state(pdev);
+ if (err) {
+ fw_error("pci_save_state failed with %d", err);
+ return err;
+ }
+ err = pci_set_power_state(pdev, pci_choose_state(pdev, state));
+ if (err) {
+ fw_error("pci_set_power_state failed with %d", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static int pci_resume(struct pci_dev *pdev)
+{
+ struct fw_ohci *ohci = pci_get_drvdata(pdev);
+ int err;
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+ err = pci_enable_device(pdev);
+ if (err) {
+ fw_error("pci_enable_device failed with %d", err);
+ return err;
+ }
+
+ return ohci_enable(&ohci->card, ohci->config_rom, CONFIG_ROM_SIZE);
+}
+#endif
+
static struct pci_device_id pci_table[] = {
{ PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
{ }
.id_table = pci_table,
.probe = pci_probe,
.remove = pci_remove,
+#ifdef CONFIG_PM
+ .resume = pci_resume,
+ .suspend = pci_suspend,
+#endif
};
MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
MODULE_LICENSE("GPL");
+/* Provide a module alias so root-on-sbp2 initrds don't break. */
+#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
+MODULE_ALIAS("ohci1394");
+#endif
+
static int __init fw_ohci_init(void)
{
return pci_register_driver(&fw_ohci_pci_driver);
projects / linux-2.6-omap-h63xx.git / blobdiff