DBG(("%s(drive:%s)\n", __func__, drive->name));
- ret = __ide_dma_end(drive);
+ ret = ide_dma_end(drive);
pci_write_config_word(dev, reg, drive->drive_data);
* channel 0 here at least, but channel 1 has to be enabled by
* firmware or arch code. We still set both to 16 bits mode.
*/
-static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev)
+static unsigned int init_chipset_sl82c105(struct pci_dev *dev)
{
u32 val;
};
MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
-static struct pci_driver driver = {
+static struct pci_driver sl82c105_pci_driver = {
.name = "W82C105_IDE",
.id_table = sl82c105_pci_tbl,
.probe = sl82c105_init_one,
.remove = ide_pci_remove,
+ .suspend = ide_pci_suspend,
+ .resume = ide_pci_resume,
};
static int __init sl82c105_ide_init(void)
{
- return ide_pci_register_driver(&driver);
+ return ide_pci_register_driver(&sl82c105_pci_driver);
}
static void __exit sl82c105_ide_exit(void)
{
- pci_unregister_driver(&driver);
+ pci_unregister_driver(&sl82c105_pci_driver);
}
module_init(sl82c105_ide_init);