ARM: DaVinci: Update IO address pointer typechecking

[linux-2.6-omap-h63xx.git] / drivers / net / bnx2x.h

diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 98d6f85fdeb5164d8a25b3abf425e5372c25b8c6..fd705d1295a7b0ea78c27d79a905b5d21ba165cf 100644 (file)
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -40,20 +40,20 @@
 #define DP(__mask, __fmt, __args...) do { \
        if (bp->msglevel & (__mask)) \
                printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
-                       bp->dev?(bp->dev->name):"?", ##__args); \
+                       bp->dev ? (bp->dev->name) : "?", ##__args); \
        } while (0)
 
 /* errors debug print */
 #define BNX2X_DBG_ERR(__fmt, __args...) do { \
        if (bp->msglevel & NETIF_MSG_PROBE) \
                printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
-                       bp->dev?(bp->dev->name):"?", ##__args); \
+                       bp->dev ? (bp->dev->name) : "?", ##__args); \
        } while (0)
 
 /* for errors (never masked) */
 #define BNX2X_ERR(__fmt, __args...) do { \
        printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
-               bp->dev?(bp->dev->name):"?", ##__args); \
+               bp->dev ? (bp->dev->name) : "?", ##__args); \
        } while (0)
 
 /* before we have a dev->name use dev_info() */
@@ -121,16 +121,7 @@
 #define SHMEM_WR(bp, field, val)       REG_WR(bp, SHMEM_ADDR(bp, field), val)
 
 #define EMAC_RD(bp, reg)               REG_RD(bp, emac_base + reg)
-#define NIG_WR(reg, val)       REG_WR(bp, reg, val)
-#define EMAC_WR(reg, val)      REG_WR(bp, emac_base + reg, val)
-#define BMAC_WR(reg, val)      REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
-
-
-#define for_each_queue(bp, var)        for (var = 0; var < bp->num_queues; var++)
-
-#define for_each_nondefault_queue(bp, var) \
-                               for (var = 1; var < bp->num_queues; var++)
-#define is_multi(bp)           (bp->num_queues > 1)
+#define EMAC_WR(bp, reg, val)          REG_WR(bp, emac_base + reg, val)
 
 
 /* fast path */
@@ -160,11 +151,13 @@ struct sw_rx_page {
 #define PAGES_PER_SGE_SHIFT            0
 #define PAGES_PER_SGE                  (1 << PAGES_PER_SGE_SHIFT)
 
+#define BCM_RX_ETH_PAYLOAD_ALIGN       64
+
 /* SGE ring related macros */
 #define NUM_RX_SGE_PAGES               2
 #define RX_SGE_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
 #define MAX_RX_SGE_CNT                 (RX_SGE_CNT - 2)
-/* RX_SGE_CNT is promissed to be a power of 2 */
+/* RX_SGE_CNT is promised to be a power of 2 */
 #define RX_SGE_MASK                    (RX_SGE_CNT - 1)
 #define NUM_RX_SGE                     (RX_SGE_CNT * NUM_RX_SGE_PAGES)
 #define MAX_RX_SGE                     (NUM_RX_SGE - 1)
@@ -280,7 +273,7 @@ struct bnx2x_fastpath {
                         (fp->tx_pkt_prod != fp->tx_pkt_cons))
 
 #define BNX2X_HAS_RX_WORK(fp) \
-                       (fp->rx_comp_cons != le16_to_cpu(*fp->rx_cons_sb))
+                       (fp->rx_comp_cons != rx_cons_sb)
 
 #define BNX2X_HAS_WORK(fp)     (BNX2X_HAS_RX_WORK(fp) || BNX2X_HAS_TX_WORK(fp))
 
@@ -326,7 +319,7 @@ struct bnx2x_fastpath {
 #define RCQ_BD(x)                      ((x) & MAX_RCQ_BD)
 
 
-/* This is needed for determening of last_max */
+/* This is needed for determining of last_max */
 #define SUB_S16(a, b)                  (s16)((s16)(a) - (s16)(b))
 
 #define __SGE_MASK_SET_BIT(el, bit) \
@@ -759,8 +752,7 @@ struct bnx2x {
 
        u32                     rx_csum;
        u32                     rx_offset;
-       u32                     rx_buf_use_size;        /* useable size */
-       u32                     rx_buf_size;            /* with alignment */
+       u32                     rx_buf_size;
 #define ETH_OVREHEAD                   (ETH_HLEN + 8)  /* 8 for CRC + VLAN */
 #define ETH_MIN_PACKET_SIZE            60
 #define ETH_MAX_PACKET_SIZE            1500
@@ -793,7 +785,7 @@ struct bnx2x {
        u8                      stats_pending;
        u8                      set_mac_pending;
 
-       /* End of fileds used in the performance code paths */
+       /* End of fields used in the performance code paths */
 
        int                     panic;
        int                     msglevel;
@@ -815,9 +807,6 @@ struct bnx2x {
 #define BP_FUNC(bp)                    (bp->func)
 #define BP_E1HVN(bp)                   (bp->func >> 1)
 #define BP_L_ID(bp)                    (BP_E1HVN(bp) << 2)
-/* assorted E1HVN */
-#define IS_E1HMF(bp)                   (bp->e1hmf != 0)
-#define BP_MAX_QUEUES(bp)              (IS_E1HMF(bp) ? 4 : 16)
 
        int                     pm_cap;
        int                     pcie_cap;
@@ -842,6 +831,7 @@ struct bnx2x {
        u32                     mf_config;
        u16                     e1hov;
        u8                      e1hmf;
+#define IS_E1HMF(bp)                   (bp->e1hmf != 0)
 
        u8                      wol;
 
@@ -872,6 +862,7 @@ struct bnx2x {
 #define BNX2X_STATE_ERROR              0xf000
 
        int                     num_queues;
+#define BP_MAX_QUEUES(bp)              (IS_E1HMF(bp) ? 4 : 16)
 
        u32                     rx_mode;
 #define BNX2X_RX_MODE_NONE             0
@@ -922,6 +913,13 @@ struct bnx2x {
 };
 
 
+#define for_each_queue(bp, var)        for (var = 0; var < bp->num_queues; var++)
+
+#define for_each_nondefault_queue(bp, var) \
+                               for (var = 1; var < bp->num_queues; var++)
+#define is_multi(bp)           (bp->num_queues > 1)
+
+
 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
                      u32 len32);
@@ -1027,10 +1025,10 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
 /* resolution of the rate shaping timer - 100 usec */
 #define RS_PERIODIC_TIMEOUT_USEC       100
 /* resolution of fairness algorithm in usecs -
-   coefficient for clauclating the actuall t fair */
+   coefficient for calculating the actual t fair */
 #define T_FAIR_COEF                    10000000
 /* number of bytes in single QM arbitration cycle -
-   coeffiecnt for calculating the fairness timer */
+   coefficient for calculating the fairness timer */
 #define QM_ARB_BYTES                   40000
 #define FAIR_MEM                       2