MLX4_MTT_ENTRY_PER_SEG = 8
};
-enum {
- MLX4_EQ_ASYNC,
- MLX4_EQ_COMP,
- MLX4_NUM_EQ
-};
-
enum {
MLX4_NUM_PDS = 1 << 15
};
struct mlx4_eq_table {
struct mlx4_bitmap bitmap;
+ char *irq_names;
void __iomem *clr_int;
- void __iomem *uar_map[(MLX4_NUM_EQ + 6) / 4];
+ void __iomem **uar_map;
u32 clr_mask;
- struct mlx4_eq eq[MLX4_NUM_EQ];
+ struct mlx4_eq *eq;
u64 icm_virt;
struct page *icm_page;
dma_addr_t icm_dma;
int mlx4_reset(struct mlx4_dev *dev);
+int mlx4_alloc_eq_table(struct mlx4_dev *dev);
+void mlx4_free_eq_table(struct mlx4_dev *dev);
+
int mlx4_init_pd_table(struct mlx4_dev *dev);
int mlx4_init_uar_table(struct mlx4_dev *dev);
int mlx4_init_mr_table(struct mlx4_dev *dev);