Merge git://git.infradead.org/mtd-2.6

[linux-2.6-omap-h63xx.git] / drivers / net / sky2.h

diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index ac24bdc429761da6f584259b5ef4f4f6337c571f..b8c4a3b5eadf9812f7bede24ebeeb20f76a41e6b 100644 (file)
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -288,6 +288,9 @@ enum {
                          | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1,
        Y2_IS_PORT_2    = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2
                          | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
+       Y2_IS_ERROR     = Y2_IS_HW_ERR |
+                         Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 |
+                         Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
 };
 
 /*     B2_IRQM_HWE_MSK 32 bit  IRQ Moderation HW Error Mask */
@@ -738,6 +741,11 @@ enum {
        TX_GMF_RP       = 0x0d70,/* 32 bit      Tx GMAC FIFO Read Pointer */
        TX_GMF_RSTP     = 0x0d74,/* 32 bit      Tx GMAC FIFO Restart Pointer */
        TX_GMF_RLEV     = 0x0d78,/* 32 bit      Tx GMAC FIFO Read Level */
+
+       /* Threshold values for Yukon-EC Ultra and Extreme */
+       ECU_AE_THR      = 0x0070, /* Almost Empty Threshold */
+       ECU_TXFF_LEV    = 0x01a0, /* Tx BMU FIFO Level */
+       ECU_JUMBO_WM    = 0x0080, /* Jumbo Mode Watermark */
 };
 
 /* Descriptor Poll Timer Registers */
@@ -1141,7 +1149,7 @@ enum {
        PHY_M_IS_JABBER         = 1<<0, /* Jabber */
 
        PHY_M_DEF_MSK           = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
-                                | PHY_M_IS_FIFO_ERROR,
+                                | PHY_M_IS_DUP_CHANGE,
        PHY_M_AN_MSK           = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
 };
 
@@ -1631,6 +1639,9 @@ enum {
        TX_VLAN_TAG_ON  = 1<<25,/* enable  VLAN tagging */
        TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
 
+       TX_JUMBO_ENA    = 1<<23,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
+       TX_JUMBO_DIS    = 1<<22,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
+
        GMF_WSP_TST_ON  = 1<<18,/* Write Shadow Pointer Test On */
        GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
        GMF_WSP_STEP    = 1<<16,/* Write Shadow Pointer Step/Increment */
@@ -1721,28 +1732,6 @@ enum {
 
 /*     GPHY_CTRL               32 bit  GPHY Control Reg (YUKON only) */
 enum {
-       GPC_SEL_BDT     = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
-       GPC_INT_POL_HI  = 1<<27, /* IRQ Polarity is Active HIGH */
-       GPC_75_OHM      = 1<<26, /* Use 75 Ohm Termination instead of 50 */
-       GPC_DIS_FC      = 1<<25, /* Disable Automatic Fiber/Copper Detection */
-       GPC_DIS_SLEEP   = 1<<24, /* Disable Energy Detect */
-       GPC_HWCFG_M_3   = 1<<23, /* HWCFG_MODE[3] */
-       GPC_HWCFG_M_2   = 1<<22, /* HWCFG_MODE[2] */
-       GPC_HWCFG_M_1   = 1<<21, /* HWCFG_MODE[1] */
-       GPC_HWCFG_M_0   = 1<<20, /* HWCFG_MODE[0] */
-       GPC_ANEG_0      = 1<<19, /* ANEG[0] */
-       GPC_ENA_XC      = 1<<18, /* Enable MDI crossover */
-       GPC_DIS_125     = 1<<17, /* Disable 125 MHz clock */
-       GPC_ANEG_3      = 1<<16, /* ANEG[3] */
-       GPC_ANEG_2      = 1<<15, /* ANEG[2] */
-       GPC_ANEG_1      = 1<<14, /* ANEG[1] */
-       GPC_ENA_PAUSE   = 1<<13, /* Enable Pause (SYM_OR_REM) */
-       GPC_PHYADDR_4   = 1<<12, /* Bit 4 of Phy Addr */
-       GPC_PHYADDR_3   = 1<<11, /* Bit 3 of Phy Addr */
-       GPC_PHYADDR_2   = 1<<10, /* Bit 2 of Phy Addr */
-       GPC_PHYADDR_1   = 1<<9,  /* Bit 1 of Phy Addr */
-       GPC_PHYADDR_0   = 1<<8,  /* Bit 0 of Phy Addr */
-                                               /* Bits  7..2:  reserved */
        GPC_RST_CLR     = 1<<1, /* Clear GPHY Reset */
        GPC_RST_SET     = 1<<0, /* Set   GPHY Reset */
 };