B0_IMSK = 0x000c,
B0_HWE_ISRC = 0x0010,
B0_HWE_IMSK = 0x0014,
- B0_SP_ISRC = 0x0018,
- B0_XM1_IMSK = 0x0020,
- B0_XM1_ISRC = 0x0028,
- B0_XM1_PHY_ADDR = 0x0030,
- B0_XM1_PHY_DATA = 0x0034,
- B0_XM2_IMSK = 0x0040,
- B0_XM2_ISRC = 0x0048,
- B0_XM2_PHY_ADDR = 0x0050,
- B0_XM2_PHY_DATA = 0x0054,
- B0_R1_CSR = 0x0060,
- B0_R2_CSR = 0x0064,
- B0_XS1_CSR = 0x0068,
- B0_XA1_CSR = 0x006c,
- B0_XS2_CSR = 0x0070,
- B0_XA2_CSR = 0x0074,
/* Special ISR registers (Yukon-2 only) */
B0_Y2_SP_ISRC2 = 0x001c,
B2_MAC_CFG = 0x011a,
B2_CHIP_ID = 0x011b,
B2_E_0 = 0x011c,
- B2_E_1 = 0x011d,
- B2_E_2 = 0x011e,
+
B2_Y2_CLK_GATE = 0x011d,
B2_Y2_HW_RES = 0x011e,
B2_E_3 = 0x011f,
B2_Y2_CLK_CTRL = 0x0120,
- B2_LD_CTRL = 0x0128,
- B2_LD_TEST = 0x0129,
+
B2_TI_INI = 0x0130,
B2_TI_VAL = 0x0134,
B2_TI_CTRL = 0x0138,
B2_TI_TEST = 0x0139,
- B2_IRQM_INI = 0x0140,
- B2_IRQM_VAL = 0x0144,
- B2_IRQM_CTRL = 0x0148,
- B2_IRQM_TEST = 0x0149,
- B2_IRQM_MSK = 0x014c,
- B2_IRQM_HWE_MSK = 0x0150,
+
B2_TST_CTRL1 = 0x0158,
B2_TST_CTRL2 = 0x0159,
B2_GP_IO = 0x015c,
+
B2_I2C_CTRL = 0x0160,
B2_I2C_DATA = 0x0164,
B2_I2C_IRQ = 0x0168,
B2_I2C_SW = 0x016c,
- B2_BSC_INI = 0x0170,
- B2_BSC_VAL = 0x0174,
- B2_BSC_CTRL = 0x0178,
- B2_BSC_STAT = 0x0179,
- B2_BSC_TST = 0x017a,
B3_RAM_ADDR = 0x0180,
B3_RAM_DATA_LO = 0x0184,
Y2_CFG_SPC = 0x1c00,
};
-/* Access pci config through board I/O */
-#define PCI_C(x) (Y2_CFG_SPC + (x))
-
-
/* B0_CTST 16 bit Control/Status register */
enum {
- Y2_VMAIN_AVAIL = 1<<17, /* VMAIN available (YUKON-2 only) */
+ Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
- CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
- CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
CS_STOP_DONE = 1<<5, /* Stop Master is finished */
CS_MRST_SET = 1<<2, /* Set Master reset */
CS_RST_CLR = 1<<1, /* Clear Software reset */
CS_RST_SET = 1, /* Set Software reset */
+};
/* B0_LED 8 Bit LED register */
+enum {
/* Bit 7.. 2: reserved */
LED_STAT_ON = 1<<1, /* Status LED on */
- LED_STAT_OFF = 1, /* Status LED off */
+ LED_STAT_OFF = 1, /* Status LED off */
+};
/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
+enum {
PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
- Y2_HWE_ALL_MASK = Y2_IS_SENSOR | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
- Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP |
+ Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
+ Y2_IS_PCI_EXP |
Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
};
CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
+ CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
enum {
- Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactiv (0 = activ) */
+ Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
- Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactiv (0 = activ) */
+ Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
/* RAM Interface Registers */
-/* B3_RI_CTRL 16 bit RAM Iface Control Register */
+/* B3_RI_CTRL 16 bit RAM Interface Control Register */
enum {
RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
-
+ RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
+ RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
- BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segmen. error (Tx) */
+ BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
BMU_START = 1<<8, /* Start Rx/Tx Queue */
BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
BMU_FIFO_ENA | BMU_OP_ON,
+
+ BMU_WM_DEFAULT = 0x600,
};
/* Tx BMU Control / Status Registers (Yukon-2) */
enum {
BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
- BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segm. length mism. */
+ BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
};
/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
-
- ST_LAST_IDX_MASK = 0x007f,/* Last Index Mask */
- ST_TXRP_IDX_MASK = 0x0fff,/* Tx Report Index Mask */
- ST_TXTH_IDX_MASK = 0x0fff,/* Tx Threshold Index Mask */
- ST_WM_IDX_MASK = 0x3f,/* FIFO Watermark Index Mask */
};
enum {
/* WOL Pattern Counter Registers (YUKON only) */
+
WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
};
/* Receive Frame Status Encoding */
enum {
GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
- GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */
- GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */
- GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
- GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */
- GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */
- GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */
- GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
- GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
- GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
- GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */
- GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */
-
- GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */
- GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */
+ GMR_FS_VLAN = 1<<13, /* VLAN Packet */
+ GMR_FS_JABBER = 1<<12, /* Jabber Packet */
+ GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
+ GMR_FS_MC = 1<<10, /* Multicast Packet */
+ GMR_FS_BC = 1<<9, /* Broadcast Packet */
+ GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
+ GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
+ GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
+ GMR_FS_MII_ERR = 1<<5, /* MII Error */
+ GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
+ GMR_FS_FRAGMENT = 1<<3, /* Fragment */
+
+ GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
+ GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
-/*
- * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
- */
GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
GMR_FS_UN_SIZE | GMR_FS_JABBER,
-/* Rx GMAC FIFO Flush Mask (default) */
- RX_FF_FL_DEF_MSK = GMR_FS_ANY_ERR,
};
/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
enum {
+ RX_TRUNC_ON = 1<<27, /* enable packet truncation */
+ RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
+ RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
+ RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
+
GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
- GMF_CLI_RX_FC = 1<<4, /* Clear IRQ Rx Frame Complete */
+ GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
+
GMF_OPER_ON = 1<<3, /* Operational Mode On */
GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
+
+ GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
};
/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
enum {
+ TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
+ TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */
+
+ TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
+ TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
+
GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
-#define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV |\
- GM_IS_TX_FF_UR | GM_IS_RX_FF_OR)
+#define GMAC_DEF_MSK GM_IS_TX_FF_UR
/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
/* Bits 15.. 2: reserved */
OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
OP_RSS_HASH = 0x65,
OP_TXINDEXLE = 0x68,
-
-/* YUKON-2 SPECIAL opcodes defines */
- OP_PUTIDX = 0x70,
};
/* Yukon 2 hardware interface
*/
struct sky2_tx_le {
union {
- u32 addr;
+ __le32 addr;
struct {
- u16 offset;
- u16 start;
- } csum;
+ __le16 offset;
+ __le16 start;
+ } csum __attribute((packed));
struct {
- u16 size;
- u16 rsvd;
- } tso;
+ __le16 size;
+ __le16 rsvd;
+ } tso __attribute((packed));
} tx;
- u16 length; /* also vlan tag or checksum start */
+ __le16 length; /* also vlan tag or checksum start */
u8 ctrl;
u8 opcode;
-};
+} __attribute((packed));
struct sky2_rx_le {
- union {
- u32 addr;
- struct {
- u16 start1;
- u16 start2;
- } csum;
- } rx;
- u16 length;
+ __le32 addr;
+ __le16 length;
u8 ctrl;
u8 opcode;
-};
+} __attribute((packed));;
struct sky2_status_le {
- u32 status; /* also checksum */
- u16 length; /* also vlan tag */
+ __le32 status; /* also checksum */
+ __le16 length; /* also vlan tag */
u8 link;
u8 opcode;
-};
+} __attribute((packed));
+struct tx_ring_info {
+ struct sk_buff *skb;
+ DECLARE_PCI_UNMAP_ADDR(mapaddr);
+ u16 idx;
+};
struct ring_info {
struct sk_buff *skb;
- DECLARE_PCI_UNMAP_ADDR(mapaddr);
- DECLARE_PCI_UNMAP_LEN(maplen);
+ dma_addr_t mapaddr;
};
struct sky2_port {
- struct sky2_hw *hw ____cacheline_aligned;
+ struct sky2_hw *hw;
struct net_device *netdev;
unsigned port;
u32 msg_enable;
- struct ring_info *tx_ring ____cacheline_aligned;
+ spinlock_t tx_lock ____cacheline_aligned_in_smp;
+ struct tx_ring_info *tx_ring;
struct sky2_tx_le *tx_le;
- spinlock_t tx_lock;
u16 tx_cons; /* next le to check */
u16 tx_prod; /* next le to use */
+ u32 tx_addr64;
+ u16 tx_pending;
u16 tx_last_put;
+ u16 tx_last_mss;
- struct ring_info *rx_ring ____cacheline_aligned;
+ struct ring_info *rx_ring ____cacheline_aligned_in_smp;
struct sky2_rx_le *rx_le;
- u16 rx_ring_size;
+ u32 rx_addr64;
u16 rx_next; /* next re to check */
u16 rx_put; /* next le index to use */
+ u16 rx_pending;
u16 rx_last_put;
+ u16 rx_bufsize;
+#ifdef SKY2_VLAN_TAG_USED
+ u16 rx_tag;
+ struct vlan_group *vlgrp;
+#endif
dma_addr_t rx_le_map;
dma_addr_t tx_le_map;
u8 rx_csum;
u8 wol;
- struct tasklet_struct phy_task;
struct net_device_stats net_stats;
+
+ struct work_struct phy_task;
+ struct semaphore phy_sema;
};
struct sky2_hw {
u32 intr_mask;
struct net_device *dev[2];
+ int pm_cap;
+ int msi;
u8 chip_id;
u8 chip_rev;
u8 copper;
struct sky2_status_le *st_le;
u32 st_idx;
dma_addr_t st_dma;
-
- spinlock_t phy_lock;
};
/* Register accessor for memory mapped device */
return readb(hw->regs + reg);
}
-static inline int is_pciex(const struct sky2_hw *hw)
-{
- return (sky2_read32(hw, PCI_C(PCI_DEV_STATUS)) & PCI_OS_PCI_X) == 0;
-}
-
-
static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
{
writel(val, hw->regs + reg);
projects / linux-2.6-omap-h63xx.git / blobdiff