[TG3]: Add A1 revs

[linux-2.6-omap-h63xx.git] / drivers / net / tg3.c

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index b865c5d448378d1fa2aa0ecd9c540092c2507a98..8e76092a171ec2fc6396f1a889e8f83f06f32254 100644 (file)
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1106,8 +1106,7 @@ static int tg3_phy_reset(struct tg3 *tp)
        if (err)
                return err;
 
-       if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
-           tp->pci_chip_rev_id == CHIPREV_ID_5761_A0) {
+       if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
                u32 val;
 
                val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
@@ -1117,6 +1116,12 @@ static int tg3_phy_reset(struct tg3 *tp)
                        udelay(40);
                        tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
                }
+
+               /* Disable GPHY autopowerdown. */
+               tg3_writephy(tp, MII_TG3_MISC_SHDW,
+                            MII_TG3_MISC_SHDW_WREN |
+                            MII_TG3_MISC_SHDW_APD_SEL |
+                            MII_TG3_MISC_SHDW_APD_WKTM_84MS);
        }
 
 out:
@@ -1346,8 +1351,7 @@ static void tg3_power_down_phy(struct tg3 *tp)
             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
                return;
 
-       if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
-           tp->pci_chip_rev_id == CHIPREV_ID_5761_A0) {
+       if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
                val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
                val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
                val |= CPMU_LSPD_1000MB_MACCLK_12_5;
@@ -3148,6 +3152,23 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
                err = tg3_setup_copper_phy(tp, force_reset);
        }
 
+       if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
+           tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
+               u32 val, scale;
+
+               val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
+               if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
+                       scale = 65;
+               else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
+                       scale = 6;
+               else
+                       scale = 12;
+
+               val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
+               val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
+               tw32(GRC_MISC_CFG, val);
+       }
+
        if (tp->link_config.active_speed == SPEED_1000 &&
            tp->link_config.active_duplex == DUPLEX_HALF)
                tw32(MAC_TX_LENGTHS,
@@ -5076,12 +5097,15 @@ static void tg3_restore_pci_state(struct tg3 *tp)
 
        pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
+       if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
+               pcie_set_readrq(tp->pdev, 4096);
+       else {
                pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
                                      tp->pci_cacheline_sz);
                pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
                                      tp->pci_lat_timer);
        }
+
        /* Make sure PCI-X relaxed ordering bit is clear. */
        if (tp->pcix_cap) {
                u16 pcix_cmd;
@@ -6365,7 +6389,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 
        tg3_write_sig_legacy(tp, RESET_KIND_INIT);
 
-       if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0) {
+       if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
+           tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
                val = tr32(TG3_CPMU_CTRL);
                val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
                tw32(TG3_CPMU_CTRL, val);
@@ -8701,7 +8726,9 @@ static void tg3_get_ethtool_stats (struct net_device *dev,
 }
 
 #define NVRAM_TEST_SIZE 0x100
-#define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
+#define NVRAM_SELFBOOT_FORMAT1_0_SIZE  0x14
+#define NVRAM_SELFBOOT_FORMAT1_2_SIZE  0x18
+#define NVRAM_SELFBOOT_FORMAT1_3_SIZE  0x1c
 #define NVRAM_SELFBOOT_HW_SIZE 0x20
 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
 
@@ -8716,9 +8743,22 @@ static int tg3_test_nvram(struct tg3 *tp)
        if (magic == TG3_EEPROM_MAGIC)
                size = NVRAM_TEST_SIZE;
        else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
-               if ((magic & 0xe00000) == 0x200000)
-                       size = NVRAM_SELFBOOT_FORMAT1_SIZE;
-               else
+               if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
+                   TG3_EEPROM_SB_FORMAT_1) {
+                       switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
+                       case TG3_EEPROM_SB_REVISION_0:
+                               size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
+                               break;
+                       case TG3_EEPROM_SB_REVISION_2:
+                               size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
+                               break;
+                       case TG3_EEPROM_SB_REVISION_3:
+                               size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
+                               break;
+                       default:
+                               return 0;
+                       }
+               } else
                        return 0;
        } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
                size = NVRAM_SELFBOOT_HW_SIZE;
@@ -8745,8 +8785,17 @@ static int tg3_test_nvram(struct tg3 *tp)
            TG3_EEPROM_MAGIC_FW) {
                u8 *buf8 = (u8 *) buf, csum8 = 0;
 
-               for (i = 0; i < size; i++)
-                       csum8 += buf8[i];
+               if ((cpu_to_be32(buf[0]) & TG3_EEPROM_SB_REVISION_MASK) ==
+                   TG3_EEPROM_SB_REVISION_2) {
+                       /* For rev 2, the csum doesn't include the MBA. */
+                       for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
+                               csum8 += buf8[i];
+                       for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
+                               csum8 += buf8[i];
+               } else {
+                       for (i = 0; i < size; i++)
+                               csum8 += buf8[i];
+               }
 
                if (csum8 == 0) {
                        err = 0;
@@ -9330,7 +9379,7 @@ static int tg3_test_loopback(struct tg3 *tp)
        if (err)
                return TG3_LOOPBACK_FAILED;
 
-       if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
+       if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
                int i;
                u32 status;
 
@@ -9347,17 +9396,17 @@ static int tg3_test_loopback(struct tg3 *tp)
                if (status != CPMU_MUTEX_GNT_DRIVER)
                        return TG3_LOOPBACK_FAILED;
 
-               cpmuctrl = tr32(TG3_CPMU_CTRL);
-
                /* Turn off power management based on link speed. */
+               cpmuctrl = tr32(TG3_CPMU_CTRL);
                tw32(TG3_CPMU_CTRL,
-                    cpmuctrl & ~CPMU_CTRL_LINK_SPEED_MODE);
+                    cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
+                                 CPMU_CTRL_LINK_AWARE_MODE));
        }
 
        if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
                err |= TG3_MAC_LOOPBACK_FAILED;
 
-       if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
+       if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
                tw32(TG3_CPMU_CTRL, cpmuctrl);
 
                /* Release the mutex */
@@ -10578,6 +10627,10 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
                    tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
                        tp->led_ctrl = LED_CTRL_MODE_PHY_2;
 
+               if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
+                   tp->pci_chip_rev_id == CHIPREV_ID_5784_A1)
+                       tp->led_ctrl = LED_CTRL_MODE_MAC;
+
                if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
                        tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
                        if ((tp->pdev->subsystem_vendor ==
@@ -11164,6 +11217,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
        pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
        if (pcie_cap != 0) {
                tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
+
+               pcie_set_readrq(tp->pdev, 4096);
+
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
                        u16 lnkctl;
 
@@ -11344,9 +11400,16 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
        }
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
                tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
 
+               if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
+                   tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
+                   tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
+                   tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
+                       tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
+       }
+
        /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
         * GPIO1 driven high will bring 5700's external PHY out of reset.
         * It is also used as eeprom write protect on LOMs.