[SCSI] qla2xxx: Drop legacy 'bypass lun scan for tape device' code.

[linux-2.6-omap-h63xx.git] / drivers / scsi / qla2xxx / qla_sup.c

diff --git a/drivers/scsi/qla2xxx/qla_sup.c b/drivers/scsi/qla2xxx/qla_sup.c
index d7f5c608009c3435da3bf10fb52897842a92cf68..f4d755a643e44d985d0378b06e6c134930da531f 100644 (file)
--- a/drivers/scsi/qla2xxx/qla_sup.c
+++ b/drivers/scsi/qla2xxx/qla_sup.c
@@ -1,22 +1,9 @@
-/******************************************************************************
- *                  QLOGIC LINUX SOFTWARE
- *
- * QLogic ISP2x00 device driver for Linux 2.6.x
- * Copyright (C) 2003-2005 QLogic Corporation
- * (www.qlogic.com)
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2, or (at your option) any
- * later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
+/*
+ * QLogic Fibre Channel HBA Driver
+ * Copyright (c)  2003-2005 QLogic Corporation
  *
- ******************************************************************************/
-
+ * See LICENSE.qla2xxx for copyright and licensing details.
+ */
 #include "qla_def.h"
 
 #include <linux/delay.h>
@@ -139,6 +126,7 @@ qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
 
        /* Wait for NVRAM to become ready */
        WRT_REG_WORD(&reg->nvram, NVR_SELECT);
+       RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
        do {
                NVRAM_DELAY();
                word = RD_REG_WORD(&reg->nvram);
@@ -191,6 +179,7 @@ qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
 
        /* Wait for NVRAM to become ready */
        WRT_REG_WORD(&reg->nvram, NVR_SELECT);
+       RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
        do {
                NVRAM_DELAY();
                word = RD_REG_WORD(&reg->nvram);
@@ -248,6 +237,7 @@ qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
        /* Read data from NVRAM. */
        for (cnt = 0; cnt < 16; cnt++) {
                WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
+               RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
                NVRAM_DELAY();
                data <<= 1;
                reg_data = RD_REG_WORD(&reg->nvram);
@@ -350,6 +340,7 @@ qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
 
                /* Wait for NVRAM to become ready. */
                WRT_REG_WORD(&reg->nvram, NVR_SELECT);
+               RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
                do {
                        NVRAM_DELAY();
                        word = RD_REG_WORD(&reg->nvram);
@@ -401,6 +392,7 @@ qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
 
        /* Wait for NVRAM to become ready. */
        WRT_REG_WORD(&reg->nvram, NVR_SELECT);
+       RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
        do {
                NVRAM_DELAY();
                word = RD_REG_WORD(&reg->nvram);
@@ -468,21 +460,12 @@ qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
     uint32_t dwords)
 {
        uint32_t i;
-       struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
-
-       /* Pause RISC. */
-       WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
-       RD_REG_DWORD(&reg->hccr);               /* PCI Posting. */
 
        /* Dword reads to flash. */
        for (i = 0; i < dwords; i++, faddr++)
                dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
                    flash_data_to_access_addr(faddr)));
 
-       /* Release RISC pause. */
-       WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
-       RD_REG_DWORD(&reg->hccr);               /* PCI Posting. */
-
        return dwptr;
 }
 
@@ -532,10 +515,6 @@ qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
 
        ret = QLA_SUCCESS;
 
-       /* Pause RISC. */
-       WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
-       RD_REG_DWORD(&reg->hccr);               /* PCI Posting. */
-
        qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
        DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
            ha->host_no, man_id, flash_id));
@@ -594,15 +573,14 @@ qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
                }
        } while (0);
 
+       /* Enable flash write-protection. */
+       qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0x9c);
+
        /* Disable flash write. */
        WRT_REG_DWORD(&reg->ctrl_status,
            RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
        RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 
-       /* Release RISC pause. */
-       WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
-       RD_REG_DWORD(&reg->hccr);               /* PCI Posting. */
-
        return ret;
 }
 
@@ -630,11 +608,6 @@ qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 {
        uint32_t i;
        uint32_t *dwptr;
-       struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
-
-       /* Pause RISC. */
-       WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
-       RD_REG_DWORD(&reg->hccr);       /* PCI Posting. */
 
        /* Dword reads to flash. */
        dwptr = (uint32_t *)buf;
@@ -642,10 +615,6 @@ qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
                dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
                    nvram_data_to_access_addr(naddr)));
 
-       /* Release RISC pause. */
-       WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
-       RD_REG_DWORD(&reg->hccr);       /* PCI Posting. */
-
        return buf;
 }
 
@@ -690,10 +659,6 @@ qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 
        ret = QLA_SUCCESS;
 
-       /* Pause RISC. */
-       WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
-       RD_REG_DWORD(&reg->hccr);               /* PCI Posting. */
-
        /* Enable flash write. */
        WRT_REG_DWORD(&reg->ctrl_status,
            RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
@@ -728,9 +693,5 @@ qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
            RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
        RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 
-       /* Release RISC pause. */
-       WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
-       RD_REG_DWORD(&reg->hccr);               /* PCI Posting. */
-
        return ret;
 }