/*************************** Forwards ***************************/
static void musb_ep_program(struct musb *musb, u8 epnum,
- struct urb *pUrb, unsigned int nOut,
- u8 * pBuffer, u32 dwLength);
+ struct urb *urb, unsigned int nOut,
+ u8 * buf, u32 len);
/*
* Clear TX fifo. Needed to avoid BABBLE errors.
musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
{
u16 wFrame;
- u32 dwLength;
- void *pBuffer;
+ u32 len;
+ void *buf;
void __iomem *mbase = musb->mregs;
struct urb *urb = next_urb(qh);
struct musb_hw_ep *hw_ep = qh->hw_ep;
- unsigned nPipe = urb->pipe;
- u8 address = usb_pipedevice(nPipe);
+ unsigned pipe = urb->pipe;
+ u8 address = usb_pipedevice(pipe);
int epnum = hw_ep->epnum;
/* initialize software qh state */
is_in = 0;
hw_ep->out_qh = qh;
musb->ep0_stage = MGC_END0_START;
- pBuffer = urb->setup_packet;
- dwLength = 8;
+ buf = urb->setup_packet;
+ len = 8;
break;
case USB_ENDPOINT_XFER_ISOC:
qh->iso_idx = 0;
qh->frame = 0;
- pBuffer = urb->transfer_buffer + urb->iso_frame_desc[0].offset;
- dwLength = urb->iso_frame_desc[0].length;
+ buf = urb->transfer_buffer + urb->iso_frame_desc[0].offset;
+ len = urb->iso_frame_desc[0].length;
break;
default: /* bulk, interrupt */
- pBuffer = urb->transfer_buffer;
- dwLength = urb->transfer_buffer_length;
+ buf = urb->transfer_buffer;
+ len = urb->transfer_buffer_length;
}
DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
default: s = "-intr"; break;
}; s;}),
- epnum, pBuffer, dwLength);
+ epnum, buf, len);
/* Configure endpoint */
if (is_in || hw_ep->is_shared_fifo)
hw_ep->in_qh = qh;
else
hw_ep->out_qh = qh;
- musb_ep_program(musb, epnum, urb, !is_in, pBuffer, dwLength);
+ musb_ep_program(musb, epnum, urb, !is_in, buf, len);
/* transmit may have more work: start it when it is time */
if (is_in)
/*
* PIO RX for a packet (or part of it).
*/
-static u8 musb_host_packet_rx(struct musb *musb, struct urb *pUrb,
- u8 epnum, u8 bIsochError)
+static u8 musb_host_packet_rx(struct musb *musb, struct urb *urb,
+ u8 epnum, u8 iso_err)
{
- u16 wRxCount;
- u8 *pBuffer;
+ u16 rx_count;
+ u8 *buf;
u16 csr;
- u8 bDone = FALSE;
+ u8 done = FALSE;
u32 length;
int do_flush = 0;
struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
void __iomem *epio = hw_ep->regs;
struct musb_qh *qh = hw_ep->in_qh;
- int nPipe = pUrb->pipe;
- void *buffer = pUrb->transfer_buffer;
+ int pipe = urb->pipe;
+ void *buffer = urb->transfer_buffer;
// musb_ep_select(mbase, epnum);
- wRxCount = musb_readw(epio, MUSB_RXCOUNT);
- DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, wRxCount,
- pUrb->transfer_buffer, qh->offset,
- pUrb->transfer_buffer_length);
+ rx_count = musb_readw(epio, MUSB_RXCOUNT);
+ DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
+ urb->transfer_buffer, qh->offset,
+ urb->transfer_buffer_length);
/* unload FIFO */
- if (usb_pipeisoc(nPipe)) {
+ if (usb_pipeisoc(pipe)) {
int status = 0;
struct usb_iso_packet_descriptor *d;
- if (bIsochError) {
+ if (iso_err) {
status = -EILSEQ;
- pUrb->error_count++;
+ urb->error_count++;
}
- d = pUrb->iso_frame_desc + qh->iso_idx;
- pBuffer = buffer + d->offset;
+ d = urb->iso_frame_desc + qh->iso_idx;
+ buf = buffer + d->offset;
length = d->length;
- if (wRxCount > length) {
+ if (rx_count > length) {
if (status == 0) {
status = -EOVERFLOW;
- pUrb->error_count++;
+ urb->error_count++;
}
- DBG(2, "** OVERFLOW %d into %d\n", wRxCount, length);
+ DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
do_flush = 1;
} else
- length = wRxCount;
- pUrb->actual_length += length;
+ length = rx_count;
+ urb->actual_length += length;
d->actual_length = length;
d->status = status;
/* see if we are done */
- bDone = (++qh->iso_idx >= pUrb->number_of_packets);
+ done = (++qh->iso_idx >= urb->number_of_packets);
} else {
/* non-isoch */
- pBuffer = buffer + qh->offset;
- length = pUrb->transfer_buffer_length - qh->offset;
- if (wRxCount > length) {
- if (pUrb->status == -EINPROGRESS)
- pUrb->status = -EOVERFLOW;
- DBG(2, "** OVERFLOW %d into %d\n", wRxCount, length);
+ buf = buffer + qh->offset;
+ length = urb->transfer_buffer_length - qh->offset;
+ if (rx_count > length) {
+ if (urb->status == -EINPROGRESS)
+ urb->status = -EOVERFLOW;
+ DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
do_flush = 1;
} else
- length = wRxCount;
- pUrb->actual_length += length;
+ length = rx_count;
+ urb->actual_length += length;
qh->offset += length;
/* see if we are done */
- bDone = (pUrb->actual_length == pUrb->transfer_buffer_length)
- || (wRxCount < qh->maxpacket)
- || (pUrb->status != -EINPROGRESS);
- if (bDone
- && (pUrb->status == -EINPROGRESS)
- && (pUrb->transfer_flags & URB_SHORT_NOT_OK)
- && (pUrb->actual_length
- < pUrb->transfer_buffer_length))
- pUrb->status = -EREMOTEIO;
+ done = (urb->actual_length == urb->transfer_buffer_length)
+ || (rx_count < qh->maxpacket)
+ || (urb->status != -EINPROGRESS);
+ if (done
+ && (urb->status == -EINPROGRESS)
+ && (urb->transfer_flags & URB_SHORT_NOT_OK)
+ && (urb->actual_length
+ < urb->transfer_buffer_length))
+ urb->status = -EREMOTEIO;
}
- musb_read_fifo(hw_ep, length, pBuffer);
+ musb_read_fifo(hw_ep, length, buf);
csr = musb_readw(epio, MUSB_RXCSR);
csr |= MUSB_RXCSR_H_WZC_BITS;
else {
/* REVISIT this assumes AUTOCLEAR is never set */
csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
- if (!bDone)
+ if (!done)
csr |= MUSB_RXCSR_H_REQPKT;
musb_writew(epio, MUSB_RXCSR, csr);
}
- return bDone;
+ return done;
}
/* we don't always need to reinit a given side of an endpoint...
* Context: irqs blocked, controller lock held
*/
static void musb_ep_program(struct musb *musb, u8 epnum,
- struct urb *pUrb, unsigned int is_out,
- u8 * pBuffer, u32 dwLength)
+ struct urb *urb, unsigned int is_out,
+ u8 * buf, u32 len)
{
struct dma_controller *dma_controller;
- struct dma_channel *pDmaChannel;
- u8 bDmaOk;
+ struct dma_channel *dma_channel;
+ u8 dma_ok;
void __iomem *mbase = musb->mregs;
struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
void __iomem *epio = hw_ep->regs;
DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
"h_addr%02x h_port%02x bytes %d\n",
is_out ? "-->" : "<--",
- epnum, pUrb, pUrb->dev->speed,
+ epnum, urb, urb->dev->speed,
qh->addr_reg, qh->epnum, is_out ? "out" : "in",
qh->h_addr_reg, qh->h_port_reg,
- dwLength);
+ len);
musb_ep_select(mbase, epnum);
/* candidate for DMA? */
dma_controller = musb->dma_controller;
if (is_dma_capable() && epnum && dma_controller) {
- pDmaChannel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
- if (!pDmaChannel) {
- pDmaChannel = dma_controller->channel_alloc(
+ dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
+ if (!dma_channel) {
+ dma_channel = dma_controller->channel_alloc(
dma_controller, hw_ep, is_out);
if (is_out)
- hw_ep->tx_channel = pDmaChannel;
+ hw_ep->tx_channel = dma_channel;
else
- hw_ep->rx_channel = pDmaChannel;
+ hw_ep->rx_channel = dma_channel;
}
} else
- pDmaChannel = NULL;
+ dma_channel = NULL;
/* make sure we clear DMAEnab, autoSet bits from previous run */
/* OUT/transmit/EP0 or IN/receive? */
if (is_out) {
u16 csr;
- u16 wIntrTxE;
- u16 wLoadCount;
+ u16 int_txe;
+ u16 load_count;
csr = musb_readw(epio, MUSB_TXCSR);
/* disable interrupt in case we flush */
- wIntrTxE = musb_readw(mbase, MUSB_INTRTXE);
- musb_writew(mbase, MUSB_INTRTXE, wIntrTxE & ~(1 << epnum));
+ int_txe = musb_readw(mbase, MUSB_INTRTXE);
+ musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
/* general endpoint setup */
if (epnum) {
);
csr |= MUSB_TXCSR_MODE;
- if (usb_gettoggle(pUrb->dev,
+ if (usb_gettoggle(urb->dev,
qh->epnum, 1))
csr |= MUSB_TXCSR_H_WR_DATATOGGLE
| MUSB_TXCSR_H_DATATOGGLE;
}
if (can_bulk_split(musb, qh->type))
- wLoadCount = min((u32) hw_ep->max_packet_sz_tx,
- dwLength);
+ load_count = min((u32) hw_ep->max_packet_sz_tx,
+ len);
else
- wLoadCount = min((u32) packet_sz, dwLength);
+ load_count = min((u32) packet_sz, len);
#ifdef CONFIG_USB_INVENTRA_DMA
- if (pDmaChannel) {
+ if (dma_channel) {
/* clear previous state */
csr = musb_readw(epio, MUSB_TXCSR);
musb_writew(epio, MUSB_TXCSR,
csr | MUSB_TXCSR_MODE);
- qh->segsize = min(dwLength, pDmaChannel->max_len);
+ qh->segsize = min(len, dma_channel->max_len);
if (qh->segsize <= packet_sz)
- pDmaChannel->desired_mode = 0;
+ dma_channel->desired_mode = 0;
else
- pDmaChannel->desired_mode = 1;
+ dma_channel->desired_mode = 1;
- if (pDmaChannel->desired_mode == 0) {
+ if (dma_channel->desired_mode == 0) {
csr &= ~(MUSB_TXCSR_AUTOSET
| MUSB_TXCSR_DMAMODE);
csr |= (MUSB_TXCSR_DMAENAB);
musb_writew(epio, MUSB_TXCSR, csr);
- bDmaOk = dma_controller->channel_program(
- pDmaChannel, packet_sz,
- pDmaChannel->desired_mode,
- pUrb->transfer_dma,
+ dma_ok = dma_controller->channel_program(
+ dma_channel, packet_sz,
+ dma_channel->desired_mode,
+ urb->transfer_dma,
qh->segsize);
- if (bDmaOk) {
- wLoadCount = 0;
+ if (dma_ok) {
+ load_count = 0;
} else {
- dma_controller->channel_release(pDmaChannel);
+ dma_controller->channel_release(dma_channel);
if (is_out)
hw_ep->tx_channel = NULL;
else
hw_ep->rx_channel = NULL;
- pDmaChannel = NULL;
+ dma_channel = NULL;
}
}
#endif
/* candidate for DMA */
- if ((is_cppi_enabled() || tusb_dma_omap()) && pDmaChannel) {
+ if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
/* program endpoint CSRs first, then setup DMA.
* assume CPPI setup succeeds.
musb_writew(epio, MUSB_TXCSR,
csr | MUSB_TXCSR_MODE);
- pDmaChannel->actual_len = 0L;
- qh->segsize = dwLength;
+ dma_channel->actual_len = 0L;
+ qh->segsize = len;
/* TX uses "rndis" mode automatically, but needs help
* to identify the zero-length-final-packet case.
*/
- bDmaOk = dma_controller->channel_program(
- pDmaChannel, packet_sz,
- (pUrb->transfer_flags
+ dma_ok = dma_controller->channel_program(
+ dma_channel, packet_sz,
+ (urb->transfer_flags
& URB_ZERO_PACKET)
== URB_ZERO_PACKET,
- pUrb->transfer_dma,
+ urb->transfer_dma,
qh->segsize);
- if (bDmaOk) {
- wLoadCount = 0;
+ if (dma_ok) {
+ load_count = 0;
} else {
- dma_controller->channel_release(pDmaChannel);
- pDmaChannel = hw_ep->tx_channel = NULL;
+ dma_controller->channel_release(dma_channel);
+ dma_channel = hw_ep->tx_channel = NULL;
/* REVISIT there's an error path here that
* needs handling: can't do dma, but
}
}
- if (wLoadCount) {
+ if (load_count) {
/* ASSERT: TXCSR_DMAENAB was already cleared */
/* PIO to load FIFO */
- qh->segsize = wLoadCount;
- musb_write_fifo(hw_ep, wLoadCount, pBuffer);
+ qh->segsize = load_count;
+ musb_write_fifo(hw_ep, load_count, buf);
csr = musb_readw(epio, MUSB_TXCSR);
csr &= ~(MUSB_TXCSR_DMAENAB
| MUSB_TXCSR_DMAMODE
}
/* re-enable interrupt */
- musb_writew(mbase, MUSB_INTRTXE, wIntrTxE);
+ musb_writew(mbase, MUSB_INTRTXE, int_txe);
/* IN/receive */
} else {
musb_rx_reinit(musb, qh, hw_ep);
/* init new state: toggle and NYET, maybe DMA later */
- if (usb_gettoggle(pUrb->dev, qh->epnum, 0))
+ if (usb_gettoggle(urb->dev, qh->epnum, 0))
csr = MUSB_RXCSR_H_WR_DATATOGGLE
| MUSB_RXCSR_H_DATATOGGLE;
else
/* kick things off */
- if ((is_cppi_enabled() || tusb_dma_omap()) && pDmaChannel) {
+ if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
/* candidate for DMA */
- if (pDmaChannel) {
- pDmaChannel->actual_len = 0L;
- qh->segsize = dwLength;
+ if (dma_channel) {
+ dma_channel->actual_len = 0L;
+ qh->segsize = len;
/* AUTOREQ is in a DMA register */
musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
/* unless caller treats short rx transfers as
* errors, we dare not queue multiple transfers.
*/
- bDmaOk = dma_controller->channel_program(
- pDmaChannel, packet_sz,
- !(pUrb->transfer_flags
+ dma_ok = dma_controller->channel_program(
+ dma_channel, packet_sz,
+ !(urb->transfer_flags
& URB_SHORT_NOT_OK),
- pUrb->transfer_dma,
+ urb->transfer_dma,
qh->segsize);
- if (!bDmaOk) {
+ if (!dma_ok) {
dma_controller->channel_release(
- pDmaChannel);
- pDmaChannel = hw_ep->rx_channel = NULL;
+ dma_channel);
+ dma_channel = hw_ep->rx_channel = NULL;
} else
csr |= MUSB_RXCSR_DMAENAB;
}
* Return TRUE until it's time to start the status stage.
*/
static int musb_h_ep0_continue(struct musb *musb,
- u16 len, struct urb *pUrb)
+ u16 len, struct urb *urb)
{
int bMore = FALSE;
- u8 *pFifoDest = NULL;
+ u8 *fifo_dest = NULL;
u16 fifo_count = 0;
struct musb_hw_ep *hw_ep = musb->control_ep;
struct musb_qh *qh = hw_ep->in_qh;
switch (musb->ep0_stage) {
case MGC_END0_IN:
- pFifoDest = pUrb->transfer_buffer + pUrb->actual_length;
- fifo_count = min(len, ((u16) (pUrb->transfer_buffer_length
- - pUrb->actual_length)));
+ fifo_dest = urb->transfer_buffer + urb->actual_length;
+ fifo_count = min(len, ((u16) (urb->transfer_buffer_length
+ - urb->actual_length)));
if (fifo_count < len)
- pUrb->status = -EOVERFLOW;
+ urb->status = -EOVERFLOW;
- musb_read_fifo(hw_ep, fifo_count, pFifoDest);
+ musb_read_fifo(hw_ep, fifo_count, fifo_dest);
- pUrb->actual_length += fifo_count;
+ urb->actual_length += fifo_count;
if (len < qh->maxpacket) {
/* always terminate on short read; it's
* rarely reported as an error.
*/
- } else if (pUrb->actual_length <
- pUrb->transfer_buffer_length)
+ } else if (urb->actual_length <
+ urb->transfer_buffer_length)
bMore = TRUE;
break;
case MGC_END0_START:
- request = (struct usb_ctrlrequest *) pUrb->setup_packet;
+ request = (struct usb_ctrlrequest *) urb->setup_packet;
if (!request->wLength) {
DBG(4, "start no-DATA\n");
/* FALLTHROUGH */
case MGC_END0_OUT:
fifo_count = min(qh->maxpacket, ((u16)
- (pUrb->transfer_buffer_length
- - pUrb->actual_length)));
+ (urb->transfer_buffer_length
+ - urb->actual_length)));
if (fifo_count) {
- pFifoDest = (u8 *) (pUrb->transfer_buffer
- + pUrb->actual_length);
+ fifo_dest = (u8 *) (urb->transfer_buffer
+ + urb->actual_length);
DBG(3, "Sending %d bytes to %p\n",
- fifo_count, pFifoDest);
- musb_write_fifo(hw_ep, fifo_count, pFifoDest);
+ fifo_count, fifo_dest);
+ musb_write_fifo(hw_ep, fifo_count, fifo_dest);
- pUrb->actual_length += fifo_count;
+ urb->actual_length += fifo_count;
bMore = TRUE;
}
break;
*/
irqreturn_t musb_h_ep0_irq(struct musb *musb)
{
- struct urb *pUrb;
+ struct urb *urb;
u16 csr, len;
int status = 0;
void __iomem *mbase = musb->mregs;
irqreturn_t retval = IRQ_NONE;
/* ep0 only has one queue, "in" */
- pUrb = next_urb(qh);
+ urb = next_urb(qh);
musb_ep_select(mbase, 0);
csr = musb_readw(epio, MUSB_CSR0);
: 0;
DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
- csr, qh, len, pUrb, musb->ep0_stage);
+ csr, qh, len, urb, musb->ep0_stage);
/* if we just did status stage, we are done */
if (MGC_END0_STATUS == musb->ep0_stage) {
if (status) {
DBG(6, "aborting\n");
retval = IRQ_HANDLED;
- if (pUrb)
- pUrb->status = status;
+ if (urb)
+ urb->status = status;
bComplete = TRUE;
/* use the proper sequence to abort the transfer */
musb_writew(epio, MUSB_CSR0, 0);
}
- if (unlikely(!pUrb)) {
+ if (unlikely(!urb)) {
/* stop endpoint since we have no place for its data, this
* SHOULD NEVER HAPPEN! */
ERR("no URB for end 0\n");
if (!bComplete) {
/* call common logic and prepare response */
- if (musb_h_ep0_continue(musb, len, pUrb)) {
+ if (musb_h_ep0_continue(musb, len, urb)) {
/* more packets required */
csr = (MGC_END0_IN == musb->ep0_stage)
? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
} else {
/* data transfer complete; perform status phase */
- if (usb_pipeout(pUrb->pipe)
- || !pUrb->transfer_buffer_length)
+ if (usb_pipeout(urb->pipe)
+ || !urb->transfer_buffer_length)
csr = MUSB_CSR0_H_STATUSPKT
| MUSB_CSR0_H_REQPKT;
else
/* call completion handler if done */
if (bComplete)
- musb_advance_schedule(musb, pUrb, hw_ep, 1);
+ musb_advance_schedule(musb, urb, hw_ep, 1);
done:
return retval;
}
/* Service a Tx-Available or dma completion irq for the endpoint */
void musb_host_tx(struct musb *musb, u8 epnum)
{
- int nPipe;
- u8 bDone = FALSE;
+ int pipe;
+ u8 done = FALSE;
u16 tx_csr;
size_t wLength = 0;
- u8 *pBuffer = NULL;
- struct urb *pUrb;
+ u8 *buf = NULL;
+ struct urb *urb;
struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
void __iomem *epio = hw_ep->regs;
struct musb_qh *qh = hw_ep->out_qh;
void __iomem *mbase = musb->mregs;
struct dma_channel *dma;
- pUrb = next_urb(qh);
+ urb = next_urb(qh);
musb_ep_select(mbase, epnum);
tx_csr = musb_readw(epio, MUSB_TXCSR);
/* with CPPI, DMA sometimes triggers "extra" irqs */
- if (!pUrb) {
+ if (!urb) {
DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
goto finish;
}
- nPipe = pUrb->pipe;
+ pipe = urb->pipe;
dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
dma ? ", dma" : "");
musb_writew(epio, MUSB_TXCSR, tx_csr);
musb_writeb(epio, MUSB_TXINTERVAL, 0);
- bDone = TRUE;
+ done = TRUE;
}
/* second cppi case */
}
/* REVISIT this looks wrong... */
- if (!status || dma || usb_pipeisoc(nPipe)) {
+ if (!status || dma || usb_pipeisoc(pipe)) {
if (dma)
wLength = dma->actual_len;
else
wLength = qh->segsize;
qh->offset += wLength;
- if (usb_pipeisoc(nPipe)) {
+ if (usb_pipeisoc(pipe)) {
struct usb_iso_packet_descriptor *d;
- d = pUrb->iso_frame_desc + qh->iso_idx;
+ d = urb->iso_frame_desc + qh->iso_idx;
d->actual_length = qh->segsize;
- if (++qh->iso_idx >= pUrb->number_of_packets) {
- bDone = TRUE;
+ if (++qh->iso_idx >= urb->number_of_packets) {
+ done = TRUE;
} else if (!dma) {
d++;
- pBuffer = pUrb->transfer_buffer + d->offset;
+ buf = urb->transfer_buffer + d->offset;
wLength = d->length;
}
} else if (dma) {
- bDone = TRUE;
+ done = TRUE;
} else {
/* see if we need to send more data, or ZLP */
if (qh->segsize < qh->maxpacket)
- bDone = TRUE;
- else if (qh->offset == pUrb->transfer_buffer_length
- && !(pUrb-> transfer_flags
+ done = TRUE;
+ else if (qh->offset == urb->transfer_buffer_length
+ && !(urb-> transfer_flags
& URB_ZERO_PACKET))
- bDone = TRUE;
- if (!bDone) {
- pBuffer = pUrb->transfer_buffer
+ done = TRUE;
+ if (!done) {
+ buf = urb->transfer_buffer
+ qh->offset;
- wLength = pUrb->transfer_buffer_length
+ wLength = urb->transfer_buffer_length
- qh->offset;
}
}
/* urb->status != -EINPROGRESS means request has been faulted,
* so we must abort this transfer after cleanup
*/
- if (pUrb->status != -EINPROGRESS) {
- bDone = TRUE;
+ if (urb->status != -EINPROGRESS) {
+ done = TRUE;
if (status == 0)
- status = pUrb->status;
+ status = urb->status;
}
- if (bDone) {
+ if (done) {
/* set status */
- pUrb->status = status;
- pUrb->actual_length = qh->offset;
- musb_advance_schedule(musb, pUrb, hw_ep, USB_DIR_OUT);
+ urb->status = status;
+ urb->actual_length = qh->offset;
+ musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
} else if (!(tx_csr & MUSB_TXCSR_DMAENAB)) {
- // WARN_ON(!pBuffer);
+ // WARN_ON(!buf);
/* REVISIT: some docs say that when hw_ep->tx_double_buffered,
* (and presumably, fifo is not half-full) we should write TWO
*/
/* PIO: start next packet in this URB */
wLength = min(qh->maxpacket, (u16) wLength);
- musb_write_fifo(hw_ep, wLength, pBuffer);
+ musb_write_fifo(hw_ep, wLength, buf);
qh->segsize = wLength;
musb_ep_select(mbase, epnum);
*/
void musb_host_rx(struct musb *musb, u8 epnum)
{
- struct urb *pUrb;
+ struct urb *urb;
struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
void __iomem *epio = hw_ep->regs;
struct musb_qh *qh = hw_ep->in_qh;
size_t xfer_len;
void __iomem *mbase = musb->mregs;
- int nPipe;
- u16 rx_csr, wVal;
- u8 bIsochError = FALSE;
- u8 bDone = FALSE;
+ int pipe;
+ u16 rx_csr, val;
+ u8 iso_err = FALSE;
+ u8 done = FALSE;
u32 status;
struct dma_channel *dma;
musb_ep_select(mbase, epnum);
- pUrb = next_urb(qh);
+ urb = next_urb(qh);
dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
status = 0;
xfer_len = 0;
- wVal = rx_csr = musb_readw(epio, MUSB_RXCSR);
+ val = rx_csr = musb_readw(epio, MUSB_RXCSR);
- if (unlikely(!pUrb)) {
+ if (unlikely(!urb)) {
/* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
* usbtest #11 (unlinks) triggers it regularly, sometimes
* with fifo full. (Only with DMA??)
*/
- DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, wVal,
+ DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
musb_readw(epio, MUSB_RXCOUNT));
musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
return;
}
- nPipe = pUrb->pipe;
+ pipe = urb->pipe;
DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zd)\n",
- epnum, rx_csr, pUrb->actual_length,
+ epnum, rx_csr, urb->actual_length,
dma ? dma->actual_len : 0);
/* check for errors, concurrent stall & unlink is not really
} else {
DBG(4, "RX end %d ISO data error\n", epnum);
/* packet error reported later */
- bIsochError = TRUE;
+ iso_err = TRUE;
}
}
}
musb_h_flush_rxfifo(hw_ep, 0);
musb_writeb(epio, MUSB_RXINTERVAL, 0);
- bDone = TRUE;
+ done = TRUE;
goto finish;
}
dma->status = MGC_DMA_STATUS_CORE_ABORT;
(void) musb->dma_controller->channel_abort(dma);
xfer_len = dma->actual_len;
- bDone = TRUE;
+ done = TRUE;
}
DBG(2, "RXCSR%d %04x, reqpkt, len %zd%s\n", epnum, rx_csr,
if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
xfer_len = dma->actual_len;
- wVal &= ~(MUSB_RXCSR_DMAENAB
+ val &= ~(MUSB_RXCSR_DMAENAB
| MUSB_RXCSR_H_AUTOREQ
| MUSB_RXCSR_AUTOCLEAR
| MUSB_RXCSR_RXPKTRDY);
- musb_writew(hw_ep->regs, MUSB_RXCSR, wVal);
+ musb_writew(hw_ep->regs, MUSB_RXCSR, val);
#ifdef CONFIG_USB_INVENTRA_DMA
- /* bDone if pUrb buffer is full or short packet is recd */
- bDone = ((pUrb->actual_length + xfer_len) >=
- pUrb->transfer_buffer_length)
+ /* done if urb buffer is full or short packet is recd */
+ done = ((urb->actual_length + xfer_len) >=
+ urb->transfer_buffer_length)
|| (dma->actual_len & (qh->maxpacket - 1));
/* send IN token for next packet, without AUTOREQ */
- if (!bDone) {
- wVal |= MUSB_RXCSR_H_REQPKT;
+ if (!done) {
+ val |= MUSB_RXCSR_H_REQPKT;
musb_writew(epio, MUSB_RXCSR,
- MUSB_RXCSR_H_WZC_BITS | wVal);
+ MUSB_RXCSR_H_WZC_BITS | val);
}
DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
- bDone ? "off" : "reset",
+ done ? "off" : "reset",
musb_readw(epio, MUSB_RXCSR),
musb_readw(epio, MUSB_RXCOUNT));
#else
- bDone = TRUE;
+ done = TRUE;
#endif
- } else if (pUrb->status == -EINPROGRESS) {
+ } else if (urb->status == -EINPROGRESS) {
/* if no errors, be sure a packet is ready for unloading */
if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
status = -EPROTO;
// SCRUB (RX)
/* do the proper sequence to abort the transfer */
musb_ep_select(mbase, epnum);
- wVal &= ~MUSB_RXCSR_H_REQPKT;
- musb_writew(epio, MUSB_RXCSR, wVal);
+ val &= ~MUSB_RXCSR_H_REQPKT;
+ musb_writew(epio, MUSB_RXCSR, val);
goto finish;
}
#ifdef CONFIG_USB_INVENTRA_DMA
if (dma) {
struct dma_controller *c;
- u16 wRxCount;
+ u16 rx_count;
int status;
- wRxCount = musb_readw(epio, MUSB_RXCOUNT);
+ rx_count = musb_readw(epio, MUSB_RXCOUNT);
DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
- epnum, wRxCount,
- pUrb->transfer_dma
- + pUrb->actual_length,
+ epnum, rx_count,
+ urb->transfer_dma
+ + urb->actual_length,
qh->offset,
- pUrb->transfer_buffer_length);
+ urb->transfer_buffer_length);
c = musb->dma_controller;
/* because of the issue below, mode 1 will
* only rarely behave with correct semantics.
*/
- if ((pUrb->transfer_flags &
+ if ((urb->transfer_flags &
URB_SHORT_NOT_OK)
- && (pUrb->transfer_buffer_length -
- pUrb->actual_length)
+ && (urb->transfer_buffer_length -
+ urb->actual_length)
> qh->maxpacket)
dma->desired_mode = 1;
#endif
* wait for an interrupt when the pkt is recd. Well, you won't get any!
*/
- wVal = musb_readw(epio, MUSB_RXCSR);
- wVal &= ~MUSB_RXCSR_H_REQPKT;
+ val = musb_readw(epio, MUSB_RXCSR);
+ val &= ~MUSB_RXCSR_H_REQPKT;
if (dma->desired_mode == 0)
- wVal &= ~MUSB_RXCSR_H_AUTOREQ;
+ val &= ~MUSB_RXCSR_H_AUTOREQ;
else
- wVal |= MUSB_RXCSR_H_AUTOREQ;
- wVal |= MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAENAB;
+ val |= MUSB_RXCSR_H_AUTOREQ;
+ val |= MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAENAB;
musb_writew(epio, MUSB_RXCSR,
- MUSB_RXCSR_H_WZC_BITS | wVal);
+ MUSB_RXCSR_H_WZC_BITS | val);
/* REVISIT if when actual_length != 0,
* transfer_buffer_length needs to be
status = c->channel_program(
dma, qh->maxpacket,
dma->desired_mode,
- pUrb->transfer_dma
- + pUrb->actual_length,
+ urb->transfer_dma
+ + urb->actual_length,
(dma->desired_mode == 0)
- ? wRxCount
- : pUrb->transfer_buffer_length);
+ ? rx_count
+ : urb->transfer_buffer_length);
if (!status) {
c->channel_release(dma);
#endif /* Mentor DMA */
if (!dma) {
- bDone = musb_host_packet_rx(musb, pUrb,
- epnum, bIsochError);
- DBG(6, "read %spacket\n", bDone ? "last " : "");
+ done = musb_host_packet_rx(musb, urb,
+ epnum, iso_err);
+ DBG(6, "read %spacket\n", done ? "last " : "");
}
}
finish:
- pUrb->actual_length += xfer_len;
+ urb->actual_length += xfer_len;
qh->offset += xfer_len;
- if (bDone) {
- if (pUrb->status == -EINPROGRESS)
- pUrb->status = status;
- musb_advance_schedule(musb, pUrb, hw_ep, USB_DIR_IN);
+ if (done) {
+ if (urb->status == -EINPROGRESS)
+ urb->status = status;
+ musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
}
}
* transfer scheduling logic to try some other qh, e.g. try
* for 2 msec first:
*
- * interval = (USB_SPEED_HIGH == pUrb->dev->speed) ? 16 : 2;
+ * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
*
* The downside of disabling this is that transfer scheduling
* gets VERY unfair for nonperiodic transfers; a misbehaving
projects / linux-2.6-omap-h63xx.git / blobdiff