-/******************************************************************
+/*
+ * MUSB OTG driver internal DMA controller support
+ *
* Copyright 2005 Mentor Graphics Corporation
* Copyright (C) 2005-2007 by Texas Instruments
*
- * This file is part of the Inventra Controller Driver for Linux.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
*
- * The Inventra Controller Driver for Linux is free software; you
- * can redistribute it and/or modify it under the terms of the GNU
- * General Public License version 2 as published by the Free Software
- * Foundation.
- *
- * The Inventra Controller Driver for Linux is distributed in
- * the hope that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- * License for more details.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
*
* You should have received a copy of the GNU General Public License
- * along with The Inventra Controller Driver for Linux ; if not,
- * write to the Free Software Foundation, Inc., 59 Temple Place,
- * Suite 330, Boston, MA 02111-1307 USA
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
- * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
- * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
- * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
- * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
- * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
- * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
- * GRAPHICS SUPPORT CUSTOMER.
- ******************************************************************/
+ */
/*
* Implementation for the DMA controller within the MUSBMHDRC.
#define MGC_O_HSDMA_ADDRESS 0x8
#define MGC_O_HSDMA_COUNT 0xc
-#define MGC_HSDMA_CHANNEL_OFFSET(_bChannel, _bOffset) \
- (MGC_O_HSDMA_BASE + (_bChannel << 4) + _bOffset)
+#define MGC_HSDMA_CHANNEL_OFFSET(_bChannel, _offset) \
+ (MGC_O_HSDMA_BASE + (_bChannel << 4) + _offset)
/* control register (16-bit): */
-#define MGC_S_HSDMA_ENABLE 0
-#define MGC_S_HSDMA_TRANSMIT 1
-#define MGC_S_HSDMA_MODE1 2
-#define MGC_S_HSDMA_IRQENABLE 3
-#define MGC_S_HSDMA_ENDPOINT 4
-#define MGC_S_HSDMA_BUSERROR 8
-#define MGC_S_HSDMA_BURSTMODE 9
-#define MGC_M_HSDMA_BURSTMODE (3 << MGC_S_HSDMA_BURSTMODE)
+#define MUSB_HSDMA_ENABLE_SHIFT 0
+#define MUSB_HSDMA_TRANSMIT_SHIFT 1
+#define MUSB_HSDMA_MODE1_SHIFT 2
+#define MUSB_HSDMA_IRQENABLE_SHIFT 3
+#define MUSB_HSDMA_ENDPOINT_SHIFT 4
+#define MUSB_HSDMA_BUSERROR_SHIFT 8
+#define MUSB_HSDMA_BURSTMODE_SHIFT 9
+#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
#define MGC_HSDMA_BURSTMODE_UNSPEC 0
#define MGC_HSDMA_BURSTMODE_INCR4 1
#define MGC_HSDMA_BURSTMODE_INCR8 2
u32 len;
u16 wMaxPacketSize;
u8 bIndex;
- u8 bEnd;
- u8 bTransmit;
+ u8 epnum;
+ u8 transmit;
};
struct musb_dma_controller {
}
static struct dma_channel* dma_channel_allocate(struct dma_controller *c,
- struct musb_hw_ep *hw_ep, u8 bTransmit)
+ struct musb_hw_ep *hw_ep, u8 transmit)
{
u8 bBit;
struct dma_channel *pChannel = NULL;
pImplChannel = &(pController->aChannel[bBit]);
pImplChannel->pController = pController;
pImplChannel->bIndex = bBit;
- pImplChannel->bEnd = hw_ep->epnum;
- pImplChannel->bTransmit = bTransmit;
+ pImplChannel->epnum = hw_ep->epnum;
+ pImplChannel->transmit = transmit;
pChannel = &(pImplChannel->Channel);
- pChannel->pPrivateData = pImplChannel;
- pChannel->bStatus = MGC_DMA_STATUS_FREE;
- pChannel->dwMaxLength = 0x10000;
+ pChannel->private_data = pImplChannel;
+ pChannel->status = MGC_DMA_STATUS_FREE;
+ pChannel->max_len = 0x10000;
/* Tx => mode 1; Rx => mode 0 */
- pChannel->bDesiredMode = bTransmit;
- pChannel->dwActualLength = 0;
+ pChannel->desired_mode = transmit;
+ pChannel->actual_len = 0;
break;
}
}
static void dma_channel_release(struct dma_channel *pChannel)
{
struct musb_dma_channel *pImplChannel =
- (struct musb_dma_channel *) pChannel->pPrivateData;
+ (struct musb_dma_channel *) pChannel->private_data;
- pChannel->dwActualLength = 0;
+ pChannel->actual_len = 0;
pImplChannel->dwStartAddress = 0;
pImplChannel->len = 0;
pImplChannel->pController->bmUsedChannels &=
~(1 << pImplChannel->bIndex);
- pChannel->bStatus = MGC_DMA_STATUS_UNKNOWN;
+ pChannel->status = MGC_DMA_STATUS_UNKNOWN;
}
static void configure_channel(struct dma_channel *pChannel,
- u16 wPacketSize, u8 bMode,
- dma_addr_t dma_addr, u32 dwLength)
+ u16 packet_sz, u8 mode,
+ dma_addr_t dma_addr, u32 len)
{
struct musb_dma_channel *pImplChannel =
- (struct musb_dma_channel *) pChannel->pPrivateData;
+ (struct musb_dma_channel *) pChannel->private_data;
struct musb_dma_controller *pController = pImplChannel->pController;
u8 *mbase = pController->pCoreBase;
u8 bChannel = pImplChannel->bIndex;
- u16 wCsr = 0;
+ u16 csr = 0;
DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
- pChannel, wPacketSize, dma_addr, dwLength, bMode);
+ pChannel, packet_sz, dma_addr, len, mode);
- if (bMode) {
- wCsr |= 1 << MGC_S_HSDMA_MODE1;
- if (dwLength < wPacketSize) {
+ if (mode) {
+ csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
+ if (len < packet_sz) {
return FALSE;
}
- if (wPacketSize >= 64) {
- wCsr |=
- MGC_HSDMA_BURSTMODE_INCR16 << MGC_S_HSDMA_BURSTMODE;
- } else if (wPacketSize >= 32) {
- wCsr |=
- MGC_HSDMA_BURSTMODE_INCR8 << MGC_S_HSDMA_BURSTMODE;
- } else if (wPacketSize >= 16) {
- wCsr |=
- MGC_HSDMA_BURSTMODE_INCR4 << MGC_S_HSDMA_BURSTMODE;
+ if (packet_sz >= 64) {
+ csr |=
+ MGC_HSDMA_BURSTMODE_INCR16 << MUSB_HSDMA_BURSTMODE_SHIFT;
+ } else if (packet_sz >= 32) {
+ csr |=
+ MGC_HSDMA_BURSTMODE_INCR8 << MUSB_HSDMA_BURSTMODE_SHIFT;
+ } else if (packet_sz >= 16) {
+ csr |=
+ MGC_HSDMA_BURSTMODE_INCR4 << MUSB_HSDMA_BURSTMODE_SHIFT;
}
}
- wCsr |= (pImplChannel->bEnd << MGC_S_HSDMA_ENDPOINT)
- | (1 << MGC_S_HSDMA_ENABLE)
- | (1 << MGC_S_HSDMA_IRQENABLE)
- | (pImplChannel->bTransmit ? (1 << MGC_S_HSDMA_TRANSMIT) : 0);
+ csr |= (pImplChannel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
+ | (1 << MUSB_HSDMA_ENABLE_SHIFT)
+ | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
+ | (pImplChannel->transmit ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) : 0);
/* address/count */
musb_writel(mbase,
dma_addr);
musb_writel(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_COUNT),
- dwLength);
+ len);
/* control (this should start things) */
musb_writew(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_CONTROL),
- wCsr);
+ csr);
}
static int dma_channel_program(struct dma_channel * pChannel,
- u16 wPacketSize, u8 bMode,
- dma_addr_t dma_addr, u32 dwLength)
+ u16 packet_sz, u8 mode,
+ dma_addr_t dma_addr, u32 len)
{
struct musb_dma_channel *pImplChannel =
- (struct musb_dma_channel *) pChannel->pPrivateData;
+ (struct musb_dma_channel *) pChannel->private_data;
DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
- pImplChannel->bEnd,
- pImplChannel->bTransmit ? "Tx" : "Rx",
- wPacketSize, dma_addr, dwLength, bMode);
+ pImplChannel->epnum,
+ pImplChannel->transmit ? "Tx" : "Rx",
+ packet_sz, dma_addr, len, mode);
- BUG_ON(pChannel->bStatus == MGC_DMA_STATUS_UNKNOWN ||
- pChannel->bStatus == MGC_DMA_STATUS_BUSY);
+ BUG_ON(pChannel->status == MGC_DMA_STATUS_UNKNOWN ||
+ pChannel->status == MGC_DMA_STATUS_BUSY);
- pChannel->dwActualLength = 0;
+ pChannel->actual_len = 0;
pImplChannel->dwStartAddress = dma_addr;
- pImplChannel->len = dwLength;
- pImplChannel->wMaxPacketSize = wPacketSize;
- pChannel->bStatus = MGC_DMA_STATUS_BUSY;
+ pImplChannel->len = len;
+ pImplChannel->wMaxPacketSize = packet_sz;
+ pChannel->status = MGC_DMA_STATUS_BUSY;
- if ((bMode == 1) && (dwLength >= wPacketSize)) {
- configure_channel(pChannel, wPacketSize, 1, dma_addr,
- dwLength);
+ if ((mode == 1) && (len >= packet_sz)) {
+ configure_channel(pChannel, packet_sz, 1, dma_addr,
+ len);
} else
- configure_channel(pChannel, wPacketSize, 0, dma_addr,
- dwLength);
+ configure_channel(pChannel, packet_sz, 0, dma_addr,
+ len);
return TRUE;
}
static int dma_channel_abort(struct dma_channel *pChannel)
{
struct musb_dma_channel *pImplChannel =
- (struct musb_dma_channel *) pChannel->pPrivateData;
+ (struct musb_dma_channel *) pChannel->private_data;
u8 bChannel = pImplChannel->bIndex;
u8 *mbase = pImplChannel->pController->pCoreBase;
u16 csr;
- if (pChannel->bStatus == MGC_DMA_STATUS_BUSY) {
- if (pImplChannel->bTransmit) {
+ if (pChannel->status == MGC_DMA_STATUS_BUSY) {
+ if (pImplChannel->transmit) {
csr = musb_readw(mbase,
- MGC_END_OFFSET(pImplChannel->bEnd,MGC_O_HDRC_TXCSR));
- csr &= ~(MGC_M_TXCSR_AUTOSET |
- MGC_M_TXCSR_DMAENAB |
- MGC_M_TXCSR_DMAMODE);
+ MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR));
+ csr &= ~(MUSB_TXCSR_AUTOSET |
+ MUSB_TXCSR_DMAENAB |
+ MUSB_TXCSR_DMAMODE);
musb_writew(mbase,
- MGC_END_OFFSET(pImplChannel->bEnd,MGC_O_HDRC_TXCSR),
+ MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
csr);
}
else {
csr = musb_readw(mbase,
- MGC_END_OFFSET(pImplChannel->bEnd,MGC_O_HDRC_RXCSR));
- csr &= ~(MGC_M_RXCSR_AUTOCLEAR |
- MGC_M_RXCSR_DMAENAB |
- MGC_M_RXCSR_DMAMODE);
+ MGC_END_OFFSET(pImplChannel->epnum,MUSB_RXCSR));
+ csr &= ~(MUSB_RXCSR_AUTOCLEAR |
+ MUSB_RXCSR_DMAENAB |
+ MUSB_RXCSR_DMAMODE);
musb_writew(mbase,
- MGC_END_OFFSET(pImplChannel->bEnd,MGC_O_HDRC_RXCSR),
+ MGC_END_OFFSET(pImplChannel->epnum,MUSB_RXCSR),
csr);
}
musb_writel(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_COUNT), 0);
- pChannel->bStatus = MGC_DMA_STATUS_FREE;
+ pChannel->status = MGC_DMA_STATUS_FREE;
}
return 0;
}
-static irqreturn_t dma_controller_irq(int irq, void *pPrivateData)
+static irqreturn_t dma_controller_irq(int irq, void *private_data)
{
struct musb_dma_controller *pController =
- (struct musb_dma_controller *)pPrivateData;
+ (struct musb_dma_controller *)private_data;
struct musb_dma_channel *pImplChannel;
u8 *mbase = pController->pCoreBase;
struct dma_channel *pChannel;
u8 bChannel;
- u16 wCsr;
+ u16 csr;
u32 dwAddress;
- u8 bIntr;
+ u8 int_hsdma;
irqreturn_t retval = IRQ_NONE;
- bIntr = musb_readb(mbase, MGC_O_HSDMA_INTR);
- if (!bIntr)
+ int_hsdma = musb_readb(mbase, MGC_O_HSDMA_INTR);
+ if (!int_hsdma)
goto done;
for (bChannel = 0; bChannel < MGC_HSDMA_CHANNELS; bChannel++) {
- if (bIntr & (1 << bChannel)) {
+ if (int_hsdma & (1 << bChannel)) {
pImplChannel = (struct musb_dma_channel *)
&(pController->aChannel[bChannel]);
pChannel = &pImplChannel->Channel;
- wCsr = musb_readw(mbase,
+ csr = musb_readw(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel,
MGC_O_HSDMA_CONTROL));
- if (wCsr & (1 << MGC_S_HSDMA_BUSERROR)) {
- pImplChannel->Channel.bStatus =
+ if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
+ pImplChannel->Channel.status =
MGC_DMA_STATUS_BUS_ABORT;
} else {
dwAddress = musb_readl(mbase,
MGC_HSDMA_CHANNEL_OFFSET(
bChannel,
MGC_O_HSDMA_ADDRESS));
- pChannel->dwActualLength =
+ pChannel->actual_len =
dwAddress - pImplChannel->dwStartAddress;
DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
pChannel, pImplChannel->dwStartAddress,
- dwAddress, pChannel->dwActualLength,
+ dwAddress, pChannel->actual_len,
pImplChannel->len,
- (pChannel->dwActualLength <
+ (pChannel->actual_len <
pImplChannel->len) ?
"=> reconfig 0": "=> complete");
u8 devctl = musb_readb(mbase,
- MGC_O_HDRC_DEVCTL);
+ MUSB_DEVCTL);
- pChannel->bStatus = MGC_DMA_STATUS_FREE;
+ pChannel->status = MGC_DMA_STATUS_FREE;
/* completed */
- if ((devctl & MGC_M_DEVCTL_HM)
- && (pImplChannel->bTransmit)
- && ((pChannel->bDesiredMode == 0)
- || (pChannel->dwActualLength &
+ if ((devctl & MUSB_DEVCTL_HM)
+ && (pImplChannel->transmit)
+ && ((pChannel->desired_mode == 0)
+ || (pChannel->actual_len &
(pImplChannel->wMaxPacketSize - 1)))
) {
/* Send out the packet */
- MGC_SelectEnd(mbase,
- pImplChannel->bEnd);
+ musb_ep_select(mbase,
+ pImplChannel->epnum);
musb_writew(mbase,
- MGC_END_OFFSET(pImplChannel->bEnd,MGC_O_HDRC_TXCSR),
- MGC_M_TXCSR_TXPKTRDY);
+ MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
+ MUSB_TXCSR_TXPKTRDY);
} else
musb_dma_completion(
pController->pDmaPrivate,
- pImplChannel->bEnd,
- pImplChannel->bTransmit);
+ pImplChannel->epnum,
+ pImplChannel->transmit);
}
}
}
void dma_controller_destroy(struct dma_controller *c)
{
struct musb_dma_controller *pController =
- (struct musb_dma_controller *) c->pPrivateData;
+ (struct musb_dma_controller *) c->private_data;
if (!pController)
return;
free_irq(pController->irq, c);
kfree(pController);
- c->pPrivateData = NULL;
+ c->private_data = NULL;
}
struct dma_controller *__init
pController->pDmaPrivate = musb;
pController->pCoreBase = pCoreBase;
- pController->Controller.pPrivateData = pController;
+ pController->Controller.private_data = pController;
pController->Controller.start = dma_controller_start;
pController->Controller.stop = dma_controller_stop;
pController->Controller.channel_alloc = dma_channel_allocate;
projects / linux-2.6-omap-h63xx.git / blobdiff