-/******************************************************************
- * Copyright 2005 Mentor Graphics Corporation
- * Copyright (C) 2005-2006 by Texas Instruments
+/*
+ * MUSB OTG driver internal DMA controller support
*
- * This file is part of the Inventra Controller Driver for Linux.
+ * Copyright 2005 Mentor Graphics Corporation
+ * Copyright (C) 2005-2007 by Texas Instruments
*
- * The Inventra Controller Driver for Linux is free software; you
- * can redistribute it and/or modify it under the terms of the GNU
- * General Public License version 2 as published by the Free Software
- * Foundation.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
*
- * The Inventra Controller Driver for Linux is distributed in
- * the hope that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- * License for more details.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
*
* You should have received a copy of the GNU General Public License
- * along with The Inventra Controller Driver for Linux ; if not,
- * write to the Free Software Foundation, Inc., 59 Temple Place,
- * Suite 330, Boston, MA 02111-1307 USA
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
- * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
- * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
- * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
- * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
- * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
- * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
- * GRAPHICS SUPPORT CUSTOMER.
- ******************************************************************/
+ */
/*
- * DMA implementation for high-speed controllers.
+ * Implementation for the DMA controller within the MUSBMHDRC.
*/
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
#include "musbdefs.h"
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
+#include "omap2430.h"
+#endif
-/****************************** CONSTANTS ********************************/
-
-#define MGC_O_HSDMA_BASE 0x200
-#define MGC_O_HSDMA_INTR 0x200
-
-#define MGC_O_HSDMA_CONTROL 4
-#define MGC_O_HSDMA_ADDRESS 8
-#define MGC_O_HSDMA_COUNT 0xc
+#define MGC_O_HSDMA_BASE 0x200
+#define MGC_O_HSDMA_INTR (MGC_O_HSDMA_BASE + 0)
+#define MGC_O_HSDMA_CONTROL 0x4
+#define MGC_O_HSDMA_ADDRESS 0x8
+#define MGC_O_HSDMA_COUNT 0xc
-#define MGC_HSDMA_CHANNEL_OFFSET(_bChannel, _bOffset) \
- (MGC_O_HSDMA_BASE + (_bChannel << 4) + _bOffset)
+#define MGC_HSDMA_CHANNEL_OFFSET(_bChannel, _offset) \
+ (MGC_O_HSDMA_BASE + (_bChannel << 4) + _offset)
/* control register (16-bit): */
-#define MGC_S_HSDMA_ENABLE 0
-#define MGC_S_HSDMA_TRANSMIT 1
-#define MGC_S_HSDMA_MODE1 2
-#define MGC_S_HSDMA_IRQENABLE 3
-#define MGC_S_HSDMA_ENDPOINT 4
-#define MGC_S_HSDMA_BUSERROR 8
-#define MGC_S_HSDMA_BURSTMODE 9
-#define MGC_M_HSDMA_BURSTMODE (3 << MGC_S_HSDMA_BURSTMODE)
-#define MGC_HSDMA_BURSTMODE_UNSPEC 0
-#define MGC_HSDMA_BURSTMODE_INCR4 1
-#define MGC_HSDMA_BURSTMODE_INCR8 2
-#define MGC_HSDMA_BURSTMODE_INCR16 3
-
-#define MGC_HSDMA_CHANNELS 8
-
-/******************************* Types ********************************/
-
-struct _MGC_HsDmaController;
-
-typedef struct {
- struct dma_channel Channel;
- struct _MGC_HsDmaController *pController;
- u32 dwStartAddress;
- u32 dwCount;
- u8 bIndex;
- u8 bEnd;
- u8 bTransmit;
-} MGC_HsDmaChannel;
-
-struct hsdma {
- struct dma_controller Controller;
- MGC_HsDmaChannel aChannel[MGC_HSDMA_CHANNELS];
- void *pDmaPrivate;
- void __iomem *pCoreBase;
- u8 bChannelCount;
- u8 bmUsedChannels;
+#define MUSB_HSDMA_ENABLE_SHIFT 0
+#define MUSB_HSDMA_TRANSMIT_SHIFT 1
+#define MUSB_HSDMA_MODE1_SHIFT 2
+#define MUSB_HSDMA_IRQENABLE_SHIFT 3
+#define MUSB_HSDMA_ENDPOINT_SHIFT 4
+#define MUSB_HSDMA_BUSERROR_SHIFT 8
+#define MUSB_HSDMA_BURSTMODE_SHIFT 9
+#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
+#define MGC_HSDMA_BURSTMODE_UNSPEC 0
+#define MGC_HSDMA_BURSTMODE_INCR4 1
+#define MGC_HSDMA_BURSTMODE_INCR8 2
+#define MGC_HSDMA_BURSTMODE_INCR16 3
+
+#define MGC_HSDMA_CHANNELS 8
+
+struct musb_dma_controller;
+
+struct musb_dma_channel {
+ struct dma_channel Channel;
+ struct musb_dma_controller *pController;
+ u32 dwStartAddress;
+ u32 len;
+ u16 wMaxPacketSize;
+ u8 bIndex;
+ u8 epnum;
+ u8 transmit;
};
-/* FIXME remove typedef noise */
-typedef struct hsdma MGC_HsDmaController;
-
-/****************************** FUNCTIONS ********************************/
+struct musb_dma_controller {
+ struct dma_controller Controller;
+ struct musb_dma_channel aChannel[MGC_HSDMA_CHANNELS];
+ void *pDmaPrivate;
+ void __iomem *pCoreBase;
+ u8 bChannelCount;
+ u8 bmUsedChannels;
+ u8 irq;
+};
-static int MGC_HsDmaStartController(struct dma_controller *c)
+static int dma_controller_start(struct dma_controller *c)
{
/* nothing to do */
return 0;
}
-static int MGC_HsDmaStopController(struct dma_controller *c)
+static void dma_channel_release(struct dma_channel *pChannel);
+
+static int dma_controller_stop(struct dma_controller *c)
{
- /* nothing to do */
+ struct musb_dma_controller *pController =
+ container_of(c, struct musb_dma_controller, Controller);
+ struct musb *musb = (struct musb *) pController->pDmaPrivate;
+ struct dma_channel *pChannel;
+ u8 bBit;
+
+ if (pController->bmUsedChannels != 0) {
+ dev_err(musb->controller,
+ "Stopping DMA controller while channel active\n");
+
+ for (bBit = 0; bBit < MGC_HSDMA_CHANNELS; bBit++) {
+ if (pController->bmUsedChannels & (1 << bBit)) {
+ pChannel = &(pController->aChannel[bBit].Channel);
+ dma_channel_release(pChannel);
+
+ if (!pController->bmUsedChannels)
+ break;
+ }
+ }
+ }
return 0;
}
-static struct dma_channel *MGC_HsDmaAllocateChannel(
- struct dma_controller *c,
- struct musb_hw_ep *hw_ep,
- u8 bTransmit)
+static struct dma_channel* dma_channel_allocate(struct dma_controller *c,
+ struct musb_hw_ep *hw_ep, u8 transmit)
{
u8 bBit;
struct dma_channel *pChannel = NULL;
- MGC_HsDmaChannel *pImplChannel = NULL;
- MGC_HsDmaController *pController;
+ struct musb_dma_channel *pImplChannel = NULL;
+ struct musb_dma_controller *pController =
+ container_of(c, struct musb_dma_controller, Controller);
- pcontroller = container_of(c, struct hsdma, Controller);
for (bBit = 0; bBit < MGC_HSDMA_CHANNELS; bBit++) {
if (!(pController->bmUsedChannels & (1 << bBit))) {
pController->bmUsedChannels |= (1 << bBit);
pImplChannel = &(pController->aChannel[bBit]);
pImplChannel->pController = pController;
pImplChannel->bIndex = bBit;
- pImplChannel->bEnd = hw_ep->bLocalEnd;
- pImplChannel->bTransmit = bTransmit;
+ pImplChannel->epnum = hw_ep->epnum;
+ pImplChannel->transmit = transmit;
pChannel = &(pImplChannel->Channel);
- pChannel->pPrivateData = pImplChannel;
- pChannel->bStatus = MGC_DMA_STATUS_FREE;
- pChannel->dwMaxLength = 0x10000;
+ pChannel->private_data = pImplChannel;
+ pChannel->status = MGC_DMA_STATUS_FREE;
+ pChannel->max_len = 0x10000;
/* Tx => mode 1; Rx => mode 0 */
- pChannel->bDesiredMode = bTransmit;
- pChannel->dwActualLength = 0;
+ pChannel->desired_mode = transmit;
+ pChannel->actual_len = 0;
break;
}
}
return pChannel;
}
-static void MGC_HsDmaReleaseChannel(struct dma_channel *pChannel)
+static void dma_channel_release(struct dma_channel *pChannel)
{
- MGC_HsDmaChannel *pImplChannel =
- (MGC_HsDmaChannel *) pChannel->pPrivateData;
-
- pImplChannel->pController->bmUsedChannels &=
- ~(1 << pImplChannel->bIndex);
- pChannel->bStatus = MGC_DMA_STATUS_FREE;
-}
+ struct musb_dma_channel *pImplChannel =
+ (struct musb_dma_channel *) pChannel->private_data;
-static void clear_state(struct dma_channel *pChannel)
-{
- MGC_HsDmaChannel *pImplChannel =
- (MGC_HsDmaChannel *) pChannel->pPrivateData;
- MGC_HsDmaController *pController = pImplChannel->pController;
- u8 *pBase = pController->pCoreBase;
- u8 bChannel = pImplChannel->bIndex;
+ pChannel->actual_len = 0;
+ pImplChannel->dwStartAddress = 0;
+ pImplChannel->len = 0;
- musb_writew(pBase,
- MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_CONTROL),
- 0);
- musb_writel(pBase,
- MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_ADDRESS),
- 0);
- musb_writel(pBase,
- MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_COUNT),
- 0);
+ pImplChannel->pController->bmUsedChannels &=
+ ~(1 << pImplChannel->bIndex);
- pChannel->dwActualLength = 0L;
- pImplChannel->dwStartAddress = 0;
- pImplChannel->dwCount = 0;
+ pChannel->status = MGC_DMA_STATUS_UNKNOWN;
}
-static u8 configure_channel(struct dma_channel *pChannel,
- u16 wPacketSize, u8 bMode,
- dma_addr_t dma_addr, u32 dwLength)
+static void configure_channel(struct dma_channel *pChannel,
+ u16 packet_sz, u8 mode,
+ dma_addr_t dma_addr, u32 len)
{
- MGC_HsDmaChannel *pImplChannel =
- (MGC_HsDmaChannel *) pChannel->pPrivateData;
- MGC_HsDmaController *pController = pImplChannel->pController;
- u8 *pBase = pController->pCoreBase;
+ struct musb_dma_channel *pImplChannel =
+ (struct musb_dma_channel *) pChannel->private_data;
+ struct musb_dma_controller *pController = pImplChannel->pController;
+ u8 *mbase = pController->pCoreBase;
u8 bChannel = pImplChannel->bIndex;
- u16 wCsr = 0;
+ u16 csr = 0;
- DBG(2, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
- pChannel, wPacketSize, dma_addr, dwLength, bMode);
+ DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
+ pChannel, packet_sz, dma_addr, len, mode);
- if (bMode) {
- wCsr |= 1 << MGC_S_HSDMA_MODE1;
- if (dwLength < wPacketSize) {
+ if (mode) {
+ csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
+ if (len < packet_sz) {
return FALSE;
}
- if (wPacketSize >= 64) {
- wCsr |=
- MGC_HSDMA_BURSTMODE_INCR16 << MGC_S_HSDMA_BURSTMODE;
- } else if (wPacketSize >= 32) {
- wCsr |=
- MGC_HSDMA_BURSTMODE_INCR8 << MGC_S_HSDMA_BURSTMODE;
- } else if (wPacketSize >= 16) {
- wCsr |=
- MGC_HSDMA_BURSTMODE_INCR4 << MGC_S_HSDMA_BURSTMODE;
+ if (packet_sz >= 64) {
+ csr |=
+ MGC_HSDMA_BURSTMODE_INCR16 << MUSB_HSDMA_BURSTMODE_SHIFT;
+ } else if (packet_sz >= 32) {
+ csr |=
+ MGC_HSDMA_BURSTMODE_INCR8 << MUSB_HSDMA_BURSTMODE_SHIFT;
+ } else if (packet_sz >= 16) {
+ csr |=
+ MGC_HSDMA_BURSTMODE_INCR4 << MUSB_HSDMA_BURSTMODE_SHIFT;
}
}
- wCsr |= (pImplChannel->bEnd << MGC_S_HSDMA_ENDPOINT)
- | (1 << MGC_S_HSDMA_ENABLE)
- | (1 << MGC_S_HSDMA_IRQENABLE)
- | (pImplChannel->bTransmit ? (1 << MGC_S_HSDMA_TRANSMIT) : 0);
+ csr |= (pImplChannel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
+ | (1 << MUSB_HSDMA_ENABLE_SHIFT)
+ | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
+ | (pImplChannel->transmit ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) : 0);
/* address/count */
- musb_writel(pBase,
+ musb_writel(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_ADDRESS),
dma_addr);
- musb_writel(pBase,
+ musb_writel(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_COUNT),
- dwLength);
+ len);
/* control (this should start things) */
- musb_writew(pBase,
+ musb_writew(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_CONTROL),
- wCsr);
-
- return TRUE;
+ csr);
}
-static int MGC_HsDmaProgramChannel(struct dma_channel * pChannel,
- u16 wPacketSize, u8 bMode,
- dma_addr_t dma_addr, u32 dwLength)
+static int dma_channel_program(struct dma_channel * pChannel,
+ u16 packet_sz, u8 mode,
+ dma_addr_t dma_addr, u32 len)
{
- MGC_HsDmaChannel *pImplChannel =
- (MGC_HsDmaChannel *) pChannel->pPrivateData;
+ struct musb_dma_channel *pImplChannel =
+ (struct musb_dma_channel *) pChannel->private_data;
- DBG(2, "pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
- wPacketSize, dma_addr, dwLength, bMode);
+ DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
+ pImplChannel->epnum,
+ pImplChannel->transmit ? "Tx" : "Rx",
+ packet_sz, dma_addr, len, mode);
- BUG_ON(pChannel->bStatus != MGC_DMA_STATUS_FREE);
+ BUG_ON(pChannel->status == MGC_DMA_STATUS_UNKNOWN ||
+ pChannel->status == MGC_DMA_STATUS_BUSY);
- pChannel->dwActualLength = 0L;
+ pChannel->actual_len = 0;
pImplChannel->dwStartAddress = dma_addr;
- pImplChannel->dwCount = dwLength;
-
- pChannel->bStatus = MGC_DMA_STATUS_BUSY;
-
- if ((bMode == 1) && (dwLength >= wPacketSize)) {
-
-#if 0
- /* mode 1 sends an extra IN token at the end of
- * full packet transfer in host Rx
- */
- if (dwLength % wPacketSize == 0)
- dwLength -= wPacketSize;
-
- /* mode 1 doesn't give an interrupt on short packet */
- configure_channel(pChannel, wPacketSize, 1, dma_addr,
- dwLength & ~(wPacketSize - 1));
- /* the rest (<= pkt_size) will be transferred in mode 0 */
-#endif
-
- configure_channel(pChannel, wPacketSize, 1, dma_addr,
- dwLength);
+ pImplChannel->len = len;
+ pImplChannel->wMaxPacketSize = packet_sz;
+ pChannel->status = MGC_DMA_STATUS_BUSY;
+ if ((mode == 1) && (len >= packet_sz)) {
+ configure_channel(pChannel, packet_sz, 1, dma_addr,
+ len);
} else
- configure_channel(pChannel, wPacketSize, 0, dma_addr,
- dwLength);
+ configure_channel(pChannel, packet_sz, 0, dma_addr,
+ len);
return TRUE;
}
-// REVISIT...
-static int MGC_HsDmaAbortChannel(struct dma_channel *pChannel)
+static int dma_channel_abort(struct dma_channel *pChannel)
{
- clear_state(pChannel);
- pChannel->bStatus = MGC_DMA_STATUS_FREE;
+ struct musb_dma_channel *pImplChannel =
+ (struct musb_dma_channel *) pChannel->private_data;
+ u8 bChannel = pImplChannel->bIndex;
+ u8 *mbase = pImplChannel->pController->pCoreBase;
+ u16 csr;
+
+ if (pChannel->status == MGC_DMA_STATUS_BUSY) {
+ if (pImplChannel->transmit) {
+
+ csr = musb_readw(mbase,
+ MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR));
+ csr &= ~(MUSB_TXCSR_AUTOSET |
+ MUSB_TXCSR_DMAENAB |
+ MUSB_TXCSR_DMAMODE);
+ musb_writew(mbase,
+ MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
+ csr);
+ }
+ else {
+ csr = musb_readw(mbase,
+ MGC_END_OFFSET(pImplChannel->epnum,MUSB_RXCSR));
+ csr &= ~(MUSB_RXCSR_AUTOCLEAR |
+ MUSB_RXCSR_DMAENAB |
+ MUSB_RXCSR_DMAMODE);
+ musb_writew(mbase,
+ MGC_END_OFFSET(pImplChannel->epnum,MUSB_RXCSR),
+ csr);
+ }
+
+ musb_writew(mbase,
+ MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_CONTROL), 0);
+ musb_writel(mbase,
+ MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_ADDRESS), 0);
+ musb_writel(mbase,
+ MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_COUNT), 0);
+
+ pChannel->status = MGC_DMA_STATUS_FREE;
+ }
return 0;
}
-static irqreturn_t
-hsdma_irq(int irq, void *pPrivateData, struct pt_regs *regs)
+static irqreturn_t dma_controller_irq(int irq, void *private_data)
{
+ struct musb_dma_controller *pController =
+ (struct musb_dma_controller *)private_data;
+ struct musb_dma_channel *pImplChannel;
+ u8 *mbase = pController->pCoreBase;
+ struct dma_channel *pChannel;
u8 bChannel;
- u16 wCsr;
+ u16 csr;
u32 dwAddress;
- MGC_HsDmaChannel *pImplChannel;
- MGC_HsDmaController *pController = pPrivateData;
- u8 *pBase = pController->pCoreBase;
- struct dma_channel *pChannel;
- u8 bIntr = musb_readb(pBase, MGC_O_HSDMA_INTR);
+ u8 int_hsdma;
+ irqreturn_t retval = IRQ_NONE;
- if (!bIntr)
- return IRQ_NONE;
+ int_hsdma = musb_readb(mbase, MGC_O_HSDMA_INTR);
+ if (!int_hsdma)
+ goto done;
for (bChannel = 0; bChannel < MGC_HSDMA_CHANNELS; bChannel++) {
- if (bIntr & (1 << bChannel)) {
-
- pImplChannel = (MGC_HsDmaChannel *)
+ if (int_hsdma & (1 << bChannel)) {
+ pImplChannel = (struct musb_dma_channel *)
&(pController->aChannel[bChannel]);
pChannel = &pImplChannel->Channel;
- wCsr = musb_readw(pBase,
+ csr = musb_readw(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel,
MGC_O_HSDMA_CONTROL));
- if (wCsr & (1 << MGC_S_HSDMA_BUSERROR)) {
- pImplChannel->Channel.bStatus =
+ if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
+ pImplChannel->Channel.status =
MGC_DMA_STATUS_BUS_ABORT;
} else {
- dwAddress = musb_readl(pBase,
- MGC_HSDMA_CHANNEL_OFFSET
- (bChannel,
+ dwAddress = musb_readl(mbase,
+ MGC_HSDMA_CHANNEL_OFFSET(
+ bChannel,
MGC_O_HSDMA_ADDRESS));
- pChannel->dwActualLength =
+ pChannel->actual_len =
dwAddress - pImplChannel->dwStartAddress;
DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
pChannel, pImplChannel->dwStartAddress,
- dwAddress, pChannel->dwActualLength,
- pImplChannel->dwCount,
- (pChannel->dwActualLength <
- pImplChannel->dwCount) ?
+ dwAddress, pChannel->actual_len,
+ pImplChannel->len,
+ (pChannel->actual_len <
+ pImplChannel->len) ?
"=> reconfig 0": "=> complete");
-#if 0
- if (pChannel->dwActualLength <
- pImplChannel->dwCount) {
- /* mode 1 sends an extra IN request if
- the last packet is a complete packet */
- u16 newcsr = MGC_ReadCsr16(pBase,
- MGC_O_HDRC_RXCSR,
- pImplChannel->bEnd);
- newcsr &= ~(MGC_M_RXCSR_H_AUTOREQ |
- MGC_M_RXCSR_H_REQPKT);
- MGC_WriteCsr16(pBase, MGC_O_HDRC_RXCSR,
- pImplChannel->bEnd,
- MGC_M_RXCSR_H_WZC_BITS |
- newcsr);
-
- configure_channel(pChannel,
- pImplChannel->wMaxPacketSize,
- 0, dwAddress,
- pImplChannel->dwCount -
- pChannel->dwActualLength);
- }
- else
-#endif
- {
- pChannel->bStatus = MGC_DMA_STATUS_FREE;
- /* completed */
+
+ u8 devctl = musb_readb(mbase,
+ MUSB_DEVCTL);
+
+ pChannel->status = MGC_DMA_STATUS_FREE;
+
+ /* completed */
+ if ((devctl & MUSB_DEVCTL_HM)
+ && (pImplChannel->transmit)
+ && ((pChannel->desired_mode == 0)
+ || (pChannel->actual_len &
+ (pImplChannel->wMaxPacketSize - 1)))
+ ) {
+ /* Send out the packet */
+ musb_ep_select(mbase,
+ pImplChannel->epnum);
+ musb_writew(mbase,
+ MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
+ MUSB_TXCSR_TXPKTRDY);
+ } else
musb_dma_completion(
pController->pDmaPrivate,
- pImplChannel->bEnd,
- pImplChannel->bTransmit);
- }
+ pImplChannel->epnum,
+ pImplChannel->transmit);
}
}
}
- return IRQ_HANDLED;
+ retval = IRQ_HANDLED;
+done:
+ return retval;
}
-static void hsdma_controller_destroy(struct dma_controller *pController)
+void dma_controller_destroy(struct dma_controller *c)
{
- MGC_HsDmaController *pHsController = pController->pPrivateData;
+ struct musb_dma_controller *pController =
+ (struct musb_dma_controller *) c->private_data;
- if (pHsController) {
- pHsController->Controller.pPrivateData = NULL;
- kfree(pHsController);
- }
+ if (!pController)
+ return;
+
+ if (pController->irq)
+ free_irq(pController->irq, c);
+
+ kfree(pController);
+ c->private_data = NULL;
}
-static struct dma_controller *
-hsdma_controller_new(struct musb *pThis, void __iomem *pCoreBase)
+struct dma_controller *__init
+dma_controller_create(struct musb *musb, void __iomem *pCoreBase)
{
- MGC_HsDmaController *pController;
- struct device *dev = pThis->controller;
+ struct musb_dma_controller *pController;
+ struct device *dev = musb->controller;
struct platform_device *pdev = to_platform_device(dev);
int irq = platform_get_irq(pdev, 1);
return NULL;
}
- if (!(pController = kzalloc(sizeof(MGC_HsDmaController), GFP_KERNEL)))
+ if (!(pController = kzalloc(sizeof(struct musb_dma_controller),
+ GFP_KERNEL)))
return NULL;
pController->bChannelCount = MGC_HSDMA_CHANNELS;
- pController->pDmaPrivate = pThis;
+ pController->pDmaPrivate = musb;
pController->pCoreBase = pCoreBase;
- pController->Controller.pPrivateData = pController;
- pController->Controller.start = MGC_HsDmaStartController;
- pController->Controller.stop = MGC_HsDmaStopController;
- pController->Controller.channel_alloc = MGC_HsDmaAllocateChannel;
- pController->Controller.channel_release = MGC_HsDmaReleaseChannel;
- pController->Controller.channel_program = MGC_HsDmaProgramChannel;
- pController->Controller.channel_abort = MGC_HsDmaAbortChannel;
+ pController->Controller.private_data = pController;
+ pController->Controller.start = dma_controller_start;
+ pController->Controller.stop = dma_controller_stop;
+ pController->Controller.channel_alloc = dma_channel_allocate;
+ pController->Controller.channel_release = dma_channel_release;
+ pController->Controller.channel_program = dma_channel_program;
+ pController->Controller.channel_abort = dma_channel_abort;
- if (request_irq(irq, hsdma_irq, SA_INTERRUPT,
- pThis->controller->bus_id, &pController->Controller)) {
+ if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
+ musb->controller->bus_id, &pController->Controller)) {
dev_err(dev, "request_irq %d failed!\n", irq);
- hsdma_controller_destroy(&pController->Controller);
+ dma_controller_destroy(&pController->Controller);
return NULL;
}
+ pController->irq = irq;
+
return &pController->Controller;
}
-
-const struct dma_controller_factory dma_controller_factory = {
- .create = hsdma_controller_new,
- .destroy = hsdma_controller_destroy,
-};
projects / linux-2.6-omap-h63xx.git / blobdiff