[PATCH] ARM: 2752/1: disable ixp2000 PCI I/O software workaround on chips that don...

[linux-2.6-omap-h63xx.git] / include / asm-arm / arch-ixp2000 / io.h

diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h
index 083462668e184a8953ef49ed8eb9753c38d35d24..3241cd6f0778e0384e188a945a8747f705f68750 100644 (file)
--- a/include/asm-arm/arch-ixp2000/io.h
+++ b/include/asm-arm/arch-ixp2000/io.h
@@ -17,18 +17,23 @@
 
 #define IO_SPACE_LIMIT         0xffffffff
 #define __mem_pci(a)           (a)
-#define ___io(p)               ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
 
 /*
- * The IXP2400 before revision B0 asserts byte lanes for PCI I/O
+ * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
  * transactions the other way round (MEM transactions don't have this
- * issue), so we need to override the standard functions.  B0 and later
- * have a bit that can be set to 1 to get the 'proper' behavior, but
- * since that isn't available on the A? revisions we just keep doing
- * things manually.
+ * issue), so if we want to support those models, we need to override
+ * the standard I/O functions.
+ *
+ * B0 and later have a bit that can be set to 1 to get the proper
+ * behavior for I/O transactions, which then allows us to use the
+ * standard I/O functions.  This is what we do if the user does not
+ * explicitly ask for support for pre-B0.
  */
-#define alignb(addr)           (void __iomem *)((unsigned long)addr ^ 3)
-#define alignw(addr)           (void __iomem *)((unsigned long)addr ^ 2)
+#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
+#define ___io(p)               ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
+
+#define alignb(addr)           (void __iomem *)((unsigned long)(addr) ^ 3)
+#define alignw(addr)           (void __iomem *)((unsigned long)(addr) ^ 2)
 
 #define outb(v,p)              __raw_writeb((v),alignb(___io(p)))
 #define outw(v,p)              __raw_writew((v),alignw(___io(p)))
@@ -48,6 +53,81 @@
 #define insw(p,d,l)            __raw_readsw(alignw(___io(p)),d,l)
 #define insl(p,d,l)            __raw_readsl(___io(p),d,l)
 
+#define __is_io_address(p)     ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
+
+#define ioread8(p)                                             \
+       ({                                                      \
+               unsigned int __v;                               \
+                                                               \
+               if (__is_io_address(p)) {                       \
+                       __v = __raw_readb(alignb(p));           \
+               } else {                                        \
+                       __v = __raw_readb(p);                   \
+               }                                               \
+                                                               \
+               __v;                                            \
+       })                                                      \
+
+#define ioread16(p)                                            \
+       ({                                                      \
+               unsigned int __v;                               \
+                                                               \
+               if (__is_io_address(p)) {                       \
+                       __v = __raw_readw(alignw(p));           \
+               } else {                                        \
+                       __v = le16_to_cpu(__raw_readw(p));      \
+               }                                               \
+                                                               \
+               __v;                                            \
+       })
+
+#define ioread32(p)                                            \
+       ({                                                      \
+               unsigned int __v;                               \
+                                                               \
+               if (__is_io_address(p)) {                       \
+                       __v = __raw_readl(p);                   \
+               } else {                                        \
+                       __v = le32_to_cpu(__raw_readl(p));      \
+               }                                               \
+                                                               \
+                __v;                                           \
+       })
+
+#define iowrite8(v,p)                                          \
+       ({                                                      \
+               if (__is_io_address(p)) {                       \
+                       __raw_writeb((v), alignb(p));           \
+               } else {                                        \
+                       __raw_writeb((v), p);                   \
+               }                                               \
+       })
+
+#define iowrite16(v,p)                                         \
+       ({                                                      \
+               if (__is_io_address(p)) {                       \
+                       __raw_writew((v), alignw(p));           \
+               } else {                                        \
+                       __raw_writew(cpu_to_le16(v), p);        \
+               }                                               \
+       })
+
+#define iowrite32(v,p)                                         \
+       ({                                                      \
+               if (__is_io_address(p)) {                       \
+                       __raw_writel((v), p);                   \
+               } else {                                        \
+                       __raw_writel(cpu_to_le32(v), p);        \
+               }                                               \
+       })
+
+#define ioport_map(port, nr)   ___io(port)
+
+#define ioport_unmap(addr)
+#else
+#define __io(p)                        ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
+#endif
+
 
 #ifdef CONFIG_ARCH_IXDP2X01
 /*