Merge master.kernel.org:/home/rmk/linux-2.6-arm

[linux-2.6-omap-h63xx.git] / include / asm-blackfin / mach-bf527 / blackfin.h

diff --git a/include/asm-blackfin/mach-bf527/blackfin.h b/include/asm-blackfin/mach-bf527/blackfin.h
index 1bd07e30781c5581d72a928b9605d065f4cdfc07..297821e2d79a7217f1551d38bcbaf920fea50ea4 100644 (file)
--- a/include/asm-blackfin/mach-bf527/blackfin.h
+++ b/include/asm-blackfin/mach-bf527/blackfin.h
@@ -39,22 +39,22 @@
 #include "defBF522.h"
 #include "anomaly.h"
 
-#if defined(CONFIG_BF527)
+#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
 #include "defBF527.h"
 #endif
 
-#if defined(CONFIG_BF525)
+#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
 #include "defBF525.h"
 #endif
 
 #if !defined(__ASSEMBLY__)
 #include "cdefBF522.h"
 
-#if defined(CONFIG_BF527)
+#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
 #include "cdefBF527.h"
 #endif
 
-#if defined(CONFIG_BF525)
+#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
 #include "cdefBF525.h"
 #endif
 #endif
@@ -64,6 +64,21 @@
 #define STATUS_P1      0x02
 #define STATUS_P0      0x01
 
+#define BFIN_UART_NR_PORTS     2
+
+#define OFFSET_THR              0x00   /* Transmit Holding register            */
+#define OFFSET_RBR              0x00   /* Receive Buffer register              */
+#define OFFSET_DLL              0x00   /* Divisor Latch (Low-Byte)             */
+#define OFFSET_IER              0x04   /* Interrupt Enable Register            */
+#define OFFSET_DLH              0x04   /* Divisor Latch (High-Byte)            */
+#define OFFSET_IIR              0x08   /* Interrupt Identification Register    */
+#define OFFSET_LCR              0x0C   /* Line Control Register                */
+#define OFFSET_MCR              0x10   /* Modem Control Register               */
+#define OFFSET_LSR              0x14   /* Line Status Register                 */
+#define OFFSET_MSR              0x18   /* Modem Status Register                */
+#define OFFSET_SCR              0x1C   /* SCR Scratch Register                 */
+#define OFFSET_GCTL             0x24   /* Global Control Register              */
+
 /* DPMC*/
 #define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
 #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)