mm/allocpercpu.c: make 4 functions static

[linux-2.6-omap-h63xx.git] / include / asm-mips / io.h

diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 7ba92890ea13eeeef95f55d9bb0e9b9429ed593b..501a40b9f18da08f17d7939a14125f7db83f6693 100644 (file)
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -40,11 +40,11 @@
  * hardware.  An example use would be for flash memory that's used for
  * execute in place.
  */
-# define __raw_ioswabb(a,x)    (x)
-# define __raw_ioswabw(a,x)    (x)
-# define __raw_ioswabl(a,x)    (x)
-# define __raw_ioswabq(a,x)    (x)
-# define ____raw_ioswabq(a,x)  (x)
+# define __raw_ioswabb(a, x)   (x)
+# define __raw_ioswabw(a, x)   (x)
+# define __raw_ioswabl(a, x)   (x)
+# define __raw_ioswabq(a, x)   (x)
+# define ____raw_ioswabq(a, x) (x)
 
 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
 
@@ -160,13 +160,6 @@ static inline void * isa_bus_to_virt(unsigned long address)
 #define virt_to_bus virt_to_phys
 #define bus_to_virt phys_to_virt
 
-/*
- * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
- * for the processor.  This implies the assumption that there is only
- * one of these busses.
- */
-extern unsigned long isa_slot_offset;
-
 /*
  * Change "struct page" to physical address.
  */
@@ -273,7 +266,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
  * memory-like regions on I/O busses.
  */
 #define ioremap_cachable(offset, size)                                 \
-       __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT)
+       __ioremap_mode((offset), (size), _page_cachable_default)
 
 /*
  * These two are MIPS specific ioremap variant.  ioremap_cacheable_cow
@@ -527,16 +520,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
        memcpy((void __force *) dst, src, count);
 }
 
-/*
- * ISA space is 'always mapped' on currently supported MIPS systems, no need
- * to explicitly ioremap() it. The fact that the ISA IO space is mapped
- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
- * are physical addresses. The following constant pointer can be
- * used as the IO-area pointer (it can be iounmapped as well, so the
- * analogy with PCI is quite large):
- */
-#define __ISA_IO_base ((char *)(isa_slot_offset))
-
 /*
  * The caches on some architectures aren't dma-coherent and have need to
  * handle this in software.  There are three types of operations that
@@ -554,6 +537,8 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
  *    caches.  Dirty lines of the caches may be written back or simply
  *    be discarded.  This operation is necessary before dma operations
  *    to the memory.
+ *
+ * This API used to be exported; it now is for arch code internal use only.
  */
 #ifdef CONFIG_DMA_NONCOHERENT
 
@@ -561,9 +546,9 @@ extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 
-#define dma_cache_wback_inv(start, size)       _dma_cache_wback_inv(start,size)
-#define dma_cache_wback(start, size)           _dma_cache_wback(start,size)
-#define dma_cache_inv(start, size)             _dma_cache_inv(start,size)
+#define dma_cache_wback_inv(start, size)       _dma_cache_wback_inv(start, size)
+#define dma_cache_wback(start, size)           _dma_cache_wback(start, size)
+#define dma_cache_inv(start, size)             _dma_cache_inv(start, size)
 
 #else /* Sane hardware */
 
@@ -587,7 +572,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 #define __CSR_32_ADJUST 0
 #endif
 
-#define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
+#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
 #define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
 
 /*