[MIPS] Alchemy: kill unused PCI_IRQ_TABLE_LOOKUP macro

[linux-2.6-omap-h63xx.git] / include / asm-mips / mach-au1x00 / au1000.h

diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 3bdce9126f16c9eccb8b7fa6143f2d15a7526b6d..a05555165d05b14192c8ed7f19411a49382dbfbf 100644 (file)
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -3,9 +3,8 @@
  * BRIEF MODULE DESCRIPTION
  *     Include file for Alchemy Semiconductor's Au1k CPU.
  *
- * Copyright 2000,2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *             ppopov@mvista.com or source@mvista.com
+ * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
  *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
@@ -117,13 +116,6 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
 
 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
-#ifdef CONFIG_PM
-/* no CP0 timer irq */
-#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
-#else
-#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
-#endif
-
 /*
  * SDRAM Register Offsets
  */
@@ -526,7 +518,7 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
 /* Au1000 */
 #ifdef CONFIG_SOC_AU1000
 enum soc_au1000_ints {
-       AU1000_FIRST_INT        = MIPS_CPU_IRQ_BASE,
+       AU1000_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
        AU1000_UART0_INT        = AU1000_FIRST_INT,
        AU1000_UART1_INT,                               /* au1000 */
        AU1000_UART2_INT,                               /* au1000 */
@@ -605,7 +597,7 @@ enum soc_au1000_ints {
 /* Au1500 */
 #ifdef CONFIG_SOC_AU1500
 enum soc_au1500_ints {
-       AU1500_FIRST_INT        = MIPS_CPU_IRQ_BASE,
+       AU1500_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
        AU1500_UART0_INT        = AU1500_FIRST_INT,
        AU1000_PCI_INTA,                                /* au1500 */
        AU1000_PCI_INTB,                                /* au1500 */
@@ -686,7 +678,7 @@ enum soc_au1500_ints {
 /* Au1100 */
 #ifdef CONFIG_SOC_AU1100
 enum soc_au1100_ints {
-       AU1100_FIRST_INT        = MIPS_CPU_IRQ_BASE,
+       AU1100_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
        AU1100_UART0_INT,
        AU1100_UART1_INT,
        AU1100_SD_INT,
@@ -761,7 +753,7 @@ enum soc_au1100_ints {
 
 #ifdef CONFIG_SOC_AU1550
 enum soc_au1550_ints {
-       AU1550_FIRST_INT        = MIPS_CPU_IRQ_BASE,
+       AU1550_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
        AU1550_UART0_INT        = AU1550_FIRST_INT,
        AU1550_PCI_INTA,
        AU1550_PCI_INTB,
@@ -851,7 +843,7 @@ enum soc_au1550_ints {
 
 #ifdef CONFIG_SOC_AU1200
 enum soc_au1200_ints {
-       AU1200_FIRST_INT        = MIPS_CPU_IRQ_BASE,
+       AU1200_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
        AU1200_UART0_INT        = AU1200_FIRST_INT,
        AU1200_SWT_INT,
        AU1200_SD_INT,
@@ -948,11 +940,12 @@ enum soc_au1200_ints {
 
 #endif /* CONFIG_SOC_AU1200 */
 
-#define AU1000_INTC0_INT_BASE  (MIPS_CPU_IRQ_BASE + 0)
-#define AU1000_INTC0_INT_LAST  (MIPS_CPU_IRQ_BASE + 31)
-#define AU1000_INTC1_INT_BASE  (MIPS_CPU_IRQ_BASE + 32)
-#define AU1000_INTC1_INT_LAST  (MIPS_CPU_IRQ_BASE + 63)
-#define AU1000_MAX_INTR                (MIPS_CPU_IRQ_BASE + 63)
+#define AU1000_INTC0_INT_BASE  (MIPS_CPU_IRQ_BASE + 8)
+#define AU1000_INTC0_INT_LAST  (AU1000_INTC0_INT_BASE + 31)
+#define AU1000_INTC1_INT_BASE  (AU1000_INTC0_INT_BASE + 32)
+#define AU1000_INTC1_INT_LAST  (AU1000_INTC1_INT_BASE + 31)
+
+#define AU1000_MAX_INTR        AU1000_INTC1_INT_LAST
 #define INTX                   0xFF                    /* not valid */
 
 /* Programmable Counters 0 and 1 */
@@ -1679,10 +1672,11 @@ enum soc_au1200_ints {
 #define Au1500_PCI_MEM_START      0x440000000ULL
 #define Au1500_PCI_MEM_END        0x44FFFFFFFULL
 
-#define PCI_IO_START    (Au1500_PCI_IO_START + 0x1000)
-#define PCI_IO_END      (Au1500_PCI_IO_END)
-#define PCI_MEM_START   (Au1500_PCI_MEM_START)
-#define PCI_MEM_END     (Au1500_PCI_MEM_END)
+#define PCI_IO_START   0x00001000
+#define PCI_IO_END     0x000FFFFF
+#define PCI_MEM_START  0x40000000
+#define PCI_MEM_END    0x4FFFFFFF
+
 #define PCI_FIRST_DEVFN (0<<3)
 #define PCI_LAST_DEVFN  (19<<3)
 
@@ -1691,20 +1685,6 @@ enum soc_au1200_ints {
 #define IOMEM_RESOURCE_START  0x10000000
 #define IOMEM_RESOURCE_END    0xffffffff
 
-  /*
-   * Borrowed from the PPC arch:
-   * The following macro is used to lookup irqs in a standard table
-   * format for those PPC systems that do not already have PCI
-   * interrupts properly routed.
-   */
-  /* FIXME - double check this from asm-ppc/pci-bridge.h */
-#define PCI_IRQ_TABLE_LOOKUP                            \
-  ({ long _ctl_ = -1;                                 \
-      if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot)    \
-              _ctl_ = pci_irq_table[idsel - min_idsel][pin-1];               \
-                     _ctl_; })
-
-
 #else /* Au1000 and Au1100 and Au1200 */
 
 /* don't allow any legacy ports probing */
@@ -1784,6 +1764,7 @@ struct cpu_spec {
        char            *cpu_name;
        unsigned char   cpu_od;         /* Set Config[OD] */
        unsigned char   cpu_bclk;       /* Enable BCLK switching */
+       unsigned char   cpu_pll_wo;     /* sys_cpupll reg. write-only */
 };
 
 extern struct cpu_spec         cpu_specs[];