[S390] cio: Make ccw_dev_id_is_equal() more robust.

[linux-2.6-omap-h63xx.git] / include / asm-mips / mips-boards / maltaint.h

diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h
index 376181882e81a8bd5a4470339b6fb53dbc7b7ce9..da6cc2fbbc780990e1685973b064697aa7bb19ea 100644 (file)
--- a/include/asm-mips/mips-boards/maltaint.h
+++ b/include/asm-mips/mips-boards/maltaint.h
@@ -25,9 +25,63 @@
 #ifndef _MIPS_MALTAINT_H
 #define _MIPS_MALTAINT_H
 
-/* Number of IRQ supported on hw interrupt 0. */
-#define MALTAINT_END      16
+/*
+ * Interrupts 0..15 are used for Malta ISA compatible interrupts
+ */
+#define MALTA_INT_BASE         0
+
+/*
+ * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode)
+ */
+#define MIPSCPU_INT_BASE       16
+
+/* CPU interrupt offsets */
+#define MIPSCPU_INT_SW0                0
+#define MIPSCPU_INT_SW1                1
+#define MIPSCPU_INT_MB0                2
+#define MIPSCPU_INT_I8259A     MIPSCPU_INT_MB0
+#define MIPSCPU_INT_MB1                3
+#define MIPSCPU_INT_SMI                MIPSCPU_INT_MB1
+#define MIPSCPU_INT_MB2                4
+#define MIPSCPU_INT_MB3                5
+#define MIPSCPU_INT_COREHI     MIPSCPU_INT_MB3
+#define MIPSCPU_INT_MB4                6
+#define MIPSCPU_INT_CORELO     MIPSCPU_INT_MB4
+#define MIPSCPU_INT_CPUCTR     7
+
+/*
+ * Interrupts 64..127 are used for Soc-it Classic interrupts
+ */
+#define MSC01C_INT_BASE                64
+
+/* SOC-it Classic interrupt offsets */
+#define MSC01C_INT_TMR         0
+#define MSC01C_INT_PCI         1
+
+/*
+ * Interrupts 64..127 are used for Soc-it EIC interrupts
+ */
+#define MSC01E_INT_BASE                64
+
+/* SOC-it EIC interrupt offsets */
+#define MSC01E_INT_SW0         1
+#define MSC01E_INT_SW1         2
+#define MSC01E_INT_MB0         3
+#define MSC01E_INT_I8259A      MSC01E_INT_MB0
+#define MSC01E_INT_MB1         4
+#define MSC01E_INT_SMI         MSC01E_INT_MB1
+#define MSC01E_INT_MB2         5
+#define MSC01E_INT_MB3         6
+#define MSC01E_INT_COREHI      MSC01E_INT_MB3
+#define MSC01E_INT_MB4         7
+#define MSC01E_INT_CORELO      MSC01E_INT_MB4
+#define MSC01E_INT_TMR         8
+#define MSC01E_INT_PCI         9
+#define MSC01E_INT_PERFCTR     10
+#define MSC01E_INT_CPUCTR      11
 
+#ifndef __ASSEMBLY__
 extern void maltaint_init(void);
+#endif
 
 #endif /* !(_MIPS_MALTAINT_H) */