]> pilppa.org Git - linux-2.6-omap-h63xx.git/blobdiff - include/asm-mips/system.h
[MIPS] Cobalt: Move UART base definition to arch/mips/cobalt/console.c
[linux-2.6-omap-h63xx.git] / include / asm-mips / system.h
index 3713d256d36958d52d6ac750315f414c3610ff77..480b574e2483a6a22581280e8091d23ba9afaa5d 100644 (file)
@@ -17,6 +17,7 @@
 
 #include <asm/addrspace.h>
 #include <asm/barrier.h>
+#include <asm/cmpxchg.h>
 #include <asm/cpu-features.h>
 #include <asm/dsp.h>
 #include <asm/war.h>
@@ -44,42 +45,34 @@ struct task_struct;
  * different thread.
  */
 
-#define switch_to(prev,next,last)                                      \
+#define __mips_mt_fpaff_switch_to(prev)                                        \
 do {                                                                   \
+       struct thread_info *__prev_ti = task_thread_info(prev);         \
+                                                                       \
        if (cpu_has_fpu &&                                              \
-           (prev->thread.mflags & MF_FPUBOUND) &&                      \
-            (!(KSTK_STATUS(prev) & ST0_CU1))) {                        \
-               prev->thread.mflags &= ~MF_FPUBOUND;                    \
+           test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) &&             \
+           (!(KSTK_STATUS(prev) & ST0_CU1))) {                         \
+               clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND);          \
                prev->cpus_allowed = prev->thread.user_cpus_allowed;    \
        }                                                               \
-       if (cpu_has_dsp)                                                \
-               __save_dsp(prev);                                       \
        next->thread.emulated_fp = 0;                                   \
-       (last) = resume(prev, next, task_thread_info(next));            \
-       if (cpu_has_dsp)                                                \
-               __restore_dsp(current);                                 \
 } while(0)
 
 #else
+#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
+#endif
+
 #define switch_to(prev,next,last)                                      \
 do {                                                                   \
+       __mips_mt_fpaff_switch_to(prev);                                \
        if (cpu_has_dsp)                                                \
                __save_dsp(prev);                                       \
        (last) = resume(prev, next, task_thread_info(next));            \
        if (cpu_has_dsp)                                                \
                __restore_dsp(current);                                 \
+       if (cpu_has_userlocal)                                          \
+               write_c0_userlocal(task_thread_info(current)->tp_value);\
 } while(0)
-#endif
-
-/*
- * On SMP systems, when the scheduler does migration-cost autodetection,
- * it needs a way to flush as much of the CPU's caches as possible.
- *
- * TODO: fill this in!
- */
-static inline void sched_cacheflush(void)
-{
-}
 
 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
 {
@@ -127,7 +120,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
                raw_local_irq_restore(flags);   /* implies memory barrier  */
        }
 
-       smp_mb();
+       smp_llsc_mb();
 
        return retval;
 }
@@ -175,7 +168,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
                raw_local_irq_restore(flags);   /* implies memory barrier  */
        }
 
-       smp_mb();
+       smp_llsc_mb();
 
        return retval;
 }
@@ -202,269 +195,12 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
 
 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 
-#define __HAVE_ARCH_CMPXCHG 1
-
-static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
-       unsigned long new)
-{
-       __u32 retval;
-
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
-               __asm__ __volatile__(
-               "       .set    push                                    \n"
-               "       .set    noat                                    \n"
-               "       .set    mips3                                   \n"
-               "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
-               "       bne     %0, %z3, 2f                             \n"
-               "       .set    mips0                                   \n"
-               "       move    $1, %z4                                 \n"
-               "       .set    mips3                                   \n"
-               "       sc      $1, %1                                  \n"
-               "       beqzl   $1, 1b                                  \n"
-               "2:                                                     \n"
-               "       .set    pop                                     \n"
-               : "=&r" (retval), "=R" (*m)
-               : "R" (*m), "Jr" (old), "Jr" (new)
-               : "memory");
-       } else if (cpu_has_llsc) {
-               __asm__ __volatile__(
-               "       .set    push                                    \n"
-               "       .set    noat                                    \n"
-               "       .set    mips3                                   \n"
-               "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
-               "       bne     %0, %z3, 2f                             \n"
-               "       .set    mips0                                   \n"
-               "       move    $1, %z4                                 \n"
-               "       .set    mips3                                   \n"
-               "       sc      $1, %1                                  \n"
-               "       beqz    $1, 3f                                  \n"
-               "2:                                                     \n"
-               "       .subsection 2                                   \n"
-               "3:     b       1b                                      \n"
-               "       .previous                                       \n"
-               "       .set    pop                                     \n"
-               : "=&r" (retval), "=R" (*m)
-               : "R" (*m), "Jr" (old), "Jr" (new)
-               : "memory");
-       } else {
-               unsigned long flags;
-
-               raw_local_irq_save(flags);
-               retval = *m;
-               if (retval == old)
-                       *m = new;
-               raw_local_irq_restore(flags);   /* implies memory barrier  */
-       }
-
-       smp_mb();
-
-       return retval;
-}
-
-static inline unsigned long __cmpxchg_u32_local(volatile int * m,
-       unsigned long old, unsigned long new)
-{
-       __u32 retval;
-
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
-               __asm__ __volatile__(
-               "       .set    push                                    \n"
-               "       .set    noat                                    \n"
-               "       .set    mips3                                   \n"
-               "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
-               "       bne     %0, %z3, 2f                             \n"
-               "       .set    mips0                                   \n"
-               "       move    $1, %z4                                 \n"
-               "       .set    mips3                                   \n"
-               "       sc      $1, %1                                  \n"
-               "       beqzl   $1, 1b                                  \n"
-               "2:                                                     \n"
-               "       .set    pop                                     \n"
-               : "=&r" (retval), "=R" (*m)
-               : "R" (*m), "Jr" (old), "Jr" (new)
-               : "memory");
-       } else if (cpu_has_llsc) {
-               __asm__ __volatile__(
-               "       .set    push                                    \n"
-               "       .set    noat                                    \n"
-               "       .set    mips3                                   \n"
-               "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
-               "       bne     %0, %z3, 2f                             \n"
-               "       .set    mips0                                   \n"
-               "       move    $1, %z4                                 \n"
-               "       .set    mips3                                   \n"
-               "       sc      $1, %1                                  \n"
-               "       beqz    $1, 1b                                  \n"
-               "2:                                                     \n"
-               "       .set    pop                                     \n"
-               : "=&r" (retval), "=R" (*m)
-               : "R" (*m), "Jr" (old), "Jr" (new)
-               : "memory");
-       } else {
-               unsigned long flags;
-
-               local_irq_save(flags);
-               retval = *m;
-               if (retval == old)
-                       *m = new;
-               local_irq_restore(flags);       /* implies memory barrier  */
-       }
-
-       return retval;
-}
-
-#ifdef CONFIG_64BIT
-static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
-       unsigned long new)
-{
-       __u64 retval;
-
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
-               __asm__ __volatile__(
-               "       .set    push                                    \n"
-               "       .set    noat                                    \n"
-               "       .set    mips3                                   \n"
-               "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
-               "       bne     %0, %z3, 2f                             \n"
-               "       move    $1, %z4                                 \n"
-               "       scd     $1, %1                                  \n"
-               "       beqzl   $1, 1b                                  \n"
-               "2:                                                     \n"
-               "       .set    pop                                     \n"
-               : "=&r" (retval), "=R" (*m)
-               : "R" (*m), "Jr" (old), "Jr" (new)
-               : "memory");
-       } else if (cpu_has_llsc) {
-               __asm__ __volatile__(
-               "       .set    push                                    \n"
-               "       .set    noat                                    \n"
-               "       .set    mips3                                   \n"
-               "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
-               "       bne     %0, %z3, 2f                             \n"
-               "       move    $1, %z4                                 \n"
-               "       scd     $1, %1                                  \n"
-               "       beqz    $1, 3f                                  \n"
-               "2:                                                     \n"
-               "       .subsection 2                                   \n"
-               "3:     b       1b                                      \n"
-               "       .previous                                       \n"
-               "       .set    pop                                     \n"
-               : "=&r" (retval), "=R" (*m)
-               : "R" (*m), "Jr" (old), "Jr" (new)
-               : "memory");
-       } else {
-               unsigned long flags;
-
-               raw_local_irq_save(flags);
-               retval = *m;
-               if (retval == old)
-                       *m = new;
-               raw_local_irq_restore(flags);   /* implies memory barrier  */
-       }
-
-       smp_mb();
-
-       return retval;
-}
-
-static inline unsigned long __cmpxchg_u64_local(volatile int * m,
-       unsigned long old, unsigned long new)
-{
-       __u64 retval;
-
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
-               __asm__ __volatile__(
-               "       .set    push                                    \n"
-               "       .set    noat                                    \n"
-               "       .set    mips3                                   \n"
-               "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
-               "       bne     %0, %z3, 2f                             \n"
-               "       move    $1, %z4                                 \n"
-               "       scd     $1, %1                                  \n"
-               "       beqzl   $1, 1b                                  \n"
-               "2:                                                     \n"
-               "       .set    pop                                     \n"
-               : "=&r" (retval), "=R" (*m)
-               : "R" (*m), "Jr" (old), "Jr" (new)
-               : "memory");
-       } else if (cpu_has_llsc) {
-               __asm__ __volatile__(
-               "       .set    push                                    \n"
-               "       .set    noat                                    \n"
-               "       .set    mips3                                   \n"
-               "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
-               "       bne     %0, %z3, 2f                             \n"
-               "       move    $1, %z4                                 \n"
-               "       scd     $1, %1                                  \n"
-               "       beqz    $1, 1b                                  \n"
-               "2:                                                     \n"
-               "       .set    pop                                     \n"
-               : "=&r" (retval), "=R" (*m)
-               : "R" (*m), "Jr" (old), "Jr" (new)
-               : "memory");
-       } else {
-               unsigned long flags;
-
-               local_irq_save(flags);
-               retval = *m;
-               if (retval == old)
-                       *m = new;
-               local_irq_restore(flags);       /* implies memory barrier  */
-       }
-
-       return retval;
-}
-
-#else
-extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
-       volatile int * m, unsigned long old, unsigned long new);
-#define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
-extern unsigned long __cmpxchg_u64_local_unsupported_on_32bit_kernels(
-       volatile int * m, unsigned long old, unsigned long new);
-#define __cmpxchg_u64_local __cmpxchg_u64_local_unsupported_on_32bit_kernels
-#endif
-
-/* This function doesn't exist, so you'll get a linker error
-   if something tries to do an invalid cmpxchg().  */
-extern void __cmpxchg_called_with_bad_pointer(void);
-
-static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
-       unsigned long new, int size)
-{
-       switch (size) {
-       case 4:
-               return __cmpxchg_u32(ptr, old, new);
-       case 8:
-               return __cmpxchg_u64(ptr, old, new);
-       }
-       __cmpxchg_called_with_bad_pointer();
-       return old;
-}
-
-static inline unsigned long __cmpxchg_local(volatile void * ptr,
-       unsigned long old, unsigned long new, int size)
-{
-       switch (size) {
-       case 4:
-               return __cmpxchg_u32_local(ptr, old, new);
-       case 8:
-               return __cmpxchg_u64_local(ptr, old, new);
-       }
-       __cmpxchg_called_with_bad_pointer();
-       return old;
-}
-
-#define cmpxchg(ptr,old,new) \
-       ((__typeof__(*(ptr)))__cmpxchg((ptr), \
-               (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
-
-#define cmpxchg_local(ptr,old,new) \
-       ((__typeof__(*(ptr)))__cmpxchg_local((ptr), \
-               (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
-
 extern void set_handler (unsigned long offset, void *addr, unsigned long len);
 extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
-extern void *set_vi_handler (int n, void *addr);
+
+typedef void (*vi_handler_t)(void);
+extern void *set_vi_handler (int n, vi_handler_t addr);
+
 extern void *set_except_vector(int n, void *addr);
 extern unsigned long ebase;
 extern void per_cpu_trap_init(void);
@@ -477,6 +213,6 @@ extern int stop_a_enabled;
  */
 #define __ARCH_WANT_UNLOCKED_CTXSW
 
-#define arch_align_stack(x) (x)
+extern unsigned long arch_align_stack(unsigned long sp);
 
 #endif /* _ASM_SYSTEM_H */