Merge commit 'gcl/gcl-next'

[linux-2.6-omap-h63xx.git] / include / asm-powerpc / mpc52xx_psc.h

diff --git a/include/asm-powerpc/mpc52xx_psc.h b/include/asm-powerpc/mpc52xx_psc.h
index 26690d2b32f53dc7b9b6581c7e8cc3b480a1ceeb..8917ed63056593377498abaf721e3f33ecaa3b1e 100644 (file)
--- a/include/asm-powerpc/mpc52xx_psc.h
+++ b/include/asm-powerpc/mpc52xx_psc.h
@@ -60,10 +60,12 @@
 #define MPC52xx_PSC_RXTX_FIFO_ALARM    0x0002
 #define MPC52xx_PSC_RXTX_FIFO_EMPTY    0x0001
 
-/* PSC interrupt mask bits */
+/* PSC interrupt status/mask bits */
 #define MPC52xx_PSC_IMR_TXRDY          0x0100
 #define MPC52xx_PSC_IMR_RXRDY          0x0200
 #define MPC52xx_PSC_IMR_DB             0x0400
+#define MPC52xx_PSC_IMR_TXEMP          0x0800
+#define MPC52xx_PSC_IMR_ORERR          0x1000
 #define MPC52xx_PSC_IMR_IPC            0x8000
 
 /* PSC input port change bit */
@@ -92,6 +94,34 @@
 
 #define MPC52xx_PSC_RFNUM_MASK 0x01ff
 
+#define MPC52xx_PSC_SICR_DTS1                  (1 << 29)
+#define MPC52xx_PSC_SICR_SHDR                  (1 << 28)
+#define MPC52xx_PSC_SICR_SIM_MASK              (0xf << 24)
+#define MPC52xx_PSC_SICR_SIM_UART              (0x0 << 24)
+#define MPC52xx_PSC_SICR_SIM_UART_DCD          (0x8 << 24)
+#define MPC52xx_PSC_SICR_SIM_CODEC_8           (0x1 << 24)
+#define MPC52xx_PSC_SICR_SIM_CODEC_16          (0x2 << 24)
+#define MPC52xx_PSC_SICR_SIM_AC97              (0x3 << 24)
+#define MPC52xx_PSC_SICR_SIM_SIR               (0x8 << 24)
+#define MPC52xx_PSC_SICR_SIM_SIR_DCD           (0xc << 24)
+#define MPC52xx_PSC_SICR_SIM_MIR               (0x5 << 24)
+#define MPC52xx_PSC_SICR_SIM_FIR               (0x6 << 24)
+#define MPC52xx_PSC_SICR_SIM_CODEC_24          (0x7 << 24)
+#define MPC52xx_PSC_SICR_SIM_CODEC_32          (0xf << 24)
+#define MPC52xx_PSC_SICR_GENCLK                        (1 << 23)
+#define MPC52xx_PSC_SICR_I2S                   (1 << 22)
+#define MPC52xx_PSC_SICR_CLKPOL                        (1 << 21)
+#define MPC52xx_PSC_SICR_SYNCPOL               (1 << 20)
+#define MPC52xx_PSC_SICR_CELLSLAVE             (1 << 19)
+#define MPC52xx_PSC_SICR_CELL2XCLK             (1 << 18)
+#define MPC52xx_PSC_SICR_ESAI                  (1 << 17)
+#define MPC52xx_PSC_SICR_ENAC97                        (1 << 16)
+#define MPC52xx_PSC_SICR_SPI                   (1 << 15)
+#define MPC52xx_PSC_SICR_MSTR                  (1 << 14)
+#define MPC52xx_PSC_SICR_CPOL                  (1 << 13)
+#define MPC52xx_PSC_SICR_CPHA                  (1 << 12)
+#define MPC52xx_PSC_SICR_USEEOF                        (1 << 11)
+#define MPC52xx_PSC_SICR_DISABLEEOF            (1 << 10)
 
 /* Structure of the hardware registers */
 struct mpc52xx_psc {
@@ -132,8 +162,12 @@ struct mpc52xx_psc {
        u8              reserved5[3];
        u8              ctlr;           /* PSC + 0x1c */
        u8              reserved6[3];
-       u16             ccr;            /* PSC + 0x20 */
-       u8              reserved7[14];
+       /* BitClkDiv field of CCR is byte swapped in
+        * the hardware for mpc5200/b compatibility */
+       u32             ccr;            /* PSC + 0x20 */
+       u32             ac97_slots;     /* PSC + 0x24 */
+       u32             ac97_cmd;       /* PSC + 0x28 */
+       u32             ac97_data;      /* PSC + 0x2c */
        u8              ivr;            /* PSC + 0x30 */
        u8              reserved8[3];
        u8              ip;             /* PSC + 0x34 */
@@ -153,6 +187,9 @@ struct mpc52xx_psc {
        u8              reserved16[3];
        u8              irfdr;          /* PSC + 0x54 */
        u8              reserved17[3];
+};
+
+struct mpc52xx_psc_fifo {
        u16             rfnum;          /* PSC + 0x58 */
        u16             reserved18;
        u16             tfnum;          /* PSC + 0x5c */
@@ -187,5 +224,53 @@ struct mpc52xx_psc {
        u16             tflwfptr;       /* PSC + 0x9e */
 };
 
+#define MPC512x_PSC_FIFO_RESET_SLICE   0x80
+#define MPC512x_PSC_FIFO_ENABLE_SLICE  0x01
+#define MPC512x_PSC_FIFO_ENABLE_DMA    0x04
+
+#define MPC512x_PSC_FIFO_EMPTY         0x1
+#define MPC512x_PSC_FIFO_FULL          0x2
+#define MPC512x_PSC_FIFO_ALARM         0x4
+#define MPC512x_PSC_FIFO_URERR         0x8
+#define MPC512x_PSC_FIFO_ORERR         0x01
+#define MPC512x_PSC_FIFO_MEMERROR      0x02
+
+struct mpc512x_psc_fifo {
+       u32             reserved1[10];
+       u32             txcmd;          /* PSC + 0x80 */
+       u32             txalarm;        /* PSC + 0x84 */
+       u32             txsr;           /* PSC + 0x88 */
+       u32             txisr;          /* PSC + 0x8c */
+       u32             tximr;          /* PSC + 0x90 */
+       u32             txcnt;          /* PSC + 0x94 */
+       u32             txptr;          /* PSC + 0x98 */
+       u32             txsz;           /* PSC + 0x9c */
+       u32             reserved2[7];
+       union {
+               u8      txdata_8;
+               u16     txdata_16;
+               u32     txdata_32;
+       } txdata;                       /* PSC + 0xbc */
+#define txdata_8 txdata.txdata_8
+#define txdata_16 txdata.txdata_16
+#define txdata_32 txdata.txdata_32
+       u32             rxcmd;          /* PSC + 0xc0 */
+       u32             rxalarm;        /* PSC + 0xc4 */
+       u32             rxsr;           /* PSC + 0xc8 */
+       u32             rxisr;          /* PSC + 0xcc */
+       u32             rximr;          /* PSC + 0xd0 */
+       u32             rxcnt;          /* PSC + 0xd4 */
+       u32             rxptr;          /* PSC + 0xd8 */
+       u32             rxsz;           /* PSC + 0xdc */
+       u32             reserved3[7];
+       union {
+               u8      rxdata_8;
+               u16     rxdata_16;
+               u32     rxdata_32;
+       } rxdata;                       /* PSC + 0xfc */
+#define rxdata_8 rxdata.rxdata_8
+#define rxdata_16 rxdata.rxdata_16
+#define rxdata_32 rxdata.rxdata_32
+};
 
 #endif  /* __ASM_MPC52xx_PSC_H__ */